TW582141B - Receiver and method therefor - Google Patents

Abstract

Embodiments of the present invention relate generally to receivers. One embodiment relates to a digital FM receiver having multiple sensors (e.g. antennas). In one embodiment, the digital receiver includes a baseband unit having a channel processing unit. In one embodiment, the channel processing unit is capable of calculating or estimating a phase difference between the incoming signals prior to combining them. One embodiment uses phase estimation method for diversity combining the signals while another embodiment utlizes a hybrid phase lock loop method. Also, some embodiments of the present invention provide for echo-cancelling after diversity combining. An alternate embodiment of the channel processing unit utilizes a space-time unit to diversity combine and provide echo cancelling for the incoming signals. Other embodiments of the present invention allow for the incoming signals from the multiple antennas to pass through the baseband unit uncombined, where the incoming signals may have different data formats.

Description

582141 A7 B7 V. Description of the invention (1) Participants of the pre-existing technology patent This application is US Patent No. 09 / 916,915 filed on July 27, 2001. This invention relates generally to receivers, and more specifically, to radio receivers. Related technologies such as antenna multiple sensors are typically used to provide more information to the receiver. However, 'due to at least partially unwanted reflections and spreads, multiple sensors are usually versions that receive different delays and attenuations of a transmission signal. Of overlap. Multipath elements received from a transmission signal typically have different phases that are constructive or destructive together, causing attenuation of the received signal. It is therefore desirable to have an improved receiver that can effectively combine or process these received signals from multiple sensors. In addition, reducing the impact of multipath replies and increasing the confidence level of these receivers is needed. Brief Description of Formula M The present invention is described by way of example and not limited to the accompanying drawings. The same reference numerals in the figures represent similar elements: Figure 1 depicts a radio in block diagram form according to a specific embodiment of the present invention Receiver; FIG. 2 is a block diagram depicting a part of the baseband unit of FIG. 1 according to a specific embodiment of the present invention; FIG. 3-4 is a block diagram depicting a part of the channel of FIG. 1 according to different specific embodiments of the present invention Processing unit; -5-This paper size applies to China National Standard (CNS) Α4 specification (210X 297 public love)

Binding

582141 A7 ----- —_B7 ________ — V. Description of the invention (2) FIG. 5 is a block diagram depicting a part of the various combination units of FIG. 3 or 4 according to a specific embodiment of the present invention; Fig. 5 describes the various combined operation units of Fig. 5 in the form of a specific embodiment; Fig. 7 depicts a part of the weighting factor determining circuit of Fig. 5 in the form of a block diagram according to a specific embodiment of the present invention; A part of the phase evaluation circuit of FIG. 5 is described in the form of a block diagram in the embodiment; FIG. 9 is a diagram of a part of the various combined units in FIG. 5 in the form of a block diagram according to a specific embodiment of the present invention; 3 or 4 are described in block diagram form according to the embodiment; FIG. 11 is a flowchart illustrating the operation of the various combined units of FIG. 10 according to another specific embodiment of the present invention; and FIG. 12 is a diagram according to the present invention. Another specific embodiment describes a part of the signal characteristic value evaluation circuit in FIG. 10 in the form of a block diagram. FIG. 13 is a diagram illustrating another embodiment according to the present invention. A block diagram depicts a part of the multiplier, phase lock loop, and lock detection circuit of FIG. 10; FIG. 14 is a block diagram depicting a part of the lock detector of FIG. 13 according to another embodiment of the present invention; FIG. 15 FIG. 16 is a block diagram depicting a part of the space-time unit of FIG. 3 according to another embodiment of the present invention; and FIG. 16 is a block diagram depicting a part of the multipath reply of FIG. 3 or 4 according to a specific embodiment of the present invention. Detectors and signal quality monitors. -6-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 582141 A7 B7 V. Description of the invention (3) Figure 17 is a block diagram inserted in accordance with another specific embodiment of the present invention A part of the weighting factor determining circuit in FIG. 5 will be described. Fig. 18 is a block diagram depicting the operation of the weighting value determining circuit of Fig. 17 according to another embodiment of the present invention. Those skilled in the art will understand that the drawings are only used for simplicity and clear description, and are not drawn to scale. For example, some of the elements in the figure are enlarged to help understand the specific embodiments of the present invention. Detailed description of the drawings. As used herein, terminology, bus " can be used as a plurality of signals or wires' and can be used to transmit one or more of various types such as data, address, control, or status. Information. The conductors discussed here are described by a single conductor, a plurality of conductors, a unidirectional conductor, or a bidirectional conductor. However, different embodiments may change the implementation of the wires. For example, with separate unidirectional wires, bidirectional wires are not used, and vice versa. Moreover, a plurality of wires may be replaced with a single wire capable of transmitting multiple signals in series or a time multiplexing method. Similarly, a single conductor carrying multiple signals can be divided into various conductors used to carry some of these signals. Therefore, there are many options for transmitting signals. When referring to a signal, status bit, or a logically true or false state of a similar device, the terms " confirm, and " negative " ^ are used if the logically true state is a logical level 1, logically false The state is a logical level and 'If the logically true state is a logical level 0, the logically false state is a logical level. The brackets are used to indicate the position of a bus wire or a value. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) binding

Line 582141 A7 ___ B7 V. Description of the invention (4) For example, "the bus 60 [0-7], or, the wire [0-7] of the bus 00" means the eight lowest of the bus 60 Valid wires, and "address bit [0-7] " or " address [0-7] represents the 8 least significant bits of a bit value. The sign π $ before a value" The values are expressed in hexadecimal or base 16. The sign "%" before a number indicates a binary or base-2 form. As a brief introduction, note that FIG. 1 depicts a specific embodiment of a radio receiver with a baseband unit, and FIG. 2 depicts a specific embodiment of a baseband unit of FIG. Figures 3 and 4 provide different specific embodiments of a channel processing unit (in the baseband unit of Figure 2). Two specific embodiments (Figures 3 and 4) can calculate or evaluate a phase difference between the input signals before they are combined. Moreover, each of the specific embodiments of Figures 3 and 4 provides a reply cancellation option that is usually performed when using various combinations of input signals. This reply is executed by the space-time unit 302 in FIG. 3 and the reply canceller 406 in FIG. 4. Moreover, Figures 3 and 4 include a variety of combination units (304, 404) to combine a plurality of input 仏 numbers. Therefore, 'FIGS. 5 and 10 describe another specific embodiment of the various combination units 304 and 404. FIG. 5 illustrates a phase evaluation method for combining signals, and FIG. 10 illustrates a hybrid PLL method. Therefore, specific embodiments of the present invention may provide various options for use in a baseband unit (and typically in channel processing). Fig. 1 illustrates a radio receiver according to a specific embodiment of the present invention. The broadcast electrical receiver 100 includes a user interface 110 coupled bidirectionally to the control circuit 112 via a lead 144. The control circuit 112 is bidirectionally coupled to the radio frequency (radio frequency) units 106 and 108 via a wire 142: bidirectionally coupled to the intermediate frequency (IF) unit 114 via a wire 140; and coupled to -8 via a wire 138 -This paper size applies _ _ quasi_) A4 specification (plus χ 582141 A7 _____ B7 I. Description of the invention (~ ^ ~~ Baseband unit 116. The radio frequency unit 106 is coupled to the radio frequency antenna 102 via the wire 120, and also via the wire 124 and two-way coupled to the intermediate frequency unit 114. The radio frequency unit 108 is coupled to the radio frequency antenna 104 via a wire 122, and is bidirectionally coupled to the intermediate frequency unit 114 via a wire 126. The intermediate frequency unit 114 is via wires 128, 130 And 132 are coupled to the baseband unit 116. The baseband unit 116 is coupled to the audio processing unit 150 and the data processing unit 148 via a wire 134. The audio processing unit 15 is coupled to an amplifier capable of providing an output signal via a wire 136 And the team 118. The data processing unit 148 is bidirectionally coupled to the user interface lio. Moreover, the user can provide and receive information between the user interfaces 110 via the wire 146. Operationally, radio frequency The antennas 102 and 104 can capture radio signals and provide them to the radio frequency units 106 and 108, respectively. The radio frequency units 106 and 108 can convert the received radio signals into a common radio signal according to the design of the radio receiver. Intermediate frequency range. That is, the radio frequency units 106 and 108 can convert the received radio signal frequency to a lower frequency or a higher frequency, which is determined by the requirements of the intermediate frequency unit 114. The intermediate frequency unit 114 is Receive radio frequency signals via wires 124 and 126, and digitize them via an analog-to-digital converter. The IF unit 114 may also perform digital mixing to produce the same output to the baseband unit 116 via wires 2 8 and 130. Digital output with phase difference of 90 degrees. In another specific embodiment, the intermediate frequency unit n4 can be selected. That is, the radio frequency units 106 and 108 can directly convert the radio signals received from the antennas 102 and 104. Baseband; and includes an analog-to-digital converter to provide the digitized baseband number 4 directly to the baseband unit (and note that if used, RF units 106 and 108 and IF unit Π4 can be considered as one & quo t; Lower frequency unit, or -9-This paper size applies to China National Standard (CNS) A4 (210X 297 mm)

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" Higher frequency unit, 'depends on whether the received radio signal needs to be converted to a lower or higher frequency, respectively. The baseband unit 116 receives the digitized radio signal from the IF unit 114, or if no IF unit exists, directly receives it from the RF units ⑽ and ⑽. The baseband unit 116 may perform signal conditioning, demodulation, and decoding to generate audio and data information via the wire 134. The processing performed by the baseband unit 116 will be described further with reference to the following figure. The audio signal via the lead 134 is provided to the audio processing unit 150 coupled to the amplifier and the amplifier 8 to generate an audio output from the receiver 100 via the lead 136. For example, this might be music played from a radio squadron. Alternatively, the baseband unit 116 outputs the data information to the data processing unit 148 via the wire 134 for further processing. The output of the data processing unit 148 is coupled to the user interface 110 to allow the user to interact with the output of the receiver 100. For example, the user interface 110 may represent a wireless dial, a touch screen, a monitor and keyboard, a numeric keypad, or any other suitable input / output device. Information is representative of text, drawings, or any other information transmitted in digital form. In another specific embodiment, the radio receiver 100 can be used for different formats of data such as AM, FM, GPS, digital television, television digital / audio broadcasting, digital / video broadcasting, and the like. In addition, the receiver 100 is designed to receive frequencies other than radio frequencies. Therefore, the antennas 102 and 104 can be regarded as sensors to sense various data formats. In addition, each sensor or antenna of the system can receive data in different formats, so, for example, one sensor can receive radio signals and other sensors can receive data as described above. -10 — this paper standard applies China National Standard (CNS) A4 specification (210 X 297 mm) 582141 A7 B7 V. Description of invention (7) Same type. Furthermore, the receiver 100 of FIG. 1 describes two sensors or antennas (e.g., antennas 102 and 104); however, another specific embodiment is to use any number of sensors to capture signals or information. FIG. 2 illustrates a specific embodiment of a part of the baseband unit 116. The IF filter 200 receives the in-phase and 90-degree phase difference signal pairs II, Q1, and 12, Q2 via wires 128 and 130, respectively, where II and Q1 correspond to the signals received through the sensor or the antenna 102, and 12, Q2 Corresponds to signals received via a sensor or antenna 104. Series II and 12 represent digital in-phase signals, while Q1 and Q 2 represent digital 90-degree phase difference signals (for example, 90-degree different phase signals compared to in-phase signals) ^ (Note, for example, 11, Q 1 And 12, and Q2 each signal represents a complex number, where 11 and 12 represent the real part, and Q1 and Q2 represent the imaginary part, and will be discussed further below) The IF filter 200 is connected via the conductor 202 and 204 is coupled to the processing unit 206. The channel processing unit 206 is coupled to the demodulator 212 via wires 208 and 210, and the demodulator 212 is coupled to the signal processing unit 216 via wires 214. The signal processing unit 216 provides audio / data information via a lead 134. The IF filter 200, the channel processing unit 206, the demodulator 212, and the signal processing unit 216 are coupled to the control circuit 112 via a wire 138. The conductor 138 can be regarded as a control bus including a plurality of conductors for transmitting different signals to and from the units 2000, 206, 212, and 216. For example, the conductor 132 includes a portion of the conductor 138, or a full bus 13 8 provided to return to the intermediate frequency unit 114. Therefore, the control signal received via the conductor 138 is transmitted to the intermediate frequency unit 114 via the conductor 132. Similarly, these control signals or a part of these signals are transmitted back to the RF unit via the wires 124 and 126.

This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 582141 A7 B7 V. Description of the invention (No. 8 106 and 108. Alternatively, the control signal can be transmitted directly from the control circuit 112 via the wire 142 To radio frequency units 106 and 108. Operationally, the IF filter 200 removes unnecessary signals and noise from the desired frequency range of the input signals II, Q1, and 12, Q 2. The IF filter 200 can also To suppress adjacent channels, in order to generate filtered in-phase and 90-degree phase difference signal pairs Γ, Q2, and 12, Q2, where Γ, Q1 · are corresponding to II, Q1, and 12, and Q2, are Corresponds to 12, Q2. The channel processing unit 206 may receive IΓ, Q1, and 12, Q2, and combine them to generate a single combined signal Icomb, Qcomb. Alternatively, the channel processing unit 206 may also pass, for example, the wire 210 and, for example, II ·, Qi, or 12, Q2, one of the input signals. The input signal is directly provided to the demodulator 212 as Ibypass, Qbypass. Therefore, the unit 212 of the channel processing unit 206. The channel processing unit 206 also provides for example A combined signal of Icomb, Qcomb, For example, the bypass signals of Ibypass and Qbypass. The channel processing unit 206, Ibypass, and Qbypass also provide receiving different types of signal formats, so that a signal such as Γ, Q1 'can be processed by the channel processing unit 206, and output through the wire 208 And the second signal such as 12 ', Q2' is a different signal format, and can be bypassed directly to the demodulator 212. (Alternatively, II, 'Q1, may be output via the wire 208, without the need of a channel processing unit 206 processing). This allows the channel processing unit 206 to provide a single combined signal or a variety of different signals for further processing. For example, an antenna can provide signals from a radio station and a second antenna can provide signals from a second radio Channel signal, or different data formats. The channel processing unit 206 can also perform noise cancellation of the received signal. Also, note that the description of the specific embodiment of FIG. 2 only describes the use of an IF filter-12.

582141 A7 _ B7 V. Description of the invention (9) Two signals received by 200 and frequency processing unit 206. However, as discussed in FIG. 1, the receiver 100 includes any number of antennas, such as 102 and 104. In this specific embodiment, each antenna may provide, for example, the same in-phase and 90 degree phase difference signal pairs of j, q1 to the intermediate frequency filter 200. In this specific embodiment, the intermediate frequency chirper 200 may provide a plurality of filtered in-phase and 90-degree phase difference signal pairs corresponding to each antenna. In this mode, the channel processing unit 206 can output a single combined signal or multiple partial combined signals as required. Moreover, the channel processing unit 206 can provide multiple bypass signals, so more than one input signal can be directly bypassed to a further processing unit such as the demodulator 212. The demodulator 212 receives a signal 1 (: 011113,

Qcomb, Ibypass, Qbypass, and a demodulated signal are supplied to a signal processing unit 216 via a wire 214. Moreover, if the demodulator 212 receives the signals Ibypass and Qbypass, the demodulator 212 also supplies a demodulation Ibypass and Qbypass to the signal processing unit 216 via the wire 214. However, as described above, Ibypass and Qbypass are optional. For example, in a specific embodiment, the demodulator 212 may be an FM demodulator to provide a multiplexed (MPX) signal corresponding to each input signal (for example, Icomb, Qcomb, and ibypass, Qbypass). In another specific embodiment, the demodulator 212 may be an AM demodulator or demodulator of the system (such as the receiver 100) and any other signal formats required for the input signals n, 12, Q2. The signal processing unit 216 can further process the signal received via the wire 214 and output audio / data information via the wire 134. Audio / data information only includes audio information, data information, or a combination of audio and data information. Then, as shown in Figure 1, this data can be output to, for example, a data processing system-13-This paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) 582141 A7 _______B7 V. Description of the invention (1〇) Or audio processing systems. For example, in a f μ receiver, 212 may output an MPX signal to the signal processing unit 216 as described above. In this specific embodiment, the signal processing unit 216 can receive the signals, and perform stereo decoding to provide the appropriate signals to each team. For example, MPX # can be decoded with a pilot tone to provide the left and right flavors of the stereo system. Moreover, the signal processing unit 216 can demodulate other subcarrier # numbers (such as RDS or D ARC) in order to provide further information to the subsequent processing unit. FIG. 3 illustrates a specific embodiment of a part of the channel processing unit 206 in the form of a block diagram. The gain circuit 310 receives 11 ·, Q1 · and 12 'and Q2 * via the wires 202 and 204. The gain circuit 310 receives and provides control signals between the control circuits 112 via the wires 138. The gain circuit 310 is coupled to the multipath feedback detector and the signal quality monitor 300, the space-time unit 302, and the multiple combination unit 304 via the wires 3 14 and 3 16. The MUX 308 receives input signals and a control signal 138 through the wires 3 14 and 3 16 and outputs Ibypass and Qbypass through the wires 210. The MUX 306 receives an input signal through the wires 312 and 318, and a control signal through the wire 320, and outputs Icomb and Qcomb through the wire 208. The lead 320 may be a part of the lead 138, or a reception control signal received from the multi-path response detector and the signal quality monitor 300. Operationally, the gain circuit 310 receives II ·, Q1, and 12 ', Q2 ·, and adjusts the signal level of the input signal, and provides a gain-adjusted (eg, amplified) version of I Γ, Q1, via the wires 3 14 , And a gain-adjusted (eg, amplified) version of 12, Q2, is provided via the lead 316. Therefore, in the description of Figure 3-14-this paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297) 582141 A7 _ B7 _ V. Description of the invention (" " 'Description and part of Figure 3, 11' , Q 1, and ΐ2 ·, Q2 can be regarded as the gain-adjusted versions of these signals transmitted through the wires 314 and 3 16. The multi-path response detector and the signal quality monitor 3 00 receive n, Qi, and 12, , Q 2 ', and decide whether to cancel the reply. The input signal multipath elements (possibly due to unwanted spreading and reflection) at the antennas 1 02 and 104 cause too much interference (such as reply), which may affect the It is mitigated before the combined signal is output via the wire 208. If the multi-path reply detector and the signal quality monitor 300 decide that the reply needs to be cancelled (that is, the reply amount exceeds a predetermined reply threshold), the multi-path reply detector and signal The quality monitor 300 may provide a control signal to the space-time unit 302 and the multiple combination unit 304 to select a process to be performed. For example, in the case of replying to a reply request, the control signal 320 may select space-time Element 302 performs signal processing such that the input signals η ,,, and 12, and q2 can be appropriately combined with the reply before providing it as an output. However, 'if sufficient reply is not detected, multipath The reply detector and the signal quality monitor 300 may provide a control signal to the multiple combining unit 304 via the wire 320 to process the signals I Γ, Q Γ and 12, and Q 2 so as to generate a combined output through the wire 318. Therefore, the multiple combination unit 304 can provide a combination signal without cancellation of the reply. The control signal provided by the multi-path response detector 300 through the wire 320 can also provide a selector signal to the MIJX 306 to determine The output of the space-time unit 302 or the output of the multiple combination unit 304 is provided by Icomb and Qcomb via the wire 208. The operation of the signal quality supervisor of the multi-path reply tester will be further discussed in FIG. 16. Measured conditions, multi-path response detectors and signals -15-This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 582141 A7 B7 (12). The quality supervisor 300 can select the space-time unit 302 as described above. The space-time unit 302 provided through the wire 312 is fed back to the multi-path reply detector and the signal quality supervision is 300 to determine whether the signal quality is sufficient (If the detected reply volume is lower than the predetermined reply threshold, the signal quality is considered sufficient.) If it is not enough, 'just output the feedback to the multipath signal detector and signal quality monitor 300 again' Will be performed. The operation of space-time unit 302 will be discussed in further detail in FIG. 15. As long as the signal is considered to be of sufficient quality, that is, below the threshold of the pre-echo reply, the multi-path reply detector and the signal quality monitor 300 are considered to be control signals via the wire 320 to the MUX 306. In order to select the signals provided by Icomb and Qcomb, Output 312. Therefore, the repetition will continue until there is sufficient reply to cancel execution. FIG. 4 illustrates a part of the channel processing unit 206 according to another embodiment of the present invention. A part of the channel processing unit 206 in FIG. 4 includes a gain circuit 400, a multi-path feedback detector and signal quality monitor 402, a multi-combination unit 404, a reply canceller 406, and a MUX 408. The various combination units 404 and MUX 408 receive I Γ, Q Γ and 12 ·, Q2 · via the wires 202 and 204. The multiple combining unit 404 supplies a combined signal to the MUX 408 via a wire 422. The gain circuit 400 supplies a gain adjustment signal to the multi-path response detector and the signal quality monitor 402 via a lead 416. The MUX 408 receives a control signal from the control circuit 112, and provides IΓ and Q1 * via a wire 412, and I21 and Q2 · via a wire 414, or supplies a combined signal from the 422 to the wire 412. In the latter case, no signal is provided to the wire 414; or, in another embodiment, in addition to combining signals, one of I1, Q1, and 12, and Q2, may be provided to the wire 414. Gain circuit -16-This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 582141 A7 __ B7 ____ 5. Description of the invention (13) is also coupled to the reply canceller 406 via the wire 416. The multipath reply detector and signal quality monitor 402 are coupled to the reply canceller 406 via wires 410 and 418. The reply canceller 406 provides outputs Icomb and Qcomb via the wire 208, and the gain circuit 400 provides outputs Ibypass and Qbypass via the wire 210. The lead 138 provides control signals from the control circuit 112 to and from the gain circuit 400, the multi-path feedback detector and the signal quality monitor 402, the multiple combination unit 404, the reply canceller 406, and the MUX 408. (Note that in the specific embodiment of FIG. 4, unlike the specific embodiment of FIG. 3, the multi-combination unit 404 does not receive gain adjustment inputs corresponding to IΓ, Q1, and 12, and Q2. Operationally, IΓ, Q1 may be processed in combination or separately via the channel processing unit 206. In the former case, the multi-combination unit 404 receives the signals I Γ, Q 1, 12, Q 2 via wires 202 and 204, and combines them so that a combined signal via MUX 408 via wire 412 via wire 412 Provided to the gain circuit 400. The gain circuit 400 provides a gain adjustment combination of II, Q1, and 12 ', Q 2' to the multi-path response detector 4002 via the lead 416. The multi-path reply detector 402 may determine whether or not the reply from the multi-path elements of the antennas 102 and 104 causes a greater than a predetermined reply threshold. If the reply exceeds this predetermined threshold, the multi-path reply detector 402 allows the reply canceller 40 to execute the reply of receiving the signal from the gain circuit 400 via the lead 41 through the lead 4106. The signal output from the reply canceller 406 is fed back to the multi-path reply detector 402 via the wire 418. The multi-path reply detector and the signal quality monitor 402 can decide whether the reply canceller 406 cancels a sufficient reply so that the reply falls below a predetermined reply threshold. If the reply level is lower than the predetermined -17-This paper size applies to China National Standard (CNS) A4 (210X 297 public love)

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582141 A7 __B7 5. If I clearly state (14) '" critical value', then the signal quality is sufficient, and the echo canceller 406 can output the combined signals Icomb and Qcomb via the wire 208. However, if the reply still exceeds the predetermined threshold, the signal can be repeatedly processed by the reply canceller 406 until it is judged that the signal quality is sufficient through the multi-path reply detector and the signal quality monitor 402 (for example, below the predetermined reply threshold). value). If it is sufficient, the reply canceller 406 outputs the last signal 1 (: 〇1 ^ 、 Qcomb 0 回 #eliminator 4 06) via the wire 208. Any method of reply cancellation can be used to provide the signals Icomb, Qcomb. For example, when needed A fixed-amplitude FM radio signal case 'a fixed coefficient algorithm (CM A) is applicable to the reply canceller 406. That is, the' back-k canceller 406 'is an appropriate signal processing unit for performing reply cancellation. Another embodiment may use least root-mean-square reply cancellation (LMS), reply to small square reply #cancel (rlS), or any other appropriate algorithm. Therefore, multiple reply cancellers may be used, which are due to processed signals If IΓ, Q1 'and 12', Q2 'are not combined, II, Qi, and 12, and q2 can be provided to MUX 408 (multiple multiple combination unit 404) via wires 202 and 204. A control signal It is coupled to the MUX 408 via a control signal back and forth between the control circuits 112. Therefore, 'If one of the signals ip, Qr or 12, and Q2, need not be combined, the MUX 408 can combine II, ,, and 12, One of Q2, Q2, is output to wire 412, The other of II ', Q1, and 12, and Q2 · are output to the lead 414. Each of the two signals can obtain an adjusted gain and output to the leads 416 and 210. The lead 416 is passed through the echo canceller 4. 6 (in this case, it is closed by a control signal via wire 410) and it is treated as -18-This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 582141 A7 B7 V. Description of the invention ( 15)

The output of Icomb is treated as Icomb and Qcomb via the wire 208. Another output of the gain circuit 400 is to provide the outputs Ibypass and Qbypass via the wire 210. Therefore, if no signal combination is needed, the gain adjustments 11 * and Q Γ are output as Icomb, Qcomb and Ibypass and Qbypass, and the gain adjustments 12 ’and Q2’ are output as the other of Icomb, Qcomb, Ibypass, and Qbypass. This allows selection of one or more signals to bypass the multiple combining unit 404. As mentioned above, this is useful in situations where different types or ranges of signals are desired. In this specific embodiment, Icomb, Qcomb and Ibypass, Qbypass are uncombined signals. Alternatively, although an uncombined signal (e.g. 11 ', Q Γ or 12', Q2 ') can be provided as Icomb, Qcomb or Ibypass, Qbypass. That is, if only one signal is desired, two signals need not be transmitted. In still another specific embodiment, a combined signal can be provided by Icomb, Qcomb, and a single (uncombined) signal (such as I Γ, Q Γ, or 12 ·, Q2 ') can be provided by Ibypass or Qbypass. Therefore, a bypass signal in the specific embodiments of FIGS. 3 and 4 can be used to select whether the output of the channel processing unit 206 is a combined or uncombined signal. This bypass signal may be a control signal of MUX 308 and MUX 408, for example. Therefore, in a specific embodiment, the bypass signal may be generated in the control circuit 112. However, another embodiment can generate and utilize a bypass signal, or a plurality of bypass signals in a number of different ways. Fig. 5 illustrates a part of the various combination units 304 and 404 of Figs. 3 and 4, respectively, according to a specific embodiment of the present invention. Therefore, the circuit of FIG. 5 may use the specific embodiment described in FIGS. 3 and 4, or any other specific embodiment as required. Note that if the circuit of FIG. 5 is used in the specific embodiment of FIG. 3, -19-This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 582141 A7 __B7 V. Description of the invention (~ 16) ^ ~ I Γ, Q 1 · and 12 ′, Q2 ′ can be regarded as the beneficial adjustment versions of the signal; however, since the gain circuit 400 is coupled downstream to the multiple combination unit 4O4, if the circuit of FIG. 5 is used in FIG. 4 In a specific embodiment, 1 ′, q ′, and 12 ′, Q2W are not regarded as a gain adjustment version of the signal. FIG. 5 includes demultiplexers (DEMUX) 500 and 504, a weighting factor determination circuit 502, multipliers 508, 510, 512, and 514, an adder 510, and a phase evaluation circuit 50o. The DEMUX 500 is coupled to the weighting factor determining circuit 502, the multiplier 508, and the multiplier 51 via wires 518 and 52. DEMUX 504 is coupled to weighting factor decision circuit 502, multiplier 51, and multiplier 514 via wires 522 and 524. The weighting factor determining circuit 502 supplies W1 to the multiplier 508 via the wire 526, and supplies W2 to the multiplier 512 via the wire 528. The phase evaluation circuit 506 is coupled to the multiplier 510 via the wires 530 and 532, and provides the phase correction 1 via the wire W8 and the phase correction 2 to the multiplier 5 12 via the wire 540. The multiplier is via the wire 542. And 544 are coupled to the multiplier 514. Adder 516 is coupled to multiplier 508 via leads 534 and 536, and to multiplier 514 via leads 546 and 548. The adder 516 provides the outputs I, Q via the wires 318 or 422, depending on the specific embodiment. DEMUX 500 receives I1 ', Q1' via wires 314 or 414, which depends on the specific embodiment, and DEMUX 504 receives 12, Q2, via wires 316 or 416, which depends on the specific embodiment. In operation, the DEMUX 500 receives II, Qr via the lead 314 or 202, which is determined by the specific embodiment, and outputs IΓ via the lead 520 and Q1 via the lead 5118. Note that II · is the real number part representing the complex signal -20-This paper size applies to China National Standard (CNS) A4 (210X297 mm) 582141

Divide 'and Q1' is the imaginary part of the complex signal. That is, qi is out of phase with Π, 90 degrees. Furthermore, DEMUX 504 receives 12 ', Q2 via the lead 316 or 204, which is determined by the specific embodiment, and outputs 12 via the lead 524, and Q2 via the lead 522. As mentioned above, 12 is the real part of the complex signal 12, Q2, and q2 is the imaginary part of the complex signal. (Note that each signal such as II, Q1, and 12, Q2, can be represented in a plural form such as 11, + j Q1, and ί 2, + j Q 2, respectively.) Ir, Qi ·, 12 ,, And Q2 are provided to the weighting factor determining circuit 502 to calculate the weighting factor based on, for example, the amplitude or power of each of the input signals Ir, Q1, and 12, Q2. This circuit will be further described in FIGS. 7 and 17. Therefore, the weighting factor determining circuit 502 can output W1 (the weighting factor of I1, Q1 ·) to the multiplier 528 via the wire 526, and output W2 (the weighting factor of I2 ', Q2 *) via the wire 508. Gives the multiplier 512. The weighting factor determining circuit 502 determines the weighting factors W1 and W2 according to the signal characteristics of at least one of π ′, Q1 ′ and 12, and Q2. Another specific embodiment may be based on the corresponding I Γ, Q Γ, and 12 ·, Q 2 · determine w 1 and W 2. The signal characteristic can be considered as the amplitude, power, or any other appropriate characteristic of the k signal. In addition, any combination of signal characteristics can be used to determine the weighting factors. The multiplier 510 may receive II ', Q1, and 12', Q2, and multiply II ,, Qi, and 12 ,, Q2 ,. This calculation can capture the phase difference information between the two signals and pass it to the phase evaluation circuit 506 via the wires 530 and 532. The phase evaluation circuit 506 calculates the phase difference between the signals IΓ, QT and 12 ', Q2' using I 1 ', q 1 as references. Then, the phase difference is output as a phase correction 1 to the multiplier 5 12 via the wire 538, and via the -21-this paper size applies the Chinese National Standard (CNS) A4 specification (21〇x 297 mm) 582141 A7 ___B7 V. Description of the invention 1 ~~ ^ Line 540 and output phase correction 2 to the multiplier 5 12. This phase difference is determined by W2 through the connector 528 and is supplied to the multiplier 514 through the wires 542 and 544. The multiplier 514 receives 12, Q2 'via the wires 522 and 524, and multiplies the result by the multiplier 512. Therefore, the output of 514 is supplied to the adder 516 via the wires 546 and 548. The multiplier 508 multiplies η ·, Q 1 'by W 1'. Thus, for example, the signal characteristics of the signal power and amplitude of the scale determining factor w 1 can be used. The result of the multiplier 508 is supplied to the adder 516 via the wires 534 and 536. Therefore, the final combined signals I, q can be provided via the wires 3 1 8 or 422, depending on the specific embodiment. The equations and calculations can be better understood with reference to the flowchart in FIG. FIG. 6 illustrates the operations of the various combined operation units 304 '404 of FIG. 5 according to a specific embodiment of the present invention. At blocks 602, n, Q1, and I2, Q2, can be received. At block 604, the weighting factors w! And W2 are determined based on at least the signal characteristics of at least one of the corresponding IΓ, Q1 'and 12', Q2 '. For example, in a specific embodiment, the power can be selected according to the signal characteristics used to determine wi and W2, where W1 is equal to or proportional to the square root value of n ,, 卩 丨, the power, and W2 is equal to or equal to 12 , Q2, the square root of the power is proportional. Wang Yi, in a specific embodiment, the power or amplitude is calculated according to the combined effect of the useful signal and the system noise, and does not attempt to influence the noise from the useful signal m. In the specific embodiment, the weighting factor The decision circuit 502 can evaluate the power (pl) m2, and Q2, of the power (P2), of which the weight and W2 = condition. Alternatively, choose an amplitude where they and 2 are amplitude functions of II Qi or 12, q2, or both. Therefore, in this specific embodiment, the weighting factor determining circuit 502 can evaluate n ,, -22-

582141 A7 B7 V. Description of the invention (19)

The amplitudes of Ql '(AMP1), and 12, and Q2, (AMP2). (The amplitude characteristics of the signal characteristics are further described in Figures 17 and 18 below.

Please refer to FIG. 6. At block 606, I Γ, Q Γ is a complex combination multiplied by 12 ,, Q2 ,. This can be performed through the multiplier 510. The calculation is expressed by the following equation: Equation 1: (Il, + jQl,) · (I2, -jQ2,) = IM + jQM In the above equation, the phase of the IM and QM signals is in the form of ej (ei ^ 2) = ejAe , Where ePi represents the phase of n, Q1, ^ 02 represents the phase of 12 ', Q2', and ejw represents the phase of n ,, Q1, and 12, Q2, and can be further expressed by the following formula : Equation 2: ejA0 = cos (A9) + jsin (A0) Therefore, at block 608, the phase difference ^^ can be evaluated, where the output of the phase evaluation circuit 506 of FIG. 5 is represented by two signals: Phase correction 1 indicated by A0) and phase correction 2 indicated by sin (Ae) (where phase correction ι is the real number part and phase correction 2 is the imaginary number part of the phase difference). At blocks 610, 12, and Q2, multiply the phase difference and W2 to obtain the result shown in Equation 3 below. (This calculation is performed by the multiplier 512). Equation 3: W2 · ejAe · (I2, + jQ2,) At block 612, II, and Q1, multiply by W1 to obtain the result shown in Equation 4 below. (This calculation is performed by the multiplier 508). Equation 4 ·· W1 · (Il, + jQi,) Therefore, in Equations 3 and 4, the comments 丨 and ~ 2 are used as weighting factors for each corresponding signal II ', Qi, *! 2, Q2, respectively. , Where “丨 and bound 2 are based on signal characteristics such as power or amplitude.

Binding

Line -23-

582141 A7 ____B7 _ _ ^, invention description (20) '' and the combination of 612 results can obtain the final combined signal i, Q (can be expressed by the formula of i + jQ). This final calculation can be performed by the adder 5 6, where the adder 516 provides the outputs I, Q through the wires 318 or 422, which depends on the specific embodiment of the channel processing unit 206. Therefore, the equation can be expressed as follows: Equation 5: I + jQ = W2 · ejA0 · (I2, + jQ2,) + Wl · (ir + jQr) Please refer to Equation 5 above, the first term of the equation W2 · ejAe · (12, + jQ2 ·) represents the phase difference between the phases of 12 ′, Q2 ′ between II, Q1, and 12, Q2, and the weight is W 2. The second term of the equation W 1 · (11, + jQ 1 ′) represents I Γ, Q Γ is weighted by its weighting factor W 1. In another specific embodiment, no weighting factor is used. Therefore, Equation 5 will not include the two weighting factors W1 and W2, and the multiple combination unit will not include the weighting factor decision circuit 502, or the multipliers 508 and 512. Alternatively, other weighting factors besides signal power or amplitude can be used as needed. FIG. 7 is a specific embodiment of a part of the weighting factor determining circuit 502 of FIG. 5. The circuit is described with reference to inputs II 'and Q1', where the same descriptions and circuits apply to inputs 12 ', Q 2'. Also note that in another specific embodiment, the circuit for receiving 11 ′ and Q Γ can be given to 12 ′ and q 2 in a time-division multiplexing manner, shared, or the entire circuit (or part thereof) may be as shown in FIG. 7 Mentioned replication. In the concrete example described, a part of the weighting factor decision circuit 502 corresponding to I Γ, Q 1 'can operate in the same manner as a part of the diagonal response 斜 2', Q 2. Generally, the weighting factor determining circuit 502 includes a signal characteristic value determining circuit and a weighting value determining circuit. The former can calculate, for example, the signal characteristic value 'of the power or amplitude of each signal, and the latter can use the signal characteristic values to calculate W 1 and W 2. Regarding the inputs II 'and Q1', the weighting factor determining circuit 502 includes a guide -24-the paper size is suitable & SS home standard (CNS) A4 specification (21GX 297 public love) " " 582141 A7 B7 ' ------- 5. Description of the invention () Line 5 18 receives a multiplier 700 of IΓ, and 1 / N via line 746. The multiplier 702 is coupled to receive q1 through the wire 52, and is turned 1 / N through the line 746. The multiplier 700 is coupled to the adder 704, and the adder is coupled to the delay unit 708 and the storage circuit 712. The multiplier 702 is coupled to an adder 706 ', and the adder 706 is a combination of a delay unit 714 and a storage circuit 718. The adder 720 is coupled to the storage circuits 712 and 71, the inverse square root unit 722, and the multiplier 724. Therefore, the adder 720 supplies the power ρ 1 of I 1, Q 1, to the inverse square rooting unit 722 and the multiplier 724. The reciprocal square root unit 722 is coupled to the multiplier 724, and the multiplier 724 is supplied to the output W1 via the lead 526. With regard to the inputs 12 ', q2, the weighting factor determining circuit 5 includes: multipliers 750, 752, and 770; adders 754, 760, and 766; delay units 756 and 762; storage circuits 758 and 764; and inverse numbers The square root unit 768 ′ is the same as the multipliers 700, 702, and 72, the adders 704, 706, and 720, the delay units 708 and 714, the storage circuits 712 and 71, and the inverse square root unit 722, respectively. "Light-on" Therefore, as shown in FIG. 7, the signal characteristic value determination circuit 78o includes a circuit between the multipliers 700, 702, 750, and 752 and the adders 72o and 766. The weight determination circuit 782 includes multipliers 724 and 770 and inverse square root units 722 and 768. Operationally, the output of the multiplier 700 is to provide the value Qr2 / N to the adder 704 ', where N is the number of samples or self-frame size used to collect the input signal value over time. Similarly, the output of the multiplier 702 may provide the value q | >> 2 / n to the adder 706. The adder 704 and the delay unit 708 function as the same accumulator 'to accumulate the value of 11'2 / N over time. The delay unit 708 receives the reset signal 710 'and resets it according to the sampling frequency fraction fs / n of Ir, q !, -25-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 582141 A7 _____B7 V. Description of the invention (22). Delay unit 708. Before resetting the delay unit 708, the storage circuit 712 stores a class product value and supplies this value to the adder 72. Similarly, the adder 706 functions as the same accumulator as the delay unit 714 to accumulate the value of QP2 / N over time. The delay unit 714 may receive the reset signal 716 so that

Fs / N and the delay unit 714 is reset. Before resetting the delay unit 714 <, the storage circuit 7118 may store the accumulated value and provide the value to the adder 720. Therefore, the reset signals 71 and 716 usually use the same rate corresponding to Fs / N; similarly, the storage circuits 712 and 718 are timed at the same rate corresponding to the reset signals 710 and 716, so that the accumulated value can be supplemented over time. . Therefore, N can be adjusted appropriately in order to change the window frame size of the accumulated value (that is, the number of samples used). The adder 720 combines the I i, 2 / n accumulation value from the storage circuit 712 and the Ql, 2 / N accumulation value from the storage circuit 718 to obtain pi: Equation 6: pl = Y (^ 7 * + ^ — ) = / 1,2 + β1,2 ν ν Ν Ν In the above equation 6, j is a discontinuous sampling value related to Fs. Therefore, the value of Pi is calculated per Fs / N. This result pi is supplied to the multiplier 724 and the inverse square root unit 722. The result of the inverse square root unit 722 is shown in Equation 7 below. "The inverse square root unit 722 can be implemented in a variety of different ways, such as a hardware circuit that performs calculations, a state machine embedded in memory, a software routine, and so on. Equation 7: J__ 1 A® Α4 specification (21〇 × 297 public love) ____—-26-582141 A7

this,. The result is provided to the multiplier 724, which can multiply the output of the adder 720 (equation 6) by the output of the reciprocal square root unit 722 (equation) to obtain the output W 1 'The equation is as follows: Equation 10: Phase = Equation (Equation 6-8) applies to 12, and Q2, where each occurrence of II ′ is replaced by 12 ′, each occurrence of Qi ′ can be replaced by Q2, and each occurrence of pi can be replaced by p2. Therefore, W2 can be expressed as: Equation 9: = Therefore, Equation 6-9 describes a calculation example used to obtain an input signal power. Another embodiment may be implemented using circuitry or software different from the embodiment described in FIG. FIG. 17 illustrates another embodiment of the weighting factor determining circuit 502 using amplitudes to determine wr and W2. Therefore, FIG. 17 may be used instead of FIG. 7 of the weighting factor determining circuit 502, which is determined by the specific embodiment used (for example, whether power or amplitude is used as a signal characteristic). FIG. 17 includes a signal characteristic value determination circuit 1716, and the signal characteristic value determination circuit includes an amplitude determination circuit 1700 and an amplitude determination circuit 1702. The amplitude determination circuit 1700 receives IΓ and Q1 via wires 518 and 520, respectively, and the amplitude determination circuit 1702 receives 12 'and Q 2' via wires 522 and 524, respectively. The amplitude determination circuit 1700 is to provide AMP1 to the multiply accumulate circuit 1708, and the amplitude determination circuit is -27.-This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 582141 A7 B7 V. Description of the invention (~ 24) ~ The way 1702 is to provide AMP2 to the multiply accumulate circuit 1708. The control circuit 170 and the shift circuit 1710 are bidirectionally coupled to the multiply-accumulate circuit 170. The multiply-accumulate circuit 1708 provides Wi via a wire 1712 and W2 via a wire 1714. Therefore, the weight value determination circuit 1718 includes a control circuit 1704, a multiply-accumulate circuit 1708, and a shift circuit 1710. In operation, the amplitude determination circuit 1700 receives π, and Q1, and outputs the amplitude AMP1 of the signal. Amplitude can be calculated using standard methods currently available, for example, by using the sum of square roots of the II, 2 and Ql, 2 signals. Moreover, the amplitude determination circuit 1702 can receive 12, and q2, and the amplitude AMP2 of the output signal. This amplitude can be calculated in the same way as before. As described in FIG. 18 below, the multiply-accumulate circuit 1708 can receive AMP1 and AMP2 and generate weighting factors W1 and W2. The multiply accumulate circuit 1708 also includes a storage circuit for storing any needed temporary values. The control circuit 1704 and the shift circuit 1710 can provide and receive signals back and forth between the multiply-accumulate circuit 1708. The control circuit 1704, the multiply-accumulate circuit 1708, and the shift circuit 1710 may implement a part of the state machine to perform the calculations discussed in FIG. Fig. 18 is a flow chart describing a specific embodiment for calculating W 1 and W 2 based on the amplitudes of 11 ', q 丨' and 12 ', Q2 ,. Flowchart 800 starts at block 1802, where Ir, Q1, and 12, and q2 can be received. The process will execute a judgment diamond 1804, which can determine whether the amplitude of n, Q1, is greater than the amplitude AMP2 of 12 ', Q2 ,. If so, the process will continue to execute block 1813, of which AMP1 and AMP2 It is a selective ratio decision. Then the process will continue to execute blocks 丨 8 丨 4, where w 1 is set to a predetermined value. The predetermined number indicates a preset value for trade. Therefore, in a specific embodiment -28-i Paper size is suitable for wealth country @ 家 standard (CNS) A4 specification (21GX297 public love) 582141 A7 _____B7 _ V. Description of the invention (25) In the embodiment, the predetermined value is less than or equal to 0.5. By using a predetermined value less than or equal to 0.5 The value can ensure that the amplitude of the last combined signal (that is, 11, 11, Q 丨, combined with 12 ', Q21) does not exceed the value 1. Then, the flow continues to execute block 1816' where the inverse amplitude 丨 / AMPl can be determined. This can be determined by Performed using standard techniques such as a look-up table. At block 1818, the calculation of W2 is half the ratio of AMP2 to AMP1 (refer to Equation 1 above). Note that 0.5 described in this equation is the predetermined value described above; therefore, if a different If it is selected, for example, 0.4, then 0.5 will be replaced by 0.4. In the judgment block 1804, if AMP1 is not greater than AMP2, the process will execute block 1805, where AMP1 and AMP2 are determined by the selectivity ratio. The process will execute block 1806, W2 is set to a predetermined value that is usually less than 0.5 ', for example, 0.5. This predetermined value is as described in block 1814 above. The process then continues to block 1808, where the amplitude reciprocal 1 / A MP2 can be determined. As previously described' this may It is performed using standard techniques such as a look-up table. At blocks 1 8 10, W1 is calculated as half the ratio of AMP1 to AMP2 (refer to Equation 2 above). Also note that 0.5 described in this equation is Box 18 above. The predetermined value discussed in 6; therefore, if a different value is selected, this different value will be replaced by 0.5. Therefore, another specific embodiment may use other ratios between AMP1 and AMP2 to determine W1 and W2. Another specific embodiment is to use a proportionality factor (such as AMP 1 and A) before performing calculations to determine weighting factors such as W 1 and W 2 (for example, refer to the selectivity blocks 1805 and 1813). MP2) is determined by the ratio. However, the ratio is determined by the option; or it can be set to 1. Therefore, the weighting factor may be expressed as follows: If AMP1 > AMP2: -29-This paper standard applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 582141 A7 B7 V. Description of the invention (26) Equation 10a: Wl = 0.5 Equation 11a: W2 = AMP2 · 0.5 · 1 AMP \ If AMP1 < AMP2: Equation 10b: W2 = 0.5 Equation 1 lb: W 1 = AMP1 · 0.5 · 1 AMP2 Note that the weighting factors such as W1 and W2 are a function of each signal or any combination of signals. Moreover, besides these, many different weighting factors can be used. For example, of the systems available at this stage, only the signal-to-noise (SNR) ratio is used as a weighting factor. However, using the SNR method is expensive from a circuit point of view, which increases the price of the system. In addition, the weighting factors in these systems using the SNR method are complex numbers (that is, they depend on the phase of the signal). However, the specific embodiment of the present invention does not use snr to determine the weighting factors, but uses other signal characteristics such as amplitude and power to achieve an effective solution with more cost. Moreover, the weighting factor discussed here (wi * W2) is a quantitative factor. That is, they are independent of phase. They can be phase independent because a phase calculation or evaluation is performed individually and is used with a quantity weighting factor to combine the input signals and will be explained in more detail below. As mentioned above, another specific embodiment includes only more than two input signals; therefore, it has more than two weighting factors and is also dependent on one or more signal characteristics. In some embodiments, these weighting factors are also selective. For example, only some input signals can use weighting factors. Fig. 8 illustrates a part of the multiplier 51 and a part of the phase evaluation circuit 506. The multiplier 510 includes a multiplier 800 and a multiplier 802 coupled to the adder 804, and the adder 804 is coupled to the multiplier 812. The multiplier 51 is further advanced by -30-

A7 B7 V. Description of the invention (27), the multiplier _ and multiplier _ coupled to the adder 810, and the addition is coupled to the multiplier ⑴. The multiplier 812 is coupled to the multiplier 14 and the adder 816, and receives the input 1 / N and the gain. The adder ㈣ 2 is coupled to the delay unit 82G and the storage circuit m, and the multiplier 814 is not an adder 818, and the adder 818 is coupled to the delay unit 822 and the storage circuit 826. The storage circuit S24 is coupled to the multiplier 828, and the storage circuit 826 is coupled to the multiplier 83. Multipliers 828 and 83 are provided as inputs to an adder 832, and the adder 832 is coupled to an inverse square root unit 834. Storage circuits 824 and 826 are coupled to multipliers 836 and 838 and inverse square root units. The multiplier 836 provides a representative output of cos (Ae) via a wire 538, and the multiplier 838 provides a representative output of 3? (ΔΘ) via a wire 54. In operation, the multipliers 800, 802, 806, and 808 and the adders 804 and 810 perform calculations corresponding to π '., Q 丨, multiplied by 12 ,, q2 • complex. (Reference Equation 3) Therefore, the output of the adder 804 is the real part IM of the calculation result, and the output of the adder 810 is the imaginary part of the calculation result. The phase evaluation circuit 506 receives IM and QM, and the calculation corresponds to Equation 4 above. The phase in question can be calculated in terms of iM + jQM. Here, the phase system represents the phase difference between I Γ, Q 1, and 12, and Q2, and I Γ and Q 1 are used as a reference signal. The multiplier 812 receives the IM and multiplies this combination by 1 / N and the gain 801 to supply it to the adder 816. In a specific embodiment, the gain 801 is the reciprocal of the larger amplitude of AMP1 and AMP2 (for example, if AMP2 > AMP1, the gain 801 can be set to 1 / AMP2). Gain 801 energy-31-This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 582141 A7 ____ B7________ V. Description of the invention (28) Help Wit larger signal as far as possible 丨 丨, Q 丨, , While still guaranteeing that the calculations do not exceed the number system chosen for the design. (Therefore, note that the QM and IM used in Figure 8 can now be regarded as gain adjustment values adjusted by the gain 801. Also note that the gain 801 is selective or can be set to 丨). The functions of the adder 8, 6, the delay unit 820, and the storage circuit 824 are to accumulate the value of I μ on a time window frame. Furthermore, as described above, N is the number of samples or window frame size used to collect the IM value. As long as the sampling frequency fraction FS / n is reached, the delay unit 820 and the storage circuit 824 can be reset, where F s is the sampling frequency corresponding to the input signal (eg, I Γ, Q 1,). That is, each time a sufficient amount of data 'value determined by Fs and N is used, it can be stored in the storage circuit 824. Therefore, the multiplier 828 can receive the accumulated value of IM / N from the storage circuit 824. The same analysis is suitable for qM. That is, the 'multiplier 814 receives the QM, multiplies it by 1 / N and the gain 801, and supplies the output to the adder 818. The functions of the adder 818, the delay unit 822, and the storage circuit 826 are similar to an accumulator, so that the value of QM / N is accumulated over a period of time. The number of samples is determined by fs and N. That is, at each n-th sample (related to the sampling frequency Fs), the value in the storage circuit 826 can be supplied to the multiplier 830. Therefore, the output of the ^ multiplier 828 is represented by ^ 5, and the output of the multiplier 830 is represented by ^. (Note that & and ^ are treated as the average of IM2 and QM2 over a defined time period). These are provided to the adder 832, and the results may be provided to the inverse square unit 834. The inverse square root unit 834 can calculate the inverse square root unit as shown in Equation 12: Equation 12: -32-

582141

This result is provided to the multipliers 836 and 838. The multiplier 836 also receives two from the storage circuit 824, and the multiplier 838 receives from the storage circuit 826 ^. In this way, the results of the multipliers 836 and 838 as shown in the following equations 3 and 14 indicate the phase difference between Γ, Q1, and 12, Q2, and ^, Q1 are used as reference signals. Equation 13: —_1 [一》 im2 + qm2

QM Equation 14: In the above equation, Equation 13 corresponds to the output cos (Ae), and Equation 14 corresponds to the output "η (ΔΘ), where C0S (Ae) + jsin (Ae) represents the phase difference. (Refer to Equation 4 above) ^ Figure 9 describes the implementation of multipliers 508, 512, and 514 and adder 516 of Figure 5. Figure 9 includes multipliers 922, 902, 904, 912, 914, 908, 918, and 924. Figure 9 Also included are adders 906, 910, 916, and 920. Multiplier 922 receives II as input, and W1, and supplies the output to adder 910. Multiplier 902 receives 12, and phase corrects 1, and adds Its output is provided to the adder 906. The multiplier 904 receives Q2, with a phase correction of 2 'and supplies its output negative bit to the adder 906. The result of the adder 906 is provided to the multiplier. 9〇8, and also receives W2 as an input. The result of the multiplier 908 is provided to the adder 91, and the output of the multiplier 922 is also received. Provided by I, -33-This paper is compliant with the Financial Standards for Family Care (CNS). 1 () χ297 公 爱) 582141

This depends on the specific implementation. Further, the multiplier 924 receives 卩, and wi, and supplies an output to the adder 92. The multiplier 912 receives 12 and the phase correction 2 and supplies its output to the adder 910. The multiplier 914 receives Q2 'and the phase correction 1 and supplies it to the adder 916. The adder 916 supplies its output to the multiplier 918, receives W2 as an input, and supplies the output of the dagger to the adder 92. The adder 92 is provided as its output Q via a wire 318 or 422, which is also determined by the specific embodiment. Therefore, the circuit of FIG. 9 is representing Equation 7 above. FIG. 8 illustrates another specific embodiment of the various combination units 304 and 404, that is, the circuit of FIG. 10 can be exchanged with the circuit of FIG. 5. In the specific embodiment of FIG. 10, 'various combination units 304 and 404 include demultiplexers (DEMUXs) 100 * 1002, and are coupled to the signal characteristic value evaluation circuit 1004 and multiplexer 1006; and multiplication器 1〇12. The signal characteristic value evaluation circuit 1004 is coupled to 1006 through a wire 1028. The multiplier 1012 is coupled to the phase lock loop and the lock detection circuit 1008, and the phase lock loop and the lock detection circuit 1008 are coupled to the multiplier 1018. dEmuX 1002 is also coupled to multiplier 1018, and multiplier 1018 is coupled to adder 1014. The adder 1014 is coupled to a demultiplexer 1000 and a multiplexer 1010. The phase-locked loop and the lock detection circuit 1008 are also coupled to the multiplexer 1010 via the wire 1046. The multiplexer 1010 provides outputs I and q via wires 318 or 422 corresponding to Figs. 3 or 4, respectively. Each of DEMUX 100, DEMUX 1002, signal power evaluation circuit 1004, Μχχ 1006, and the phase lock loop and lock detection circuit 1008 receives a control signal via a wire 138. Lead wire 1028 can be a part of lead wire 138, or through letter-34-This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 582141 A7 B7 V. Description of the invention (31) No. characteristic value evaluation circuit 1 004 directly provide. In operation, the DEMUX 1000 receives signals II ·, Q1, and provides II 'via a wire 1020, and ⑴ via a wire 1022. Further, dEmuX 1002 receives I2 ', Q2', and provides 12 via a lead 1024, and Q2 'via a lead 1026. (Further, note that when the specific embodiment of FIG. 3 is used, 'I Γ, Q 1' and 12 ', Q2' can be gain adjusted, but if the specific embodiment of FIG. 4 is used, gain adjustment is still not performed.) Signal characteristic value The evaluation circuit 1004 receives II, Q1 ', 12, and Q2, and evaluates a signal characteristic value of lr, Q1, and 12, Q2, in order to determine a stronger signal. For example, the signal characteristic value evaluation circuit 1004 may evaluate the power or amplitude of each signal, and determine a stronger signal based on the power, amplitude, or both. Note that in another embodiment, other signal characteristics or other methods can be used to determine the stronger signal. The No. characteristic value evaluation circuit 1004 outputs a control signal to the multiplexer 1006 via the wire 1028. In order to select a stronger signal from the two signals output to the multiplexer 1010 via the wires 1030 and 1032. The multiplier 1012 receives II, Qr, and 12, and Q2, and calculates phase information by combining n, Q1, and a complex number multiplied by 12 'and Q2'. The calculation result is expressed in terms of jQM and provided to the phase-locked loop and lock detection circuit through a wire delete and filter. The bit-locked loop and lock detection circuit 1008 is used to evaluate the values in Ir, Q1, and 12, , Q2, and the phase difference between them, and output to the multiplier 1018 via the wire 1038 as a phase correction! And output as phase correction 2 via the lead 104G. If the phase-locked loop is locked, I2, and Q2 will be multiplied by the phase difference of the result. In order to delete I2 ,, Q2, and n, and Ql by the adder, appropriately decompose a ,, and • 35 -

582141 袄 7

shift. Therefore, the output of the adder 1014 is representative of the combined signals J 丨, 'Q 丨 · and the phase shifts 12, Q2. Moreover, if the phase lock loop is locked, a control signal will be provided to the MUX 1010. In order to select the output of the adder 1014, which is the output of Q, instead of the output of MUX 1006, and only indicates 11, Q Γ, and 12 Strong signal of ', 〇2'. However, if the phase-locked loop circuit 1008 cannot be locked, a control signal is output to the MUX 1010 via the wire 1046 to select the signals transmitted by the wires 1030 and 1032, and via the wire 3 18 Or 422 and provided as outputs I, Q. Therefore, the specific embodiment of the various combination units described in FIG. 10 is an attempt to evaluate the phase difference and offset 12 ,, q2 ,. However, if the phase-locked loop is not locked in the correct phase, then the signal power evaluation circuit 1004 can provide a stronger signal as the two signals of Q and Q. Therefore, Fig. 10 can be regarded as a hybrid phase locked loop (PLL) system. When combining signals in the adder 104, another specific embodiment is to use the signal characteristics (such as amplitude, power, etc.) of each signal as a weighting factor. As discussed in Figure 5, for example, n ·, Q1 can be weighted by its related power, while 12, Q2 can be weighted by its related power. Other embodiments may even use different weighting factors in addition to depending on signal characteristics. The operation of FIG. 10 can be better understood with reference to FIG. Fig. 11 is a flowchart describing a specific embodiment of the operation of the various combination units 3, 404 of Fig. 10. At blocks 1102, II, (1), and 12, Q2, are received. At block 1104, a signal characteristic value (for example, power or amplitude) of each signal can be evaluated (which can be performed through the signal characteristic value evaluation circuit 1004), and a stronger signal can be selected. At block 11 〇6,11, and q 丨 • is a complex combination of multiplying by I2 *, Q2 * to obtain IM + jQM (refer to the above equation -36-this paper size applies Chinese National Standard (CNS) A4 specifications ( 210 X 297 mm)

Binding

582141 A7

3). At 10000, the phase difference ^ ΔΘ between n, Q1 •, 12, and Q2, can be evaluated, where the phase difference is expressed as cosUe) + jsin (Ae). This can be performed through the phase lock loop and the lock detection circuit 1008 to output a phase correction 1 (indicated by cos (Ae)) via the wire 1038 and a phase correction 2 (sinUe) to be output via the wire 1040. ). In block 111, if the phase lock circuit is locked with the phase lock circuit of the lock detection circuit 1008, the lock control signal can be confirmed. (The operation of the phase lock loop and lock detection circuit ι 08 will be discussed further with reference to Figure 12 below). The weighting factor determining circuit 502 described in FIG. 5 is described above. In block 1115, the weighting values of n, Q1, and 12, Q2, may be determined. However, block 1115 is optional, and the specific embodiment described with reference to Figures 10 and 11 assumes that no weighting factor is used for the signal combination. At block 1116, if the lock control signal is confirmed, the signals 12, and Q2 can be multiplied by the phase difference calculated at block 1108, as shown in the following equation (see also block n 12). TF · Equation 15: ejA0 · (I2f + jQ2f) In block 1114, if the lock control signal is confirmed, the result of block 丨 丨 12 is combined with 11 'and Q Γ to obtain I and Q, as shown in the following equation: Equation 16: l4-jQ = ejAe • (I2i + jQ2 ») + (Ir + jQ1,) at block 111 8 'If the lock control signal is not confirmed, this indicates that the phase lock loop is not locked. The stronger of the signals II ,, Q1, and 12, and Q2, can be provided by Qi ^ . (Note that equations 15 and 16 are similar to equations 5 and 7 except that there are no weighting factors in Fangfangwang 15 and 16. However, as discussed in Figure 10 and selection box 1115 above, weighting factors can be used u ·, Q1 · are combined with 12 *, Q2 ', similar to blocks 610, 612, and 614 in Figure 6.) -37-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 582141 A7

FIG. 12 illustrates a specific embodiment of the signal characteristic value evaluation circuit 1004, and the signal characteristic value evaluation circuit 1004 uses each signal power to determine the stronger # number. The signal characteristic value evaluation circuit of FIG. 12 includes: a multiplier 1200, which is coupled to the multiplier 1204; and a multiplier 120, which is coupled to the multiplier 1206. The multipliers 1204 and 1206 are coupled to the adder 1208. The adder 1208 is coupled to the delay unit 121 and the storage circuit 1212. The storage circuit 1212 is coupled to the adder 1214, and the adder 1214 is coupled to the selector unit 1216. The multiplier 1228 is coupled to the multiplier 1224, and the multiplier 1230 is coupled to the multiplier 1226. Multipliers 1224 and 1226 are coupled to an adder 1222. The adder 1222 is coupled to the delay unit 1220 and the storage circuit 1218. The storage circuit 121 is connected to the adder 1214 by an 8-series crane. The selector unit 1216 疋 provides a control signal to the multiplexer via the wire 1028. Operationally, the 'multiplier 1200 receives π' and i / N, so that n, / N is supplied to the multiplier 1204 to calculate a square value (Ii, / N) 2 and the result is supplied to the adder 1208. Furthermore, the multiplier 1202 receives Q1, and 1 / N, so that Ql '/ N is supplied to the multiplier 1206 to calculate the square of the result, so that (Q17N) 2 is supplied to the adder 1208. The adder 12〇8 supplies the result (11, / > 〇2 + ((^ 1, / > 〇2) to the storage circuit 1212 and the delay unit 121. The adder 1208, the delay unit 1210, and the storage circuit 12 〇2 is the value of (I1, / N) 2+ (Q1, / N) 2 accumulated over a period of time. In addition, this period of time is determined by the sampling frequency of the corresponding input signals I Γ, Q Γ ^ N again reference The number of samples used (that is, the size of the window frame). As long as the appropriate sample size is used, the storage circuit ^^ can provide the result ^ + 给 to the adder ^^ where the sum and ^ are in a period of time is II · 2 The average of Q1'2. The same, the same -38-This paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) 582141

Calculations can be performed at 12 ', Q2'. Furthermore, the 'circuit may be repeated at i2 ,, Q2' as shown in Fig. I2, or the circuit corresponding to IΓ, Q1, may be shared by two signals II ', Q1 * and 12', Q2 '. Therefore, the accumulated value ^^, the operation of the delay unit 1220, and the storage circuit 1218 can be accumulated in the time window frame (12 / N) + (Q2 / N), where the predetermined time window frame is transmitted through U Therefore, the sampling frequency is determined to be two. Therefore, the result of the addition is + / 2'2 ++, 2, where 0 and & are the average values of I2 * 2 and Q2,2 on the predetermined time window frame, respectively. Note that each of the values p + p corresponds to the power of the relative signals Π ,, Q1, and 12, Q2. The results from the storage circuits 1212 and 1218 are provided to the adder 1214, and the adder 1214 supplies the difference between the two result values p + p and p + p to the selector unit 1216. The selector unit 1216 can determine which signal II ', Q1' or I2 ', Q2' is stronger and output a control signal via the wire 1028. If II 'and Q1 are stronger signals, the control signal output via the wire 1028 allows the MUX 1026 to select II, Q1 to transmit to the wires 1030 and 1032 and to MUX 1010. However, if the selector unit 1216 selects the stronger k number 12, Q2 ', then] V1UX 1006 can output 12', Q2 to MUX 1010 via wires 1030 and 1032. Therefore, the selector unit 1216 can decide which number has greater power. For example, if the value supplied to the selector unit 1216 from the adders 12 to 14 is greater than 0, this means that the power of II, Qi, is greater than I2f, Q2 ,. However, if the difference is less than 0 (that is, a negative value), this means that the power of 12 ', Q 2 · is greater than n, Q1, so the selector unit 1216 can output a control signal. Figure 13 is a description of a part of the multiplier according to a specific embodiment of the present invention-39-This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 582141 A7 _ B7 V. Description of the invention (36) 1 012 and a part Phase-locked loop and lock detection circuit〗 008. The multiplier 1012 includes multipliers 1300, 1302, 1306, and 1310, and adders 1304 and 1308. The multiplier 1300 receives IΓ and 12 ·, and the multiplier 1302 receives Q1 'and Q2 ,. The results of the multipliers 1300 and 130 are provided to the adder 1304, and the output is provided to the phase-locked loop and lock detection circuit 1008 via the wire 1034. Moreover, the multiplier 1306 receives the inputs 12, and Q1 ' And, the multiplier 131 is receiving the inputs Q2, and π. The multipliers 1306 and 1310 provide their output to the adder 130, to calculate the difference between the two values, and provide the result to the phase lock loop and lock detection circuit 1008 via the wire 1036. Therefore, in operation, the multiplier 1012 is the output I Γ, Q Γ is multiplied by 12, and Q2 in the form of IM + jQM, where IM refers to the transmission of the real part via the wire 1034, and QM refers to Imaginary part conducted via wire 1036. (Refer to Equation 3 above). The phase lock loop and lock detection circuit 1008 includes: a multiplier 1 3 14 which is coupled to the adder 1312; and a multiplier 1320 which is coupled to the adder 1322. The adder 1312 is also coupled to the multiplier 1316 and the lock detector 1324. Adder 1322 is also coupled to multiplier 1318 and multiplier 1328. Gain adjuster 1326 is coupled to the output of lock detector 1324, and provides an input to multiplier 1328. Multiplier 1328 is coupled to delay unit 1330 and delay unit 1330 is coupled to adder 1334. The adder 1334 is coupled to the calculation circuit 1336 and the delay unit 1332. The delay unit can provide the feedback value to the adder U34. The calculation circuit η% outputs a phase correction through the lead wire 103_8 and a phase correction through the lead wire 1040]. The coupling of the juice calculation circuit 1336 also provides the input to the multipliers i32〇, i3i8, -40-

582141

1316, and 1314. On the twist, the phase-locked loop and the lock detection circuit include a phase-locked loop (PLL) section to evaluate the phase difference of the input signal IM + jQM. This is performed by using a phase-locked loop, and the phase-locked loop is implemented through a gain adjuster 1326, a multiplier 1328, a delay unit 133, an adder U34, a delay unit ^ 32, and a calculation circuit 1336. The phase-locked loop starts with an initial value of ΔΘ, and the initial value is an input calculation circuit 1336, where Θ, represents the phase value of the PLL. For example, the initial value can be 0. During the repetition of the PLL, Δθ can be adjusted until the PLL locks up in a phase value. When Δθ is approximately equal to Δ θ of the pair, the PLL is locked. As discussed further below, the lock detector 1324 can determine whether the PLL is locked. The calculation circuit 1336 may receive the value Δθ, and provide the results of the cosine and sine calculations to the multipliers 1320, 1318, 1316, and 1314. Multipliers 1314, 1316, 1320, and 1318 and adders 1312 and 1322 are calculated by multiplying the input signal IM + jQM by PLL, ΔΘ, and the complex phase of the resulting phase can be expressed as e-jAG •, where: Equation 17: e 'jAe, = cos (Aef)-jsin (AG') is shown in Equation 4 'The phase of IM + jQM is represented by ^ Λθ. Therefore, the calculation result can be expressed as follows: Fang Kao Wang 18 · ejA0 · e'jA0 = ej (A0'A0) = cos (A0-A0,) + jsin (A0-Ae,) is output in adder 13 12 The lead 134 on the line is to provide the real part of the calculation result (005 (ΔΘ-ΑΘ,) to the lock detector 1324, and the adder 1322 is to provide the imaginary part sin (A0-ΔΘ ') of the calculation result. Multiplier 1328 ^ such as -41-This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 582141 A7 _______B7 V. Description of the invention (38) If the lock detector 1324 decides that the PLL is not locked (ie Is A Θ, not quite close to Δ Θ) 'then the gain adjuster 1326 can adjust the imaginary part of the signal from 1322 via the multiplier 1328, and an updated ㊀ can be calculated. The updated Δ θ ′ is provided to the calculation circuit 1336, and the calculation circuit 1336 is provided to the multipliers 1314, 1316, 1318, and 132 to the cosine and sine of Δθ, in order to combine the complex numbers of Δθ, again Multiply the input signal ιμ + jQM. This iterative process is continued until the real part of the calculation result provided by the adder 1312 to the locked debt detector 1324 determines that Δ Θ * which can be provided in a predetermined range from Aθ. When ΔΘ * approximates ΔΘ, since the real part of the calculation result is expressed as (^ (△ Θ-ΔΘ '), so when 003 (〇) = 1, the cosine calculation result will be approximately 1. If the detector 1324 is locked It is determined that the input signal exceeds the lock threshold 1338 (that is, ΑΘ, which is quite close to ΑΘ). A lock signal is provided to MUX 1010 via wire 1046 to allow the combined output of I and Q via wires 1042 and 1044. Moreover, as long as the lock detection The tester confirms the lock signal via the lead 1046. This lock signal can also be provided to the gain adjuster 1326, in order to select a smaller gain value for greater stability of the PLL. That is, as long as Pll is locked, a smaller gain is A more stable system can be provided. FIG. 14 illustrates a specific embodiment of the lock detector 1324 of FIG. 13. The real part of the calculation result discussed in FIG. 13 is provided to the lock detector 1324 via the wire 1340 as The input of the low-pass filter 1400. The low-pass filter can remove the noise term of the high-frequency components of the input signal. The output of the low-pass filter 丨 400 is provided to the adder 1402, and the adder 1402 also receives the lock threshold 1338. Add The implement 1402 is to find the difference between the filtered input from the filter 1400 and the lock threshold 1338, and the result is provided to the lock judgment -42-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 5%) 582141 A7 _ _B7 V. Description of the invention (39) Disconnect the circuit 1404 to provide the output lock signal to the MUX 1010 via the wire 1046. The lock judgment circuit 1404 can determine whether the difference on the output of the adder 1402 is greater than 0 or less than 〇 to determine whether the input signal is greater than or less than the lock threshold 1338. If the input of the lock judgment circuit is a positive signal, the lock judgment circuit can confirm the lock signal 1046. In order to select the wires 1042 and 1044, it is provided as an output on the MUX 1010 as Combined signal of I and q. However, if the lock judgment circuit 1404 determines that the output of the adder 1402 is a negative signal, the lock signal 1046 is not confirmed. In this way, the output of MUX 1006 can be selected so that The MUX 1010 output provides signals as I and Q. Fig. 15 illustrates a specific embodiment of the space-time unit 302 of Fig. 3. The space-time unit 302 is via a wire 31. 4 and 3 16 and various combinations of the input signals j 丨, q 丨, and Ϊ2, Q2, and the reply for the result break is cancelled. The space-time unit 3 〇2 is the Shiba combination for the input number And the time domain of the resulting signal. The time domain part is also called the equalizer part that performs reply cancellation. (This equalizer part is also called the appropriate filter 1530 'Including efficiency measure and error signal generator 522, multipliers 1512, 1514 , And 1516, adder 1520, shunt updater 1518, and delays 1506, 1508, and 1510. ) The input signals n,, and 12, Q2 疋 are combined with the adder 1504 via multipliers 1500 and 1502. IΓ, Q1 'are weighted by a weighting factor W1, and this weighting factor ... is input from the weighting updater 1524 to the multiplier 1500. Moreover, 12, and q2 are weighted by the weighting factor W2 by the multiplier 1502, and w2 is also provided by the weighting updater 1524. Therefore, the weighted result is provided to the adder 1504 to generate a combined weighted signal, which is then provided to the delay unit 1506 and the multiplier -43-This paper standard applies the Chinese National Standard (CNS) A4 specification (210 X 297 (Mm) 582141 V. Description of the invention (40) m2. W1 and W2 represent complex numbers. The output of the adder 1504 is passed via the delay units 1506, 1508, and 1510. The output of the adder 1504, for example = 06, 1508, and 1510 each delay cell output is provided to the corresponding multipliers 1512, 1514, and 1516, where the result is multiplied by the corresponding scores of A1, A2, and al, for example. road. The outputs of the multipliers 1512, 1514, and i5i6 are provided to the adder 1520 after cooking to generate a combined reply cancellation output, and the combined reply cancellation output can be provided to the output measurement and error signal generator 1522 and MUX 306 via the lead 312. With a multipath reply detector and a signal quality monitor 300. The efficiency measure and error signal generator 1522 provides information to the weighted updater 1524 and the branch updater 1518; therefore, the values of the weighting and branch can be updated. Note that the shunts (A1, A2, and aL) also represent plural numbers. The number of delay units such as 1506 and 1508 and the multipliers such as 1512 and 1514 and the branches such as A 1 and A2 are determined by the number of branches in this equalizer section. The weighting of the spatial combiner (such as W1 and w2) and the equalizer (such as AJ, A2, ..., AL) can be selected, so the result #number amplitude change on the output of the adder 1520 can be reduced. The number of branches in the equalizer section can also be selected to improve the quality of the resulting signal, but more hardware or software is required, depending on the implementation. The efficiency measure and error signal generator 522 may execute a modified fixed coefficient algorithm to update the weighting and shunting, in order to reduce the amplitude variation of the resulting signal on the output of the adder 1520. (Therefore, in a specific embodiment, the same standard can be used to update the weighting of the spatial domain. As for updating the appropriate filter branch of the time domain, refer to the following equations 9-26.) Therefore, the space-time unit 302 can use the input FM signal Fixed coefficient characteristic signal. That is -44-A7 B7 V. Description of the Invention (41) 疋, the FMk number should maintain a fixed amplitude. However, the amplitude of the input FM signal cannot be kept fixed due to multi-path reply and noise intervention. Therefore, weighting and shunting can be used to reduce the amplitude variation caused by multipath reply. And / mind, the implementation described in Figure 15 is not only applicable to receiving two antenna signals but also to expand the combination and reply to cancel signals from any number of antennas. In this specific embodiment, each input signal is weighted by a corresponding weighting factor before being provided to the adder 1504. Similarly, the equalizer section (that is, suitable filter 1530) can use any number of shunt designs. The efficiency measure and error signal generator 1522 provides appropriate information to the weighted updater 524 and the shunt updater 1518 by using a modified fixed coefficient algorithm, and will be described in the following equation. In this algorithm, a cost function is defined as follows: Equation 19: 7 = ~ ψ (*) | 2-ΐ} The resulting signal after the spatiotemporal processing on the output of Additive Yi 1520 from the above equation X (k) 疋, And k is the sampling time example provided by t = kTs, where Ts 疋 sampling period. The above equation system expresses the expectation of an arbitrary process, because the received signals (such as II, Q1, * I2, Q2,) are statistics rather than decisions. One goal of the space-time unit 302 is to reduce the cost function J, which can be achieved through weighting and shunt changes, and will be discussed further below. Note that the received signals IΓ, Q1, and 12, and Q2 are usually also represented by "(", where 111 = 1, 2,. &Quot;.,: ^, And 1 ^ is the number of antennas of the receiver, and 1 < : Is the sampling time example provided by t = kTs. Also note that the weighted WwW2 may be -45-this paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 582141 A7 B7 V. Description of the invention (42) Represented as W 1 = W lR + j W 1 and W2 = W2R + j W2. The subscript R is used to represent the real part of a complex number, and the subscript I is used to represent the imaginary part. And 'they can use Wm (k) represents, where m == 1, 2, ..N, and n is the number of antennas of the receiver, and k is an example of sampling time. Moreover, A1, A2, ..., AL is A1 = person 111+ Enter 11 and so on, or use An (k), where n = 1, 2, ..., L, and L is the number of branches of the equalizer, and k is an example of the sampling time. Therefore, the equation provided here In the following, different representations can be used. The following equations represent all signal combinations from different antennas. The signal γ (^) on the output of the adder 1504 is expressed as the following equation: square Equation 20: y (fc) = trm (fe) xWm (/ :) m = l The above equation is a general equation for any number of antennas in the system. The specific embodiment described in FIG. 15 has two antennas, Y (k) The equation can be expressed by the following equation: Equation 21: Y (k) = (ir + jQr) · (wiR + jwiI) + (ir + jQ2,) · (W2R + jW2,) Therefore, the 'adder 1520 output etc. The signal can be expressed as follows: Equation 22: X (k) = X (k) ^ Y (kn) xAn (k) In the above equation, L is the number of branches in the equalizer part of the space-time unit 30. .Y (kn) means that in the adder 1504 (also refer to Equation 2) -46-I paper size applicable national time standard (CNS) M specifications _> < Norgod love) A7 B7 V. Invention Note (43) that the output affected by time offsets such as 1510 is weighted and combined by the delay units 1506 and 1508. The function is equal to "the number J, which is related to the weighted complex number.疋 成 ° 'is derived as a cost number related to the combination of branch and complex numbers. Therefore, the equation can be expressed as:

Equation 23: 1 97 ---- 〇 dw; m = 1,2, ··· N Equation 24: dJ f = 0 n = 1,2, ... L A statistical gradient can be used to find the solution to the above equation. Therefore, the update equations for weighting and shunting are expressed as follows: Wan Cheng 25 ·· Wm (k + l) = Wm (k) ix (| X (k) | 2]) xX (k) xAi * (k) fn / (k), where π = 1, 2, ..., N Equation 26: An (k + l) = An (k) 4x (| x (k) | 2-1) xX (k) xY * (kn),

Where 11 = 1, 2, ...,; L In the two equations of the above equations 25 and 26, " is a constant used to indicate the step size 'and k is the sampling example t = kT. Therefore, the above equation is Represents a time average of weighting and shunting. As discussed in Figure 3, the output of the adder 1520 is fed back to the multi-path response detector and the signal quality monitor 300 to determine whether the response of the calculated signal is reduced below a predetermined threshold that allows the response. If so, the control signal via the wire 32 can be selected as the wire 312 to be regarded as -47 through the MUX 306-This paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 582141 A7 _____ B7 5 Description of the invention (44)

Icomb, QC0mb are provided to the wire 208. However, if the multi-path reply detector 仏 number quality supervisor 300 decides that the reply keeps exceeding a predetermined threshold, the unit 2 302 performs another repetition to further reduce the multi-path reply from the signal, so it can be repeated in deal with. FIG. 16 depicts a specific embodiment of the multipath response detector signal product monitors 300, 402 used in FIGS. 3 and 4. FIG. If the specific embodiment of FIG. 3 is used, the coefficient circuit 1600 can receive input signals IΓ, Q1, and 12, Q2, via wires 314 and 316, respectively. In the specific embodiment of FIG. 4, the multi-path loopback #detector and signal quality monitoring 402 receive the combined signals Π *, Q1, and 12 ', Q2' via the wires 4 丨 6. The coefficient circuit 160 then calculates the coefficients of the digitally complex baseband signal. Ideally, the result should be equal to a constant value. However, in time-varying mobile channels, the transmission signal is affected by channel attenuation. In an FM radio system, although the channel change is usually slower than the bandwidth of a wideband FM signal. Therefore, the band-pass filter 1602 can be used to extract the coefficient change caused by the multipath reply, and the slower change of the channel can be ignored. The average signal strength output by the band-pass filter 1602 can then be calculated by the average signal strength detector 1604. The comparison circuit 1606 then compares the average signal strength with a preset value such as the threshold strength 1608. A judgement can then be reached based on the results of the comparison. If the average signal strength is greater than the threshold strength value of 1608 ′, then the received signal I, qi, or 12, Q2, or a combination of them needs to reply to cancel the processing. That is, in the specific embodiment of FIG. 3, '11', Q Γ, and 12 ', Q2' are transmitted to the space-time unit 302 to select the attenuation channel according to the processing frequency. In the specific embodiment of FIG. 4, the multi-path reply detection k-number quality supervisor 402 may start the reply canceller 406 so that the national paper (CNS) A4 specification (21 〇X 297 public love) 582141 A7 A ____B7 V. Description of the invention (~ 45 ^ ~ '— Before Icomb and Qc〇mb are output to the wire 208, the reply of the signal received from the multiple combination unit 404 is cancelled. Note' The various hardware units and circuits described throughout the application can be reused or shared with a variety of different functions. For example, the circuit 1718 described in FIG. 17 can be used to implement a state machine to control the execution of the other functions described above, and is not limited to computing only Weighting factors W 丨 and W2. Specific embodiments of the present invention can be implemented in hardware, style, or a combination of both. For example, some specific embodiments can be implemented with a finite state machine with a microcode control circuit to Control the execution of the machine. Alternatively, software code can be used to perform the above functions. In the description, the invention describes a specific embodiment. However, it is well known in the art. The person can understand that various modifications and can be achieved without departing from the scope of the present invention disclosed in the scope of the patent application below. Therefore, the description and drawings are only illustrative and not limiting, and all such modifications are in the present invention Benefits, other advantages, and problem solving have been described above with reference to specific embodiments. However, benefits, advantages, problem solving, and any element that causes any benefit, advantage, or solution should not constitute any or all patent applications. A decisive, required, or essential feature or element. As used herein, terminology, including, ",, including, or any other relevant variation covers a non-exclusive inclusion, so as to include the processing of a list of components , Method 'literature, or device includes not only these elements, but also other elements not represented in this process, method, literature, or device. -49-

Claims (1)

93. 1. Amended and supplemented Patent Application No. 091115349_Chinese Patent Application Replacement (January 1993) Patent Application Scope 1. A first signal from a first sensor A method for generating a combined signal by combining with a second signal from a second sensor, the method includes: determining a phase difference between the first signal and the second signal, wherein determining the phase difference includes: The first signal is multiplied by the complex conjugate of the second signal to produce an intermediate result; the intermediate result is filtered to produce a filtered intermediate result; the intermediate result filtered by S is used to obtain the phase difference, Determine a first weighted value, wherein the first weighted value is independent of the phase difference; determine a second weighted value, wherein the second weighted value is independent of the phase difference; apply a first weighted value to the A first signal to generate a first weighted signal; applying a first weighted value to the second signal to generate a second weighted signal; and when the first weighted signal is combined with the second weighted signal Use this phase difference. 2. —A method for combining a first signal from a first sensor and a second signal from a second sensor to generate a combined signal, the method includes determining a first characteristic signal of the signal The characteristic of the first signal in 纟 is not a signal-to-noise ratio characteristic; This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 582141 Prepare the first signal of the child and the second signal; when μ and the combined signal are generated, weight the first signal by using the characteristics of the first signal of the second; decide on the first signal and the second signal The phase difference includes: the interphase-phase difference multiplying the first signal by the second signal of the inter-vehicle results; ϋ 1 filtering the intermediate results to produce a filtered intermediate result; from the filtered The intermediate result separates the phase difference; and uses the phase difference to correct at least one of the first and second signals. A method for combining a first signal from a first sensor and a second signal from a first sensor to generate a combined signal, the method includes: determining a first of the first signal Signal characteristics, wherein the first signal rhyme characteristic is not a signal-to-noise ratio characteristic; using the first signal characteristic to weight the first signal when the first signal and the second signal are combined to generate the combined signal ; Determining a second signal characteristic of one of the second signals; using the second signal characteristic to weight the second signal when the first signal and the second signal are combined to generate the combined signal; according to the first The first signal characteristic of the signal and the second signal characteristic of the second signal determine a first weighting value; the friend determines a second value based on the first signal characteristic of the first signal and the / signal characteristic of the second signal. Weighted value. -2-This paper size applies Chinese National Standard (CNS) Α4 specification (210 X 297 public directors) 4 1 2 8 8 8 8) 8 A BCD Said a second signal of one of the two sensors to generate ~ 知 know people: the method of combining signals, this method includes the first signal characteristics of the first signal of the child, where the first / The signal characteristic is not a signal-to-noise ratio characteristic; the first signal characteristic is used to weight the first signal when the first signal and the second signal are combined to generate the combined signal. Calculate the first signal A square root of a power; and the steps of using the first signal characteristic to weight the first signal include: using a square root of the power of the first signal to combine the first signal with the second signal to When the combined signal is generated, the first signal is weighted. A method for combining a first signal from a first sensor and a second signal from a second sensor to generate a combined signal, the method includes: determining a first of the first signal Signal characteristics, wherein the first / signal characteristic is not a signal-to-noise ratio characteristic; using the first signal characteristic to weight the first signal when the first signal and the second signal are combined to generate the combined signal; Determine a second signal characteristic of one of the second signals; use the second signal characteristic to weight the second signal when the first signal and the brother 'signal are combined to generate the combined signal; according to the first signal Characteristics, determine a first weighted value, in which the first paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 582141 An additional value is independent of phase; and a second weighting value is determined according to the characteristics of the second signal, wherein the second weighting value is independent of phase; determining which of the first signal and the second signal has a larger value Amplitude; if one of the first signals has an amplitude greater than the amplitude of the second signal, confirm that the first weighted value is greater than the second weighted value; and if one of the second signals has an amplitude greater than the amplitude of the first signal, Confirm that the second weighted value is greater than the first weighted value. 6. · A method for combining a first signal from a first sensor with a second signal from a second sensor to generate a combined signal. The method includes: ^ Evaluation using a phase locked loop A phase difference between the first signal and the second signal; °; When the phase-locked loop is locked, the first signal is multiplied by the phase difference to generate a phase correction signal, wherein an output of the phase-locked loop provides the phase difference, and the phase correction signal is added to the second Signal to generate a combined signal; and if the phase-locked loop is not locked, one of the first signal and the second signal is selected instead of the combined signal to be provided as an output. 7. A receiver comprising: a higher frequency unit, the higher frequency units having: a first input for receiving a first radio frequency signal from a first sensor, a second input, It is used for receiving a second radio frequency signal from the second sensor, and has a first output for providing a signal corresponding to the first radio frequency signal— 582141 Patent application scope AB c D * Month IX S3. The first baseband signal is in year 1 and Dorp, and has a second output for providing a second baseband signal corresponding to one of the second radio frequency signals. In a selected state, the first signal and the second signal represent the same information value; and a baseband unit, the baseband unit is coupled to the higher frequency unit, and the baseband unit has at least one bypass signal and at least one Output, the bypass signal can select whether to output according to a combined function of the first baseband signal and the second baseband signal in at least the first selected state. 8 · A receiver, comprising: a first device for receiving a first signal from a first sensor, and a second signal from a second sensor, wherein the first The signal and the second signal represent the same information value of a first selection state, and wherein the first device converts the first and second signals to baseband; and the baseband device is configured to generate a bypass signal and an output representation, The baseband device is coupled to the first device for receiving digital information related to at least one of the first and second signals, and the baseband device may be selected from the bypass signal according to at least the first selection state. Whether the output of is a combination function of the first converted signal and the second converted signal. 9. A baseband unit for receiving a first signal from a first receiving source; and a second signal for receiving a first signal from a first receiving source. The baseband unit may provide an output. The baseband unit includes: a first unit The first unit can use a first algorithm to convert the -5-This paper size is applicable ® 81 standards (CNS) A4 specifications (21GX 297 public directors) ----- 582141 L month 1X 9 6. The scope of the patent application is a combination of a signal and the second signal, wherein the first unit combines the first and second signals to form a combined signal and includes: an adaptive filter to filter the combined signal, And a weighted updater coupled to the adaptive filter, wherein the weighted updater provides a weighted value to weight at least one of the first and second signals when the first and second signals are combined to form the combined signal. One; and a second unit, which can use a second algorithm to combine the first signal with the second signal; and a signal quality monitor for supervising a first signal of the first signal A quality level and a second quality level of the second signal; and used to select whether the first unit or the second unit can provide an output. ίο. —A baseband unit for receiving a first signal from a first receiving source and a second signal from a second receiving source. The baseband unit provides an output. The baseband unit includes: A first unit for combining the first signal and the second signal using a first algorithm; a second unit for combining the first signal and the second signal using a second algorithm; and a signal quality A monitor for monitoring a first quality level of the first signal and a second quality level of the second signal, and for selecting whether the first unit or the second unit is used to provide the output, wherein the signal The quality supervisor includes: a module circuit; a filter coupled to the module circuit; -6-this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 582141 A B c D 6. Patent application range: an average signal strength detector coupled to the filter; and a comparison circuit coupled to the average signal strength detector, the comparison circuit compares an average signal strength of one of the first signals with a predetermined threshold And compare the average signal strength of one of the second signals with the predetermined threshold. 11. A baseband unit for receiving a first signal from a first receiving source and a second signal from a second receiving source. The baseband unit can provide an output. The baseband unit includes: a combination unit for: Combining the first signal with the second signal and providing a combined signal; a signal quality monitor for determining a quality characteristic of the combined signal and providing a control signal, wherein the quality characteristic includes multi-path reply information; and The reply canceller receives a control signal from a signal supervisor and is selectively used to perform reply cancellation of the combined signal according to the quality characteristic. 12 · —Base τ unit 'is used to receive a first signal from a first receiving source and a second signal from a second receiving source. The baseband unit can provide an output. The baseband unit includes: a signal quality supervision A device for determining the quality characteristics of at least one of the first signal and the second signal, and providing a control signal, wherein the quality characteristic includes multi-path reply information; a combination unit for A signal is combined with a second signal, and a combined signal is provided; and this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 582141 8 8 8 8 AB c D Patent application scope The reply canceller is used to receive the control signal from the signal supervisor, and is selectively used to perform the reply cancellation of the combined signal according to the quality characteristic. -8-This paper size applies to China National Standard (CNS) A4 (210X297 mm)