TW582141B - Receiver and method therefor - Google Patents
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- TW582141B TW582141B TW91115349A TW91115349A TW582141B TW 582141 B TW582141 B TW 582141B TW 91115349 A TW91115349 A TW 91115349A TW 91115349 A TW91115349 A TW 91115349A TW 582141 B TW582141 B TW 582141B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/08—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
- H04B7/0868—Hybrid systems, i.e. switching and combining
- H04B7/0871—Hybrid systems, i.e. switching and combining using different reception schemes, at least one of them being a diversity reception scheme
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
- H04B1/1081—Reduction of multipath noise
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/26—Circuits for superheterodyne receivers
- H04B1/28—Circuits for superheterodyne receivers the receiver comprising at least one semiconductor device having three or more electrodes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/08—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
- H04B7/0837—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station using pre-detection combining
- H04B7/084—Equal gain combining, only phase adjustments
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/08—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
- H04B7/0837—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station using pre-detection combining
- H04B7/0842—Weighted combining
- H04B7/0865—Independent weighting, i.e. weights based on own antenna reception parameters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/02—Arrangements for detecting or preventing errors in the information received by diversity reception
- H04L1/06—Arrangements for detecting or preventing errors in the information received by diversity reception using space diversity
- H04L1/0618—Space-time coding
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/38—Demodulator circuits; Receiver circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/08—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
- H04B7/0891—Space-time diversity
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Radio Transmission System (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
582141 A7 B7 五、發明説明(1 ) 先-前技藝專利之參者 本申請案是在2001年7月27日所申請的美國專利案號 09/916,915。 發明範轉 本發明大致關於接收器,而更.明確而言,係有關無線電 接收器。 相關技藝 例如天線的多重感測器典型是用來將更多資訊提供給接 收器°然而’由於至少部分不想要的反射與散佈,多重感 測器通常是接收一傳輸信號的不同延遲與衰減版本的重 疊。從傳輸信號接收的多路徑元件典型具有建構性或解建 構一起加入的不同相位,藉使造成接收信號的衰減。因 此’一改良的接收器可有效組合或處理來自多重感測器的 這些接收信號是需要的。此外,減少多路徑回信的影響及 增加這些接收器的可信度位準是需要的。 Μ式之簡單說明 本發明經是經由範例與非局限於附圖說明,在圖中的相 同參考數字是表示類似元件: 圖1係根據本發明的一具體實施例而以方塊圖形式描述一 無線電接收器; 圖2係根據本發明的具體實施例而以方塊圖形式描述圖1 的一部分基帶單元; 圖3- 4係根據本發明的不同具體實施例而以方塊圖形式描 述圖1的一部分頻道處理單元; -5 - 本紙張尺度適用中國國家標準(CNS) Α4規格(210X 297公爱)582141 A7 B7 V. Description of the invention (1) Participants of the pre-existing technology patent This application is US Patent No. 09 / 916,915 filed on July 27, 2001. This invention relates generally to receivers, and more specifically, to radio receivers. Related technologies such as antenna multiple sensors are typically used to provide more information to the receiver. However, 'due to at least partially unwanted reflections and spreads, multiple sensors are usually versions that receive different delays and attenuations of a transmission signal. Of overlap. Multipath elements received from a transmission signal typically have different phases that are constructive or destructive together, causing attenuation of the received signal. It is therefore desirable to have an improved receiver that can effectively combine or process these received signals from multiple sensors. In addition, reducing the impact of multipath replies and increasing the confidence level of these receivers is needed. Brief Description of Formula M The present invention is described by way of example and not limited to the accompanying drawings. The same reference numerals in the figures represent similar elements: Figure 1 depicts a radio in block diagram form according to a specific embodiment of the present invention Receiver; FIG. 2 is a block diagram depicting a part of the baseband unit of FIG. 1 according to a specific embodiment of the present invention; FIG. 3-4 is a block diagram depicting a part of the channel of FIG. 1 according to different specific embodiments of the present invention Processing unit; -5-This paper size applies to China National Standard (CNS) Α4 specification (210X 297 public love)
裝 訂Binding
582141 A7 ---— —_B7________ — 五、發明説明(2 ) 圖5係根據本發明的具體實施例而以方塊圖形式描述圖3 或4的一部分多樣組合單元; 圖6係根據本發明的一具體實施例而以流程圖形式描述圖 5的多樣組合操作單元; 圖7係根據本發明的具體實施例而以方塊圖形式描述圖5 的一部分加權因素決定電路; 圖8係根據本發明的具體實施例而以方塊圖形式描述圖5 的一部分相位評估電路; 圖9係根據本發明的一具體實施例而以方塊圖形式描述圖 5的一部分多樣組合單元; 圖10係根據本發明的一具體實施例而以方塊圖形式描述 圖3或4的一部分多樣組合單元; 圖11係根據本發明的另一具體實施例而以流程圖描述圖 10的多樣組合單元操作; 圖12係根據本發明的另一具體實施例而以方塊圖形式描 述圖10的一部分信號特性值評估電路; 圖1 3係根據本發明的另一具體實施例而以方塊圖形式描 述圖1 0的一部分乘法器與相位鎖定迴路與鎖定偵測電路; 圖14係根據本發明的另一具體實施例而以方塊圖形式描 述圖13的一部分鎖定偵測器; 圖15係根據本發明的另一具體實施例而以方塊圖形式描 述圖3的一部分時空單元;及 圖16係根據本發明的一具體實施例而以方塊圖形式描述 圖3或4的一部分多路徑回信偵測器與信號品質監督器。 -6 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 582141 A7 B7 五、發明説明(3 ) 圖17係根據本發明的另一具體實施例而以方塊圖形式插 述圖5的一部分加權因素決定電路。 圖18係根據本發明的另一具體實施例而以方塊圖形式描 述圖17的加權值決定電路操作。 熟諳此技者可了解到圖式只用於簡化與清楚描述,而未 依比例繪出。例如,圖中的一些元件是放大表示,以幫助 對本發明具體實施例的了解。 圖式之詳細說明 如在此的使用,術語,,匯流排"可用來視為複數個信號或 導線’而可用來傳輸例如資料、位址、控制、或狀態的一 或多個各種不同類型資訊。在此討論的導線是以單一導 線、複數個導線、單向導線、或雙向導線描述。然而,不 同具體實施例可改變導線的實施。例如,使用分開的單向 導線,就不使用雙向導線,反之亦然。而且,複數個導線 可使用能以串列傳輸多信號、或一時間多工方式的單一導 線取代。同樣地,運送多信號的單一導線可分成用以運送 部分這些信號的各種不同導線。因此,傳輸信號能有許多 選擇。 當分別參考一信號、狀態位元、或類似裝置的邏輯真或 邏輯假狀態時,可使用術語"確認,,與"否定"^如果邏輯真 狀態是一邏輯位準1,邏輯假狀態是一邏輯位準而且’ 如果邏輯真狀態是一邏輯位準0,邏輯假狀態便是一邏輯位 準卜 中括弧是用來表示一匯流排的導線或一值的位元位置。 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 裝 訂582141 A7 ----- —_B7 ________ — V. Description of the invention (2) FIG. 5 is a block diagram depicting a part of the various combination units of FIG. 3 or 4 according to a specific embodiment of the present invention; Fig. 5 describes the various combined operation units of Fig. 5 in the form of a specific embodiment; Fig. 7 depicts a part of the weighting factor determining circuit of Fig. 5 in the form of a block diagram according to a specific embodiment of the present invention; A part of the phase evaluation circuit of FIG. 5 is described in the form of a block diagram in the embodiment; FIG. 9 is a diagram of a part of the various combined units in FIG. 5 in the form of a block diagram according to a specific embodiment of the present invention; 3 or 4 are described in block diagram form according to the embodiment; FIG. 11 is a flowchart illustrating the operation of the various combined units of FIG. 10 according to another specific embodiment of the present invention; and FIG. 12 is a diagram according to the present invention. Another specific embodiment describes a part of the signal characteristic value evaluation circuit in FIG. 10 in the form of a block diagram. FIG. 13 is a diagram illustrating another embodiment according to the present invention. A block diagram depicts a part of the multiplier, phase lock loop, and lock detection circuit of FIG. 10; FIG. 14 is a block diagram depicting a part of the lock detector of FIG. 13 according to another embodiment of the present invention; FIG. 15 FIG. 16 is a block diagram depicting a part of the space-time unit of FIG. 3 according to another embodiment of the present invention; and FIG. 16 is a block diagram depicting a part of the multipath reply of FIG. 3 or 4 according to a specific embodiment of the present invention. Detectors and signal quality monitors. -6-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 582141 A7 B7 V. Description of the invention (3) Figure 17 is a block diagram inserted in accordance with another specific embodiment of the present invention A part of the weighting factor determining circuit in FIG. 5 will be described. Fig. 18 is a block diagram depicting the operation of the weighting value determining circuit of Fig. 17 according to another embodiment of the present invention. Those skilled in the art will understand that the drawings are only used for simplicity and clear description, and are not drawn to scale. For example, some of the elements in the figure are enlarged to help understand the specific embodiments of the present invention. Detailed description of the drawings. As used herein, terminology, bus " can be used as a plurality of signals or wires' and can be used to transmit one or more of various types such as data, address, control, or status. Information. The conductors discussed here are described by a single conductor, a plurality of conductors, a unidirectional conductor, or a bidirectional conductor. However, different embodiments may change the implementation of the wires. For example, with separate unidirectional wires, bidirectional wires are not used, and vice versa. Moreover, a plurality of wires may be replaced with a single wire capable of transmitting multiple signals in series or a time multiplexing method. Similarly, a single conductor carrying multiple signals can be divided into various conductors used to carry some of these signals. Therefore, there are many options for transmitting signals. When referring to a signal, status bit, or a logically true or false state of a similar device, the terms " confirm, and " negative " ^ are used if the logically true state is a logical level 1, logically false The state is a logical level and 'If the logically true state is a logical level 0, the logically false state is a logical level. The brackets are used to indicate the position of a bus wire or a value. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) binding
線 582141 A7 ___ B7 五、發明説明(4 ) 例如,’’匯流排60[0-7],,或,,匯流排00的導線[0-7]"係表示 匯流排60的8個最低有效導線,而且”位址位元[〇-7]"或"位 址[0- 7]係表示一位址值的8個最低有效位元。在一數值前 的付號π $ ”係表示數值是以十六近制或底數16形式。在一數 值前的符號” %”係表示二進制或底數2形式。 如一簡短介紹概述,注意,圖丨係描述具有一基帶單元的 一無線電接收器的一具體實施例,而且圖2係描述圖1的一 基帶單元的具體實施例。圖3和4係提供一頻道處理單元(在 圖2的基帶單元中)的不同具體實施例。兩具體實施例(圖3 和4)可在他們組合之前計算或評估在輸入信號之間的一相 位差。而且,圖3和4的每一具體實施例係提供通常在使用 •輸入信號多樣組合時執行的回信消除選項。此回信是透過 圖3的時空單元302與圖4的回信消除器4〇6執行。而且,圖3 和4係包括一多樣組合單元(3〇4、4〇4),以組合複數個輸入 仏號。因此’圖5和1〇係描述多樣組合單元3〇4和4〇4的另一 具體實施例。圖5係描述用以組合信號的一相位評估方法, 而且圖10係描述一混合PLL方法。因此,本發明的具體實 施例可提供給在基帶單元(且通常是在頻道處理中)中所使 用的各種不同選擇。 圖1係根據本發明的一具體實施例而描述一無線電接收 器。播線電接收器10〇包括經由導線144而雙向耦合到控制 电路112的使用者界面11〇。控制電路112是經由導線142而 雙向耦合到無線電頻率(射頻)單元1〇6和1〇8 :經由導線14〇 而雙向耦合到中頻(IF)單元114 ;及經由導線138而耦合到 -8 - 本紙張尺度適用_ _準_) A4規格(加χ 582141 A7 _____ B7 I、發明説明(~^ ~~ 基帶單元116。射頻單元106是經由導線12〇而耦合到射頻天 線102 ,而且經由導線124而雙向耦合到中頻單元114。射頻 單元108係經由導線122而耦合到射頻天線1〇4,而且是經由 導線126而雙向耦合到中頻單元114。中頻單元114是經由導 線128、130、和132而耦合到基帶單元116。基帶單元116係 經由導線13 4而耦合到聲頻處理單元1 5 〇與資料處理單元 148。聲頻處理單元15〇係經由導線136耦合到可提供輸出信 號的放大器與喇队118。資料處理單元148係雙向耦合到使 用者界面lio。而且,使用者可經由導線146而在使用者界 面110之間提供及接收資訊。 操作上,射頻天線1〇2和1〇4可捕捉無線電信號,及將他 們分別提供給射頻單元106和108。射頻單元1〇6和1〇8可依 無線電接收器的設計而將接收的無線電信號轉換成一通常 中頻範圍。即是,射頻單元106和1〇8可將接收的無線電信 號頻率轉換成一較低頻率、或一較高頻率,此是因中頻單 元114的需求而定。中頻單元114是經由導線124和126而接 收射頻信號,及經由一類比-數位轉換器而將他們數位化。 中頻單元114亦可執行數位混合,以產生經由導線〗2 8和 130輸出給基帶單元116的同相位與9〇度相位差數位輸出。 在另一具體實施例中,中頻單元n4可選擇。即是,射頻單 元106和108可將從天線1〇2和1〇4接收的無線電信號直接轉 換成基帶;及包括一類比-數位轉換器,以便將數位化基帶 4吕號直接提供給基帶單元(而且注意,如果使用,射 頻單元106和108與中頻單元Π4可視為一"較低頻率單元,,或 -9 - 本纸張尺度適用中國國家標準(CNS) A4規格(210X 297公釐)Line 582141 A7 ___ B7 V. Description of the invention (4) For example, "the bus 60 [0-7], or, the wire [0-7] of the bus 00" means the eight lowest of the bus 60 Valid wires, and "address bit [0-7] " or " address [0-7] represents the 8 least significant bits of a bit value. The sign π $ before a value" The values are expressed in hexadecimal or base 16. The sign "%" before a number indicates a binary or base-2 form. As a brief introduction, note that FIG. 1 depicts a specific embodiment of a radio receiver with a baseband unit, and FIG. 2 depicts a specific embodiment of a baseband unit of FIG. Figures 3 and 4 provide different specific embodiments of a channel processing unit (in the baseband unit of Figure 2). Two specific embodiments (Figures 3 and 4) can calculate or evaluate a phase difference between the input signals before they are combined. Moreover, each of the specific embodiments of Figures 3 and 4 provides a reply cancellation option that is usually performed when using various combinations of input signals. This reply is executed by the space-time unit 302 in FIG. 3 and the reply canceller 406 in FIG. 4. Moreover, Figures 3 and 4 include a variety of combination units (304, 404) to combine a plurality of input 仏 numbers. Therefore, 'FIGS. 5 and 10 describe another specific embodiment of the various combination units 304 and 404. FIG. 5 illustrates a phase evaluation method for combining signals, and FIG. 10 illustrates a hybrid PLL method. Therefore, specific embodiments of the present invention may provide various options for use in a baseband unit (and typically in channel processing). Fig. 1 illustrates a radio receiver according to a specific embodiment of the present invention. The broadcast electrical receiver 100 includes a user interface 110 coupled bidirectionally to the control circuit 112 via a lead 144. The control circuit 112 is bidirectionally coupled to the radio frequency (radio frequency) units 106 and 108 via a wire 142: bidirectionally coupled to the intermediate frequency (IF) unit 114 via a wire 140; and coupled to -8 via a wire 138 -This paper size applies _ _ quasi_) A4 specification (plus χ 582141 A7 _____ B7 I. Description of the invention (~ ^ ~~ Baseband unit 116. The radio frequency unit 106 is coupled to the radio frequency antenna 102 via the wire 120, and also via the wire 124 and two-way coupled to the intermediate frequency unit 114. The radio frequency unit 108 is coupled to the radio frequency antenna 104 via a wire 122, and is bidirectionally coupled to the intermediate frequency unit 114 via a wire 126. The intermediate frequency unit 114 is via wires 128, 130 And 132 are coupled to the baseband unit 116. The baseband unit 116 is coupled to the audio processing unit 150 and the data processing unit 148 via a wire 134. The audio processing unit 15 is coupled to an amplifier capable of providing an output signal via a wire 136 And the team 118. The data processing unit 148 is bidirectionally coupled to the user interface lio. Moreover, the user can provide and receive information between the user interfaces 110 via the wire 146. Operationally, radio frequency The antennas 102 and 104 can capture radio signals and provide them to the radio frequency units 106 and 108, respectively. The radio frequency units 106 and 108 can convert the received radio signals into a common radio signal according to the design of the radio receiver. Intermediate frequency range. That is, the radio frequency units 106 and 108 can convert the received radio signal frequency to a lower frequency or a higher frequency, which is determined by the requirements of the intermediate frequency unit 114. The intermediate frequency unit 114 is Receive radio frequency signals via wires 124 and 126, and digitize them via an analog-to-digital converter. The IF unit 114 may also perform digital mixing to produce the same output to the baseband unit 116 via wires 2 8 and 130. Digital output with phase difference of 90 degrees. In another specific embodiment, the intermediate frequency unit n4 can be selected. That is, the radio frequency units 106 and 108 can directly convert the radio signals received from the antennas 102 and 104. Baseband; and includes an analog-to-digital converter to provide the digitized baseband number 4 directly to the baseband unit (and note that if used, RF units 106 and 108 and IF unit Π4 can be considered as one & quo t; Lower frequency unit, or -9-This paper size applies to China National Standard (CNS) A4 (210X 297 mm)
線 582141Line 582141
"較高頻率單元,,’其是因接收無線電信號是否需要分別轉 換成較低或較高頻率而定。) 基帶單元116是從中頻單元114接收數位化無線電信號, 或如果沒有中頻單元存在,直接從射頻單元⑽和⑽接 收。基帶單元116可執行信號條件化、解調變、與解碼為 了要經由導線134而產生聲頻與資料資訊❶透過基帶單元 116執行的處理將進一步參考後圖描述。經由導線134的聲 頻^訊是提供給耦合到放大器與喇P八丨i 8的聲頻處理單元 150,以便經由導線136從接收器1〇〇產生一聲頻輸出。例 如,此可能是從無線電喇队播放的音樂。或者,基帶單元 116是經由導線134而將資料資訊輸出給資料處理單元148, 用以進一步處理。資料處理單元148的輸出係耦合到使用 者界面110,以允許使用者與接收器1〇〇的輸出互作用。例 如,使用者界面110可代表一無線撥號、觸摸式螢幕、監督 器與鍵盤、數字鍵盤、或任何其他適當輸入/輸出裝置。資 訊係代表文字、繪圖、或以數位形式傳輸的任何其他資 訊。 在另一具體實施例中,無線電接收器100可用於例如 AM、FM、GPS、數位電視、電視數位/聲頻廣播、數位/ 影像廣播等的資料不同格式。此外,接收器1 〇〇的設計可接 收除了無線電頻率之外的頻率❶因此,天線1〇2和1〇4可視 為感測器,以感測各種資料格式。此外,系統的每一感測 器或天線可接收資料的不同格式,所以,例如,一感測器 可接收無線電信號,而其他感測器可接收如上述的資料不 -10 — 本紙張尺度適用中國國家標準(CNS) A4规格(210 X 297公釐) 582141 A7 B7 五、發明説明(7 ) 同類型。而且,圖1的接收器100係描述兩感測器或天線(例 如天線102和104);然而,另一具體實施例是使用任何數量 的感測器以捕捉信號或資訊。 圖2係描述一部分基帶單元116的具體實施例。中頻濾波 器200分別經由導線128和130接收同相位與90度相位差信號 對II、Q1和12、Q2,其中II、Q1係對應經由感測器或天 線102接收的信號,而且12、Q2係對應經由感測器或天線 104接收的信號。II和12係代表數位同相位信號,而Q1和 Q 2係代表數位化9 0度相位差信號(例如,與同相位信號相 較是90度不同相位信號)^ (注意,例如11、Q 1和12、Q 2的 每個信號係代表一複數,其中11和12係代表實數部分,而 且Q 1和Q2係代表虛數部分,且將在下面進一步討論)中頻 濾波器200係經由導線202和204而耦合到處理單元206。頻 道處理單元206係經由導線208和210而耦合到解調變器 212,而且解調變器212係經由導線214而耦合到信號處理單 元216。信號處理單元216係經由導線134而提供聲頻/資料 資訊。中頻濾波器200、頻道處理單元206、解調變器212、 與信號處理單元216係經由導線138而耦合到控制電路112。 導線13 8可視為一控制匯流排,包括用以將不同信號來回於 單元2〇0、206、212和216傳輸的多種導線。例如,導線132 包括一部分導線138,或提供傳回給中頻單元114的完全匯 流排13 8 ^因此’經由導線13 8接收的控制信號係經由導線 132而傳送給中頻頻率單元114。同樣地,這些控制信號或 一部分這些信號係經由導線124和126而傳回給射頻單元信 -11 - 裝 訂" Higher frequency unit, 'depends on whether the received radio signal needs to be converted to a lower or higher frequency, respectively. The baseband unit 116 receives the digitized radio signal from the IF unit 114, or if no IF unit exists, directly receives it from the RF units ⑽ and ⑽. The baseband unit 116 may perform signal conditioning, demodulation, and decoding to generate audio and data information via the wire 134. The processing performed by the baseband unit 116 will be described further with reference to the following figure. The audio signal via the lead 134 is provided to the audio processing unit 150 coupled to the amplifier and the amplifier 8 to generate an audio output from the receiver 100 via the lead 136. For example, this might be music played from a radio squadron. Alternatively, the baseband unit 116 outputs the data information to the data processing unit 148 via the wire 134 for further processing. The output of the data processing unit 148 is coupled to the user interface 110 to allow the user to interact with the output of the receiver 100. For example, the user interface 110 may represent a wireless dial, a touch screen, a monitor and keyboard, a numeric keypad, or any other suitable input / output device. Information is representative of text, drawings, or any other information transmitted in digital form. In another specific embodiment, the radio receiver 100 can be used for different formats of data such as AM, FM, GPS, digital television, television digital / audio broadcasting, digital / video broadcasting, and the like. In addition, the receiver 100 is designed to receive frequencies other than radio frequencies. Therefore, the antennas 102 and 104 can be regarded as sensors to sense various data formats. In addition, each sensor or antenna of the system can receive data in different formats, so, for example, one sensor can receive radio signals and other sensors can receive data as described above. -10 — this paper standard applies China National Standard (CNS) A4 specification (210 X 297 mm) 582141 A7 B7 V. Description of invention (7) Same type. Furthermore, the receiver 100 of FIG. 1 describes two sensors or antennas (e.g., antennas 102 and 104); however, another specific embodiment is to use any number of sensors to capture signals or information. FIG. 2 illustrates a specific embodiment of a part of the baseband unit 116. The IF filter 200 receives the in-phase and 90-degree phase difference signal pairs II, Q1, and 12, Q2 via wires 128 and 130, respectively, where II and Q1 correspond to the signals received through the sensor or the antenna 102, and 12, Q2 Corresponds to signals received via a sensor or antenna 104. Series II and 12 represent digital in-phase signals, while Q1 and Q 2 represent digital 90-degree phase difference signals (for example, 90-degree different phase signals compared to in-phase signals) ^ (Note, for example, 11, Q 1 And 12, and Q2 each signal represents a complex number, where 11 and 12 represent the real part, and Q1 and Q2 represent the imaginary part, and will be discussed further below) The IF filter 200 is connected via the conductor 202 and 204 is coupled to the processing unit 206. The channel processing unit 206 is coupled to the demodulator 212 via wires 208 and 210, and the demodulator 212 is coupled to the signal processing unit 216 via wires 214. The signal processing unit 216 provides audio / data information via a lead 134. The IF filter 200, the channel processing unit 206, the demodulator 212, and the signal processing unit 216 are coupled to the control circuit 112 via a wire 138. The conductor 138 can be regarded as a control bus including a plurality of conductors for transmitting different signals to and from the units 2000, 206, 212, and 216. For example, the conductor 132 includes a portion of the conductor 138, or a full bus 13 8 provided to return to the intermediate frequency unit 114. Therefore, the control signal received via the conductor 138 is transmitted to the intermediate frequency unit 114 via the conductor 132. Similarly, these control signals or a part of these signals are transmitted back to the RF unit via the wires 124 and 126.
本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 582141 A7 B7 五、發明説明(8 號106和108。或者,控制信號可經由導線142而將信號從控 制電路112直接傳送給無線電頻率單元106和108。 操作上,中頻濾波器200是從輸入信號II、Q1,和12、 Q 2的想要頻率範圍移除不必要信號與雜訊。中頻濾波器 200亦可抑制相鄰頻道,為了要產生濾波的同相位與9〇度相 位差信號對ΙΓ、Q2,,和12,、Q2,,其中ΙΓ、Q1·係對應 II、Q1,而且12,和Q2,係對應12、Q2。頻道處理單元206 可接收ΙΓ、Q1,和12,、Q2,,且將他們組合,以產生單一 組合信號Icomb、Qcomb。或者,頻道處理單元206可經由 導線210而亦將例如II·、Qi,或12,、Q2,輸入信號之一輸入 信號直接提供給解調變器212,當作Ibypass、Qbypass。因 此,頻道處理單元206的212的單元。頻道處理單元206亦提 供例如Icomb、Qcomb的一組合信號、及例如Ibypass和 Qbypass的旁路信號。頻道處理單元2〇6與Ibypass、 Qbypass亦提供接收不同類型信號格式,以致於例如ΙΓ、 Q1’的一信號可透過頻道處理單元206處理,並且經由導線 208輸出,而例如12’、Q2’的第二信號是一不同信號格式, 且可直接旁路到解調變器212。(或者,II,' Q1,可能經由 導線208輸出,而無需由頻道處理單元2〇6處理)。此允許頻 道處理單元206提供單一組合信號或各種不同信號做進一步 處理。例如,一天線可提供來自一無線電台的信號,而一 第二天線可提供來自一第二無線電台的信號、或不同資料 格式。頻道處理單元206亦可執行接收信號的雜訊取消。 而且注意,圖2的具體實施例描述只描述經由中頻濾波器 -12 ·This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 582141 A7 B7 V. Description of the invention (No. 8 106 and 108. Alternatively, the control signal can be transmitted directly from the control circuit 112 via the wire 142 To radio frequency units 106 and 108. Operationally, the IF filter 200 removes unnecessary signals and noise from the desired frequency range of the input signals II, Q1, and 12, Q 2. The IF filter 200 can also To suppress adjacent channels, in order to generate filtered in-phase and 90-degree phase difference signal pairs Γ, Q2, and 12, Q2, where Γ, Q1 · are corresponding to II, Q1, and 12, and Q2, are Corresponds to 12, Q2. The channel processing unit 206 may receive IΓ, Q1, and 12, Q2, and combine them to generate a single combined signal Icomb, Qcomb. Alternatively, the channel processing unit 206 may also pass, for example, the wire 210 and, for example, II ·, Qi, or 12, Q2, one of the input signals. The input signal is directly provided to the demodulator 212 as Ibypass, Qbypass. Therefore, the unit 212 of the channel processing unit 206. The channel processing unit 206 also provides for example A combined signal of Icomb, Qcomb, For example, the bypass signals of Ibypass and Qbypass. The channel processing unit 206, Ibypass, and Qbypass also provide receiving different types of signal formats, so that a signal such as Γ, Q1 'can be processed by the channel processing unit 206, and output through the wire 208 And the second signal such as 12 ', Q2' is a different signal format, and can be bypassed directly to the demodulator 212. (Alternatively, II, 'Q1, may be output via the wire 208, without the need of a channel processing unit 206 processing). This allows the channel processing unit 206 to provide a single combined signal or a variety of different signals for further processing. For example, an antenna can provide signals from a radio station and a second antenna can provide signals from a second radio Channel signal, or different data formats. The channel processing unit 206 can also perform noise cancellation of the received signal. Also, note that the description of the specific embodiment of FIG. 2 only describes the use of an IF filter-12.
582141 A7 _ B7 五、發明説明(9 ) 200與頻遒處理單元206接收的兩信號。然而,如圖1的討 論,接收器1〇〇包括例如102和104的任何數量天線。在此具 體實施例中,每個天線可將例如j丨、q 1的本身同相與9〇度 相位差信號對提供給中頻濾波器2〇〇。在此具體實施例中, 中頻遽波器200可提供對應每一天線的複數個濾波同相位與 90度相位差信號對。在此方式中,頻道處理單元2〇6可依需 要輸出單一組合信號或多重部分組合信號。而且,頻道處 理單元206可提供多重旁路信號,所以超過一輸入信號可直 接旁路給例如解調變器212的進一步處理單元。 解調變器212是從頻道處理單元206接收信號1(:011113、582141 A7 _ B7 V. Description of the invention (9) Two signals received by 200 and frequency processing unit 206. However, as discussed in FIG. 1, the receiver 100 includes any number of antennas, such as 102 and 104. In this specific embodiment, each antenna may provide, for example, the same in-phase and 90 degree phase difference signal pairs of j, q1 to the intermediate frequency filter 200. In this specific embodiment, the intermediate frequency chirper 200 may provide a plurality of filtered in-phase and 90-degree phase difference signal pairs corresponding to each antenna. In this mode, the channel processing unit 206 can output a single combined signal or multiple partial combined signals as required. Moreover, the channel processing unit 206 can provide multiple bypass signals, so more than one input signal can be directly bypassed to a further processing unit such as the demodulator 212. The demodulator 212 receives a signal 1 (: 011113,
Qcomb和Ibypass、Qbypass,並且經由導線214而將解調變 信號提供給信號處理單元216。而且,如果解調變器212接 收信號Ibypass、Qbypass,解調變器212亦經由導線214而 將一解調變Ibypass、Qbypass提供給信號處理單元216。然 而’如上述,Ibypass、Qbypass是選擇性。例如,在一具 體實施例中,解調變器212可以是一FM解調變器,用以提 供對應每一輸入信號(例如Icomb、Qcomb和ibypass、 Qbypass)的多工(MPX)信號。在另一具體實施例中,解調 變器212可以是系統(例如接收器100)與輸入信號n、 12、Q2所需任何其他信號格式的一 AM解調變器或解調變 器。信號處理單元216可執行經由導線214接收的信號進一 步處理,及經由導線134而輸出聲頻/資料資訊。聲頻/資料 資訊只包括聲頻資訊、資料資訊、或聲頻與資料資訊的組 合。然後,如圖1所述,此資料可輸出給例如資料處理系統 -13 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 582141 A7 _______B7 五、發明説明(1〇 ) 或聲頻處理系統的各種不同系統。例如,在一 f μ接收器 中,212可如上述將一 ΜΡΧ信號輸出給信號處理單元216。 在此具體實施例中,信號處理單元216可接收]^1>又信號,及 執行立體聲解碼,了要將適當信號提供給每個喇队。例 如,ΜΡΧ #號可利用一導頻音調解碼,以提供立體音響系 統的左與右味j ρ八。而且,信號處理單元216可解調變其他子 載波#號(例如RDS或D ARC ),以便將進一步資訊提供給隨 後處理單元。 圖3係以方塊圖形式描述一部分頻道處理單元206的一具 體實施例。增益電路310是經由導線202和204而接收11·、 Q1·和12’和Q2*。增益電路310是經由導線138而亦在控制 電路112之間接收及提供控制信號。增益電路310係經由導 線3 14和3 16耦合到多路徑回信偵測器與信號品質監督器 300、時空單元302、與多樣組合單元304。MUX 308是經 由導線3 14和3 16而接收輸入信號與一控制信號138,而且經 由導線210輸出Ibypass、Qbypass。MUX 306是經由導線 312和318而接收輸入信號、及經由導線320的一控制信號, 並且經由導線208而輸出Icomb、Qcomb。導線320可以是一 部分導線138,或從多路徑回信偵測器與信號品質監督器 3 00接收的一接收控制信號。 操作上,增益電路310接收II·、Q1,、和12’、Q2·,並且 調整輸入信號的信號位準,並且經由導線3 14而提供I Γ、 Q1,的一增益調整(例如放大)版本、及經由導線316而提供 12,、Q2,的一增益調整(例如放大)版本。因此,在圖3的描 -14 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公嫠) 582141 A7 _ B7 _ 五、發明説明(""' 述與部分圖3,11’、Q 1,和ΐ2·、Q2,可視為經由導線314和 3 16所傳送這些信號的增益調整版本。多路徑回信偵測器與 信號品質監督器3 00是接收n,、Qi,和12,、Q 2’,並且決定 是否需要取消回信。在天線1 〇2和1 〇4的輸入信號多路徑元 件(可能由於不想要的散佈與反射)元件造成太多干擾情況 (例如回信),影響可在經由導線208輸出組合信號之前被減 輕。 如果多路徑回信偵測器與信號品質監督器300決定回信需 要取消(即是,回信量超過一預定回信臨界值),多路徑回 信偵測器與信號品質監督器3〇〇可將一控制信號提供給時空 單元302與多樣組合單元3〇4,以選取要執行的處理。例 如,在回信想要取消情況中,控制信號320可選取時空單元 302執行信號處理,以致於輸入信號η,、,和12,、q2,可 在將它當作輸出提供之前,能與回信取消適當組合。然 而’如果足夠的回信未被偵測,多路徑回信偵測器與信號 品質監督器300可經由導線320而將一控制信號提供給多樣 組合單元304來處理信號I Γ、Q Γ和12,、Q 2,,以便經由導 線318產生一組合輸出。因此,多樣組合單元3〇4可提供沒 有回信取消的一組合信號。經由導線320而經由多路徑回信 偵測器300提供的控制信號亦可將一選擇器信號提供給MIJX 3〇6,以決定時空單元302的輸出或多樣組合單元3〇4的輸出 疋否經由導線208而以Icomb、Qcomb提供。多路徑回信伯 測器信號品質監督器的操作將在圖16中進一步討論。 在足夠回信偵測到的情況,多路徑回信偵測器與信號品 -15 - 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐) 582141 A7 B7 五、發明説明(12 ). 質監督器300可如上述選取時空單元3〇2。經由導線312提供 的時空單兀302是回授給多路徑回信偵測器與信號品質監督 為300,以決定信號品質是否足夠(如果偵測的回信量是低 於預定的回信臨界值,信號品質便認為足夠)。如果不足 夠’只要再次輸出回授給多路徑信偵測器與信號品質監督 器300 ’隨後的重複便會執行。時空單元3〇2的操作將在圖 1 5進一步細節討論。只要信號認為足夠品質,亦即低於預 疋回信臨界值,多路徑回信偵測器與信號品質監督器300便 認為是經由導線320到MUX 306的控制信號,為了要選取如 同Icomb、Qcomb提供的輸出312。因此,重複會持續,直 到足夠回信取消執行為止。 圖4係根據本發明的一另一具體實施例而描述一部分的頻 道處理單元206。圖4的一部分頻道處理單元206包括增益電 路400、多路徑回信偵測器與信號品質監督器402、多樣組 合單元404、回信消除器406與MUX 408。多樣組合單元404 與MUX 408是經由導線202和204接收I Γ、Q Γ和12·、 Q2·。多樣組合單元404是經由導線422而將一組合信號提供 給MUX 408。增益電路400是經由導線416而將一增益調整 信號提供給多路徑回信偵測器與信號品質監督器402。MUX 408是從控制電路112接收一控制信號,並且經由導線412提 供ΙΓ、Q1*,及經由導線414而提供I21、Q2·,或將一組合 信號從422提供給導線412。在後者情況,沒有信號提供給 導線414 ;或者,在另一具體實施例中,除了組合信號之 夕卜,ΙΓ、Q1·和12,、Q2,之一可提供給導線414。增益電路 -16 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 582141 A7 __ B7 ____ 五、發明説明(13 ) 經由導線416而亦耦合到回信消除器406。多路徑回信偵測 器與信號品質監督器402係經由導線410和41 8而耦合到回信 消除器406。回信消除器406是經由導線208而提供輸出 Icomb、Qcomb,而且增益電路400是經由導線210而提供輸 出Ibypass、Qbypass。導線138是將控制信號從控制電路 112在增益電路400、多路徑回信偵測器與信號品質監督器 402、多樣組合單元404、回信消除器406、與MUX 408之間 來回提供。(注意,在圖4的具體實施例中,不像圖3的具體 實施例,多樣組合單元404不接收對應ΙΓ、Q1,和12,、Q 2, 的增益調整輸入。) 操作上,ΙΓ、Q1,可組合或經由頻道處理單元206而分開 處理。在前者情況,多樣組合單元404是經由導線202和204 接收信號I Γ、Q 1,的12,、Q 2,,並且將他們組合,以便經 由導線422將一組合信號藉著MUX 408經由導線412提供給 增益電路400。增益電路4〇〇是經由導線416而將II,、Q1,和 12’、Q 2’的一增益調整組合提供給多路徑回信偵測器4〇2。 多路徑回信偵測器402可決定在天線1〇2和1〇4的多路徑元件 回信是否造成大於一預定回信臨界值。如果回信超過此預 定臨界值,多路徑回信偵測器4〇2便允許回信消除器4〇6經 由導線41 6執行經由導線41〇而從增益電路4〇〇接收信號的回 信取消。在回信消除器406輸出的信號是經由導線41 8回授 給多路徑回信偵測器402。多路徑回信偵測器與信號品質監 督器402可決定回信消除器4〇6是否取消足夠回信,以使回 信降到低於預定的回信臨界值。如果回信位準是低於預定 -17 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公爱)Qcomb, Ibypass, Qbypass, and a demodulated signal are supplied to a signal processing unit 216 via a wire 214. Moreover, if the demodulator 212 receives the signals Ibypass and Qbypass, the demodulator 212 also supplies a demodulation Ibypass and Qbypass to the signal processing unit 216 via the wire 214. However, as described above, Ibypass and Qbypass are optional. For example, in a specific embodiment, the demodulator 212 may be an FM demodulator to provide a multiplexed (MPX) signal corresponding to each input signal (for example, Icomb, Qcomb, and ibypass, Qbypass). In another specific embodiment, the demodulator 212 may be an AM demodulator or demodulator of the system (such as the receiver 100) and any other signal formats required for the input signals n, 12, Q2. The signal processing unit 216 can further process the signal received via the wire 214 and output audio / data information via the wire 134. Audio / data information only includes audio information, data information, or a combination of audio and data information. Then, as shown in Figure 1, this data can be output to, for example, a data processing system-13-This paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) 582141 A7 _______B7 V. Description of the invention (1〇) Or audio processing systems. For example, in a f μ receiver, 212 may output an MPX signal to the signal processing unit 216 as described above. In this specific embodiment, the signal processing unit 216 can receive the signals, and perform stereo decoding to provide the appropriate signals to each team. For example, MPX # can be decoded with a pilot tone to provide the left and right flavors of the stereo system. Moreover, the signal processing unit 216 can demodulate other subcarrier # numbers (such as RDS or D ARC) in order to provide further information to the subsequent processing unit. FIG. 3 illustrates a specific embodiment of a part of the channel processing unit 206 in the form of a block diagram. The gain circuit 310 receives 11 ·, Q1 · and 12 'and Q2 * via the wires 202 and 204. The gain circuit 310 receives and provides control signals between the control circuits 112 via the wires 138. The gain circuit 310 is coupled to the multipath feedback detector and the signal quality monitor 300, the space-time unit 302, and the multiple combination unit 304 via the wires 3 14 and 3 16. The MUX 308 receives input signals and a control signal 138 through the wires 3 14 and 3 16 and outputs Ibypass and Qbypass through the wires 210. The MUX 306 receives an input signal through the wires 312 and 318, and a control signal through the wire 320, and outputs Icomb and Qcomb through the wire 208. The lead 320 may be a part of the lead 138, or a reception control signal received from the multi-path response detector and the signal quality monitor 300. Operationally, the gain circuit 310 receives II ·, Q1, and 12 ', Q2 ·, and adjusts the signal level of the input signal, and provides a gain-adjusted (eg, amplified) version of I Γ, Q1, via the wires 3 14 , And a gain-adjusted (eg, amplified) version of 12, Q2, is provided via the lead 316. Therefore, in the description of Figure 3-14-this paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297) 582141 A7 _ B7 _ V. Description of the invention (" " 'Description and part of Figure 3, 11' , Q 1, and ΐ2 ·, Q2 can be regarded as the gain-adjusted versions of these signals transmitted through the wires 314 and 3 16. The multi-path response detector and the signal quality monitor 3 00 receive n, Qi, and 12, , Q 2 ', and decide whether to cancel the reply. The input signal multipath elements (possibly due to unwanted spreading and reflection) at the antennas 1 02 and 104 cause too much interference (such as reply), which may affect the It is mitigated before the combined signal is output via the wire 208. If the multi-path reply detector and the signal quality monitor 300 decide that the reply needs to be cancelled (that is, the reply amount exceeds a predetermined reply threshold), the multi-path reply detector and signal The quality monitor 300 may provide a control signal to the space-time unit 302 and the multiple combination unit 304 to select a process to be performed. For example, in the case of replying to a reply request, the control signal 320 may select space-time Element 302 performs signal processing such that the input signals η ,,, and 12, and q2 can be appropriately combined with the reply before providing it as an output. However, 'if sufficient reply is not detected, multipath The reply detector and the signal quality monitor 300 may provide a control signal to the multiple combining unit 304 via the wire 320 to process the signals I Γ, Q Γ and 12, and Q 2 so as to generate a combined output through the wire 318. Therefore, the multiple combination unit 304 can provide a combination signal without cancellation of the reply. The control signal provided by the multi-path response detector 300 through the wire 320 can also provide a selector signal to the MIJX 306 to determine The output of the space-time unit 302 or the output of the multiple combination unit 304 is provided by Icomb and Qcomb via the wire 208. The operation of the signal quality supervisor of the multi-path reply tester will be further discussed in FIG. 16. Measured conditions, multi-path response detectors and signals -15-This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 582141 A7 B7 (12). The quality supervisor 300 can select the space-time unit 302 as described above. The space-time unit 302 provided through the wire 312 is fed back to the multi-path reply detector and the signal quality supervision is 300 to determine whether the signal quality is sufficient (If the detected reply volume is lower than the predetermined reply threshold, the signal quality is considered sufficient.) If it is not enough, 'just output the feedback to the multipath signal detector and signal quality monitor 300 again' Will be performed. The operation of space-time unit 302 will be discussed in further detail in FIG. 15. As long as the signal is considered to be of sufficient quality, that is, below the threshold of the pre-echo reply, the multi-path reply detector and the signal quality monitor 300 are considered to be control signals via the wire 320 to the MUX 306. In order to select the signals provided by Icomb and Qcomb, Output 312. Therefore, the repetition will continue until there is sufficient reply to cancel execution. FIG. 4 illustrates a part of the channel processing unit 206 according to another embodiment of the present invention. A part of the channel processing unit 206 in FIG. 4 includes a gain circuit 400, a multi-path feedback detector and signal quality monitor 402, a multi-combination unit 404, a reply canceller 406, and a MUX 408. The various combination units 404 and MUX 408 receive I Γ, Q Γ and 12 ·, Q2 · via the wires 202 and 204. The multiple combining unit 404 supplies a combined signal to the MUX 408 via a wire 422. The gain circuit 400 supplies a gain adjustment signal to the multi-path response detector and the signal quality monitor 402 via a lead 416. The MUX 408 receives a control signal from the control circuit 112, and provides IΓ and Q1 * via a wire 412, and I21 and Q2 · via a wire 414, or supplies a combined signal from the 422 to the wire 412. In the latter case, no signal is provided to the wire 414; or, in another embodiment, in addition to combining signals, one of I1, Q1, and 12, and Q2, may be provided to the wire 414. Gain circuit -16-This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 582141 A7 __ B7 ____ 5. Description of the invention (13) is also coupled to the reply canceller 406 via the wire 416. The multipath reply detector and signal quality monitor 402 are coupled to the reply canceller 406 via wires 410 and 418. The reply canceller 406 provides outputs Icomb and Qcomb via the wire 208, and the gain circuit 400 provides outputs Ibypass and Qbypass via the wire 210. The lead 138 provides control signals from the control circuit 112 to and from the gain circuit 400, the multi-path feedback detector and the signal quality monitor 402, the multiple combination unit 404, the reply canceller 406, and the MUX 408. (Note that in the specific embodiment of FIG. 4, unlike the specific embodiment of FIG. 3, the multi-combination unit 404 does not receive gain adjustment inputs corresponding to IΓ, Q1, and 12, and Q2. Operationally, IΓ, Q1 may be processed in combination or separately via the channel processing unit 206. In the former case, the multi-combination unit 404 receives the signals I Γ, Q 1, 12, Q 2 via wires 202 and 204, and combines them so that a combined signal via MUX 408 via wire 412 via wire 412 Provided to the gain circuit 400. The gain circuit 400 provides a gain adjustment combination of II, Q1, and 12 ', Q 2' to the multi-path response detector 4002 via the lead 416. The multi-path reply detector 402 may determine whether or not the reply from the multi-path elements of the antennas 102 and 104 causes a greater than a predetermined reply threshold. If the reply exceeds this predetermined threshold, the multi-path reply detector 402 allows the reply canceller 40 to execute the reply of receiving the signal from the gain circuit 400 via the lead 41 through the lead 4106. The signal output from the reply canceller 406 is fed back to the multi-path reply detector 402 via the wire 418. The multi-path reply detector and the signal quality monitor 402 can decide whether the reply canceller 406 cancels a sufficient reply so that the reply falls below a predetermined reply threshold. If the reply level is lower than the predetermined -17-This paper size applies to China National Standard (CNS) A4 (210X 297 public love)
裝 訂Binding
582141 A7 __B7 五、i明説明(14 ) ' " 臨界值’那麼信號品質是足夠,而且回信消除器4〇6可經由 導線208輸出組合信號Icomb、Qcomb。然而,如果回信仍 然超越預定臨界值,信號便可經由回信消除器406反覆處 理,直到透過多路徑回信偵測器與信號品質監督器4〇2判斷 為足夠信號品質為止(例如低於預定回信臨界值)。如果足 夠,回信消除器406便經由導線208輸出最後的信號1(:〇1^、 Qcomb 0 回#消除器4 0 6可使用回信取消的任何方法,以提供信號 Icomb、Qcomb。例如,在需要固定振幅的一 FM無線電信 號情況’一固定係數演算法(CM A)適用於回信消除器406。 即疋’回k消除器4 0 6是一適當的信號處理單元,以用來執 行回信取消。另一具體實施例可使用最少均方根回信取消 (LMS )、回覆取小平方回#取消(rlS )、或任何其他適當 演算法。因此,可使用多種回信消除器,其是因處理的信 號而定。 如果 ΙΓ、Q1’和 12’、Q2’未組合,II,、Qi,和 12,、q2•能 經由導線202和204提供給MUX 408(多路多樣組合單元 404)。一控制信號係經由在控制電路112之間來回的控制信 號而镇合到MUX 408。因此’如果信號ip、Qr或12,、 Q2,之一需要不組合,MUX 408便可將II,、,和12,、Q2, 之一輸出給導線412,及將II’、Q1,和12,、Q2·的另一輸出 給導線414。兩信號之中的每一信號可獲得調整的增益及輸 出給導線416和210。導線416是經由回信消除器4〇6(在此情 況,是透過經由導線410的控制信號而關閉)並且是當作 -18 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 582141 A7 B7 五、發明説明(15 )582141 A7 __B7 5. If I clearly state (14) '" critical value', then the signal quality is sufficient, and the echo canceller 406 can output the combined signals Icomb and Qcomb via the wire 208. However, if the reply still exceeds the predetermined threshold, the signal can be repeatedly processed by the reply canceller 406 until it is judged that the signal quality is sufficient through the multi-path reply detector and the signal quality monitor 402 (for example, below the predetermined reply threshold). value). If it is sufficient, the reply canceller 406 outputs the last signal 1 (: 〇1 ^ 、 Qcomb 0 回 #eliminator 4 06) via the wire 208. Any method of reply cancellation can be used to provide the signals Icomb, Qcomb. For example, when needed A fixed-amplitude FM radio signal case 'a fixed coefficient algorithm (CM A) is applicable to the reply canceller 406. That is, the' back-k canceller 406 'is an appropriate signal processing unit for performing reply cancellation. Another embodiment may use least root-mean-square reply cancellation (LMS), reply to small square reply #cancel (rlS), or any other appropriate algorithm. Therefore, multiple reply cancellers may be used, which are due to processed signals If IΓ, Q1 'and 12', Q2 'are not combined, II, Qi, and 12, and q2 can be provided to MUX 408 (multiple multiple combination unit 404) via wires 202 and 204. A control signal It is coupled to the MUX 408 via a control signal back and forth between the control circuits 112. Therefore, 'If one of the signals ip, Qr or 12, and Q2, need not be combined, the MUX 408 can combine II, ,, and 12, One of Q2, Q2, is output to wire 412, The other of II ', Q1, and 12, and Q2 · are output to the lead 414. Each of the two signals can obtain an adjusted gain and output to the leads 416 and 210. The lead 416 is passed through the echo canceller 4. 6 (in this case, it is closed by a control signal via wire 410) and it is treated as -18-This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 582141 A7 B7 V. Description of the invention ( 15)
Icomb的輸出,且經由導線208當作Icomb、Qcomb輸出。 增益電路400的另一輸出是經由導線210提供輸出Ibypass、 Qbypass。因此,如果不需要信號組合,增益調整11*、Q Γ 是當作Icomb、Qcomb和Ibypass、Qbypass輸出,而且增益 調整 12’、Q2’是以 Icomb、Qcomb 和 Ibypass、Qbypass 之另 一者輸出。此允許一或多個信號的選擇旁路多樣組合單元 404。如上述,此在不同類型或範圍信號想要的情況是很有 用。在此具體實施例中,Icomb、Qcomb和Ibypass、 Qbypass是未組合信號。或者,雖然一未組合信號(例如 11’、Q Γ 或 12’、Q2’)能以 Icomb、Qcomb 或 Ibypass、 Qbypass提供。即是,如果只想要一信號,兩信號不需要傳 輸。在仍然另一具體實施例中,一組合信號能以Icomb、 Qcomb提供,而且單一(未組合)信號(例如I Γ、Q Γ或 12·、Q2’)能以Ibypass、Qbypass提供。因此,在圖3和4具 體實施例的一旁路信號可用來選取頻道處理單元206的輸出 是否為一組合或未組合信號。此旁路信號可以是例如MUX 308與MUX 408的控制信號。因此,在一具體實施例中,旁 路信號可在控制電路112中產生。然而,另一具體實施例能 以多種不同方式產生及利用一旁路信號、或複數個旁路信 號。 圖5係根據本發明的具體實施例而分別描述圖3和4的一部 分多樣組合單元304和404。因此,圖5的電路可使用在圖3 和圖4描述的具體實施例、或視需要的任何其他具體實施 例。注意,如果圖5的電路是使用在圖3的具體實施例, -19 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 582141 A7 __B7 五、發明説明(~16 ) ^~ I Γ、Q 1·和12’、Q2’可視為信號的増益調整版本;然而, 既然增益電路400係下游耦合到多樣組合單元4〇4,所以如 果圖5的電路是使用在圖4的具體實施例,1丨,、q〗,和12,、 Q2W更不視為信號的增益調整版本。圖5包括解多工器 (DEMUX) 500和504、加權因素決定電路5〇2、乘法器508、 510、512、和514、加法器510、與相位評估電路50ό。 DEMUX 500係經由導線518和52〇而耦合到加權因素決定電 路502、乘法器508、與乘法器51〇。DEMUX 504係經由導 線522和524而耦合到加權因素決定電路5〇2、乘法器51〇、 與乘法器514。加權因素決定電路5〇2係經由導線526而將 W1提供給乘法器508,及經由導線528而將W2提供給乘法 器512。相位評估電路506係經由導線530和532而耦合到乘 法器510,而且經由導線W8而將相位修正1及經由導線540 而將相位修正2提供給乘法器5 12,且該乘法器係經由導線 542和544而耦合到乘法器514。加法器516係經由導線534和 536耦合到乘法器508,及經由導線546和548耦合到乘法器 514。加法器516係經由導線318或422而提供輸出I、Q,其 是因具體實施例而定。DEMUX 500是經由導線314或414接 收I1’、Q1’,其是因具體實施例而定,而且DEMUX 504是 經由導線316或416接收12,、Q2,,其是因具體實施例而 定。 操作上,DEMUX 500是經由導線314或202接收II,、 Qr,其是因具體實施例而定,及經由導線520輸出ΙΓ與經 由導線51 8輸出Q1,。注意,II·是是代表複數信號的實數部 -20 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 582141The output of Icomb is treated as Icomb and Qcomb via the wire 208. Another output of the gain circuit 400 is to provide the outputs Ibypass and Qbypass via the wire 210. Therefore, if no signal combination is needed, the gain adjustments 11 * and Q Γ are output as Icomb, Qcomb and Ibypass and Qbypass, and the gain adjustments 12 ’and Q2’ are output as the other of Icomb, Qcomb, Ibypass, and Qbypass. This allows selection of one or more signals to bypass the multiple combining unit 404. As mentioned above, this is useful in situations where different types or ranges of signals are desired. In this specific embodiment, Icomb, Qcomb and Ibypass, Qbypass are uncombined signals. Alternatively, although an uncombined signal (e.g. 11 ', Q Γ or 12', Q2 ') can be provided as Icomb, Qcomb or Ibypass, Qbypass. That is, if only one signal is desired, two signals need not be transmitted. In still another specific embodiment, a combined signal can be provided by Icomb, Qcomb, and a single (uncombined) signal (such as I Γ, Q Γ, or 12 ·, Q2 ') can be provided by Ibypass or Qbypass. Therefore, a bypass signal in the specific embodiments of FIGS. 3 and 4 can be used to select whether the output of the channel processing unit 206 is a combined or uncombined signal. This bypass signal may be a control signal of MUX 308 and MUX 408, for example. Therefore, in a specific embodiment, the bypass signal may be generated in the control circuit 112. However, another embodiment can generate and utilize a bypass signal, or a plurality of bypass signals in a number of different ways. Fig. 5 illustrates a part of the various combination units 304 and 404 of Figs. 3 and 4, respectively, according to a specific embodiment of the present invention. Therefore, the circuit of FIG. 5 may use the specific embodiment described in FIGS. 3 and 4, or any other specific embodiment as required. Note that if the circuit of FIG. 5 is used in the specific embodiment of FIG. 3, -19-This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 582141 A7 __B7 V. Description of the invention (~ 16) ^ ~ I Γ, Q 1 · and 12 ′, Q2 ′ can be regarded as the beneficial adjustment versions of the signal; however, since the gain circuit 400 is coupled downstream to the multiple combination unit 4O4, if the circuit of FIG. 5 is used in FIG. 4 In a specific embodiment, 1 ′, q ′, and 12 ′, Q2W are not regarded as a gain adjustment version of the signal. FIG. 5 includes demultiplexers (DEMUX) 500 and 504, a weighting factor determination circuit 502, multipliers 508, 510, 512, and 514, an adder 510, and a phase evaluation circuit 50o. The DEMUX 500 is coupled to the weighting factor determining circuit 502, the multiplier 508, and the multiplier 51 via wires 518 and 52. DEMUX 504 is coupled to weighting factor decision circuit 502, multiplier 51, and multiplier 514 via wires 522 and 524. The weighting factor determining circuit 502 supplies W1 to the multiplier 508 via the wire 526, and supplies W2 to the multiplier 512 via the wire 528. The phase evaluation circuit 506 is coupled to the multiplier 510 via the wires 530 and 532, and provides the phase correction 1 via the wire W8 and the phase correction 2 to the multiplier 5 12 via the wire 540. The multiplier is via the wire 542. And 544 are coupled to the multiplier 514. Adder 516 is coupled to multiplier 508 via leads 534 and 536, and to multiplier 514 via leads 546 and 548. The adder 516 provides the outputs I, Q via the wires 318 or 422, depending on the specific embodiment. DEMUX 500 receives I1 ', Q1' via wires 314 or 414, which depends on the specific embodiment, and DEMUX 504 receives 12, Q2, via wires 316 or 416, which depends on the specific embodiment. In operation, the DEMUX 500 receives II, Qr via the lead 314 or 202, which is determined by the specific embodiment, and outputs IΓ via the lead 520 and Q1 via the lead 5118. Note that II · is the real number part representing the complex signal -20-This paper size applies to China National Standard (CNS) A4 (210X297 mm) 582141
分’而Q1’是代表複數信號的虛數部分。即是,qi,是與 Π, 90度非同相位。而且,DEMUX 5〇4是經由導線316或 204接收12’、Q2,,其是因具體實施例而定,且經由導線 524輸出12,及經由導線522輸出Q2,。如前述,12,是代表複 數信號12,、Q2,的實數部分,且q2,是代表複數信號的虛數 部分。(注意,例如II,、Q1,和12,、Q2,的每個信號能以分 別例如11,+ j Q1,和ί 2,+ j Q 2,的一複數形式表示) ir、Qi·、12,、和Q2,是提供給加權因素決定電路5〇2 , 以根據例如每個輸入信號Ir、Q1,和12,、Q2,的振幅或功 率而計算加權因素。此電路將在圖7和17進一步描述。因 此,加權因素決定電路502可經由導線526而將W1(I1,、 Q1·的加權因素)輸出給乘法器528 ,及經由導線5〇8而將 W2(I2’、Q2*的加權因素)輸出給乘法器512。加權因素決 定電路502是根據對應π’、Q1’和12,、Q2,之中至少一者的 信號特性而決定加權因素W1和W2〇另一具體實施例可根 據對應I Γ、Q Γ和12·、Q 2·的信號特性而決定w 1和W2。信 號特性可視為k號的振幅、功率、或任何其他適當特性。 此外,信號特性的任何組合可用來決定加權因素。乘法器 510 可接收 II’、Q1·和 12’、Q2,,及將 II,、Qi,與 12,、Q2, 相乘。此計算可擷取在這兩信號之間的相位差資訊,及經 由導線530和532而將它傳遞給相位評估電路506。 相位評估電路506是使用當作參考的I 1 ’、q 1,而計算在信 號ΙΓ、QT與12’、Q2’之間的相位差。然後,相位差是經 由導線538而將當作相位修正1輸出給乘法器5 12,及經由導 -21 - 本紙張尺度適用中國國家標準(CNS) A4規格(21〇 x 297公釐) 582141 A7 ___B7 五、發明説明1 ~~^ 線540而將相位修正2輸出給乘法器5 12。此相位差是經由連 接器528而透過W2決定大小,而且經由導線542和544提供 給乘法器514。乘法器514是經由導線522和524接收12,、 Q2’,及將它乘以乘法器512的結果。因此,514的輸出是經 由導線546和548提供給加法器516。乘法器508是將η·、 Q 1 ’乘以W 1 ’如此可使用例如比例決定因素w 1的信號功率 與振幅的信號特性。乘法器508的結果是經由導線534和 536而供應給加法器516。因此,最後組合信號I、q能經由 導線3 1 8或422提供,此是因具體實施例而定。方程式與計 算可參考圖6的流程圖而更了解。 圖6係根據本發明的具體實施例而描述圖5的多樣組合操 作單元304 ' 404的操作。在方塊6〇2 , n,、Q1,和I2,、Q2, 可被接收。在方塊604 ,加權因素w !和W2是根據對應 ΙΓ、Q1’和12’、Q2’之中至少-者的至少_信號特性而決 定。例如,在一具體實施例中,功率能以用來決定w i和 W2的信號特性選取,其中W1是等於或與n,、卩丨,乘方的 平方根值成比例,且W2是等於或與12,、Q2,乘方的平方根 值成比例。,王意,在一具體實施例中,功率或振幅是根據 有用信號與系統雜訊的組合效果來計#,而且不嘗試將雜 訊影響從有用信號m在,的具體實施例中,加權因素 決定電路502可評估ΙΓ、Q1,的功率(pl)m2,、Q2,的功率 (P2),其中昨斤和W2=况。或者,選取振幅,其中们 和2是II Qi或12、q2,、或兩者的振幅函數。因此, 在此具體實施例中,加權因素決定電路5〇2可評估n,、 -22 -Divide 'and Q1' is the imaginary part of the complex signal. That is, qi is out of phase with Π, 90 degrees. Furthermore, DEMUX 504 receives 12 ', Q2 via the lead 316 or 204, which is determined by the specific embodiment, and outputs 12 via the lead 524, and Q2 via the lead 522. As mentioned above, 12 is the real part of the complex signal 12, Q2, and q2 is the imaginary part of the complex signal. (Note that each signal such as II, Q1, and 12, Q2, can be represented in a plural form such as 11, + j Q1, and ί 2, + j Q 2, respectively.) Ir, Qi ·, 12 ,, And Q2 are provided to the weighting factor determining circuit 502 to calculate the weighting factor based on, for example, the amplitude or power of each of the input signals Ir, Q1, and 12, Q2. This circuit will be further described in FIGS. 7 and 17. Therefore, the weighting factor determining circuit 502 can output W1 (the weighting factor of I1, Q1 ·) to the multiplier 528 via the wire 526, and output W2 (the weighting factor of I2 ', Q2 *) via the wire 508. Gives the multiplier 512. The weighting factor determining circuit 502 determines the weighting factors W1 and W2 according to the signal characteristics of at least one of π ′, Q1 ′ and 12, and Q2. Another specific embodiment may be based on the corresponding I Γ, Q Γ, and 12 ·, Q 2 · determine w 1 and W 2. The signal characteristic can be considered as the amplitude, power, or any other appropriate characteristic of the k signal. In addition, any combination of signal characteristics can be used to determine the weighting factors. The multiplier 510 may receive II ', Q1, and 12', Q2, and multiply II ,, Qi, and 12 ,, Q2 ,. This calculation can capture the phase difference information between the two signals and pass it to the phase evaluation circuit 506 via the wires 530 and 532. The phase evaluation circuit 506 calculates the phase difference between the signals IΓ, QT and 12 ', Q2' using I 1 ', q 1 as references. Then, the phase difference is output as a phase correction 1 to the multiplier 5 12 via the wire 538, and via the -21-this paper size applies the Chinese National Standard (CNS) A4 specification (21〇x 297 mm) 582141 A7 ___B7 V. Description of the invention 1 ~~ ^ Line 540 and output phase correction 2 to the multiplier 5 12. This phase difference is determined by W2 through the connector 528 and is supplied to the multiplier 514 through the wires 542 and 544. The multiplier 514 receives 12, Q2 'via the wires 522 and 524, and multiplies the result by the multiplier 512. Therefore, the output of 514 is supplied to the adder 516 via the wires 546 and 548. The multiplier 508 multiplies η ·, Q 1 'by W 1'. Thus, for example, the signal characteristics of the signal power and amplitude of the scale determining factor w 1 can be used. The result of the multiplier 508 is supplied to the adder 516 via the wires 534 and 536. Therefore, the final combined signals I, q can be provided via the wires 3 1 8 or 422, depending on the specific embodiment. The equations and calculations can be better understood with reference to the flowchart in FIG. FIG. 6 illustrates the operations of the various combined operation units 304 '404 of FIG. 5 according to a specific embodiment of the present invention. At blocks 602, n, Q1, and I2, Q2, can be received. At block 604, the weighting factors w! And W2 are determined based on at least the signal characteristics of at least one of the corresponding IΓ, Q1 'and 12', Q2 '. For example, in a specific embodiment, the power can be selected according to the signal characteristics used to determine wi and W2, where W1 is equal to or proportional to the square root value of n ,, 卩 丨, the power, and W2 is equal to or equal to 12 , Q2, the square root of the power is proportional. Wang Yi, in a specific embodiment, the power or amplitude is calculated according to the combined effect of the useful signal and the system noise, and does not attempt to influence the noise from the useful signal m. In the specific embodiment, the weighting factor The decision circuit 502 can evaluate the power (pl) m2, and Q2, of the power (P2), of which the weight and W2 = condition. Alternatively, choose an amplitude where they and 2 are amplitude functions of II Qi or 12, q2, or both. Therefore, in this specific embodiment, the weighting factor determining circuit 502 can evaluate n ,, -22-
582141 A7 B7 五、發明説明(19 )582141 A7 B7 V. Description of the invention (19)
Ql’(AMPl)、與12,、Q2,(AMP2)的振幅。(信號特性的振 幅使用將在下圖17和18進一步描述。The amplitudes of Ql '(AMP1), and 12, and Q2, (AMP2). (The amplitude characteristics of the signal characteristics are further described in Figures 17 and 18 below.
請即參考圖6,在方塊606,I Γ、Q Γ是乘以12,、Q2,的複 數結合。此可透過乘法器510執行。計算是以下式表示: 方程式 1 : (Il,+jQl,)·(I2,-jQ2,)=IM+jQM 在上述方程式,結果IM、QM信號的相位是以ej(ei^2) = ejAe形式表示,其中ePi係表示n,、Q1,的相位,^02係 表示12’、Q2’的相位,及ejw係表示n,、Q1,和12,、Q2,的 相位,且可進一步以下式表示: 方程式2 : ejA0 =cos(A9)+jsin(A0) 因此,在方塊608,相位差^^可被評估,其中圖5的相 位評估電路506的輸出是以兩信號表示:以c〇s(A0)表示的 相位修正1及以sin(Ae)表示的相位修正2 (其中相位修正ι 係表示實數部分,且相位修正2係表示相位差的虛數部 分)。 在方塊610 , 12·、Q2,是乘以相位差與W2,以獲得下面 方程式3顯示的結果。(此計算是透過乘法器512執行)。 方程式3 : W2 · ejAe · (I2,+jQ2,) 在方塊612,II,、Q1,是乘以W1,以獲得下面方程式4顯 示的結果。(此計算是透過乘法器5〇8執行)。 方程式 4 ·· W1 · (Il,+jQi,) 因此,在方程式3和4,评丨和〜2是分別當作每個對應信 號II’、Qi,*!2,、Q2,的加權因素功能,其中”丨和界2是 根據例如功率或振幅的信號特性。在方塊614 ’方塊的“ΟPlease refer to FIG. 6. At block 606, I Γ, Q Γ is a complex combination multiplied by 12 ,, Q2 ,. This can be performed through the multiplier 510. The calculation is expressed by the following equation: Equation 1: (Il, + jQl,) · (I2, -jQ2,) = IM + jQM In the above equation, the phase of the IM and QM signals is in the form of ej (ei ^ 2) = ejAe , Where ePi represents the phase of n, Q1, ^ 02 represents the phase of 12 ', Q2', and ejw represents the phase of n ,, Q1, and 12, Q2, and can be further expressed by the following formula : Equation 2: ejA0 = cos (A9) + jsin (A0) Therefore, at block 608, the phase difference ^^ can be evaluated, where the output of the phase evaluation circuit 506 of FIG. 5 is represented by two signals: Phase correction 1 indicated by A0) and phase correction 2 indicated by sin (Ae) (where phase correction ι is the real number part and phase correction 2 is the imaginary number part of the phase difference). At blocks 610, 12, and Q2, multiply the phase difference and W2 to obtain the result shown in Equation 3 below. (This calculation is performed by the multiplier 512). Equation 3: W2 · ejAe · (I2, + jQ2,) At block 612, II, and Q1, multiply by W1 to obtain the result shown in Equation 4 below. (This calculation is performed by the multiplier 508). Equation 4 ·· W1 · (Il, + jQi,) Therefore, in Equations 3 and 4, the comments 丨 and ~ 2 are used as weighting factors for each corresponding signal II ', Qi, *! 2, Q2, respectively. , Where “丨 and bound 2 are based on signal characteristics such as power or amplitude.
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582141 A7 ____B7 _ _^、發明説明(20 ) ' ' 和612結果的組合可獲得最後組合信號i、Q(能以i+jQ式子 表示)。此最後的計算可透過加法器5丨6執行,其中加法器 516是經由導線318或422提供輸出I、Q,此是因頻道處理 單元206的具體實施例而定。因此,方程式能以下式表示: 方程式 5 : I+jQ=W2 · ejA0 · (I2,+jQ2,)+Wl · (ir+jQr) 請即參考上面方程式5,方程式的第一項W2 · ejAe · (12, + jQ2·)是代表12’、Q2’相位移動在在II,、Q1,和12,、Q2,之 間的相位差,且加權是W 2。方程式的第二項W 1 ·( 11, +jQ 1 ’)代表I Γ、Q Γ是以它的加權因素W 1加權。在另一具 體實施例中,未使用加權因素。因此,方程式5將不包括兩 加權因素W1和W2,而且多樣組合單元不包括加權因素決 定電路502、或乘法器508和512。或者,除了信號功率或振 幅之外的其他加權因素可視需要使用。 圖7係圖5的一部分加權因素決定電路502的具體實施例。 電路是參考輸入II’和Q1’描述,其中相同說明與電路適用 於輸入12’、Q 2’。而且注意,在另一具體實施例中,用於 接收11 ’和Q Γ的電路能以劃時多工方式給12 ’和q 2,共用, 或整個電路(或其部分)可如圖7所述複製。在描述的具體實 &例中’對應I Γ、Q 1’的一部分加權因素決定電路502與斜 應Ϊ2’、Q 2,的一部分能以相同方式操作。大體上,加權因 素決定電路502包括信號特性值決定電路與加權值诀定電 路。前者可計算例如每個信號的功率或振幅的信號特性 值’而後者可使用信號特性值來計算W 1和W2。 關於輸入II’、和Q1’,加權因素決定電路5〇2包括經由導 -24 - 本紙張尺度適& S S家標準(CNS) A4規格(21GX 297公爱) "" 582141 A7 B7 ' ------- 五、發明説明( ) 線5 18接收ΙΓ的乘法器700、及經由導線746的1/Ν。乘法器 7〇2係經由導線52〇而搞合接收q丨,及經由導線746而轉合 1/Ν。乘法器700係耦合到加法器7〇4 ,,且該加法器係耦合 到延遲單元708與儲存電路712。乘法器7〇2係耦合到加法器 706 ’且该加法器706係鶴合延遲單元714與儲存電路718。 加法器720係轉合到儲存電路712和71 8、倒數平方根單元 722、與乘法器724。因此,加法器720是將I 1,、Q 1,的功率 ρ 1提供給反平方植根單元722與乘法器724。倒數平方根單 元722係耦合到乘法器724,而且乘法器724是經由導線526 挺供輸出W1。關於輸入12’、q 2,,加權因素決定電路5 〇2 包括·乘法器750、752、和770 ;加法器754、760、和 766,延遲單元756和762 ;儲存電路758和764 ;及倒數平方 根單元768 ’且是與分別乘法器7〇〇、702、和72〇、加法器 704、706、和720、延遲單元708和714、儲存電路712和 71 8、與倒數平方根單元722的相同方式輕合《因此,如圖7 所述’信號特性值決定電路78〇包括在乘法器7〇〇、7〇2、 750、和752與加法器72〇和766之間的電路。加權值決定電 路782包括乘法器724和77〇與倒數平方根單元722和768。 操作上’乘法器7〇〇的輸出是將值Qr2/N提供給加法器 704 ’其中N是代表用以隨時間收集輸入信號值的取樣數目 或自框大小。同樣地,乘法器7〇2的輸出可將值q丨》2/ n提供 給加法器706。加法器704與延遲單元708的功能如同一累加 器’以隨時間累加11’2/N的值。延遲單元708是接收重置信 號710 ’且根據Ir、q!,的取樣頻率分數fs/n而重新設定 -25 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 582141 A7 _____B7 五、發明説明(22 ). 延遲單元708。在重新設定延遲單元708之前,儲存電路712 係儲存類積值,及將此值提供給加法器72〇。同樣地,加法 器706與延遲單元714的功能如同一累加器,以隨時間累加 QP2/N的值。延遲單元714可接收重置信號716,以便根據582141 A7 ____B7 _ _ ^, invention description (20) '' and the combination of 612 results can obtain the final combined signal i, Q (can be expressed by the formula of i + jQ). This final calculation can be performed by the adder 5 6, where the adder 516 provides the outputs I, Q through the wires 318 or 422, which depends on the specific embodiment of the channel processing unit 206. Therefore, the equation can be expressed as follows: Equation 5: I + jQ = W2 · ejA0 · (I2, + jQ2,) + Wl · (ir + jQr) Please refer to Equation 5 above, the first term of the equation W2 · ejAe · (12, + jQ2 ·) represents the phase difference between the phases of 12 ′, Q2 ′ between II, Q1, and 12, Q2, and the weight is W 2. The second term of the equation W 1 · (11, + jQ 1 ′) represents I Γ, Q Γ is weighted by its weighting factor W 1. In another specific embodiment, no weighting factor is used. Therefore, Equation 5 will not include the two weighting factors W1 and W2, and the multiple combination unit will not include the weighting factor decision circuit 502, or the multipliers 508 and 512. Alternatively, other weighting factors besides signal power or amplitude can be used as needed. FIG. 7 is a specific embodiment of a part of the weighting factor determining circuit 502 of FIG. 5. The circuit is described with reference to inputs II 'and Q1', where the same descriptions and circuits apply to inputs 12 ', Q 2'. Also note that in another specific embodiment, the circuit for receiving 11 ′ and Q Γ can be given to 12 ′ and q 2 in a time-division multiplexing manner, shared, or the entire circuit (or part thereof) may be as shown in FIG. 7 Mentioned replication. In the concrete example described, a part of the weighting factor decision circuit 502 corresponding to I Γ, Q 1 'can operate in the same manner as a part of the diagonal response 斜 2', Q 2. Generally, the weighting factor determining circuit 502 includes a signal characteristic value determining circuit and a weighting value determining circuit. The former can calculate, for example, the signal characteristic value 'of the power or amplitude of each signal, and the latter can use the signal characteristic values to calculate W 1 and W 2. Regarding the inputs II 'and Q1', the weighting factor determining circuit 502 includes a guide -24-the paper size is suitable & SS home standard (CNS) A4 specification (21GX 297 public love) " " 582141 A7 B7 ' ------- 5. Description of the invention () Line 5 18 receives a multiplier 700 of IΓ, and 1 / N via line 746. The multiplier 702 is coupled to receive q1 through the wire 52, and is turned 1 / N through the line 746. The multiplier 700 is coupled to the adder 704, and the adder is coupled to the delay unit 708 and the storage circuit 712. The multiplier 702 is coupled to an adder 706 ', and the adder 706 is a combination of a delay unit 714 and a storage circuit 718. The adder 720 is coupled to the storage circuits 712 and 71, the inverse square root unit 722, and the multiplier 724. Therefore, the adder 720 supplies the power ρ 1 of I 1, Q 1, to the inverse square rooting unit 722 and the multiplier 724. The reciprocal square root unit 722 is coupled to the multiplier 724, and the multiplier 724 is supplied to the output W1 via the lead 526. With regard to the inputs 12 ', q2, the weighting factor determining circuit 5 includes: multipliers 750, 752, and 770; adders 754, 760, and 766; delay units 756 and 762; storage circuits 758 and 764; and inverse numbers The square root unit 768 ′ is the same as the multipliers 700, 702, and 72, the adders 704, 706, and 720, the delay units 708 and 714, the storage circuits 712 and 71, and the inverse square root unit 722, respectively. "Light-on" Therefore, as shown in FIG. 7, the signal characteristic value determination circuit 78o includes a circuit between the multipliers 700, 702, 750, and 752 and the adders 72o and 766. The weight determination circuit 782 includes multipliers 724 and 770 and inverse square root units 722 and 768. Operationally, the output of the multiplier 700 is to provide the value Qr2 / N to the adder 704 ', where N is the number of samples or self-frame size used to collect the input signal value over time. Similarly, the output of the multiplier 702 may provide the value q | >> 2 / n to the adder 706. The adder 704 and the delay unit 708 function as the same accumulator 'to accumulate the value of 11'2 / N over time. The delay unit 708 receives the reset signal 710 'and resets it according to the sampling frequency fraction fs / n of Ir, q !, -25-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 582141 A7 _____B7 V. Description of the invention (22). Delay unit 708. Before resetting the delay unit 708, the storage circuit 712 stores a class product value and supplies this value to the adder 72. Similarly, the adder 706 functions as the same accumulator as the delay unit 714 to accumulate the value of QP2 / N over time. The delay unit 714 may receive the reset signal 716 so that
Fs/N而將延遲單元714重新設定。在重新設定延遲單元714 <前,儲存電路71 8可儲存累加值,及將此值提供給加法器 720。因此,重置信號71〇和716通常是使用對應Fs/N的相 同率;同樣地,儲存電路712和718是以對應重置信號710和 716的相同率計時,如此可隨時間補捉累加值。因此,N可 適當調整,為了要改變累加值的窗框大小(亦即使用的取樣 數)。 加法器720是將來自儲存電路712的I i,2/n累加值與來自 儲存電路718的Ql,2/N累加值組合,以獲得pi : 方程式6 : pl= Y (^7* + ^—) = /1,2+β1,2 卜 ν Ν· Ν 在上述方程式6,j是與Fs有關的非連續取樣數值。因 此’ Pi值是每Fs/N計算。此結果pi是提供給乘法器724和 倒數平方根單元722。反平方根單元722的結果是在下面方 程式7顯示《倒數平方根單元722能以以各種不同方式實 施’例如執行計算的硬體電路、在記憶嵌入的一狀態機 器、軟體常式等。 方程式7: J__ 1 A® Α4規格(21〇Χ297公爱) ____— - 26 - 582141 A7Fs / N and the delay unit 714 is reset. Before resetting the delay unit 714 <, the storage circuit 7118 may store the accumulated value and provide the value to the adder 720. Therefore, the reset signals 71 and 716 usually use the same rate corresponding to Fs / N; similarly, the storage circuits 712 and 718 are timed at the same rate corresponding to the reset signals 710 and 716, so that the accumulated value can be supplemented over time. . Therefore, N can be adjusted appropriately in order to change the window frame size of the accumulated value (that is, the number of samples used). The adder 720 combines the I i, 2 / n accumulation value from the storage circuit 712 and the Ql, 2 / N accumulation value from the storage circuit 718 to obtain pi: Equation 6: pl = Y (^ 7 * + ^ — ) = / 1,2 + β1,2 ν ν Ν Ν In the above equation 6, j is a discontinuous sampling value related to Fs. Therefore, the value of Pi is calculated per Fs / N. This result pi is supplied to the multiplier 724 and the inverse square root unit 722. The result of the inverse square root unit 722 is shown in Equation 7 below. "The inverse square root unit 722 can be implemented in a variety of different ways, such as a hardware circuit that performs calculations, a state machine embedded in memory, a software routine, and so on. Equation 7: J__ 1 A® Α4 specification (21〇 × 297 public love) ____—-26-582141 A7
此,。果疋提供給乘法器724,其可將加法器720的輸出(方 程式6)乘以倒數平方根單元722的輸出(方程式了),以獲得 輸出W 1 ’方程式如下所示: 方程式10 : 相=方程式(方程式6-8)適用於12,、Q2,,其中II,的每個 發生疋使用12’取代,Qi,的每個發生可使用Q2,取代,而且 pi的每個發生可使用p2取代。因此,W2能以不式表示: 方程式 9 : = 因此’方程式6- 9係描述獲得一輸入信號功率所使用的一 計算範例。另一具體實施例可使用不同於圖7描述具體實施 例的電路或軟體執行。 圖17係描述使用振幅來決定wr和W2的加權因素決定電 路502的另一具體實施例。因此,圖17可取代加權因素決定 電路502的圖7使用,此是因所使用的具體實施例而定(例如 功率或振幅是否當作信號特性使用)。圖17包括信號特性值 決定電路1716,且該信號特性值決定電路包括振幅決定電 路1700與振幅決定電路1702。振幅決定電路1700是分別經 由導線518和520而接收ΙΓ和Q1,,而且振幅決定電路1702 是分別經由導線522和524而接收12’和Q 2’。振幅決定電路 1700是將AMP1提供給乘法累加電路1708,而且振幅決定電 -27 -本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 582141 A7 B7 五、發明説明(~24 ) ~' 路1702是將AMP2提供給乘法累加電路17〇8。控制電路17〇4 與移位電路1710係雙向耦合到乘法累加電路17〇8。乘法累 加電路1708是經由導線1712而提供Wi,及經由導線1714而 提供W2。因此,加權值決定電路1718包括控制電路 1704、乘法累加電路1708、與移位電路1710。 操作上,振幅決定電路1700是接收π,和Q1,,且輸出信 號的振幅AMP1。振幅可使用目前可用的標準方法計算,例 如透過使用II,2與Ql,2信號加總的平方根近似值。而且,振 幅決定電路1702可接收12,和q2,,及輸出信號的振幅 AMP2。此振幅能以前述相同方式計算。如下圖18的描述, 乘法累加電路1708可接收AMP1和AMP2,及產生加權因素 W1和W2。乘法累加電路1708亦包括儲存電路,用以儲存 任何需要的暫時值。控制電路17〇4與移位電路171〇可在乘 法累加電路1708之間來回提供及接收信號。控制電路 1704、乘法累加電路17〇8、與移位電路171〇可實施一部分 的狀態機器,以執行圖18討論的計算。 圖18係根據11’、q丨’和12’、Q2,的振幅而以流程圖形式描 述用以計算W 1和W2的一具體實施例。流程圖丨8〇〇是在方 塊1802開始,其中Ir、Q1,和12,、q2,可被接收。流程會 執行判斷菱形方塊1804,其中可決定n,、Q1,的振幅人“" 是否大於12’、Q2,的振幅AMP2。如果是如此,流程便會持 績執行方塊1813,其中AMP1和AMP2是選擇性比例決定。 然後’流程會持續執行方塊丨8丨4,其中w 1是設定成預定 值。預定數目係表示用於貿〗的預設值。因此,在一具體實 -28 - i紙張尺度適财國@家標準(CNS) A4規格(21GX297公爱) 582141 A7 _____B7 _ 五、發明説明(25 ) 施例中,預定值是小於或等於0.5。透過使用小於或等於0.5 的一預定值可確保最後組合信號的振幅(即是11,、Q丨,與 12'、Q21組合)不超過值1。然後,流程會持續執行方塊 1816 ’其中振幅倒數丨/AMPl可決定。此可透過使用例如一 查表的標準技術執行。在方塊1818,W2的計算是AMP2與 AMP1比率的一半(參考上面方程式1)。注意,在此方程式 描述的0.5是上述的預定值;因此,如果一不同值被選取, 例如0.4,那麼〇.5將可使用0.4取代。 在判斷形方塊1804,如果AMP1不大於AMP2,流程便執 行方塊1805,其中AMP1和AMP2是選擇性比例決定。流程 會執行方塊1806,W2是設定成通常小於會等於0.5的一預 定值’例如,0.5。此預定值是如上面方塊1814的描述。流 程然後持續方塊1808,其中振幅倒數1/A MP2可決定。如前 述’此可使用例如一查表的標準技術執行。在方塊1 8 10, W1是以AMP1與AMP2比率的一半計算(參考上面方程式 2) °再者注意,在此方程式描述的〇·5是上面方塊18〇6討論 的預定值;因此,如果一不同值選取,此不同值將可使用 〇·5取代。因此,另一具體實施例可利用在AMP1與AMP2之 間的其他比率來決定W1和W2。而且,另一具體實施例是 在執行計算決定例如W 1與W2的加權因素(例如參考選擇性 方塊1805和1813)之前,先使用比例因素將振幅(例如AMP 1 和A MP2)依比例決定因素。然而,依比例決定因素是可選 擇;或者可設定成1。因此,加權因素可能下式表示: 如果 AMP1>AMP2 : -29 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 582141 A7 B7 五、發明説明(26 ) 方程式 10a : Wl = 0.5 方程式 11a: W2 = AMP2 · 0.5 · 1 AMP\ 如果AMP1 < AMP2 : 方程式 10b : W2=0.5 方程式 1 lb : W 1 = AMP1 · 0.5 · 1 AMP2 注意,例如W1和W2的加權因素是每一信號或.信號任何 組合的函數。而且,除了在此這些之外,許多不同加權因 素可使用。例如,在現階段可使用的系統中,只有信號·雜 訊(SNR)比是當作加權因素使用。然而,使用SNR方法從 電路觀點是昂貴的,如此會增加系統價格。此外,在使用 SNR方法的這些系統中的加權因素是複數(即是他們是因信 號的相位而定)。然而,本發明的具體實施例不利用snr來 決足加權因素,而是利用例如振幅、功率等的其他信號特 性來達成一更多成本的有效解決。而且,在此討論(wi* W2)的加權因素是數量因素。即是,他們是與相位無關。 他們可以是與相位無關,因為一相位計算或評估是個別執 行,而且是與數量加權因素使用,以組合輸入信號,且將 在下面更詳細說明。如上述,另一具體實施例包括只超過 兩輸入信號;因此,具有超過兩加權因素,且亦是因一或 多個信號特性而定。在一些具體實施例中,這些加權因素 亦是選擇性。例如,只有一些輸入信號可使用加權因素。’、 圖8係描述一部分乘法器51〇與一部分相位評估電路5〇6。 乘法器510包括耦合到加法器8〇4的乘法器8〇〇與乘法器 802,且該加法器804係耦合乘法器812 ^乘法器51〇是進一 -30 -this,. The result is provided to the multiplier 724, which can multiply the output of the adder 720 (equation 6) by the output of the reciprocal square root unit 722 (equation) to obtain the output W 1 'The equation is as follows: Equation 10: Phase = Equation (Equation 6-8) applies to 12, and Q2, where each occurrence of II ′ is replaced by 12 ′, each occurrence of Qi ′ can be replaced by Q2, and each occurrence of pi can be replaced by p2. Therefore, W2 can be expressed as: Equation 9: = Therefore, Equation 6-9 describes a calculation example used to obtain an input signal power. Another embodiment may be implemented using circuitry or software different from the embodiment described in FIG. FIG. 17 illustrates another embodiment of the weighting factor determining circuit 502 using amplitudes to determine wr and W2. Therefore, FIG. 17 may be used instead of FIG. 7 of the weighting factor determining circuit 502, which is determined by the specific embodiment used (for example, whether power or amplitude is used as a signal characteristic). FIG. 17 includes a signal characteristic value determination circuit 1716, and the signal characteristic value determination circuit includes an amplitude determination circuit 1700 and an amplitude determination circuit 1702. The amplitude determination circuit 1700 receives IΓ and Q1 via wires 518 and 520, respectively, and the amplitude determination circuit 1702 receives 12 'and Q 2' via wires 522 and 524, respectively. The amplitude determination circuit 1700 is to provide AMP1 to the multiply accumulate circuit 1708, and the amplitude determination circuit is -27.-This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 582141 A7 B7 V. Description of the invention (~ 24) ~ The way 1702 is to provide AMP2 to the multiply accumulate circuit 1708. The control circuit 170 and the shift circuit 1710 are bidirectionally coupled to the multiply-accumulate circuit 170. The multiply-accumulate circuit 1708 provides Wi via a wire 1712 and W2 via a wire 1714. Therefore, the weight value determination circuit 1718 includes a control circuit 1704, a multiply-accumulate circuit 1708, and a shift circuit 1710. In operation, the amplitude determination circuit 1700 receives π, and Q1, and outputs the amplitude AMP1 of the signal. Amplitude can be calculated using standard methods currently available, for example, by using the sum of square roots of the II, 2 and Ql, 2 signals. Moreover, the amplitude determination circuit 1702 can receive 12, and q2, and the amplitude AMP2 of the output signal. This amplitude can be calculated in the same way as before. As described in FIG. 18 below, the multiply-accumulate circuit 1708 can receive AMP1 and AMP2 and generate weighting factors W1 and W2. The multiply accumulate circuit 1708 also includes a storage circuit for storing any needed temporary values. The control circuit 1704 and the shift circuit 1710 can provide and receive signals back and forth between the multiply-accumulate circuit 1708. The control circuit 1704, the multiply-accumulate circuit 1708, and the shift circuit 1710 may implement a part of the state machine to perform the calculations discussed in FIG. Fig. 18 is a flow chart describing a specific embodiment for calculating W 1 and W 2 based on the amplitudes of 11 ', q 丨' and 12 ', Q2 ,. Flowchart 800 starts at block 1802, where Ir, Q1, and 12, and q2 can be received. The process will execute a judgment diamond 1804, which can determine whether the amplitude of n, Q1, is greater than the amplitude AMP2 of 12 ', Q2 ,. If so, the process will continue to execute block 1813, of which AMP1 and AMP2 It is a selective ratio decision. Then the process will continue to execute blocks 丨 8 丨 4, where w 1 is set to a predetermined value. The predetermined number indicates a preset value for trade. Therefore, in a specific embodiment -28-i Paper size is suitable for wealth country @ 家 standard (CNS) A4 specification (21GX297 public love) 582141 A7 _____B7 _ V. Description of the invention (25) In the embodiment, the predetermined value is less than or equal to 0.5. By using a predetermined value less than or equal to 0.5 The value can ensure that the amplitude of the last combined signal (that is, 11, 11, Q 丨, combined with 12 ', Q21) does not exceed the value 1. Then, the flow continues to execute block 1816' where the inverse amplitude 丨 / AMPl can be determined. This can be determined by Performed using standard techniques such as a look-up table. At block 1818, the calculation of W2 is half the ratio of AMP2 to AMP1 (refer to Equation 1 above). Note that 0.5 described in this equation is the predetermined value described above; therefore, if a different If it is selected, for example, 0.4, then 0.5 will be replaced by 0.4. In the judgment block 1804, if AMP1 is not greater than AMP2, the process will execute block 1805, where AMP1 and AMP2 are determined by the selectivity ratio. The process will execute block 1806, W2 is set to a predetermined value that is usually less than 0.5 ', for example, 0.5. This predetermined value is as described in block 1814 above. The process then continues to block 1808, where the amplitude reciprocal 1 / A MP2 can be determined. As previously described' this may It is performed using standard techniques such as a look-up table. At blocks 1 8 10, W1 is calculated as half the ratio of AMP1 to AMP2 (refer to Equation 2 above). Also note that 0.5 described in this equation is Box 18 above. The predetermined value discussed in 6; therefore, if a different value is selected, this different value will be replaced by 0.5. Therefore, another specific embodiment may use other ratios between AMP1 and AMP2 to determine W1 and W2. Another specific embodiment is to use a proportionality factor (such as AMP 1 and A) before performing calculations to determine weighting factors such as W 1 and W 2 (for example, refer to the selectivity blocks 1805 and 1813). MP2) is determined by the ratio. However, the ratio is determined by the option; or it can be set to 1. Therefore, the weighting factor may be expressed as follows: If AMP1 > AMP2: -29-This paper standard applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 582141 A7 B7 V. Description of the invention (26) Equation 10a: Wl = 0.5 Equation 11a: W2 = AMP2 · 0.5 · 1 AMP \ If AMP1 < AMP2: Equation 10b: W2 = 0.5 Equation 1 lb: W 1 = AMP1 · 0.5 · 1 AMP2 Note that the weighting factors such as W1 and W2 are a function of each signal or any combination of signals. Moreover, besides these, many different weighting factors can be used. For example, of the systems available at this stage, only the signal-to-noise (SNR) ratio is used as a weighting factor. However, using the SNR method is expensive from a circuit point of view, which increases the price of the system. In addition, the weighting factors in these systems using the SNR method are complex numbers (that is, they depend on the phase of the signal). However, the specific embodiment of the present invention does not use snr to determine the weighting factors, but uses other signal characteristics such as amplitude and power to achieve an effective solution with more cost. Moreover, the weighting factor discussed here (wi * W2) is a quantitative factor. That is, they are independent of phase. They can be phase independent because a phase calculation or evaluation is performed individually and is used with a quantity weighting factor to combine the input signals and will be explained in more detail below. As mentioned above, another specific embodiment includes only more than two input signals; therefore, it has more than two weighting factors and is also dependent on one or more signal characteristics. In some embodiments, these weighting factors are also selective. For example, only some input signals can use weighting factors. Fig. 8 illustrates a part of the multiplier 51 and a part of the phase evaluation circuit 506. The multiplier 510 includes a multiplier 800 and a multiplier 802 coupled to the adder 804, and the adder 804 is coupled to the multiplier 812. The multiplier 51 is further advanced by -30-
A7 B7 五、發明説明(27 ) 、土匕括♦禺合到加法器810的乘法器_與乘法器_,且該加 係鶴合到乘法器⑴。乘法器812係镇合到乘法器 14與加法器816,❼且接收輸入1/N與增益謝。加法器㈣ 2摘合到延遲單元82G與儲存電路m,而且乘法器814係搞 否=加法器818,且該加法器818係耦合到延遲單元822與儲 存電路826。儲存電路S24係耦合到乘法器828,而且儲存電 路826係耦合到乘法器83〇。乘法器828和83〇是當作輸入提 供給加法器832 ,且該加法器832係耦合到倒數平方根單元 834。儲存電路824和826與倒數平方根單元係耦合到乘 法器836和838。乘法器836是經由導線538提供c〇s(Ae)的代 表輸出,且乘法器838是經由導線54〇提供3ίη(ΔΘ)的代表輸 出。 操作上,乘法器800、802、806、和808與加法器804和 810執行對應π’ .、q丨,乘以12,、q2•複數結合的計算。(參 考方程式3)因此,加法器804的輸出是計算結果的實數部分 IM,而且加法器810的輸出是計算結果的虛數部分qm ^相 位評估電路506是接收IM和QM,並且計算對應上面方程式 4所討論而能以表示的iM+jQM相位計算。在此相位係 表示在I Γ、Q 1,與12,、Q2,之間的相位差,且將I Γ、Q 1, 當作一參考信號使用。 乘法器812是接收IM,且將此此結合乘以1/N與增益 801,以便將它提供給加法器816。在一具體實施例中,增 益801是AMP1和AMP2的較大振幅的倒數(例如,如果 AMP2>AMP1,增益801將可設定成1/AMP2)。增益801能 -31 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 582141 A7 ____ B7________ 五、發明説明(28 ) 儘可能幫助維特較大信號〗丨,、Q丨,,而仍然保證計算不超 過設計所使用的選擇數字系統。(因此,注意,圖8使用的 QM和IM現可視為由增益8〇1調整的增益調整值。而且注 意增益801是選擇性或可設定成丨)。加法器8丨6、延遲單元 820、與儲存電路824的功能是在一時間窗框上累加I μ值。 再者’如上述,Ν是代表用以收集ΙΜ值的取樣數或窗框大 小。只要達成取樣頻率分數FS/n,延遲單元820和儲存電 路824便可被重置,其中F s係對應輸入信號(例如I Γ、Q 1,) 的取樣頻率。即是,每次採用經由F s和N決定的足夠數量 資料’值便可儲存在儲存電路824。因此,乘法器828可從 儲存電路824接收IM/N的累加值。相同分析適於qM。即 是’乘法器814是接收QM,並且將它乘以1/N與增益801, 並且將輸出提供給加法器81 8。加法器8 18、延遲單元822、 與儲存電路826的功能是類似一累加器,以便在一段時間上 累加QM/N的值。取樣數量是由fs和N決定。即是,在每 個第η個取樣(與取樣頻率Fs有關),在儲存電路826的值可 提供給乘法器830。 因此^法器828的輸出是以^5表示,且乘法器83〇的輸 出是以^表示。(注意,&和^係視為所定義時間 週期上的IM2和QM2平均值)。這些是提供給加法器832 , 且可將結果提供給倒數平方單元834。倒數平方根 單元834可如方程式12所示計算倒數平方根單元: 方程式12: -32 -A7 B7 V. Description of the invention (27), the multiplier _ and multiplier _ coupled to the adder 810, and the addition is coupled to the multiplier ⑴. The multiplier 812 is coupled to the multiplier 14 and the adder 816, and receives the input 1 / N and the gain. The adder ㈣ 2 is coupled to the delay unit 82G and the storage circuit m, and the multiplier 814 is not an adder 818, and the adder 818 is coupled to the delay unit 822 and the storage circuit 826. The storage circuit S24 is coupled to the multiplier 828, and the storage circuit 826 is coupled to the multiplier 83. Multipliers 828 and 83 are provided as inputs to an adder 832, and the adder 832 is coupled to an inverse square root unit 834. Storage circuits 824 and 826 are coupled to multipliers 836 and 838 and inverse square root units. The multiplier 836 provides a representative output of cos (Ae) via a wire 538, and the multiplier 838 provides a representative output of 3? (ΔΘ) via a wire 54. In operation, the multipliers 800, 802, 806, and 808 and the adders 804 and 810 perform calculations corresponding to π '., Q 丨, multiplied by 12 ,, q2 • complex. (Reference Equation 3) Therefore, the output of the adder 804 is the real part IM of the calculation result, and the output of the adder 810 is the imaginary part of the calculation result. The phase evaluation circuit 506 receives IM and QM, and the calculation corresponds to Equation 4 above. The phase in question can be calculated in terms of iM + jQM. Here, the phase system represents the phase difference between I Γ, Q 1, and 12, and Q2, and I Γ and Q 1 are used as a reference signal. The multiplier 812 receives the IM and multiplies this combination by 1 / N and the gain 801 to supply it to the adder 816. In a specific embodiment, the gain 801 is the reciprocal of the larger amplitude of AMP1 and AMP2 (for example, if AMP2 > AMP1, the gain 801 can be set to 1 / AMP2). Gain 801 energy-31-This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 582141 A7 ____ B7________ V. Description of the invention (28) Help Wit larger signal as far as possible 丨 丨, Q 丨, , While still guaranteeing that the calculations do not exceed the number system chosen for the design. (Therefore, note that the QM and IM used in Figure 8 can now be regarded as gain adjustment values adjusted by the gain 801. Also note that the gain 801 is selective or can be set to 丨). The functions of the adder 8, 6, the delay unit 820, and the storage circuit 824 are to accumulate the value of I μ on a time window frame. Furthermore, as described above, N is the number of samples or window frame size used to collect the IM value. As long as the sampling frequency fraction FS / n is reached, the delay unit 820 and the storage circuit 824 can be reset, where F s is the sampling frequency corresponding to the input signal (eg, I Γ, Q 1,). That is, each time a sufficient amount of data 'value determined by Fs and N is used, it can be stored in the storage circuit 824. Therefore, the multiplier 828 can receive the accumulated value of IM / N from the storage circuit 824. The same analysis is suitable for qM. That is, the 'multiplier 814 receives the QM, multiplies it by 1 / N and the gain 801, and supplies the output to the adder 818. The functions of the adder 818, the delay unit 822, and the storage circuit 826 are similar to an accumulator, so that the value of QM / N is accumulated over a period of time. The number of samples is determined by fs and N. That is, at each n-th sample (related to the sampling frequency Fs), the value in the storage circuit 826 can be supplied to the multiplier 830. Therefore, the output of the ^ multiplier 828 is represented by ^ 5, and the output of the multiplier 830 is represented by ^. (Note that & and ^ are treated as the average of IM2 and QM2 over a defined time period). These are provided to the adder 832, and the results may be provided to the inverse square unit 834. The inverse square root unit 834 can calculate the inverse square root unit as shown in Equation 12: Equation 12: -32-
582141582141
此結果是提供給乘法器836和838。乘法器836亦從儲存電 路824接收了兩,而且乘法器838是從儲存電路826接收^。 如此’如下面方程式丨3和14顯示的乘法器836和838結果係 表示在ΙΓ、Q1,與12,、Q2,之間相位差,且^,、Q1,是當 作參考信號使用。 方程式 13 : —_1[一 」im2 + qm2This result is provided to the multipliers 836 and 838. The multiplier 836 also receives two from the storage circuit 824, and the multiplier 838 receives from the storage circuit 826 ^. In this way, the results of the multipliers 836 and 838 as shown in the following equations 3 and 14 indicate the phase difference between Γ, Q1, and 12, Q2, and ^, Q1 are used as reference signals. Equation 13: —_1 [一》 im2 + qm2
QM 方程式 14: 在上述方程式,方程式13係對應輸出cos(Ae),而且方程 式14係對應輸出“η(ΔΘ),其中C0S(Ae)+jsin(Ae)係表示 相位差。(參考上面方程式4) ^ 圖9係描述圖5的乘法器5〇8、512、和514與加法器516的 實施。圖 9 包括乘法器 922、902、904、912、914、908、 918、和924。圖9亦包括加法器906、910、916、和920。乘 法器922是接收當作輸入的II,和W1 ,而且將輸出提供給加 法器910。乘法器902是接收12,與相位修正1,而且將它的 輸出提供給加法器9〇6。乘法器904是接收Q2,與相位修正 2 ’而且將它輸出負驗位提供給加法器9〇6。加法器9〇6的結 果疋提供給乘法器9〇8,且亦接收當作一輸入的W2。乘法 器908的結果是提供給加法器91〇,且亦接收乘法器922的輸 出°加法器910的輸出是經由導線3 is或422而當作I提供, -33 - 本纸張尺度適财關家標準(CNS)織.1()χ297公爱) 582141QM Equation 14: In the above equation, Equation 13 corresponds to the output cos (Ae), and Equation 14 corresponds to the output "η (ΔΘ), where C0S (Ae) + jsin (Ae) represents the phase difference. (Refer to Equation 4 above) ^ Figure 9 describes the implementation of multipliers 508, 512, and 514 and adder 516 of Figure 5. Figure 9 includes multipliers 922, 902, 904, 912, 914, 908, 918, and 924. Figure 9 Also included are adders 906, 910, 916, and 920. Multiplier 922 receives II as input, and W1, and supplies the output to adder 910. Multiplier 902 receives 12, and phase corrects 1, and adds Its output is provided to the adder 906. The multiplier 904 receives Q2, with a phase correction of 2 'and supplies its output negative bit to the adder 906. The result of the adder 906 is provided to the multiplier. 9〇8, and also receives W2 as an input. The result of the multiplier 908 is provided to the adder 91, and the output of the multiplier 922 is also received. Provided by I, -33-This paper is compliant with the Financial Standards for Family Care (CNS). 1 () χ297 公 爱) 582141
此疋因具體貫施例而定。而且,乘法器924接收卩丨,和wi, 且將一輸出提供給加法器92〇。乘法器912是接收12,與相位 修正2,且將它的輸出提供給加法器910。乘法器914是接收 Q2’與相位修正1,且將它提供給加法器916。加法器916是 將它的輸出提供給乘法器918,且接收當作輸入的W2,並 且將匕的輸出提供給加法器92〇。加法器92〇是經由導線318 或422而當作它的輸出Q提供,此亦是因具體實施例而定。 因此,圖9的電路在代表上述方程式7。 圖ίο係描述多樣組合單元304和4〇4的一另一具體實施 例即疋,圖10的電路能與圖5的電路交換。在圖1 〇的具體 實施例中’多樣組合單元3〇4和404包括解多工器 (DEMUXs)l〇〇〇* 1002 ,且耦合到信號特性值評估電路 1004、多工器1006 ;與乘法器1〇12。信號特性值評估電路 10〇4係經由導線1〇28而摘合到以^^又1〇〇6。乘法器1〇12係轉 合到相位鎖定迴路與鎖定偵測電路1〇〇8,且該相位鎖定迴 路與鎖定偵測電路1〇〇8係耦合到乘法器1〇18。dEmuX 1002亦耦合到乘法器1018 ,而且乘法器1〇18係耦合到加法 器1014。加法器1〇14係耦合到解多工器1〇〇〇與多工器 1〇1〇。相位鎖定迴路與鎖定偵測電路1〇〇8係經由導線1〇46 而亦耦合到多工器1010。多工器1〇1〇是經由分別對應圖3或 4的導線318或422而提供輸出I、q。DEMUX 1〇〇〇、 DEMUX 1〇〇2、信號功率評估電路1〇〇4、Μυχ 1〇〇6、與相 位鎖定迴路與鎖定偵測電路1008的每一者係經由導線138而 接收控制信號。導線1028可以是一部分導線138、或透過信 -34 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 582141 A7 B7 五、發明説明(31 ) 號特性值評估電路1 004直接提供。 操作上,DEMUX 1000是接收信號II·、Q1,而且經由導線 1020提供II’,及經由導線1〇22而提供⑴,。而且,dEmuX 1002是接收I2’、Q2’,而且經由導線1〇24提供12,,及經由 導線1026提供Q2’。(再者,注意,當使用圖3的具體實施例 時’ I Γ、Q 1’和12’、Q2’可增益調整,但是如果使用圖4的 具體實施例,仍然未增益調整)信號特性值評估電路1〇〇4是 接收 II,、Q1’、12,和 Q2,,而且評估 lr、Q1,和 12,、Q2, 的一信號特性值,為了要決定較強信號。例如,信號特性 值評估電路1004可評估每個信號的功率或振幅,並且根據 功率、振幅、或兩者而決定較強信號。注意,在另一具體 實施例中,其他信號特性或其他方法可用來決定較強信 號。仏號特性值評估電路1004是經由導線1028而將一控制 信號輸出給多工器1006,為了要選取經由導線1030和1032 輸出給多工器1010的兩信號之中較強信號。乘法器1〇12是 接收II,、Qr、和12,、Q2,,而且透過將n,、Q1,乘以 12’、Q2’的複數結合而計算相位資訊。計算結果是以 ,jQM表示,而且經由導線刪和咖而提供給相位鎖 定迴路與鎖定偵測電路⑽卜彳目位鎖定迴路與鎖定偵測電 路1008是用來評估在Ir、Q1,與12,、Q2,之間的相位差, 且經由導線1038輸出給乘法器1〇18當作相位修正!,且經由 導線104G而輸出當作相位修正2。如果相位鎖定迴路是鎖 定,I2,、Q2,便會乘以結果的相位差,為了要在透過加法 器刪將I2,、Q2,與n,、Ql,組合之前適當將a,,偏 • 35 -This depends on the specific implementation. Further, the multiplier 924 receives 卩, and wi, and supplies an output to the adder 92. The multiplier 912 receives 12 and the phase correction 2 and supplies its output to the adder 910. The multiplier 914 receives Q2 'and the phase correction 1 and supplies it to the adder 916. The adder 916 supplies its output to the multiplier 918, receives W2 as an input, and supplies the output of the dagger to the adder 92. The adder 92 is provided as its output Q via a wire 318 or 422, which is also determined by the specific embodiment. Therefore, the circuit of FIG. 9 is representing Equation 7 above. FIG. 8 illustrates another specific embodiment of the various combination units 304 and 404, that is, the circuit of FIG. 10 can be exchanged with the circuit of FIG. 5. In the specific embodiment of FIG. 10, 'various combination units 304 and 404 include demultiplexers (DEMUXs) 100 * 1002, and are coupled to the signal characteristic value evaluation circuit 1004 and multiplexer 1006; and multiplication器 1〇12. The signal characteristic value evaluation circuit 1004 is coupled to 1006 through a wire 1028. The multiplier 1012 is coupled to the phase lock loop and the lock detection circuit 1008, and the phase lock loop and the lock detection circuit 1008 are coupled to the multiplier 1018. dEmuX 1002 is also coupled to multiplier 1018, and multiplier 1018 is coupled to adder 1014. The adder 1014 is coupled to a demultiplexer 1000 and a multiplexer 1010. The phase-locked loop and the lock detection circuit 1008 are also coupled to the multiplexer 1010 via the wire 1046. The multiplexer 1010 provides outputs I and q via wires 318 or 422 corresponding to Figs. 3 or 4, respectively. Each of DEMUX 100, DEMUX 1002, signal power evaluation circuit 1004, Μχχ 1006, and the phase lock loop and lock detection circuit 1008 receives a control signal via a wire 138. Lead wire 1028 can be a part of lead wire 138, or through letter-34-This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 582141 A7 B7 V. Description of the invention (31) No. characteristic value evaluation circuit 1 004 directly provide. In operation, the DEMUX 1000 receives signals II ·, Q1, and provides II 'via a wire 1020, and ⑴ via a wire 1022. Further, dEmuX 1002 receives I2 ', Q2', and provides 12 via a lead 1024, and Q2 'via a lead 1026. (Further, note that when the specific embodiment of FIG. 3 is used, 'I Γ, Q 1' and 12 ', Q2' can be gain adjusted, but if the specific embodiment of FIG. 4 is used, gain adjustment is still not performed.) Signal characteristic value The evaluation circuit 1004 receives II, Q1 ', 12, and Q2, and evaluates a signal characteristic value of lr, Q1, and 12, Q2, in order to determine a stronger signal. For example, the signal characteristic value evaluation circuit 1004 may evaluate the power or amplitude of each signal, and determine a stronger signal based on the power, amplitude, or both. Note that in another embodiment, other signal characteristics or other methods can be used to determine the stronger signal. The No. characteristic value evaluation circuit 1004 outputs a control signal to the multiplexer 1006 via the wire 1028. In order to select a stronger signal from the two signals output to the multiplexer 1010 via the wires 1030 and 1032. The multiplier 1012 receives II, Qr, and 12, and Q2, and calculates phase information by combining n, Q1, and a complex number multiplied by 12 'and Q2'. The calculation result is expressed in terms of jQM and provided to the phase-locked loop and lock detection circuit through a wire delete and filter. The bit-locked loop and lock detection circuit 1008 is used to evaluate the values in Ir, Q1, and 12, , Q2, and the phase difference between them, and output to the multiplier 1018 via the wire 1038 as a phase correction! And output as phase correction 2 via the lead 104G. If the phase-locked loop is locked, I2, and Q2 will be multiplied by the phase difference of the result. In order to delete I2 ,, Q2, and n, and Ql by the adder, appropriately decompose a ,, and • 35 -
582141 袄7582141 袄 7
移。因此,加法器1 〇 14的輸出是代表組合信號J丨,' Q丨·與 相位移12、Q 2。而且,如果相位鎖定迴路是鎖定,一控 制信號便會提供給MUX 1010 ,為了要選取當作〗、Q輸出 的加法器1014輸出,而不是MUX 1006的輸出,且只表示 11 、Q Γ和12’、〇2’的較強信號。然而,如果相位鎖定迴 路電路1008不能鎖定,一控制信號是經由導線1〇46而輸出 給MUX 1〇1〇,以選取由導線1〇3〇和1〇32傳輸的信號,且經 由導線3 18或422而當作輸出I、Q提供。 因此,在圖10描述的多樣組合單元的具體實施例係嘗試 評估相位差與偏移12,、q2,。然而,如果相位鎖定迴路不 月匕在正確相位鎖,那麼信號功率評估電路1 〇〇4可提供當作 1、Q兩信號的較強信號。因此,圖1〇可視為一混合相位鎖 足迴路(PLL)系統。當在加法器1 〇 14組合信號時,另一具 體實施例是將每個信號的信號特性(例如振幅、功率等)當 作一加權因素使用。如圖5的討論,例如,n·、Q1,可透過 它的相關功率加權,而12,、Q2,是透過它的相關功率加 權。其他具體實施例可甚至使用除了根據信號特性之外的 不同加權因素。圖10的操作可參考圖丨丨而更佳了解。 圖11係流程圖形式描述圖1 〇的多樣組合單元3、404操 作的一具體實施例。在方塊1102,II,、()1,及12,、Q2,係 被接收。在方塊1104,每個信號的一信號特性值(例如,功 率或振幅)可評估(其可透過信號特性值評估電路1〇〇4執 行),而且較強信號可選取。在方塊11 〇6,11,、q丨•是乘以 I2*、Q2*的複數結合,以獲得IM+jQM(參考上面方程式 -36 - 本纸張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)shift. Therefore, the output of the adder 1014 is representative of the combined signals J 丨, 'Q 丨 · and the phase shifts 12, Q2. Moreover, if the phase lock loop is locked, a control signal will be provided to the MUX 1010. In order to select the output of the adder 1014, which is the output of Q, instead of the output of MUX 1006, and only indicates 11, Q Γ, and 12 Strong signal of ', 〇2'. However, if the phase-locked loop circuit 1008 cannot be locked, a control signal is output to the MUX 1010 via the wire 1046 to select the signals transmitted by the wires 1030 and 1032, and via the wire 3 18 Or 422 and provided as outputs I, Q. Therefore, the specific embodiment of the various combination units described in FIG. 10 is an attempt to evaluate the phase difference and offset 12 ,, q2 ,. However, if the phase-locked loop is not locked in the correct phase, then the signal power evaluation circuit 1004 can provide a stronger signal as the two signals of Q and Q. Therefore, Fig. 10 can be regarded as a hybrid phase locked loop (PLL) system. When combining signals in the adder 104, another specific embodiment is to use the signal characteristics (such as amplitude, power, etc.) of each signal as a weighting factor. As discussed in Figure 5, for example, n ·, Q1 can be weighted by its related power, while 12, Q2 can be weighted by its related power. Other embodiments may even use different weighting factors in addition to depending on signal characteristics. The operation of FIG. 10 can be better understood with reference to FIG. Fig. 11 is a flowchart describing a specific embodiment of the operation of the various combination units 3, 404 of Fig. 10. At blocks 1102, II, (1), and 12, Q2, are received. At block 1104, a signal characteristic value (for example, power or amplitude) of each signal can be evaluated (which can be performed through the signal characteristic value evaluation circuit 1004), and a stronger signal can be selected. At block 11 〇6,11, and q 丨 • is a complex combination of multiplying by I2 *, Q2 * to obtain IM + jQM (refer to the above equation -36-this paper size applies Chinese National Standard (CNS) A4 specifications ( 210 X 297 mm)
裝 訂Binding
582141 A7582141 A7
3)。在万塊ll〇8,在n,、Q1•與12,、Q2,之間的相位差^ΔΘ 可評估,其中相位差是以c〇sUe)+jsin(Ae)表示。此可透 過相位鎖定迴路與鎖定偵測電路1〇〇8執行,以經由導線 1038輸出相位修正1(c〇s(Ae)表示),及經由導線1〇4〇輸出 相位修正2(sinUe)表示)。在方塊111〇,如果相位鎖定迴 路與鎖定偵測電路1008的相位鎖定迴路是鎖定,鎖定控制 信號便可確認。(相位鎖定迴路與鎖定偵測電路ι〇〇8的操作 將參考下圖12進一步討論)。如圖5前述的加權因素決定電 路502,在方塊1115中,n,、Q1、和12,、Q2,的加權值可 決定。然而,方塊1115是可選擇的,而且參考圖1〇和11描 述的具體貫施例係假設沒有加權因素是用於信號組合。在 方塊1116 ,如果鎖定控制信號確認,信號12,、Q2,可乘以 在方塊1108計算的相位差,如下列方程式(亦看見方塊n 12) 所TF · 方程式 15 : ejA0 · (I2f+jQ2f) 在方塊1114,如果鎖定控制信號確認,方塊丨丨12的結果 是與11 ’、Q Γ組合,以獲得I、Q,如下列方程式所示: 方程式 16 : l4-jQ=ejAe •(I2i+jQ2») + (ir+jQ1,) 在方塊111 8 ’如果未確認鎖定控制信號,此表示相位鎖 定迴路未鎖定,信號II,、Q1,與12,、Q2,的較強者能以工^ Qi疋供。(注意’除了在方牙王式15和16沒有加權因素出現之 外,方程式15和16是分別類似方程式5和7。然而,如上面 圖10與選擇方塊1115的討論,加權因素可用來將信號u·、 Q1·與12*、Q2’組合,類似圖6的方塊610、612、和614。) -37 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 582141 A73). At 10000, the phase difference ^ ΔΘ between n, Q1 •, 12, and Q2, can be evaluated, where the phase difference is expressed as cosUe) + jsin (Ae). This can be performed through the phase lock loop and the lock detection circuit 1008 to output a phase correction 1 (indicated by cos (Ae)) via the wire 1038 and a phase correction 2 (sinUe) to be output via the wire 1040. ). In block 111, if the phase lock circuit is locked with the phase lock circuit of the lock detection circuit 1008, the lock control signal can be confirmed. (The operation of the phase lock loop and lock detection circuit ι 08 will be discussed further with reference to Figure 12 below). The weighting factor determining circuit 502 described in FIG. 5 is described above. In block 1115, the weighting values of n, Q1, and 12, Q2, may be determined. However, block 1115 is optional, and the specific embodiment described with reference to Figures 10 and 11 assumes that no weighting factor is used for the signal combination. At block 1116, if the lock control signal is confirmed, the signals 12, and Q2 can be multiplied by the phase difference calculated at block 1108, as shown in the following equation (see also block n 12). TF · Equation 15: ejA0 · (I2f + jQ2f) In block 1114, if the lock control signal is confirmed, the result of block 丨 丨 12 is combined with 11 'and Q Γ to obtain I and Q, as shown in the following equation: Equation 16: l4-jQ = ejAe • (I2i + jQ2 ») + (Ir + jQ1,) at block 111 8 'If the lock control signal is not confirmed, this indicates that the phase lock loop is not locked. The stronger of the signals II ,, Q1, and 12, and Q2, can be provided by Qi ^ . (Note that equations 15 and 16 are similar to equations 5 and 7 except that there are no weighting factors in Fangfangwang 15 and 16. However, as discussed in Figure 10 and selection box 1115 above, weighting factors can be used u ·, Q1 · are combined with 12 *, Q2 ', similar to blocks 610, 612, and 614 in Figure 6.) -37-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 582141 A7
圖12係描述信號特性值評估電路1004的一具體實施例, 且該信號特性值評估電路丨〇〇4係利用每個信號功率來決定 較強#號。圖12的信號特性值評估電路丨〇〇4包括:乘法器 1200,其係耦合到乘法器12〇4 ;乘法器12〇2,其係耦合到 乘法器1206。乘法器1204和12〇6係耦合到加法器12〇8。加 法器1208係镇合到延遲單元121〇與儲存電路1212。儲存電 路1212係耦合到加法器1214,且加法器1214係耦合到選擇 器單元1216 '乘法器1228係耦合到乘法器1224,而且乘法 器1230係耦合到乘法器1226。乘法器1224和1226係耦合到 加法器1222。加法器1222係耦合到延遲單元122〇與儲存電 路121 8。儲存電路121 8係鶴合到加法器1214。選擇器單元 1216疋經由導線1 〇28而將一控制信號提供給多工器〗。 操作上’乘法器1200是接收π’和i/N,以便將n,/N提供 給乘法器1204計算平方值(Ii,/N)2,且將結果提供給加法 器1208。而且,乘法器1202是接收Q1,和1/N ,以便將 Ql’/N提供給乘法器1206計算此結果的平方,以便將 (Q17N)2提供給加法器1208。加法器12〇8是將結果 (11,/>〇2+((^1,/>〇2提供給儲存電路1212與延遲單元121〇。 加法器1208、延遲單元1210、與儲存電路12〇2是在一段時 間上累加(I1,/N)2+(Q1,/N)2的值。再者,此段時間是由對 應輸入信號I Γ、Q Γ的取樣頻率決定^ N再次參考採用的 取樣數量(即是窗框大小)。只要採用適當的取樣量,儲存 電路^^便可將結果^ +㈤提供給加法器^^其中巧和 ^是在一段時間上的為II·2和Q1’2的平均。同樣地,相同 -38 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 582141FIG. 12 illustrates a specific embodiment of the signal characteristic value evaluation circuit 1004, and the signal characteristic value evaluation circuit 1004 uses each signal power to determine the stronger # number. The signal characteristic value evaluation circuit of FIG. 12 includes: a multiplier 1200, which is coupled to the multiplier 1204; and a multiplier 120, which is coupled to the multiplier 1206. The multipliers 1204 and 1206 are coupled to the adder 1208. The adder 1208 is coupled to the delay unit 121 and the storage circuit 1212. The storage circuit 1212 is coupled to the adder 1214, and the adder 1214 is coupled to the selector unit 1216. The multiplier 1228 is coupled to the multiplier 1224, and the multiplier 1230 is coupled to the multiplier 1226. Multipliers 1224 and 1226 are coupled to an adder 1222. The adder 1222 is coupled to the delay unit 1220 and the storage circuit 1218. The storage circuit 121 is connected to the adder 1214 by an 8-series crane. The selector unit 1216 疋 provides a control signal to the multiplexer via the wire 1028. Operationally, the 'multiplier 1200 receives π' and i / N, so that n, / N is supplied to the multiplier 1204 to calculate a square value (Ii, / N) 2 and the result is supplied to the adder 1208. Furthermore, the multiplier 1202 receives Q1, and 1 / N, so that Ql '/ N is supplied to the multiplier 1206 to calculate the square of the result, so that (Q17N) 2 is supplied to the adder 1208. The adder 12〇8 supplies the result (11, / > 〇2 + ((^ 1, / > 〇2) to the storage circuit 1212 and the delay unit 121. The adder 1208, the delay unit 1210, and the storage circuit 12 〇2 is the value of (I1, / N) 2+ (Q1, / N) 2 accumulated over a period of time. In addition, this period of time is determined by the sampling frequency of the corresponding input signals I Γ, Q Γ ^ N again reference The number of samples used (that is, the size of the window frame). As long as the appropriate sample size is used, the storage circuit ^^ can provide the result ^ + 给 to the adder ^^ where the sum and ^ are in a period of time is II · 2 The average of Q1'2. The same, the same -38-This paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) 582141
計算可於12’、Q2’執行。再者’電路可於圖i2所述的i2,、 Q2’重複,或對應ΙΓ、Q1,的電路可由兩信號II’、Q1*和 12’、Q2’劃時多1而共用。目此,累加值^^,延遲單元 1220、與儲存電路1218的操作可於—敎時間窗框上累加 (12 /N) +(Q2 /N)的值’其中該預定時間窗框是透過 U,、苎取樣頻匕決定二因此,提供給加法㈣㈣ 結果疋/2’2 +以,2,其中0和&在預定時間窗框上分別是 I2*2和Q2,2的平均值。注意,值p+p的每一者 係對應相對信號Π,、Q1,和12,、Q2,的功率。 來自儲存電路1212和1218的結果是提供給加法器1214 , 且該加法器1214是將在兩結果值p+p與p+p之間的差 提供給選擇器單元1216。選擇器單元1216可決定那一信號 II’、Q1’或I2’、Q2’是較強及經由導線1〇28輸出控制信 號。如果II’、Q1,係為較強之信號,則經由導線1〇28輸出 的控制信號允許MUX 1026選取II,、Q1,來傳輸給導線1〇3〇 和1032及給MUX 1〇1〇。然而,如果選擇器單元1216選取較 強k號12,、Q2’ ’那麼]V1UX 1006便可經由導線1030和1032 而將12’、Q2,輸出給MUX 1010。因此,選擇器單元1216可 決疋那個仏號具有較大功率。例如,如果從加法器12 14提 供給選擇器單元1216的值是大於〇,此表示II,、Qi,的功率 是大於I2f、Q2,。然而,如果差是小於〇(即是負值),此表 示12’、Q 2·的功率是大於n,、Q1,,因此選擇器單元1216 可輸出控制信號。 圖13係根據本發明的具體實施例而描述一部分乘法器 -39 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 582141 A7 _ B7 五、發明説明(36 ) 1 012及一部分相位鎖定迴路與鎖定偵測電路〗008。乘法器 1012包括乘法器1300、13〇2、1306、和1310、與加法器 1304和1308。乘法器1300是接收ΙΓ和12·,而且乘法器 1302是接收Q1’和Q2,。乘法器1300和13〇2的結果是提供給 加法器1304,其輸出是經由導線1034而提供給相位鎖定迴 路與鎖定偵測電路1008 ^而且,乘法器13〇6是接收輸入12, 和Q1’,而且乘法器131〇是接收輸入Q 2,和π,。乘法器 1306和13 10是將他們的輸出提供給加法器13〇8,以計算在 兩值之間的差,及將結果經由導線1〇36而提供給相位鎖定 迴路與鎖定偵測電路1008。因此,操作上,乘法器1〇12是 輸出I Γ、Q Γ是乘上IM+jQM形式的12,、Q2,複數結合, 其中IM係表示經由導線1〇34傳送實數部分,而且QM係表 示經由導線1036傳導的虛數部分。(參考上面方程式3)。 相位鎖定迴路與鎖定偵測電路1008包括:乘法器1 3 14 , 其係耦合到加法器1312 ;及乘法器132〇,其係耦合到加法 器1322。加法器1312亦耦合到乘法器1316與鎖定偵測器 1324。加法器1322亦耦合到乘法器1318與乘法器1328。增 益調整器1326係耦合到鎖定偵測器1324的輸出,及將一輸 入提供給乘法器1328。乘法器1328係耦合到延遲單元 13 30而延遲單元1330係耦合到加法器1334。加法器1334 係耦口到计算電路1336與延遲單元1332。延遲單元能 將回授值提供給加法器U34。計算電路η%是經由導線 1〇3_8而輸出相位修正丨及經由導線1〇4〇而輸出相位修正]。 汁算电路1336的耦合亦將輸入提供給乘法器i32〇、i3i8、 -40 -Calculations can be performed at 12 ', Q2'. Furthermore, the 'circuit may be repeated at i2 ,, Q2' as shown in Fig. I2, or the circuit corresponding to IΓ, Q1, may be shared by two signals II ', Q1 * and 12', Q2 '. Therefore, the accumulated value ^^, the operation of the delay unit 1220, and the storage circuit 1218 can be accumulated in the time window frame (12 / N) + (Q2 / N), where the predetermined time window frame is transmitted through U Therefore, the sampling frequency is determined to be two. Therefore, the result of the addition is + / 2'2 ++, 2, where 0 and & are the average values of I2 * 2 and Q2,2 on the predetermined time window frame, respectively. Note that each of the values p + p corresponds to the power of the relative signals Π ,, Q1, and 12, Q2. The results from the storage circuits 1212 and 1218 are provided to the adder 1214, and the adder 1214 supplies the difference between the two result values p + p and p + p to the selector unit 1216. The selector unit 1216 can determine which signal II ', Q1' or I2 ', Q2' is stronger and output a control signal via the wire 1028. If II 'and Q1 are stronger signals, the control signal output via the wire 1028 allows the MUX 1026 to select II, Q1 to transmit to the wires 1030 and 1032 and to MUX 1010. However, if the selector unit 1216 selects the stronger k number 12, Q2 ', then] V1UX 1006 can output 12', Q2 to MUX 1010 via wires 1030 and 1032. Therefore, the selector unit 1216 can decide which number has greater power. For example, if the value supplied to the selector unit 1216 from the adders 12 to 14 is greater than 0, this means that the power of II, Qi, is greater than I2f, Q2 ,. However, if the difference is less than 0 (that is, a negative value), this means that the power of 12 ', Q 2 · is greater than n, Q1, so the selector unit 1216 can output a control signal. Figure 13 is a description of a part of the multiplier according to a specific embodiment of the present invention-39-This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 582141 A7 _ B7 V. Description of the invention (36) 1 012 and a part Phase-locked loop and lock detection circuit〗 008. The multiplier 1012 includes multipliers 1300, 1302, 1306, and 1310, and adders 1304 and 1308. The multiplier 1300 receives IΓ and 12 ·, and the multiplier 1302 receives Q1 'and Q2 ,. The results of the multipliers 1300 and 130 are provided to the adder 1304, and the output is provided to the phase-locked loop and lock detection circuit 1008 via the wire 1034. Moreover, the multiplier 1306 receives the inputs 12, and Q1 ' And, the multiplier 131 is receiving the inputs Q2, and π. The multipliers 1306 and 1310 provide their output to the adder 130, to calculate the difference between the two values, and provide the result to the phase lock loop and lock detection circuit 1008 via the wire 1036. Therefore, in operation, the multiplier 1012 is the output I Γ, Q Γ is multiplied by 12, and Q2 in the form of IM + jQM, where IM refers to the transmission of the real part via the wire 1034, and QM refers to Imaginary part conducted via wire 1036. (Refer to Equation 3 above). The phase lock loop and lock detection circuit 1008 includes: a multiplier 1 3 14 which is coupled to the adder 1312; and a multiplier 1320 which is coupled to the adder 1322. The adder 1312 is also coupled to the multiplier 1316 and the lock detector 1324. Adder 1322 is also coupled to multiplier 1318 and multiplier 1328. Gain adjuster 1326 is coupled to the output of lock detector 1324, and provides an input to multiplier 1328. Multiplier 1328 is coupled to delay unit 1330 and delay unit 1330 is coupled to adder 1334. The adder 1334 is coupled to the calculation circuit 1336 and the delay unit 1332. The delay unit can provide the feedback value to the adder U34. The calculation circuit η% outputs a phase correction through the lead wire 103_8 and a phase correction through the lead wire 1040]. The coupling of the juice calculation circuit 1336 also provides the input to the multipliers i32〇, i3i8, -40-
582141582141
1316、和 1314。 扭作上,相位鎖定迴路與鎖定偵測電路〗〇〇8包括一相位 鎖疋迴路(PLL)部分,以評估輸入信號IM+jQM的相位差 值。此是經由使用一相位鎖定迴路執行,且該相位鎖定迴 路疋透過一增盈調整器1326、乘法器1328、延遲單元 133〇、加法器U34、延遲單元^32、與計算電路1336實 施。相位鎖定迴路是以ΛΘ,的初始值開始,且該初始值是輸 入計算電路1336,其中ΑΘ,係表示PLL的相位值。例如,初 始值可以是0。在PLL的重複期間,Δθ,可被調整,直到 PLL鎖足在一相位值圍止。當Δθ,大約等於對的 △ Θ時,PLL便會鎖定。如下面進一步討論,鎖定偵測器 1324可判斷PLL是否為鎖定。計算電路1336可接收值Δθ,, 而且將餘弦與正弦計算的結果提供給乘法器132〇、1318、 1316、和1314。 乘法器1314、1316、1320、1318與加法器1312和1322是 計算輸入信號IM+jQM乘以來自PLL、ΔΘ,結果相位的複數 結合,且能以e-jAG•表示,其中: 方程式 17 : e'jAe,=cos(Aef)- jsin(AG') 如方程式4所示’ IM+jQM的相位是以^Λθ表示。因此, 計算的結果能以下列表示: 方考王式 18 · ejA0 · e'jA0 =ej(A0'A0 )=cos(A0-A0,)+jsin(A0-Ae,) 在加法器13 12輸出上的導線134〇是將計算結果的實數部 分〇〇5(ΔΘ-ΑΘ,)提供給鎖定偵測器1324 ,而加法器1322是 將计舁結果的虛數部分sin(A0 -ΔΘ ’)提供給乘法器1328 ^如 -41 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 582141 A7 _______B7 五、發明説明(38 ) 果鎖定偵測器1324決定PLL並未鎖定(即是Α Θ,不相當接近 △ Θ) ’那麼增益調整器1326可經由乘法器1328調整來自 1322的信號虛數部分,而且一更新的么㊀,可計算。此更新的 △ θ’是提供給計算電路1336,且該計算電路1336是將Δθ,的 餘弦與弦值提供給乘法器1314、1316、1318、132〇,為了 要再次將此ΔΘ,的複數結合乘以輸入信號ιμ+ jQM。此反 覆處理會持續,直到由加法器1312提供給鎖定债測器1324 的計算結果實數部分決定可提供在來自Αθ預定範圍中的 △ Θ*。當ΔΘ*近似ΔΘ時,既然計算結果的實數部分是以 (^(△Θ-ΔΘ’)表示,所以在003(〇)=1時,餘弦的計算結果 會近似1。如果鎖定偵測器1324決定輸入信號超過鎖定臨界 值1338(即是ΑΘ,相當接近ΑΘ),一鎖定信號是經由導線 1046提供給MUX 1010,以允許經由導線1〇42和1044組合輸 出I、Q。而且,只要鎖定偵測器經由導線1〇46確認鎖定信 號’此鎖定信號亦可提供給增益調整器1326,為了要選取 PLL較大穩定性的較小增益值。即是,只要Pll是鎖定,一 較小增益便可提供較穩定系統。 圖14係描述圖13的鎖定偵測器1324的一具體實施例。在 上圖13討論的計算結果的實數部分是經由導線1340而提供 給鎖定偵測器1324,當作低通濾波器1400的輸入。低通濾 波器可移除輸入信號高頻元件的雜訊項。低通濾波器丨400 的輸出是提供給加法器1402,且該加法器1402亦接收鎖定 臨界值1338。加法器1402是尋找在從濾波器1400的濾波輸 入與鎖定臨界值1338之間的差,並且將結果提供給鎖定判 -42 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 582141 A7 _ _B7 五、發明説明(39 ) 斷電路1404,以經由導線1046而將輸出鎖定信號提供給 MUX 1010。鎖定判斷電路1404可決定加法器1402輸出上的 差是否大於0或小於〇,以決定輸入信號是否大於或小於鎖 定臨界值1338。如果鎖定判斷電路的輸入是正信號,鎖定 判斷電路可確認鎖定信號1046,為了要選取導線1042和 1044,以便在MUX 1010輸出上提供當作I、q的組合信 號。然而,如果鎖定判斷電路1404決定加法器1402的輸出 是負信號,鎖定信號1046便不確認,如此可選取MUX 1〇〇6 的輸出,以便經由導線1030和1032而在MUX 1010輸出上提 供當作I、Q的信號。 圖15係描述圖3的時空單元302的一具體實施例。時空單 元302是經由導線314和3 16而多樣組合輸入信號j丨,、q丨,和 Ϊ 2、Q 2,並且^疋供結果仏破的回信取消。時空單元3 〇2是 ί疋供輸入仏號的芝間組合及結果信號的時域。時域部分亦 稱為執行回信取消的均衡器部分。(此均衡器部分亦稱為適 當濾波器1530 ’包括效率測度與錯誤信號產生器丨522、乘 法器1512、1514、和1516、加法器1520、分路更新器 1518、與延遲 1506、1508、和 1510。)輸入信號 n,、 和12、Q2疋經由乘法器1500和1502與加法器1504組合。 ΙΓ、Q1’是透過加權因素W1加權,且該加權因素…丨是從 加權更新器1524輸入乘法器1500。而且,12,、q2,是芦由 乘法器1502而與加權因素W2加權,其中w2亦透過加權更 新器1524提供。因此,加權結果是提供給加法器15〇4,以 產生一組合加權信號,然後提供給延遲單元15〇6與乘法器 -43 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 582141 五、發明説明(4〇 ) m2。W1和W2係表示複數。加法器15〇4的輸出是經由延 遲單兀1506、1508和1510傳遞。加法器15〇4的輸出、盥例 如=06、1508和1510的每個延遲單元輸出是提供給對應乘 法器1512、1514、和1516 ,其中結果是乘以例如A1、A2、 和al的對應分路。乘法器1512、1514、和i5i6的輸出炊後 提供給加法器1520,以產生一組合回信取消輸出,且該組 合回信取消輸出可經由導線312而提供給輸出測量與錯誤信 號產生器1522與MUX 306與多路徑回信偵測器與信號品質 監督器300。效率測度與錯誤信號產生器1522是將資訊提供 給加權更新器1524與分路更新器1518 ;因此,可更新壓加 權與分路的值。注意,分路(A1、A2、和aL)亦表示複 數。例如1506和1508的延遲單元數量與例如1512和1514的 乘法器與例如A 1和A2的分路是因在此均衡器部分的分路數 量而定。 空間組合器(例如W 1和w2)的加權與均衡器(例如A J、 A2、…、AL)的分路可選取,所以加法器152〇輸出上的結 果#號振幅變化可減小。在均衡器部分中的分路數量亦可 選取’以改善結果信號品質,但是需要更多硬體或軟體, 此是因實施而定。效率測度與錯誤信號產生器丨522可執行 一修正固定係數演算法,以更新加權與分路,為了要減少 加法器1520輸出上的結果信號振幅變化。(因此,在一具體 實施例中,相同標準可用於更新空域的加權,至於更新時 域的適當濾波器分路,可參考下面方程式丨9- 26。)因此, 時空單元302可使用輸入FM信號的固定係數特徵信號。即 -44 - A7 B7 五、發明説明(41 ) 疋,FMk號應該維持一固定振幅。然而,由於多路徑回信 與雜訊介入,輸入FM信號的振幅不能保持固定。因此,加 權與分路可用來減少由多路徑回信所造成的振幅變化。而 且/主思,在圖1 5描述的實施不僅可適用於接收兩天線信 號而且可擴充組合及回信來自任何數量天線的取消信 號。在此具體實施例中,每個輸入信號是在提供給加法器 1504之前透過一對應加權因素而加權。同樣地,均衡器部 分(即是適合濾波器1530)可使用任何數量分路設計。 效率測度與錯誤信號產生器1522是透過使用一修正固定 係數演算法而將適當資訊提供給加權更新器丨524與分路更 新器1518,且將在下面方程式說明。在此演算法中,一成 本函數是如下式定義: 方程式 19: 7 = ~ψ(*)|2-ΐ} 上述方程式X(k)疋在加法益1520輸出上的時空處理之後 的結果信號,而且k係表示t = kTs所提供的取樣時間範例, 其中Ts疋取樣週期。上述方程式係表示一任意處理的預 期,因為接收信號(例如II,、Q1,*I2,、Q2,)是統計而不 是決定。時空單元302的一目標是將減少成本函數J ,此可 透過加權與分路變化達成,且將在下面進一步討論。 注意,接收信號ΙΓ、Q1,和12,、Q2,通常亦以、(“表 示,其中111=1,2,.".,:^,而1^是接收器的天線數量,且1<:是 t = kTs所提供的取樣時間範例。而且注意,加權WwW2可 -45 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 582141 A7 B7 五、發明説明(42 ) 分別以W 1 = W lR + j W 1〖和W2= W2R + j W2〖表示。下標R是用 來表示複數的實數部分,而下標I是用來表示虛數部分。而 且’他們能以Wm(k)表示,其中m==1,2,..N,而n是接收器 的天線數量,且k是取樣時間範例。而且,A1、A2、…、 AL是以A1 =人111+』入11等、或以An(k)表示,其中n = 1,2,...,L,而L是均衡器的分路數量,且k使取樣時間範 例。因此,在此提供的方程式中,不同的表示法可使用。 下列方私式係表示來自不同天線的所有信號組合。在加 法器1504輸出上的此信號γ(^)是如下列方程式表示: 方程式20 : y(fc) = trm(fe)xWm(/:) m=l 上述方程式是在系統中的任何數量天線的一般方程式。 在圖15描述的具體實施例具有兩天線,Y(k)的方程式能以 下式表示: 方程式21 : Y(k)=(ir+jQr) · (wiR+jwiI)+(ir+jQ2,) · (W2R+jW2,) 因此’加法器1520輸出上獲得的等化信號能以下式表 不 · 方程式 22: X(k)= X(k)^Y(k-n)xAn(k) 在上述方程式,L係表示時空單元3〇2的均衡器部分中的 分路數量。Y(k-n)係表示在加法器15〇4(亦參考方程式2〇) -46 - I纸張尺度適用巾國时標準(CNS) Μ規格_〉<挪公爱) A7 B7 五、發明説明(43 ) 1510等時間偏移影響的 輸出上受到延遲單元1506、15〇8 加權與組合信號。 函 函 數==成“數J,與加權的複數結合有關的成本 數部1導广β又疋成°’如同與分路複數結合有關的成本 數邵分導出。因此’方程式能以下式表示:1316, and 1314. On the twist, the phase-locked loop and the lock detection circuit include a phase-locked loop (PLL) section to evaluate the phase difference of the input signal IM + jQM. This is performed by using a phase-locked loop, and the phase-locked loop is implemented through a gain adjuster 1326, a multiplier 1328, a delay unit 133, an adder U34, a delay unit ^ 32, and a calculation circuit 1336. The phase-locked loop starts with an initial value of ΔΘ, and the initial value is an input calculation circuit 1336, where Θ, represents the phase value of the PLL. For example, the initial value can be 0. During the repetition of the PLL, Δθ can be adjusted until the PLL locks up in a phase value. When Δθ is approximately equal to Δ θ of the pair, the PLL is locked. As discussed further below, the lock detector 1324 can determine whether the PLL is locked. The calculation circuit 1336 may receive the value Δθ, and provide the results of the cosine and sine calculations to the multipliers 1320, 1318, 1316, and 1314. Multipliers 1314, 1316, 1320, and 1318 and adders 1312 and 1322 are calculated by multiplying the input signal IM + jQM by PLL, ΔΘ, and the complex phase of the resulting phase can be expressed as e-jAG •, where: Equation 17: e 'jAe, = cos (Aef)-jsin (AG') is shown in Equation 4 'The phase of IM + jQM is represented by ^ Λθ. Therefore, the calculation result can be expressed as follows: Fang Kao Wang 18 · ejA0 · e'jA0 = ej (A0'A0) = cos (A0-A0,) + jsin (A0-Ae,) is output in adder 13 12 The lead 134 on the line is to provide the real part of the calculation result (005 (ΔΘ-ΑΘ,) to the lock detector 1324, and the adder 1322 is to provide the imaginary part sin (A0-ΔΘ ') of the calculation result. Multiplier 1328 ^ such as -41-This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 582141 A7 _______B7 V. Description of the invention (38) If the lock detector 1324 decides that the PLL is not locked (ie Is A Θ, not quite close to Δ Θ) 'then the gain adjuster 1326 can adjust the imaginary part of the signal from 1322 via the multiplier 1328, and an updated ㊀ can be calculated. The updated Δ θ ′ is provided to the calculation circuit 1336, and the calculation circuit 1336 is provided to the multipliers 1314, 1316, 1318, and 132 to the cosine and sine of Δθ, in order to combine the complex numbers of Δθ, again Multiply the input signal ιμ + jQM. This iterative process is continued until the real part of the calculation result provided by the adder 1312 to the locked debt detector 1324 determines that Δ Θ * which can be provided in a predetermined range from Aθ. When ΔΘ * approximates ΔΘ, since the real part of the calculation result is expressed as (^ (△ Θ-ΔΘ '), so when 003 (〇) = 1, the cosine calculation result will be approximately 1. If the detector 1324 is locked It is determined that the input signal exceeds the lock threshold 1338 (that is, ΑΘ, which is quite close to ΑΘ). A lock signal is provided to MUX 1010 via wire 1046 to allow the combined output of I and Q via wires 1042 and 1044. Moreover, as long as the lock detection The tester confirms the lock signal via the lead 1046. This lock signal can also be provided to the gain adjuster 1326, in order to select a smaller gain value for greater stability of the PLL. That is, as long as Pll is locked, a smaller gain is A more stable system can be provided. FIG. 14 illustrates a specific embodiment of the lock detector 1324 of FIG. 13. The real part of the calculation result discussed in FIG. 13 is provided to the lock detector 1324 via the wire 1340 as The input of the low-pass filter 1400. The low-pass filter can remove the noise term of the high-frequency components of the input signal. The output of the low-pass filter 丨 400 is provided to the adder 1402, and the adder 1402 also receives the lock threshold 1338. Add The implement 1402 is to find the difference between the filtered input from the filter 1400 and the lock threshold 1338, and the result is provided to the lock judgment -42-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 5%) 582141 A7 _ _B7 V. Description of the invention (39) Disconnect the circuit 1404 to provide the output lock signal to the MUX 1010 via the wire 1046. The lock judgment circuit 1404 can determine whether the difference on the output of the adder 1402 is greater than 0 or less than 〇 to determine whether the input signal is greater than or less than the lock threshold 1338. If the input of the lock judgment circuit is a positive signal, the lock judgment circuit can confirm the lock signal 1046. In order to select the wires 1042 and 1044, it is provided as an output on the MUX 1010 as Combined signal of I and q. However, if the lock judgment circuit 1404 determines that the output of the adder 1402 is a negative signal, the lock signal 1046 is not confirmed. In this way, the output of MUX 1006 can be selected so that The MUX 1010 output provides signals as I and Q. Fig. 15 illustrates a specific embodiment of the space-time unit 302 of Fig. 3. The space-time unit 302 is via a wire 31. 4 and 3 16 and various combinations of the input signals j 丨, q 丨, and Ϊ2, Q2, and the reply for the result break is cancelled. The space-time unit 3 〇2 is the Shiba combination for the input number And the time domain of the resulting signal. The time domain part is also called the equalizer part that performs reply cancellation. (This equalizer part is also called the appropriate filter 1530 'Including efficiency measure and error signal generator 522, multipliers 1512, 1514 , And 1516, adder 1520, shunt updater 1518, and delays 1506, 1508, and 1510. ) The input signals n,, and 12, Q2 疋 are combined with the adder 1504 via multipliers 1500 and 1502. IΓ, Q1 'are weighted by a weighting factor W1, and this weighting factor ... is input from the weighting updater 1524 to the multiplier 1500. Moreover, 12, and q2 are weighted by the weighting factor W2 by the multiplier 1502, and w2 is also provided by the weighting updater 1524. Therefore, the weighted result is provided to the adder 1504 to generate a combined weighted signal, which is then provided to the delay unit 1506 and the multiplier -43-This paper standard applies the Chinese National Standard (CNS) A4 specification (210 X 297 (Mm) 582141 V. Description of the invention (40) m2. W1 and W2 represent complex numbers. The output of the adder 1504 is passed via the delay units 1506, 1508, and 1510. The output of the adder 1504, for example = 06, 1508, and 1510 each delay cell output is provided to the corresponding multipliers 1512, 1514, and 1516, where the result is multiplied by the corresponding scores of A1, A2, and al, for example. road. The outputs of the multipliers 1512, 1514, and i5i6 are provided to the adder 1520 after cooking to generate a combined reply cancellation output, and the combined reply cancellation output can be provided to the output measurement and error signal generator 1522 and MUX 306 via the lead 312. With a multipath reply detector and a signal quality monitor 300. The efficiency measure and error signal generator 1522 provides information to the weighted updater 1524 and the branch updater 1518; therefore, the values of the weighting and branch can be updated. Note that the shunts (A1, A2, and aL) also represent plural numbers. The number of delay units such as 1506 and 1508 and the multipliers such as 1512 and 1514 and the branches such as A 1 and A2 are determined by the number of branches in this equalizer section. The weighting of the spatial combiner (such as W1 and w2) and the equalizer (such as AJ, A2, ..., AL) can be selected, so the result #number amplitude change on the output of the adder 1520 can be reduced. The number of branches in the equalizer section can also be selected to improve the quality of the resulting signal, but more hardware or software is required, depending on the implementation. The efficiency measure and error signal generator 522 may execute a modified fixed coefficient algorithm to update the weighting and shunting, in order to reduce the amplitude variation of the resulting signal on the output of the adder 1520. (Therefore, in a specific embodiment, the same standard can be used to update the weighting of the spatial domain. As for updating the appropriate filter branch of the time domain, refer to the following equations 9-26.) Therefore, the space-time unit 302 can use the input FM signal Fixed coefficient characteristic signal. That is -44-A7 B7 V. Description of the Invention (41) 疋, the FMk number should maintain a fixed amplitude. However, the amplitude of the input FM signal cannot be kept fixed due to multi-path reply and noise intervention. Therefore, weighting and shunting can be used to reduce the amplitude variation caused by multipath reply. And / mind, the implementation described in Figure 15 is not only applicable to receiving two antenna signals but also to expand the combination and reply to cancel signals from any number of antennas. In this specific embodiment, each input signal is weighted by a corresponding weighting factor before being provided to the adder 1504. Similarly, the equalizer section (that is, suitable filter 1530) can use any number of shunt designs. The efficiency measure and error signal generator 1522 provides appropriate information to the weighted updater 524 and the shunt updater 1518 by using a modified fixed coefficient algorithm, and will be described in the following equation. In this algorithm, a cost function is defined as follows: Equation 19: 7 = ~ ψ (*) | 2-ΐ} The resulting signal after the spatiotemporal processing on the output of Additive Yi 1520 from the above equation X (k) 疋, And k is the sampling time example provided by t = kTs, where Ts 疋 sampling period. The above equation system expresses the expectation of an arbitrary process, because the received signals (such as II, Q1, * I2, Q2,) are statistics rather than decisions. One goal of the space-time unit 302 is to reduce the cost function J, which can be achieved through weighting and shunt changes, and will be discussed further below. Note that the received signals IΓ, Q1, and 12, and Q2 are usually also represented by "(", where 111 = 1, 2,. &Quot;.,: ^, And 1 ^ is the number of antennas of the receiver, and 1 < : Is the sampling time example provided by t = kTs. Also note that the weighted WwW2 may be -45-this paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 582141 A7 B7 V. Description of the invention (42) Represented as W 1 = W lR + j W 1 and W2 = W2R + j W2. The subscript R is used to represent the real part of a complex number, and the subscript I is used to represent the imaginary part. And 'they can use Wm (k) represents, where m == 1, 2, ..N, and n is the number of antennas of the receiver, and k is an example of sampling time. Moreover, A1, A2, ..., AL is A1 = person 111+ Enter 11 and so on, or use An (k), where n = 1, 2, ..., L, and L is the number of branches of the equalizer, and k is an example of the sampling time. Therefore, the equation provided here In the following, different representations can be used. The following equations represent all signal combinations from different antennas. The signal γ (^) on the output of the adder 1504 is expressed as the following equation: square Equation 20: y (fc) = trm (fe) xWm (/ :) m = l The above equation is a general equation for any number of antennas in the system. The specific embodiment described in FIG. 15 has two antennas, Y (k) The equation can be expressed by the following equation: Equation 21: Y (k) = (ir + jQr) · (wiR + jwiI) + (ir + jQ2,) · (W2R + jW2,) Therefore, the 'adder 1520 output etc. The signal can be expressed as follows: Equation 22: X (k) = X (k) ^ Y (kn) xAn (k) In the above equation, L is the number of branches in the equalizer part of the space-time unit 30. .Y (kn) means that in the adder 1504 (also refer to Equation 2) -46-I paper size applicable national time standard (CNS) M specifications _> < Norgod love) A7 B7 V. Invention Note (43) that the output affected by time offsets such as 1510 is weighted and combined by the delay units 1506 and 1508. The function is equal to "the number J, which is related to the weighted complex number.疋 成 ° 'is derived as a cost number related to the combination of branch and complex numbers. Therefore, the equation can be expressed as:
方程式23 : 1 97 ---- 〇 dw; m = 1,2, ··· N 方程式24 : dJ f=0 n = 1,2,…L 一統計梯度可用來找出上述方程式的解決。因此,加權 與分路的更新方程式是如下式表示: 万程式 25 ·· Wm(k+l)=Wm(k)i x(|X(k)|2])xX(k)xAi*(k) fn/(k),其中πι=1,2,···,Ν 方程式 26 : An(k+l)=An(k)4x(|x(k)|2-1)xX(k)xY*(kn),Equation 23: 1 97 ---- 〇 dw; m = 1,2, ··· N Equation 24: dJ f = 0 n = 1,2, ... L A statistical gradient can be used to find the solution to the above equation. Therefore, the update equations for weighting and shunting are expressed as follows: Wan Cheng 25 ·· Wm (k + l) = Wm (k) ix (| X (k) | 2]) xX (k) xAi * (k) fn / (k), where π = 1, 2, ..., N Equation 26: An (k + l) = An (k) 4x (| x (k) | 2-1) xX (k) xY * (kn),
其中 11 =1,2,…,;L 在上述方程式25和26的兩方程式中,"是一常數,用以 表示步進大小’而k係表示取樣範例t = kT〆因此,上述方 程式係表示加權與分路的一時間平均。 如圖3的討論,加法器1520的輸出是回授給多路徑回信偵 測器與信號品質監督器300,以決定計算信號的回信是否減 少低於允許回信的預定臨界值。如果是如此,經由導線32〇 的控制信號可選取導線312,以經由MUX 306而當作 -47 - 本紙張尺度適用中國國家標準(CNS) A4规格(210 x 297公釐) 582141 A7 _____ B7 五、發明説明(44 )Where 11 = 1, 2, ...,; L In the two equations of the above equations 25 and 26, " is a constant used to indicate the step size 'and k is the sampling example t = kT. Therefore, the above equation is Represents a time average of weighting and shunting. As discussed in Figure 3, the output of the adder 1520 is fed back to the multi-path response detector and the signal quality monitor 300 to determine whether the response of the calculated signal is reduced below a predetermined threshold that allows the response. If so, the control signal via the wire 32 can be selected as the wire 312 to be regarded as -47 through the MUX 306-This paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 582141 A7 _____ B7 5 Description of the invention (44)
Icomb、QC0mb提供給導線208。然而,如果多路徑回信偵 測器仏號品質監督器3〇〇決定回信是保持超過預定臨界值, 時2單元302便執行另一重複,以進一步減少來自信號的多 路徑回信,如此可重複於處理。 圖16係描述如圖3和4所使用的多路徑回信偵測器信號品 貝監督器3〇〇、402的一具體實施例。如果使用圖3的具體實 施例,係數電路1600可分別經由導線314和316接收輸入信 號ΙΓ、Q1,和12,、Q2,。在圖4的具體實施例中,多路徑回 #偵測器與信號品質監視402是經由導線4丨6而接收組合 Π*、Q1·和12’、Q2’信號。然後,係數電路16〇〇計算數位 複雜基帶信號的係數。理想上,結果應該等於一常數值。 然而,在時間變化行動頻道中,傳輸信號會受到頻道衰減 而受影響。在一FM無線電系統中,雖然頻道的變化相較於 寬頻FM信號的頻寬通常較慢。因此,帶通濾波器16〇2可用 來掏取由多路徑回信所造成的係數變化,且可忽略頻道的 較慢變化。帶通濾波器16〇2輸出的平均信號強度然後可透 過平均信號強度偵測器1604計算。比較電路1606然後將平 均信號強度與例如臨界值強度1608的一預設值相比較。一 判斷然後可根據比較結果達成。如果平均信號強度是大於 臨界值強度值1608 ’那麼接收信號I〗,、qi,或12,、Q2,、 或他們的組合需要回信取消處理。即是,在圖3的具體實施 例中’ 11’、Q Γ和12’、Q2’會傳送給時空單元302,以處理 頻率選擇衰減頻道。在圖4的具體實施例中,多路徑回信偵 測k號品質監督器402可啟動回信消除器4〇6 ,以便在將結 -48 - 本紙張尺度適用中國國家標準(CNS) A4規格(21〇 X 297公爱) 582141 A7 一____B7 五、發明説明(~45^~' — 果當作Icomb、Qc〇mb輸出給導線208之前,執行從多樣組 合單元404接收信號的回信取消。 注意’在整個應用描述的各種不同硬體單元與電路可由 各種不同功能重複使用或共用。例如,圖17描述的電路 1718可用來實施一狀態機器,以控制上述其他功能的執 行,而且未局限於只計算加權因素W丨和W2。本發明的具 體實施例能以硬體、款體、或在兩組合實施。例如,一些 具體實施例能以具有使用微碼控制電路的一有限狀態機器 貫訑,以控制狀怨機器的執行。或者,軟體碼可用來執j于 上述功能。 在珂述說明書中,本發明是描述特殊具體實施例。然 而,在技藝中熟諳此技者可了解到各種不同修改與可達 成,而不致於達背在下面申請專利範圍中所揭露本發明的 範圍。因此,說明書與圖式只說明而不是限制,而且所有 此修改是在本發明的範圍内。 利益、其他優點、與問題解決已於上面參考特殊具體實 施例描述。然而,利益、優點、問題解決、與造成任何利 益、優點、或解決的任何元件不應該構成任何或所有申請 專利的一決定性、必需、或本質特徵或元件。如在此的使 用,術語,,包含”、,,包括,,、或任何其他相關變化係涵蓋一 非獨佔性包含,以致於包含元件清單的處理、方法 '文 獻、或裝置不僅包括這些元件,而且包括未在此處理、方 法、文獻、或裝置中表示的其他元件。 -49 -Icomb, QC0mb are provided to the wire 208. However, if the multi-path reply detector 仏 number quality supervisor 300 decides that the reply keeps exceeding a predetermined threshold, the unit 2 302 performs another repetition to further reduce the multi-path reply from the signal, so it can be repeated in deal with. FIG. 16 depicts a specific embodiment of the multipath response detector signal product monitors 300, 402 used in FIGS. 3 and 4. FIG. If the specific embodiment of FIG. 3 is used, the coefficient circuit 1600 can receive input signals IΓ, Q1, and 12, Q2, via wires 314 and 316, respectively. In the specific embodiment of FIG. 4, the multi-path loopback #detector and signal quality monitoring 402 receive the combined signals Π *, Q1, and 12 ', Q2' via the wires 4 丨 6. The coefficient circuit 160 then calculates the coefficients of the digitally complex baseband signal. Ideally, the result should be equal to a constant value. However, in time-varying mobile channels, the transmission signal is affected by channel attenuation. In an FM radio system, although the channel change is usually slower than the bandwidth of a wideband FM signal. Therefore, the band-pass filter 1602 can be used to extract the coefficient change caused by the multipath reply, and the slower change of the channel can be ignored. The average signal strength output by the band-pass filter 1602 can then be calculated by the average signal strength detector 1604. The comparison circuit 1606 then compares the average signal strength with a preset value such as the threshold strength 1608. A judgement can then be reached based on the results of the comparison. If the average signal strength is greater than the threshold strength value of 1608 ′, then the received signal I, qi, or 12, Q2, or a combination of them needs to reply to cancel the processing. That is, in the specific embodiment of FIG. 3, '11', Q Γ, and 12 ', Q2' are transmitted to the space-time unit 302 to select the attenuation channel according to the processing frequency. In the specific embodiment of FIG. 4, the multi-path reply detection k-number quality supervisor 402 may start the reply canceller 406 so that the national paper (CNS) A4 specification (21 〇X 297 public love) 582141 A7 A ____B7 V. Description of the invention (~ 45 ^ ~ '— Before Icomb and Qc〇mb are output to the wire 208, the reply of the signal received from the multiple combination unit 404 is cancelled. Note' The various hardware units and circuits described throughout the application can be reused or shared with a variety of different functions. For example, the circuit 1718 described in FIG. 17 can be used to implement a state machine to control the execution of the other functions described above, and is not limited to computing only Weighting factors W 丨 and W2. Specific embodiments of the present invention can be implemented in hardware, style, or a combination of both. For example, some specific embodiments can be implemented with a finite state machine with a microcode control circuit to Control the execution of the machine. Alternatively, software code can be used to perform the above functions. In the description, the invention describes a specific embodiment. However, it is well known in the art. The person can understand that various modifications and can be achieved without departing from the scope of the present invention disclosed in the scope of the patent application below. Therefore, the description and drawings are only illustrative and not limiting, and all such modifications are in the present invention Benefits, other advantages, and problem solving have been described above with reference to specific embodiments. However, benefits, advantages, problem solving, and any element that causes any benefit, advantage, or solution should not constitute any or all patent applications. A decisive, required, or essential feature or element. As used herein, terminology, including, ",, including, or any other relevant variation covers a non-exclusive inclusion, so as to include the processing of a list of components , Method 'literature, or device includes not only these elements, but also other elements not represented in this process, method, literature, or device. -49-
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US09/916,915 US6760386B2 (en) | 2001-07-27 | 2001-07-27 | Receiver and method therefor |
US09/916,685 US20030035498A1 (en) | 2001-07-27 | 2001-07-27 | Receiver and method therefor |
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US6369938B1 (en) | 1996-05-28 | 2002-04-09 | Fujitsu Limited | Multi-wavelength light amplifier |
US6603596B2 (en) | 1998-03-19 | 2003-08-05 | Fujitsu Limited | Gain and signal level adjustments of cascaded optical amplifiers |
DE102005054574A1 (en) * | 2005-11-16 | 2007-05-24 | Robert Bosch Gmbh | A receiver and method for receiving a digital radio signal and providing a data stream |
US20070297497A1 (en) * | 2006-06-21 | 2007-12-27 | Seibert Cristina A | Apparatus And Method For Interference Cancellation |
JP5085269B2 (en) * | 2007-10-23 | 2012-11-28 | 京セラ株式会社 | Wireless communication device |
US8130145B2 (en) * | 2009-06-24 | 2012-03-06 | Qualcomm Incorporated | Receive diversity in GNSS receivers |
US11805396B2 (en) | 2019-03-27 | 2023-10-31 | Analog Devices, Inc. | Coherent summation in wireless sensor platforms |
CN112865892B (en) * | 2021-01-19 | 2023-05-16 | 中国科学院国家空间科学中心 | Adaptive generalized selection diversity combining method and system based on signal-to-noise ratio sequencing |
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US4210871A (en) * | 1978-09-01 | 1980-07-01 | The United States Of America As Represented By The Secretary Of The Navy | Optimum diversity combining circuit for a plurality of channels |
US6067295A (en) * | 1997-01-13 | 2000-05-23 | Lucent Technologies, Inc. | Method and apparatus for reducing error in recovering information bits in a wireless system |
US5710995A (en) * | 1997-01-16 | 1998-01-20 | Ford Motor Company | Adaptive antenna receiver |
US6172970B1 (en) * | 1997-05-05 | 2001-01-09 | The Hong Kong University Of Science And Technology | Low-complexity antenna diversity receiver |
US6141536A (en) * | 1998-06-23 | 2000-10-31 | Visteon Global Technologies, Inc. | Diversity radio system with RDS |
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US6151487A (en) * | 1999-08-31 | 2000-11-21 | Hughes Electronics Corporation | Demodulation structure for fast fading cellular channels |
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