CN100566206C - Method for generating combined signal - Google Patents

Abstract

Embodiments of the present invention generally relate to receivers. One embodiment relates to a digital FM (100) receiver having multiple sensors (e.g., antennas) (102, 104). In one embodiment, a digital receiver includes a baseband unit (116) having a channel processing unit. In one embodiment, the channel processing unit is capable of calculating or estimating the phase difference between the input signals prior to combining them. One embodiment employs a phase estimation method to diversity combine the signals, while another embodiment employs a hybrid phase-locked loop method. Also, some embodiments of the invention perform echo cancellation after diversity combining. An alternative embodiment of the channel processing unit employs a space-time unit to diversity combine and echo cancel the incoming signals. Other embodiments of the present invention allow input signals from multiple antennas to pass through an uncombined baseband unit where the input signals may have different data formats.

Description

A kind of method that produces combined signal

Technical field

Present invention relates in general to receiver, more specifically to radio receiver.

Background technology

The a plurality of sensing devices of common employing for example antenna provide more information to receiver.But owing to reflect unintentionally and scattering, a plurality of transducers receive the signal that is subjected to different delays and decay of the mutual superposition that sends signal usually to small part.The multichannel component that receives from send signal has out of phase usually, and these phase places may be grown or add together mutually with disappearing mutually, makes receiving signal attenuation thus.Therefore, need a kind of improved receiver to merge effectively or handle these received signals from a plurality of transducers.In addition, the reliability standard that needs to reduce the influence of multipath echo and improve these receivers.

Summary of the invention

According to a first aspect of the invention, provide a kind of being used for to merge to produce the method for a combined signal from first signal of first sensor and secondary signal from second transducer, this method comprises: determine the phase difference between first signal and the secondary signal; Determine first weights, wherein these first weights and described phase difference are irrelevant; Determine second weights, wherein these second weights and described phase difference are irrelevant; First weights are applied to first signal to produce first weighted signal; Second weights are applied to secondary signal to produce second weighted signal; And when with first weighted signal and the merging of second weighted signal, adopt described phase difference.Wherein, determine that the step of phase difference comprises: with the complex conjugate of described first signal times, to produce an intermediate object program with described secondary signal; To described intermediate object program filtering, to produce intermediate object program once filtering; Utilization obtains phase difference through the intermediate object program of filtering.

According to a second aspect of the invention, provide a kind of being used for to merge to produce the method for a combined signal from first signal of first sensor and secondary signal from second transducer, this method comprises: determine first characteristics of signals of first signal, wherein first characteristics of signals is not a signal-to-noise characteristic; When being merged, first signal and secondary signal adopt first characteristics of signals to come when producing described combined signal to first signal weighting; Determine the phase difference between first signal and the secondary signal; Utilize at least one the phase place in described phase difference correction first and second signals.Wherein, determine that the step of phase difference comprises: with the complex conjugate of first signal times, to produce an intermediate object program with secondary signal; This intermediate object program is carried out filtering, to produce intermediate object program once filtering; From isolating described phase difference through the intermediate object program of filtering.

According to a third aspect of the invention we, provide a kind of being used for to merge to produce the method for a combined signal from first signal of first sensor and secondary signal from second transducer, this method comprises: first characteristics of signals of determining first signal, wherein, this first characteristics of signals is not a signal-to-noise characteristic; When merging first signal and secondary signal when producing described combined signal, utilize first characteristics of signals to described first signal weighting; Determine the secondary signal characteristic of secondary signal; When merging first signal and secondary signal when producing described combined signal, utilize the secondary signal characteristic to the secondary signal weighting; Determine first weights based on first characteristics of signals of first signal and the secondary signal characteristic of secondary signal; Determine second weights based on first characteristics of signals of first signal and the secondary signal characteristic of secondary signal.

According to a forth aspect of the invention, provide a kind of being used for to merge to produce the method for a combined signal from first signal of first sensor and secondary signal from second transducer, this method comprises: first characteristics of signals of determining first signal, wherein, this first characteristics of signals is not a signal-to-noise characteristic; When merging first signal and secondary signal when producing described combined signal, utilize first characteristics of signals to first signal weighting; Calculate the square root of the power of first signal; Wherein, utilize first characteristics of signals that the step of first signal weighting is comprised the steps: when merging first signal and secondary signal when producing described combined signal, the square root of power that utilizes first signal is to first signal weighting.

According to a fifth aspect of the invention, provide a kind of being used for to merge to produce the method for a combined signal from first signal of first sensor and secondary signal from second transducer, this method comprises: first characteristics of signals of determining first signal, wherein, this first characteristics of signals is not a signal-to-noise characteristic; When merging first signal and secondary signal when producing described combined signal, utilize first characteristics of signals to first signal weighting; Determine the secondary signal characteristic of secondary signal; When merging first signal and secondary signal when producing described combined signal, utilize the secondary signal characteristic to the secondary signal weighting; Determine first weights based on first characteristic, wherein this first weights and phase-independent; Determine second weights based on second characteristic, wherein this second weights and phase-independent; Determine which has bigger amplitude in first signal and the secondary signal; If the amplitude of first signal greater than the amplitude of secondary signal, then makes first weights greater than second weights; If the amplitude of secondary signal greater than the amplitude of first signal, then makes second weights greater than first weights.

According to a sixth aspect of the invention, provide a kind of being used for to merge to produce the method for a combined signal from first signal of first sensor and secondary signal from second transducer, this method comprises: adopt phase-locked loop to estimate phase difference between first signal and secondary signal; When described phase-locked loop locked: with described phase difference, to produce a phase correction signal, wherein, the output of phase-locked loop provided described phase difference with first signal times; Described phase correction signal is added on the secondary signal, to produce a combined signal; If the phase-locked loop non-locking then selects one in first signal and the secondary signal to replace described combined signal as output.

According to a seventh aspect of the invention, a kind of Base Band Unit is provided, be used to receive first signal from first reception sources, and be used to receive secondary signal from second reception sources, described Base Band Unit provides an output, described Base Band Unit comprises: first module, be used to adopt first algorithm to merge first signal and secondary signal, wherein, first module merges first and second signals and forms a combined signal, this first module comprises: to the sef-adapting filter of described combined signal filtering, and weight renovator, couple with described sef-adapting filter, wherein, this weight renovator provides when merging first and second signals and is used at least one weights that are weighted to first and second signals when forming described combined signal; Unit second is used to adopt second algorithm to merge first signal and secondary signal; And multipath echo detector and signal quality monitor, be used to monitor first quality level of first signal and second quality level of secondary signal, and to be used for selecting be to adopt first module or adopt Unit second that output is provided.

According to an eighth aspect of the invention, a kind of Base Band Unit is provided, be used to receive first signal from first reception sources, and be used to receive secondary signal from second reception sources, described Base Band Unit provides an output, described Base Band Unit comprises: first module is used to adopt first algorithm to merge first signal and secondary signal; Unit second is used to adopt second algorithm to merge first signal and secondary signal; And multipath echo detector and signal quality monitor, be used to monitor first quality level of first signal and second quality level of secondary signal, and be used for selecting is to adopt first module or adopt Unit second that output is provided, wherein, multipath echo detector and this signal quality monitor comprise: modulus circuit; Be couple to the filter of this modulus circuit; Be couple to the average signal strength detector of this filter; And comparison circuit, being couple to the average signal strength detector, this comparison circuit compares the average signal strength and the predetermined threshold value of first signal, and average signal strength and this predetermined threshold of secondary signal compared.

According to a ninth aspect of the invention, a kind of Base Band Unit is provided, be used to receive first signal from first reception sources, and be used to receive secondary signal from second reception sources, described Base Band Unit provides an output, described Base Band Unit comprises: a unit is used for first signal and secondary signal being merged and providing a combined signal; The signal quality monitor is used for determining the mass property of combined signal and be used to provide control signal that wherein, described mass property comprises the multipath echo information; And echo eliminator, this echo eliminator receives the control signal from signal monitor, and optionally is used for being combined signal according to described mass property and carries out echo and eliminate.

According to the tenth aspect of the invention, a kind of Base Band Unit is provided, be used to receive first signal from first reception sources, and be used to receive secondary signal from second reception sources, described Base Band Unit provides an output, and described Base Band Unit comprises: the signal quality monitor, be used for determining first signal and secondary signal at least one mass property and be used to provide control signal, wherein, described mass property comprises the multipath echo information; Unit one is used for first signal and secondary signal being merged and providing a combined signal; And echo eliminator, this echo eliminator receives the control signal from signal monitor, and optionally is used for being combined signal according to mass property and carries out echo and eliminate.

Description of drawings

The present invention adopts the mode of embodiment to describe and be not limited to the following drawings, and wherein identical Reference numeral is represented similar elements, wherein:

Fig. 1 demonstrates according to an embodiment of the invention radio receiver with the form of block diagram;

Fig. 2 demonstrates the part of the Base Band Unit of Fig. 1 according to an embodiment of the invention with the form of block diagram;

Fig. 3-4 with the form of block diagram demonstrate according to an embodiment of the invention Fig. 3 or the part of 4 diversity merge cells;

Fig. 5 with the form of block diagram demonstrate according to an embodiment of the invention Fig. 3 or the part of 4 diversity merge cells;

Fig. 6 demonstrates the operation of the diversity merge cells of Fig. 5 according to an embodiment of the invention in a flowchart;

The weighted factor that Fig. 7 demonstrates Fig. 5 according to an embodiment of the invention with the form of block diagram is determined the part of circuit;

Fig. 8 demonstrates the part of the phase estimation circuit of Fig. 5 according to an embodiment of the invention with the form of block diagram;

Fig. 9 demonstrates the part of the diversity merge cells of Fig. 5 according to an embodiment of the invention with the form of block diagram;

Figure 10 with the form of block diagram demonstrate according to an alternative embodiment of the present invention Fig. 3 or the part of 4 diversity merge cells;

Figure 11 demonstrates the operation of the diversity merge cells of Figure 10 according to an alternative embodiment of the present invention in a flowchart;

Figure 12 demonstrates the part of the signal characteristic numerical value estimating circuit of Figure 10 according to an embodiment of the invention with the form of block diagram;

Figure 13 demonstrates the part of multiplier and phase-locked loop and the lock detecting circuit of Figure 10 according to an embodiment of the invention with the form of block diagram;

Figure 14 demonstrates the part of the lock detector of Figure 13 according to an embodiment of the invention with the form of block diagram;

Figure 15 with the form of block diagram demonstrate according to an embodiment of the invention Fig. 3 the time dummy cell a part; And

Figure 16 demonstrates according to an embodiment of the invention Fig. 3 or 4 the multipath echo detector and the part of signal quality monitor with the form of block diagram;

The weighted factor that Figure 17 demonstrates Fig. 5 of an optional embodiment according to the present invention with the form of block diagram is determined the part of circuit;

The weights that Figure 18 demonstrates Figure 17 are according to an embodiment of the invention in a flowchart determined the operation of circuit.

Those of ordinary skill know in these drawings element just for simplify and know for the purpose of, and needn't draw in proportion.For example, some size of component in these figure are amplified to help improve the understanding to embodiment of the present invention with respect to other element.

Embodiment

Here employed term " bus " is used to refer to generation and a plurality ofly can be used for transmitting one or more different types of information for example holding wire or the lead of data, address, control or state.Lead described here can for example illustrate or be described as single lead, multiple conducting wires, unidirectional conductor or bidirectional conductor.But different embodiments can change the application of these leads.For example, can adopt unidirectional conductor rather than bidirectional conductor separately, vice versa.Also have, the solid conductor that can transmit a plurality of signals with the mode or the time division multiplex transmission manner of serial replaces multiple conducting wires.Equally, the single lead that carries a plurality of signals can be divided into the various different conductors of the subclass of carrying these signals.Therefore, there are many selections for transmitting signal.

Term " establishment " and " cancellation " are used in and refer to respectively when signal, mode bit or similar devices be set as its logical truth or logical falsehood state.If the logical truth state is a logic level 1, then the logical falsehood state is a logic level 0.If the logical truth state is a logic level 0, then the logical falsehood state is a logic level 1.

Adopt bracket to represent the lead of bus or the bit position of numerical value.Eight low level leads of " bus 60[0-7] " or " lead of bus 60 [0-7] " expression bus 60 for example, and eight low-order bit of " address bit [0-7] " or " ADDRESS[0-7] " presentation address value.Represent that at the symbol " $ " of digital front this numeral adopts the hexadecimal form.Represent that at the symbol symbol " % " of digital front this numeral adopts binary form.

In brief, notice that Fig. 1 demonstrates an embodiment of the radio receiver with Base Band Unit, and Fig. 2 demonstrates an embodiment of the Base Band Unit of Fig. 1.Fig. 3 and 4 has provided the different embodiments of channel bank (in the Base Band Unit of Fig. 2).These two embodiments (Fig. 3 and 4) can estimate the phase difference between them before input signal is merged.Also have, each selection scheme that provides echo to eliminate in Fig. 3 and 4 the embodiment, this carries out when input signal being taked diversity merge usually.In Fig. 3 by the time dummy cell 302 and in Fig. 4, carry out this echo and eliminate by echo eliminator 406.Also have, Fig. 3 and Fig. 4 comprise a diversity merge cells (304,404), and they can merge a plurality of input signals.Therefore Fig. 5 and 10 has illustrated the optional embodiment of diversity merge cells 304 and 404.Fig. 5 has illustrated the phase estimation method that is used for combined signal, and Figure 10 demonstrates a kind of mixing PLL method.Therefore, embodiment of the present invention provide various possibility, and they can be used in the Base Band Unit (and usually in channel bank).

Fig. 1 demonstrates radio receiver according to an embodiment of the invention.Radio receiver 100 comprises by lead 144 and the control circuit 112 two-way user interfaces that are connected 110.Control circuit 112 is connected with intermediate frequency (IF) unit 114 by lead 140 by lead 142 and radio frequency (RF) unit 106 and 108 two-way connections, is connected with Base Band Unit 116 by lead 138.RF unit 106 is connected with RF antenna 104 by lead 120, and by lead 126 and 114 two-way connections of IF unit.IF unit 114 is connected with Base Band Unit 116 with 132 by lead 128,130.Base Band Unit 116 is connected with data processing unit 148 with audio treatment unit 150 by lead 134.Audio treatment unit 150 is connected with loud speaker 118 with the amplifier that output signal is provided by lead 136. Data processing unit 148 and 110 two-way connections of user interface.Also have, the user can provide information and therefrom receive information to user interface 110 by lead 146.

During work, RF antenna 102 and 104 is caught radio signal and they is offered RF unit 106 and 108 respectively. RF unit 106 and 108 converts received radio signal to stipulated by the designing institute of radio receiver common intermediate frequency range.That is, RF unit 106 can become low frequency or convert high frequency to 108 according to the requirement of IF unit 114 frequency inverted with received radio signal.IF unit 114 receives the RF signal by lead 124 and 126, and by using analogue-to-digital converters with they digitlizations.IF unit 114 also carries out numeral and mixes (digital mixing) to produce homophase and orthogonal digital signal, and these signals are fed to Base Band Unit 116 by lead 128 and 130.In optional embodiment, IF114 is optional.That is to say that RF unit 106 and 108 can directly be converted to base band with the radio signal that receives from antenna 102 and 104, and can comprise that analogue-to-digital converters are directly to offer Base Band Unit 116 with the digitlization baseband signal.(it is also noted that, according to whether needs convert the radio signal that is received to low frequency or high frequency respectively, can with RF unit 106 and 108 and IF114 (if you are using) be called " low frequency cell " or " high frequency unit ".)

Base Band Unit 116 receive from intermediate frequency unit 114 or under the situation that does not have the IF unit directly from the digital radio signal of telecommunication of RF unit 106 and 108.Base Band Unit 116 carries out Signal Regulation, demodulation sign indicating number so that produce audio frequency and data message by lead 134.Accompanying drawing with reference to the back is described further the processing of being undertaken by Base Band Unit 116 below.Can audio-frequency information be offered audio treatment unit 150 by lead 134, this audio treatment unit can be connected with loud speaker 118 to produce audio frequency output from receiver 10 by lead 136 with amplifier.For example, this can be the music that plays out from radio speaker.Perhaps, Base Band Unit 116 can be exported to data processing unit 148 so that further handle with data message by lead 134.The output of data processing unit 148 can be connected with user interface 110 so that the user can interact with the output of receiver 100.For example, user interface 110 can be radio dial (radio dial), touch-screen, monitor and keyboard, keypad or other suitable input/output device arbitrarily.Data message can be text, figure or other information that transmits with digital form arbitrarily.

In optional embodiment, radio receiver 100 can adopt different data formats for example AM, FM, GPS, Digital Television, T.V., numeral/audio broadcasting, audio broadcasting, numeral/video broadcasting etc.In addition, receiver 100 can be designed to the frequency outside the received RF.Antenna 102 and 104 therefore can be called as can the various data formats of sensing transducer.In addition, each transducer or antenna in this system can receive different data formats, thereby for example a transducer can receive radio signals, and other transducer can receive the data of different types as listing above.Also have, the receiver 100 of Fig. 1 demonstrates two transducers or antenna (for example antenna 102 and 104); But optional embodiment can adopt the transducer of any amount to come lock-on signal or information.

Fig. 2 demonstrates an embodiment of the part of Base Band Unit 116.IF filter 200 receives homophase and orthogonal signalling respectively to I1, Q1 and I2, Q2 by lead 128 and 130, wherein I1, Q1 be corresponding to the signal that receives by transducer or antenna 102, and I2, Q2 are corresponding to the signal that receives by transducer or antenna 104.I1 and I2 represent the digitized inphase signal, and Q1 represents digitized quadrature signals (for example comparing the signal of phase difference 90 degree with in-phase signal) with Q2.(it is also noted that each signal for example I1, Q1 and I2, Q2 can be expressed as a plural number, wherein I1 and I2 represent real part and Q1 and Q2 represent imaginary part, and this will be described further below.) IF filter 200 is connected with channel bank 206 with 204 by lead 202.Channel bank 206 is connected with demodulator 212 with 210 by lead 208, and demodulator 212 is connected with signal processing unit 216 by lead 214.Signal processing unit 215 provides audio/data information by lead 134.IF filter 200, channel bank 206, demodulator 212 and signal processing unit 216 are connected with control circuit 112 by lead 138.Lead 138 can be called as control bus, and it comprises the various leads that are used for unlike signal being sent to/being sent unit 200,206,212 and 216.Lead 132 for example can comprise the subclass of lead 138, perhaps can be the complete bus (full bus) of getting back to intermediate frequency unit 114.Therefore, can will send IF unit 114 by the control signal that lead 138 receives to by lead 132.Equally, can send back RF unit 106 and 108 by lead 124 and 126 subclass with these control signals or these signals.Perhaps, can from control circuit 112 control signal directly be sent to radio unit 106 and 108 by lead 142.

During work, IF filter 200 is removed undesired signal and noise from input signal I1, Q1 and I2, Q2.IF filter 200 has also suppressed adjacent channel so that produce through the homophase of filtering and orthogonal signalling I1 ', Q1 ' and I2 ', Q2 ', and wherein I1 ', Q1 ' be corresponding to I1, Q1, and I2 ', Q2 ' are corresponding to I2, Q2.Channel bank 206 receives I1 ', Q1 ' and I2 ', Q2 ', and these signals are merged to produce single combined signal Icomb, Qcomb.Perhaps, channel bank 206 can also by lead 210 with its input signal for example among I1 ', Q1 ' or I2 ', the Q2 ' directly offer demodulator 212 as Ibypass, Qbypass.Therefore, channel bank 206 provides and the digitized signal of its input is merged or has made their direct bypass to for example selection of demodulator 212 of other processing unit.Channel bank 206 can also provide for example for example Ibypass, Qbypass of Icomb, Qcomb and bypass signal of composite signal.Channel bank 206 and Ibypass, Qbypass also provide the ability that receives the signal with different type form, thereby signal for example I1 ', Q1 ' can be handled and by lead 208 outputs by channel bank 206, and second signal for example I2 ', Q2 ' they can be that directly bypass is given the unlike signal form of demodulator 212.(perhaps, I1 ', Q1 ' can handle and need not pass through channel bank 206 by lead 208 outputs).This makes channel bank 206 can provide single composite signal or various unlike signal so that further handle.For example, antenna can provide the signal from a radio station, and second antenna can provide simultaneously from second radio station or different data format the signal.Channel bank 206 can also remove on received signal and make an uproar.

It is also noted that, only demonstrate two signals that receive by IF filter 200 and channel bank 206 in the embodiment shown in Fig. 2.But, as described in reference Fig. 1, the antenna that receiver 100 can comprise any amount for example 102 and 104.In this embodiment, each antenna can to IF filter 200 provide himself homophase and orthogonal signalling to for example I1, Q1.In this embodiment, IF filter 200 can provide right with corresponding a plurality of homophase and the orthogonal signalling through filtering of each antenna.Like this, channel bank 206 can be exported single combined signal or a plurality of signal subclass in due course.Also have, channel bank 206 can provide a plurality of bypass signal, thereby can make the direct bypass of more than one input signal give for example demodulator 212 of other processing unit.

Demodulator 212 receives signal Icomb, Qcomb and Ibypass, the Qbypass from channel bank 206, and provides restituted signal by lead 214 to signal processing unit 216.Also have, if demodulator 212 receives signal Ibypass, Qbypass, then demodulator 212 also can provide Ibypass, the Qbypass of demodulation by lead 214 to signal processing unit 216.But as mentioned above, Ibypss, Qbypass are optional.For example, in one embodiment, demodulator 212 can be for providing the FM demodulator with its each input signal (for example, Icomb, Qcomb and Ibypass, Qbypass) corresponding multiplexed (MPX) signal.In optional embodiment, demodulator 212 can or be exclusively used in the desired demodulator of other signal format arbitrarily of this system (for example, receiver 100) and input signal I1, Q1 and I2, Q2 for the AM demodulator.Signal processing unit 216 can further be handled on received signal by lead 214, and by lead 134 output audios/data message.Audio/data information can only comprise audio-frequency information, only comprise data message or comprise audio frequency and the combination of data message.These data can be exported to various system for example data handling system or audio frequency processing system as shown in Figure 1 then.For example, in the FM receiver, demodulator 212 is exported to signal processing unit 216 with the MPX signal as mentioned above.In this embodiment, signal processing unit 216 receives the MPX signal, and carries out stereo decoding so that provide correct signal to each loud speaker.For example, can utilize pilot tone to come the MPX signal is decoded so that left and right sides loudspeaker signal to be provided in stereophonic sound system.Also have, signal processing unit 216 can be with other subcarrier signal (for example RDS or DARC) demodulation to provide further information to subsequently processing unit.

Fig. 3 demonstrates an embodiment of the part of channel bank 206 with the form of block diagram.Gain circuitry 310 receives I1 ', Q1 ' and I2 ', Q2 ' by lead 202 and 204.Gain circuitry 310 also receives by lead 138 and offers control circuit 112 from the control signal of control circuit 112 and with control signal.Gain circuitry 310 by lead 314 with 316 with multipath echo detector and signal quality monitor 300, the time dummy cell 302 and diversity merge cells 304 be connected.MUX308 receives control signal by lead 314 and 316 receiving inputted signals by lead 138, and by lead 210 output Ibypass, Qbypass.MUX306 receives control signal by lead 312 and 318 receiving inputted signals by lead 320, and by lead 208 output Icomb, Qcomb.Lead 320 can or can be the direct control signal that receives from multipath echo detector and signal-quality detector 300 for the subclass of lead 138.

During work, gain circuitry 310 receives I1 ', Q1 ' and I2 ', Q2 ', regulate the signal level of these input signals, and by lead 314 provide I1 ', Q1 ' through the result of gain-adjusted and the result through gain-adjusted of I2 ', Q2 ' is provided by lead 316.Therefore, in the subdivision of the explanation that relates to Fig. 3 and Fig. 3, I1 ', Q1 ' and I2 ', Q2 ' will be called as the form through gain-adjusted of these signals that send by lead 314 and 316.Multipath echo detector and signal quality monitor 300 receive I1 ', Q1 ' and I2 ', Q2 ', and determine whether to carry out the echo elimination.Cause in the situation of too many interference (for example echo) at the multichannel component of the input signal at antenna 102 and 104 places (may owing to scattering and reflection occur unintentionally) therein, can before by lead 208 output combined signals, reduce these effects.

If determining to carry out echo, multipath echo detector and signal quality monitor 300 eliminate (promptly, echo volume surpasses predetermined echo threshold value), then multipath echo detector and signal quality monitor 300 to the time dummy cell 302 and diversity merge cells 304 provide control signal to select to carry out which kind of processing.For example, need to carry out in the situation of echo elimination therein, dummy cell 302 carried out signal processing when control signal 320 was selected, thereby can when carrying out the echo elimination input signal I1 ', Q1 ' and I2 ', Q2 ' correctly be merged before it provides as output.But, if do not detect enough echoes, then multipath echo detector and signal quality monitor 300 provide control signal so that these signals I1 ', Q1 ' and I2 ', Q2 ' are handled by lead 320 to diversity merge cells 304, thereby produce the output of merging by lead 318.Therefore diversity merge cells 304 provides combined signal under the situation of not carrying out the echo elimination.The control signal that is provided by lead 320 by multipath echo detector 300 has been also for MUX306 provides selector signal, and whether the output of dummy cell 302 or the output of diversity merge cells 304 are provided as Icomb, Qcomb by lead 208 when determining.With reference to Figure 16 the operation of multipath echo detector and signal quality monitor is described further below.

In the situation that detects the q.s echo, as mentioned above, dummy cell 302 when multipath echo detector and signal quality monitor 300 are selected.With the time dummy cell 302 output that provides by lead 312 feed back to multipath echo detector and signal quality monitor 300 and (, can think that then signal quality is enough good if detected echo volume is lower than predetermined echo threshold value to determine that signal quality is whether enough good.)。If enough not good, then carry out iterative operation subsequently, wherein, similarly, output is fed back to multipath echo detector and signal quality monitor 300.Below with reference to Figure 15 to the time dummy cell 302 operation illustrate in greater detail.In case determine that signal has enough good quality, promptly be lower than predetermined echo threshold value, then multipath echo detector and signal quality monitor 300 offer MUX306 by lead 320 with control signal so that select output 312 to provide as Icomb, Qcomb.Therefore these iterative operations are proceeded to eliminate up to having carried out enough echoes always.

Fig. 4 demonstrates the part of the channel bank 206 of the one optional embodiment according to the present invention.This part channel bank 206 of Fig. 4 comprises gain circuitry 400, multipath echo detector and signal quality monitor 402, diversity merge cells 404, echo eliminator 406 and MUX408.Diversity merge cells 404 and MUX408 receive I1 ', Q1 ' and I2 ', Q2 ' by lead 202 and 204.Diversity merge cells 404 offers MUX408 by lead 422 with combined signal.Gain circuitry 400 offers multipath echo detector and signal quality monitor 402 by lead 416 with the gain-adjusted signal.MUX408 receives the control signal from control circuit 112, and will offer lead 412 via I1 ', the Q1 ' of lead 412 with via I2 ', the Q2 ' of lead 414 or from 422 combined signal.In one situation of back, any signal is not offered lead 414, perhaps in optional embodiment, except combined signal, among I1 ', Q1 ' and I2 ', the Q2 ' can be offered lead 414.Gain circuitry also is connected with echo eliminator 406 by lead 416.Multipath echo detector is connected with echo eliminator 406 with 418 by lead 410 with signal quality monitor 402.Echo eliminator 406 provides output Icomb, Qcomb by lead 208, and gain circuitry 400 provides output Ibypasss, Qbypass by lead 210.Lead 138 transmits control signal between control circuit 112 and gain circuitry 400, multipath echo detector and signal quality monitor 402, diversity merge cells 404, echo eliminator 406 and MUX408.(be noted that different with the embodiment of Fig. 3, in the embodiment of Fig. 4, diversity merge cells 404 does not receive and I1 ', Q1 ' and the corresponding gain-adjusted input of I2 ', Q2 '.)

During work, can merge or individual processing I1 ', Q1 ' by channel bank 206.In last situation, diversity merge cells 404 passes through lead 202 and 204 received signal I1 ', Q1 ' and I2 ', Q2 ', and their are merged by lead 412 combined signal is offered gain circuitry 400 via lead 422 by MUX408.Gain circuitry 400 offers multipath echo detector 402 by lead 416 with the gain-adjusted combined signal of I1 ', Q1 ' and I2 ', Q2 '.Multipath echo detector 402 determines whether the multichannel component at antenna 102 and 104 places produces the echo greater than predetermined echo threshold value.If echo surpasses this predetermined threshold, then multipath echo detector 402 starts echo eliminator 406 to carry out the echo elimination at the signal that receives by lead 416 from gain circuitry 400 by lead 410.To feed back to multipath echo detector 402 at the signal of the output of echo eliminator 406 by lead 418.Thereby the echo whether multipath echo detector and signal quality monitor 402 definite echo eliminators 406 have eliminated q.s is reduced to echo is lower than predetermined echo threshold value.If the echo size is lower than predetermined threshold, then this signal quality is enough good, and echo eliminator 406 is by lead 208 output combined signal Icomb, Qcomb.But,, then determine that up to multipath echo detector and signal quality monitor 402 this signal has enough good signal quality (for example being lower than predetermined echo threshold value) by this signal of echo eliminator 406 iterative processings if echo still surpasses predetermined threshold.

Echo eliminator 406 can adopt any method for echo cancellation that signal Icomb, Qcomb are provided.For example, in the situation of the FM radio signal that needs constant amplitude, in echo eliminator 406, use and adopt constant modulus algorithm (CMA).That is to say that echo eliminator 406 is to be used for carrying out the Adaptive Signal Processing unit that echo is eliminated.Optional embodiment can adopt the lowest mean square echo to eliminate (LMS), recurrence lowest mean square echo and eliminate (RLS) or other suitable algorithm arbitrarily.Therefore, according to signal to be processed, can adopt various echo eliminators.

If nonjoinder I1 ', Q1 ' and I2 ', Q2 ' then offer MUX408 (walking around diversity merge cells 404) by lead 202 and 204 with I1 ', Q1 ' and I2 ', Q2 '.Control signal is connected with MUX408 by the control signal 408 of dealing control circuit 112.Therefore, if any among I1 ', Q1 ' or I2 ', the Q2 ' do not wanted nonjoinder, then MUX exports to lead 412 with one among I1 ', Q1 ' and I2 ', the Q2 ', and among I1 ', Q1 ' and I2 ', the Q2 ' another exported to lead 414.Each all obtains these two signals gain-adjusted and exports to lead 416 and 210.Lead 416 passes echo eliminator 406 (in this case, utilizing control signal that this echo eliminator is stopped using by lead 410), and exports as Icomb, Qcomb by lead 208.Another output of gain circuitry 400 provides output Ibypass, Qbypass by lead 210.Therefore, if merge without any need for signal, then with the I1 ' of gain-adjusted, Q1 ' output as any Icomb, Qcomb and Ibypass, Qbypass, and with the I2 ' of gain-adjusted, Q2 ' output as among Icomb, Qcomb and Ibypass, the Qbypass another.This makes it possible to select one or more signals to walk around diversity merge cells 404.As mentioned above, be useful in the situation of the signal of this or scope dissimilar at needs.In this embodiment, Icomb, Qcomb and Ibypass, Qbypass both are the signals that does not merge.Perhaps, certainly a signal (for example I1 ', Q1 ' or I2 ', Q2 ') that does not merge is provided as Icomb, Qcomb or Ibypass, Qbypass.That is to say,, then do not need to transmit these two signals if only need a signal.In also having an embodiment, combined signal can be provided as Icomb, Qcomb, and single (not merging) signal (for example I1 ', Q1 ' or I2 ', Q2 ') can be provided as Ibypass, Qbypass.Therefore can use bypass signal in the embodiment of Fig. 3 and 4 to come the output of selective channel processing unit 206 is the signals that merge or do not merge.This bypass signal for example can be the control signal of MUX308 and MUX408.Therefore, in one embodiment, can in control circuit 112, produce bypass signal.But optional embodiment can produce and utilize a bypass signal or a plurality of bypass signal according to different modes.

Fig. 5 demonstrates Fig. 3 and a diversity merge cells 304 of 4 and a part of 404 according to an embodiment of the invention respectively.Therefore, according to circumstances the circuit of Fig. 5 can be used in the embodiment shown in Fig. 3 and 4, perhaps is used in any other embodiment.Be noted that then I1 ', Q1 ' and I2 ', Q2 ' refer to the form of the process gain-adjusted of signal if the circuit of Fig. 5 is used in the embodiment of Fig. 3; But if the circuit of Fig. 5 is used in the embodiment of Fig. 4, then I1 ', Q1 ' and I2 ', Q2 ' do not represent the form of the process gain-adjusted of these signals, because gain circuitry 400 is connected on the diversity merge cells 404 in the downstream.Fig. 5 comprises that demultiplexer (DEMUX) 500 and 504, weighted factor determine circuit 502, multiplier 508,510,512 and 514, adder 516 and phase estimation circuit 506.DEMUX500 determines that with weighted factor circuit 502, multiplier 508 and multiplier 510 are connected with 520 by lead 518.DEMUX504 determines that with weighted factor circuit 502, multiplier 510 and multiplier 514 are connected with 524 by lead 522.Weighted factor determines that circuit 502 provides weighted factor W1 by lead 526 to multiplier 508, and provides weighted factor W2 by lead 528 to multiplier 512.Phase estimation circuit 506 is connected with multiplier 510 with 532 by lead 530, and phasing 1 is provided and provides phasing 2 by lead 540 to multiplier 512 to multiplier 512 by lead 538, described multiplier is connected with multiplier 514 with 544 by lead 542.Adder 516 is connected with multiplier 508 with 536 by lead 534, and is connected with multiplier 514 with 548 by lead 546.Decide with embodiment, adder 516 provides output I, Q by lead 318 or 422.Decide with embodiment, DEMUX500 receives I1 ', Q1 ' by lead 314 or 414, and decides with embodiment, and DEMUX504 receives I2 ', Q2 ' by lead 316 or 416.

During work, decide with embodiment,, DEMUX500 receives I1 ', Q1 ' by lead 314 or 202, and by lead 518 output I1 ', by lead 520 output Q1 '.Be noted that the real part of I1 ' expression complex signal, and the imaginary part of Q1 ' expression complex signal.That is to say Q1 ' and I1 ' 90 ° of phasic differences mutually.Equally, decide with embodiment, DEMUX504 receives I2 ', Q2 ' by lead 316 or 204, and by lead 522 output I2 ', and by lead 524 output Q2 '.As top, the real part of I2 ' expression complex signal I2 ', Q2 ', and the imaginary part of this complex signal of Q2 ' expression.(be noted that for example I1 ', Q1 ' and I2 ', Q2 ' can be written as the form of plural number, for example I1 '+jQ1 ' and I2 '+jQ2 ' respectively to each signal.)

I1 ', Q1 ' and I2 ', Q2 ' are provided for weighted factor and determine circuit 502, and this circuit calculates weighted factor according to amplitude or the energy of for example each input signal I1 ', Q1 ' and I2 ', Q2 '.Be described further with reference to Fig. 7 and 17 pairs of these circuit below.Therefore weighted factor determines that circuit 502 will export W1 (I1 ', the weighted factor of Q1 ') by lead 526 and offer multiplier 508, and by lead 528 W2 (I2 ', the weighted factor of Q2 ') is offered multiplier 512.Weighted factor determine circuit 502 according to I1 ', Q1 ' and I2 ', Q2 ' at least one corresponding characteristics of signals determine weighted factor W1 and W2.Optional embodiment can be according to determining W1 and W2 with I1 ', Q1 ' and both corresponding characteristics of signals of I2 ', Q2 '.This characteristics of signals can refer to the amplitude, power of signal or other suitable characteristic arbitrarily.In addition, can use the combination in any of characteristics of signals to determine weighted factor.Multiplier 510 receives I1 ', Q1 ' and I2 ', Q2 ', and makes I1 ', Q1 ' multiply by the complex conjugate of I2 ', Q2 '.This calculating can be extracted this two phase difference between signals information, and by lead 530 and 532 it is offered phase estimation circuit 506.

Phase estimation circuit 506 employing I1 ', Q1 ' calculate the phase difference between signal I1 ', Q1 ' and I2 ', the Q2 ' as a reference.By lead 538 this phase difference is exported to multiplier 512 as phasing 1 then, and it is exported to multiplier 512 as phasing 2 by lead 540.Utilize W2 to regulate this phase difference by lead 528, and offer multiplier 514 by lead 542 and 544.Multiplier 514 receives I2 ', Q2 ' and it be multiply by the result of multiplier 512 by lead 522 and 524.Therefore, by lead 546 and 548 514 output is offered adder 516.Multiplier 508 utilizes W1 to regulate I1 ', Q1 ', therefore adopt characteristics of signals for example the power of signal and amplitude as scale factor.Offer adder 516 by lead 534 and 536 results with multiplier 508.Therefore, decide, provide final combined signal I, Q by lead 318 or 422 with embodiment.Flow chart with reference to Fig. 6 will be understood these equatioies and calculating formula better.

Fig. 6 demonstrates the operation of the diversity merge cells 304,404 of Fig. 5 according to an embodiment of the invention.In square frame 602, receive I1 ', Q1 ' and I2 ', Q2 '.In square frame 604, according to I1 ', Q1 ' and I2 ', Q2 ' at least one corresponding at least one characteristics of signals determine weighted factor W1 and W2.For example, in one embodiment can be with power selection as the characteristics of signals that is used for determining W1 and W2, wherein W1 can equal the square root of power of I1 ', Q1 ' or proportional with it, and W2 can equate with the square root of the power of I2 ', Q2 ' or be proportional.Be noted that in one embodiment, calculate power or amplitude according to the combined effect of useful signal and system noise, and do not attempt to make this noise effects and useful signal to separate.In the embodiment of Fig. 6, weighted factor determines that circuit 502 can estimate the power (p2) of the power of I1 ', Q1 ' (p1) and I2 ', Q2 ', wherein $\mathrm{<figure-callout\; id="1"\; label="W"\; filenames="C028163590040H1.png,C028163590041H1.png"\; state="\{\{state\}\}">W</figure-callout>}1=\sqrt{\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="C028163590040H1.png,C028163590041H1.png"\; state="\{\{state\}\}">p</figure-callout>}1}$ And $\mathrm{<figure-callout\; id="2"\; label="W"\; filenames="C028163590052H1.png"\; state="\{\{state\}\}">W</figure-callout>}2=\sqrt{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="C028163590052H1.png"\; state="\{\{state\}\}">p</figure-callout>}2}$ 。Perhaps can select this amplitude, wherein W1 and W2 are the function of I1 ', Q1 ' or I2 ', Q2 ' or the two amplitude.Therefore, in this embodiment, weighted factor determines that circuit 502 can estimate I1 ', Q1 ' (AMP1) and I2 ', Q2 ' amplitude (AMP2).Be further described as characteristics of signals with reference to Figure 17 and 18 pairs of use amplitudes below.

With reference to Fig. 6, in square frame 606, I1 ', Q1 ' be multiply by the complex conjugate of I2 ', Q2 '.This can be undertaken by multiplier 510.This calculating can be expressed as follows:

Equation 1:(I1 '+jQ1 ') (I2 '-jQ2 ')=IM+jQM

In the superincumbent equation, can be with e ^{J (θ 1-θ 2)}=e ^{J Δ θ}The form phase place of writing resulting IM, QM signal, e wherein ^{J θ 1}The phase place of expression I1 ', Q1 ', e ^{J θ 2}The phase place of expression I2 ', Q2 ', and e ^{J Δ θ}Phase difference between expression I1 ', Q1 ' and I2 ', the Q2 ', this can further be expressed as follows:

Equation 2:e ^{J Δ θ}=cos (Δ θ)+jsin (Δ θ)

Therefore, in square frame 608, estimate phase difference e ^{J Δ θ}Wherein the output of the phase estimation circuit 506 of Fig. 5 can be expressed as two signals: the phasing 1 and the phasing 2 that is expressed as sin (Δ θ) (wherein phasing 1 is represented real part, and phasing 2 is represented the imaginary part of phase differences) that are expressed as cos (Δ θ).

In square frame 610, I2 ', Q2 ' be multiply by phase difference and W2, thereby obtain the result as shown in equation 3 below.(this calculating can be undertaken by multiplier 512.)

Equation 3:W2e ^{J Δ θ}(I2 '+jQ2 ')

In square frame 612, I1 ', Q1 ' be multiply by W1 to obtain the result as shown in equation 4 below.(this calculating can be undertaken by multiplier 508.)

Equation 4:W1 (I1 '+jQ1 ')

Therefore, in equation 3 and 4, W1 and W2 are used separately as the weighted factor of each corresponding signal I1 ', Q1 ' and I2 ', Q2 ', and wherein W1 and W2 can depend on characteristics of signals for example power or amplitude.In square frame 614, the result in square frame 610 and 612 is merged to obtain final combined signal I, Q (this can adopt the form of I+jQ to write).Can carry out this final calculating by adder 516, wherein decide according to the embodiment of channel bank 206, adder 516 provides this output I, Q by lead 318 or 422.Therefore this equation is expressed as follows:

Equation 5:I+jQ=W2e ^{J Δ θ}(I2 '+jQ2 ')+W1 (I1 '+jQ1 ')

With reference to top equation 5, first W2e in the equation ^{J Δ θ}Phase difference between (I2 '+jQ2 ') represented its phase change I1 ', Q1 ' and I2 ', the Q2 ' and by the W2 weighting I2 ', Q2 '.Second W1 in the equation (I1 '+jQ1 ') expression by its weighted factor W1 weighting I1 ', Q1 '.In optional embodiment, can not use any weighted factor.Therefore, equation 5 will not comprise this two weighted factor W1 and W2, and the diversity merge cells can not comprise that weighted factor determines circuit 502 or multiplier 508 and 512.Perhaps, can depending on circumstances adopt signal power or amplitude other weighted factor in addition.

The weighted factor that Fig. 7 demonstrates Fig. 5 is determined an embodiment of the part of circuit.To describe this circuit at input I1 ', Q1 ' below, same explanation and circuit can be applied to import I2 ', Q2 '.It is also noted that in optional embodiment, the circuit that is used to receive I1 ', Q1 ' can be shared for input I2 ', Q2 ' according to the time-division multiplex transmission manner, perhaps entire circuit (or its part) can be repetition, as shown in Figure 7.In the embodiment illustrated, weighted factor determines that circuit 502 works in an identical manner with the corresponding part of I1 ', Q1 ' with the corresponding part of I2 ', Q2 '.Usually, weighted factor determines that circuit 502 comprises that the characteristics of signals value determines that circuit and weights determine circuit.The former calculates signal characteristic self for example power of each signal or the numerical value of amplitude, and the latter uses the numerical value of this signal characteristic to calculate W1 and W2.

About input I1 ', Q1 ', weighted factor is determined that circuit 502 comprises being coupled to by lead 518 and is received I1 ' and receive the multiplier 700 of 1/N by lead 746.Multiplier 702 is coupled to by lead 520 and receives Q1 ' and receive 1/N by lead 746.Multiplier 700 is connected with adder 704, and this adder is connected with memory circuit 712 with delay cell 708.Multiplier 702 is connected with adder 706, and this adder is connected with memory circuit 718 with delay cell 714.Adder 720 is connected with memory circuit 712 and 718, inverse square root (inverse square root) unit 722 and multiplier 724.Therefore adder 720 provides the power p1 of I1 ', Q1 ' to inverse square root unit 722 and multiplier 724.Inverse square root unit 722 is connected with multiplier 724, and multiplier 724 provides output W1 by lead 526.For input I2 ', Q2 ', weighted factor determines that circuit 502 comprises the multiplier 750,752 and 770 that is connected in identical with 718 and inverse square root unit 722 with multiplier 700,702 and 720, adder 704,706 and 720, delay cell 708 and 714, memory circuit 712 respectively mode, adder 754,760 and 766, delay cell 756 and 762, memory circuit 758 and 764 and inverse square root unit 768.Therefore, as shown in Figure 7, the characteristics of signals value determines that circuit 780 comprises multiplier 700,702,750 and 752 and adder 720 and 766.Weights determine that circuit 782 comprises multiplier 724 and 770 and inverse square root unit 722 and 768.

During work, the output of multiplier 700 provides numerical value I1 ' to adder 704 ²/ N, wherein N represents the quantity of sampling or is used for gathering as time goes by the window size of the numerical value of input signal.Equally, the output of multiplier 702 provides numerical value Q1 ' to adder 706 ²/ N.Adder 704 and delay cell 708 is as accumulator, be used for along with the time with I1 ' ²The numerical value of/N adds up.Delay cell 708 receives reset signal 710, and this signal resets delay cell 708 according to the mark Fs/N of the sample frequency of I1 ', Q1 '.Make before delay cell 708 resets memory circuit 712 these numerical value that add up of storage and this numerical value offered adder 720.Equally, adder 706 and delay cell 714 is as accumulator, be used for along with the time with Q1 ' ²The numerical value of/N adds up.Delay cell 714 receives reset signal 716, and this signal resets delay cell 714 according to Fs/N.Make before delay cell 714 resets, memory circuit 718 these numerical value that add up of storage, and this numerical value offered adder 720.Therefore, reset signal 710 with 716 usually with the corresponding identical speed of Fs/N by " establishments ", same, with reset signal 710 and 716 corresponding identical speed to memory circuit 712 and 718 timing, so that along with the time is caught accumulating values.Therefore, can regulate N as one sees fit and be used for the window size (being the quantity of the sample adopted) of accumulating values so that change.

Adder 720 will be from the I1 ' of memory circuit 712 ²The accumulating values of/N and from the Q1 ' of memory circuit 718 ²The accumulating values of/N merges to obtain p1:

Equation 6: $\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="C028163590040H1.png,C028163590041H1.png"\; state="\{\{state\}\}">p</figure-callout>}1=\underset{k=j-N}{\overset{j}{\mathrm{\&Sigma;}}}(\frac{{{I1}_k}^{\&prime;2}}{N}+\frac{{{Q1}_k}^{\&prime;2}}{N})=\stackrel{\&OverBar;}{{I1}^{\&prime;2}}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="C028163590040H1.png,C028163590041H1.png"\; state="\{\{state\}\}">Q</figure-callout>}1}^{\&prime;2}}$

In the superincumbent equation 6, j is the discrete sample number relevant with Fs.Therefore, calculate the numerical value of p1 at each Fs/N place.With this as a result p1 offer multiplier 724 and inverse square root unit 722.Demonstrate the result of inverse square root unit 722 below in the equation 7.This inverse square root unit 722 can accomplished in various ways, the hardware circuit that for example calculates, is embedded in state machine (state machine) in the memory, software program etc.

Equation 7: $\frac{1}{\sqrt{\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="C028163590040H1.png,C028163590041H1.png"\; state="\{\{state\}\}">p</figure-callout>}1}}=\frac{1}{\sqrt{\stackrel{\&OverBar;}{{I1}^{\&prime;2}}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="C028163590040H1.png,C028163590041H1.png"\; state="\{\{state\}\}">Q</figure-callout>}1}^{\&prime;2}}}}$

This result is offered multiplier 724, and this multiplier multiply by the output (equation 6) of adder 720 output (equation 7) of inverse square root unit 722 with acquisition output W1, shown in following equation:

Equation 8: $\mathrm{<figure-callout\; id="1"\; label="W"\; filenames="C028163590040H1.png,C028163590041H1.png"\; state="\{\{state\}\}">W</figure-callout>}1=\sqrt{\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="C028163590040H1.png,C028163590041H1.png"\; state="\{\{state\}\}">p</figure-callout>}1}=\sqrt{\stackrel{\&OverBar;}{{I1}^{\&prime;2}}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="C028163590040H1.png,C028163590041H1.png"\; state="\{\{state\}\}">Q</figure-callout>}1}^{\&prime;2}}}$

Identical equation (equation 6-8) is applicable to I2 ', Q2 ', wherein with I2 ' replacement I1 ', uses Q2 ' replacement Q1 ', and replaces p1 with p2.Therefore, W2 can be expressed as follows:

Equation 9: $\mathrm{<figure-callout\; id="2"\; label="W"\; filenames="C028163590052H1.png"\; state="\{\{state\}\}">W</figure-callout>}2=\sqrt{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="C028163590052H1.png"\; state="\{\{state\}\}">p</figure-callout>}2}=\sqrt{\stackrel{\&OverBar;}{{I2}^{\&prime;2}}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="C028163590052H1.png"\; state="\{\{state\}\}">Q</figure-callout>}2}^{\&prime;2}}}$

Therefore, equation 6-9 has described an embodiment of the computing formula that is adopted when obtaining the power of input signal.Optional embodiment can be carried out different calculating or be adopted embodiment different circuit or the software shown in Figure 7 with reference.

Figure 17 demonstrates the employing amplitude and determines that the weighted factor of W1 and W2 determines the optional embodiment of circuit 502.Therefore, comply with the embodiment that is adopted and decide (for example be adopt power or amplitude is used as characteristics of signals), in weighted factor is determined circuit 502, can adopt Figure 17 to replace Fig. 7.Figure 17 comprises that the characteristics of signals value determines circuit 1716, and it comprises that amplitude determines that circuit 1700 and amplitude determine circuit 1702.Amplitude determines that circuit 1700 receives I1 ' and Q1 ' by lead 518 and 520 respectively, and amplitude determines that circuit 1702 receives I2 ' and Q2 ' by lead 522 and 524 respectively.Amplitude determines that circuit 1700 offers multiplication summation circuit 1708 with AMP1, and amplitude determines that circuit 1702 offers multiplication summation circuit 1708 with AMP2.Control circuit 1704 and phase- shift circuit 1710 and 1708 two-way connections of multiplication summation circuit.Multiplication summation circuit 1708 provides W1 by lead 1712, and provides W2 by lead 1714.Therefore weights determine that circuit 1718 comprises control circuit 1704, multiplication summation circuit 1708 and phase-shift circuit 1710.

During work, amplitude determines that circuit 1700 receives I1 ' and Q1 ', and exports the amplitude A MP1 of this signal.Adopt available standard method at present for example to adopt I1 ' ²And Q1 ' ²The square root of summation be similar to this amplitude that calculates.Equally, amplitude determines that circuit 1702 receives I2 ' and Q2 ', and the amplitude A MP2 of output signal.Can be according to calculating this amplitude with identical mode noted earlier.Multiplication summation circuit 1708 receives AMP1 and AMP2, and as will be below with reference to as described in Figure 18, producing weighted factor W1 and W2.Multiplication summation circuit 1708 also comprises the memory circuit of the temporary value that is used for storing any necessity.Control circuit 1704 and phase-shift circuit 1710 offer control signal multiplication summation circuit 1708 and therefrom receive control signal.Control circuit 1704, multiplication summation circuit 1708 and phase-shift circuit 1710 can constitute the part of state machine, so that carry out below with reference to the described calculating of Figure 18.

Figure 18 demonstrates an embodiment calculating W1 and W2 according to the amplitude of I1 ', Q1 ' and I2 ', Q2 ' in a flowchart.This flow process 1800 begins at square frame 1802 places, wherein receives I1 ', Q1 ' and I2 ', Q2 '.Flow process advances to judges diamond 1804, and whether the amplitude A MP1 that determines I1 ', Q1 ' there is greater than the amplitude A MP2 of I2 ', Q2 '.If then flow process advances to square frame 1813, can at random regulate AMP1 and AMP2 there.Flow process advances to square frame 1814 then, there W1 is set at predetermined value.This predetermined value is represented the default value of W1.Therefore, in one embodiment, this predetermined value is less than or equal to 0.5.Employing is less than or equal to 0.5 predetermined value and has guaranteed that the amplitude of the signal (for example I1 ', Q1 ' and I2 ', Q2 ' merging) of final merging can not surpass numerical value 1.Flow process advances to square frame 1816 then, determines the 1/AMP1 reciprocal of this amplitude there.This can adopt standard technique for example question blank carry out.In square frame 1818, W2 is calculated as half (referring to top equation 1) of AMP2/AMP1.Be noted that at 0.5 shown in this equation and be above-mentioned predetermined value; Therefore, if selected different numerical examples as 0.4, then will with 0.4 replace this 0.5.

If judging that diamond 1805 AMP1 of place are not more than AMP2, then flow process advances to square frame 1805, at random regulates AMP1 and AMP2 there.Flow process advances to square frame 1806, W2 is set at be less than or equal to 0.5 predetermined value for example 0.5 usually.This predetermined value is as above described the same about square frame 1814.Flow process advances to square frame 1808 then, determines the 1/AMP2 reciprocal of amplitude there.With top the same, can adopt standard technique for example question blank carry out this work.In square frame 1810, with W1 calculating half (referring to top equation 2) as the ratio of AMP1/AMP2.Be noted that once more on 0.5 shown in this equation is with reference to square frame 1806 described predetermined values; Therefore, if selected different numerical value, then can replace 0.5 with these different numerical value.Therefore, optional embodiment is calculating to determine that for example W1 and W2 (for example referring to choice box 1805 and 1813) can at first adopt scale factor to regulate these amplitudes (for example AMP1 and AMP2) to weighted factor before.But these scale factors are optionally, perhaps can be set at 1.Therefore, these weighted factors can be expressed as follows:

If AMP1＞AMP2:

Equation 10a:W1=0.5

Equation 11a: $\mathrm{<figure-callout\; id="2"\; label="W"\; filenames="C028163590052H1.png"\; state="\{\{state\}\}">W</figure-callout>}2=\mathrm{<figure-callout\; id="2"\; label="AMP"\; filenames="C028163590052H1.png"\; state="\{\{state\}\}">AMP</figure-callout>}2\&CenterDot;0.5\&CenterDot;\frac{1}{\mathrm{<figure-callout\; id="1"\; label="AMP"\; filenames="C028163590040H1.png,C028163590041H1.png"\; state="\{\{state\}\}">AMP</figure-callout>}1}$

If AMP1＜AMP2:

Equation 10b:W2=0.5 then

Equation 11b: $\mathrm{<figure-callout\; id="1"\; label="W"\; filenames="C028163590040H1.png,C028163590041H1.png"\; state="\{\{state\}\}">W</figure-callout>}1=\mathrm{<figure-callout\; id="1"\; label="AMP"\; filenames="C028163590040H1.png,C028163590041H1.png"\; state="\{\{state\}\}">AMP</figure-callout>}1\&CenterDot;0.5\&CenterDot;\frac{1}{\mathrm{<figure-callout\; id="2"\; label="AMP"\; filenames="C028163590052H1.png"\; state="\{\{state\}\}">AMP</figure-callout>}2}$

Be noted that for example W1 and W2 can be the function of a signal or be the function of the combination in any of signal weighted factor.Also have, can adopt the many different weighted factors different with the weighted factor here.For example, in present available system, only adopt signal to noise ratio (snr) as weighted factor.But adopting the scheme of SNR is expensive aspect circuit, has therefore increased the price of this system.In addition, are complicated numerals (that is, they depend on the phase place of signal) at those intrasystem weighted factors that adopted the SNR scheme.But embodiment of the present invention do not adopt SNR to determine weighted factor, and for example amplitude, power wait the solution that realizes saving more cost to adopt other characteristics of signals on the contrary.Also have, described here weighted factor (W1 and W2) is a scale factor.That is to say they and phase-independent.They can with phase-independent be because phase calculation or estimation be carry out separately and be used for these input signals are merged with the proportion weighted factor, as following more detailed description.As mentioned above, optional embodiment can comprise plural input signal, therefore can have the plural weighted factor that also depends on one or more characteristics of signals.In some embodiments, these weighted factors also are optional.For example, have only the some of them input signal can use weighted factor.

Fig. 8 demonstrates the part of multiplier 510 and the part of phase estimation circuit 506.Multiplier 510 comprises the multiplier 800 and 802 that is connected with adder 804, and this adder is connected with multiplier 812.Multiplier 510 also comprises multiplier 806 and the multiplier 808 that is connected with adder 810, and this adder is connected with multiplier 814.Multiplier 812 is connected with adder 816 with multiplier 814, and receives input 1/N and gain 801.Adder 816 is connected with memory circuit 824 with delay cell 820, and multiplier 814 is connected with adder 818, and this adder is connected with memory circuit 826 with delay cell 822.Memory circuit 824 is connected with multiplier 828, and memory circuit 826 is connected with multiplier 830. Multiplier 828 and 830 is set to the input of adder 832, and this adder is connected with inverse square root unit 834.Memory circuit 824 with 826 and inverse square root unit 834 be connected with 838 with multiplier 836.Multiplier 836 provides the output of representing cos (Δ θ) by lead 538, and multiplier 838 provides the output of expression sin (Δ θ) by lead 540.

During work, multiplier 800,802,806 and 808 and adder 804 and 810 carry out the corresponding calculating of complex conjugate of multiply by I2 ', Q2 ' with I1 ', Q1 '.(referring to equation 3) therefore, adder 804 is output as the real part IM of resulting result of calculation, and adder 810 is output as the imaginary part QM of resulting result of calculation.Phase estimation circuit 506 receives IM and QM, and calculates the corresponding phase place with IM+jQM, and this phase place can be expressed as e as the front with reference to as described in the equation 4 ^{J Δ θ}This phase place is represented with I1 ', Q1 ' as with reference to the phase difference of signal between I1 ', Q1 ' and I2 ' and Q2 '.

Multiplier receives IM, and this result be multiply by 1/N and gains 801 it is offered adder 816.In one embodiment, gain 801 be the inverse by a larger margin (if AMP2＞AMP1 for example then can 801 be set at 1/AMP2 with gaining) among AMP1 and the AMP2.Gain 801 helps signal I1 ', Q1 ' are remained big as far as possible, still guarantees that these result of calculations can not surpass the selected digital system that is adopted simultaneously in this design.(therefore, be noted that the QM and the IM that adopt with reference to Fig. 8 refer to the numerical value of being regulated by gain 801 through gain-adjusted now.It is also noted that gain 801 is optionally or can be set at 1.) adder 816, delay cell 820 and memory circuit 824 be used on time window, the adding up numerical value of IM.Also have as mentioned above, N represents the quantity of sample or is used to collect the window size of IM numerical value.Delay cell 820 and memory circuit 824 reset when arriving mark of sample frequency Fs/N, and wherein Fs is corresponding to the sample frequency of input signal (for example I1 ', Q1 ').That is to say, when the data of at every turn obtaining sufficient amount (this is determined by Fs and N), with this value storage in memory circuit 824.Therefore, multiplier 828 receptions are from the accumulating values of the IM/N of memory circuit 824.QM is carried out identical analysis.That is to say that multiplier 814 receives QM and it be multiply by 1/N and gain 801, and this output is offered adder 818.Adder 818, delay cell 822 and memory circuit 826 be as an accumulator, is used on a period of time the numerical value of QM/N is added up.The quantity of sample is determined by Fs and N.That is to say that every N sample (with respect to sample frequency Fs) offers multiplier 830 with the numerical value in the memory circuit 826.

Therefore, IM is represented in the output of multiplier 828 ², and QM is represented in the output of multiplier 830 ²(be noted that IM ²And QM ²Refer to IM ²And QM ²Mean value on the time period that limits by N.) these numerical value are offered adder 832, this adder is with IM as a result ²+ QM ²Offer inverse square root unit 834.Inverse square root unit 834 calculates the inverse square root unit shown in equation 12:

Equation 12: $\frac{1}{\sqrt{\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="IM"\; filenames="C028163590052H1.png"\; state="\{\{state\}\}">IM</figure-callout>}}^2}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="QM"\; filenames="C028163590052H1.png"\; state="\{\{state\}\}">QM</figure-callout>}}^2}}}$

This result is offered multiplier 836 and 838.Multiplier 836 also receives the IM from memory circuit 824, and multiplier 838 receptions are from the QM of memory circuit 826.Therefore, shown in following equation 13 and 14, multiplier 836 and 838 result represent with I1 ', Q1 ' as with reference to the phase difference of signal between I1 ', Q1 ' and I2 ', Q2 '.

Equation 13: $\frac{\stackrel{\&OverBar;}{\mathrm{IM}}}{\sqrt{\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="IM"\; filenames="C028163590052H1.png"\; state="\{\{state\}\}">IM</figure-callout>}}^2}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="QM"\; filenames="C028163590052H1.png"\; state="\{\{state\}\}">QM</figure-callout>}}^2}}}$

Equation 14: $\frac{\stackrel{\&OverBar;}{\mathrm{QM}}}{\sqrt{\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="IM"\; filenames="C028163590052H1.png"\; state="\{\{state\}\}">IM</figure-callout>}}^2}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="QM"\; filenames="C028163590052H1.png"\; state="\{\{state\}\}">QM</figure-callout>}}^2}}}$

In the superincumbent equation, equation 13 corresponding to output cos (Δ θ), and equation 14 corresponding to output sin (Δ θ), wherein cos (Δ θ)+jsin (Δ θ) represents phase difference.(referring to top equation 4)

Fig. 9 demonstrates multiplier 508,512 and 514 and the application of the adder 516 of Fig. 5.Fig. 9 comprises multiplier 922,902,904,912,914,908,918 and 924.Fig. 9 also comprises adder 906,910,916 and 920.Multiplier 922 receives I1 ' and W1 as input, and output is offered adder 910.Multiplier 902 receives I2 ' and phasing 1, and its output is offered adder 906.Multiplier 904 receives Q2 ' and phasing 2, and the negative value of its output is offered adder 906.The result of adder 906 is offered multiplier 908, and multiplier 908 also receives W2 as input.The result of multiplier 908 is offered adder 910, and adder 910 also receives the output of multiplier 922.According to this embodiment, provide as I by lead 318 or 422 outputs with adder 910.Equally, multiplier 924 receives Q1 ' and W1, and provides output to adder 920.Multiplier 912 receives I2 ' and phasing 2, and its output is offered adder 916.Multiplier 914 receives Q2 ' and phasing 1, and its output is offered adder 916.Adder 916 offers multiplier 918 with its output, and this multiplier receives W2 and offers adder 920 as input and with its output.Equally, adder 920 is fixed according to embodiment provides Q to export as it by lead 318 or 422.Therefore, the equation 7 above the circuit of Fig. 9 has been represented.

Figure 10 demonstrates the optional embodiment of diversity merge cells 304 and 404.That is to say that the circuit of Figure 10 can exchange with the circuit of Fig. 5.In the embodiment of Figure 10, diversity merge cells 304 and 404 comprises the demultiplexer (DEMUX) 1000 and 1002 that is connected with characteristics of signals value estimating circuit 1004, multiplexer 1006 and multiplier 1012.Characteristics of signals value estimating circuit 1004 is connected with MUX1006 by lead 1028.Multiplier 1012 connects with the lock detecting circuit 1008 that is connected with multiplier 1018 with phase-locked loop.DEMUX1002 also is connected with multiplier 1018, and multiplier 1018 is connected with adder 1014.Adder 1014 is connected with multiplexer 1010 with demultiplexer 1000.Phase-locked loop also is connected with multiplexer 1010 by lead 1046 with lock detecting circuit 1008.Multiplexer 1010 is respectively by providing output I, Q with Fig. 3 or 4 corresponding leads 318 or 422.Each all passes through DEMUX1000, DEMUX1002, signal power estimating circuit 1004, MUX1006 and phase-locked loop and lock detecting circuit 1008 lead 138 and receives control signals.Lead 1028 can or can directly be provided by characteristics of signals value estimating circuit 1004 for the subclass of lead 138.

During work, DEMUX1000 receives I1 ', Q1 ', and provides I1 ' by lead 1020, and provides Q1 ' by lead 1022.Equally, DEMUX1002 receives I2 ', Q2 ', and I2 ' is provided and provides Q2 ' by lead 1026 by lead 1024.(also have, be noted that I1 ', Q1 ' and I2 ', Q2 ' are subjected to gain-adjusted when adopting the embodiment of Fig. 3, if but adopt the embodiment of Fig. 4 then still be not subjected to gain-adjusted.) characteristics of signals value estimating circuit 1004 receives I1 ', Q1 ' and I2 ', Q2 ', and at the value of I1 ', Q1 ' and the two estimated signal characteristic of I2 ', Q2 ' so that determine stronger signal.For example, characteristics of signals value estimating circuit 1004 can estimate the power or the amplitude of each signal, and determines stronger signal according to power, amplitude or both.Be noted that in optional embodiment, can adopt other characteristics of signals or other method to determine which signal is stronger signal.Characteristics of signals value estimating circuit 1004 by lead 1028 to multiplexer 1006 output control signals so that select stronger signal in two signals to export to multiplexer 1010 by lead 1030 and 1032.Multiplier 1012 receives I1 ', Q1 ' and I2 ', Q2 ', and calculates phase information by the complex conjugate that I1 ', Q1 ' be multiply by I2 ', Q2 '.Resulting result of calculation is represented by IM+jQM, and is offered phase-locked loop and lock detecting circuit 1008 by lead 1034 and 1036.Phase-locked loop and lock detecting circuit 1008 are used for estimating the phase difference between I1 ', Q1 ' and I2 ', Q2 ', and this phase difference is exported to multiplier 1018 as phasing 1 and by lead 1040 as phasing 2 by lead 1038.If phase-locked loop is a lock-out state, then I2 ', Q2 ' be multiply by resulting phase difference in case by adder 1014 with it and I1 ', Q1 ' merging before correctly mobile I2 ', Q2 '.Therefore, signal I1 ', the Q1 ' of the output of adder 1014 representative merging and I2 ', the Q2 ' of phase change.Also have, if phase-locked loop at lock-out state, then provides control signal so that select the output of adder 1014 rather than the output of MUX1006 to export as I, Q to MUX1010, this expresses the stronger signal among I1 ', Q1 ' and I2 ', the Q2 ' simply.But,, then will provide as output I, Q by lead 318 or 422 by lead 1030 and 1032 signals that transmit with selection to MUX1010 output control signal by lead 1046 if phase-locked loop circuit 1008 can not lock.

Therefore, the phase place of attempting phase difference and changing I2 ', Q2 ' thus in the embodiment plan of the diversity merge cells shown in Figure 10.But if phase-locked loop can not be locked in the correct phase place, then signal power estimating circuit 1004 provides the stronger signal in these two signals as output I, Q.Therefore, Figure 10 can be called as a kind of mixing phase-locked loop (PLL) system.When merging these signals in adder 1014, optional embodiment can adopt the characteristics of signals (for example amplitude, power etc.) of each signal as weighted factor.For example, as the front with reference to Fig. 5 described, I1 ', Q1 ' can be by its related power weightings, and I2 ', Q2 ' can be by its related power weightings.Optional embodiment in addition can adopt with based on the different weighted factor of the weighted factor of characteristics of signals.Can understand the operation of Figure 10 better with reference to Figure 11.

Figure 11 demonstrates an embodiment of the diversity merge cells 304,404 of Figure 10 in a flowchart.In square frame 1012, receive I1 ', Q1 ' and I2 ', Q2 '.In square frame 1104, estimate the characteristics of signals value (for example power or amplitude) of (this can be undertaken by characteristics of signals value estimating circuit 1004) each signal, and select stronger signal.In square frame 1106, the complex conjugate that I1 ', Q1 ' be multiply by I2 ', Q2 ' is to obtain IM+jQM (referring to top equation 3).In square frame 1108, estimate the phase difference e between I1 ', Q1 ' and I2 ', the Q2 ' ^{J Δ θ}, wherein this phase difference can be expressed as cos (Δ θ)+jsin (Δ θ).This can be undertaken by phase-locked loop and lock detecting circuit 1008, and this circuit is proofreaied and correct 1 (representing cos (Δ θ)) and proofreaied and correct 2 (representing sin (Δ θ)) by lead 1040 output phases by lead 1038 output phases.In square frame 1110, if the phase-locked loop of phase-locked loop and lock detecting circuit 1008 is at lock-out state then " establishment " lock control signal.(following the operation of phase-locked loop and lock detecting circuit 1008 is further described with reference to Figure 12) is in square frame 1115, as as described in top weighted factor with reference to Fig. 5 is determined circuit 502, can determine the weights of I1 ', Q1 ' and I2 ', Q2 '.But square frame 1115 is optionally, and has here supposed not use any weighted factor in merging these signals with reference to Figure 10 and 11 described embodiments.In square frame 1116, if " establishment " lock control signal, then signal I2 ', Q2 ' be multiply by the phase difference that calculates in square frame 1108, as shown in the equation below (also referring to square frame 1112):

Equation 15:e ^{J Δ θ}(I2 '+jQ2 ')

In square frame 1114, if " establishment " lock control signal, then shown in equation below with the result of square frame 1112 and I1 ', Q1 ' merging to obtain I, Q:

Equation 16:I+jQ=e ^{J Δ θ}(I2 '+jQ2 ')+(I1 '+jQ1 ')

In square frame 1118, if there is not " establishment " lock control signal, thereby the not locking of expression phase-locked loop then provides the stronger signal among signal I1 ', Q1 ' and I2 ', the Q2 ' as I, Q.(be noted that equation 15 and 16 is similar to equation 5 and 7 respectively, except any weighted factor in equation 15 and 16, not occurring.But, similar as the same as described in reference Figure 10 and the top optional square frame 1115 with the square frame 610,612 and 614 of Fig. 6, can use weighted factor at combined signal I1 ', Q1 ' and I2 ', Q2 ' time.)

Figure 12 demonstrates the embodiment that the power that utilizes each signal is determined the characteristics of signals value estimating circuit 1004 of stronger signal.The characteristics of signals value estimating circuit 1004 of Figure 12 comprises multiplier 1200 that is connected with multiplier 1204 and the multiplier 1002 that is connected with multiplier 1206.Multiplier 1204 is connected with adder 1208 with 1206.Adder 1208 is connected with memory circuit 1212 with delay cell 1210.Memory circuit 1212 is connected with adder 1214, and this adder is connected with selector unit 1216.Multiplier 1228 is connected with multiplier 1224, and multiplier 1230 is connected with multiplier 1226.Multiplier 1224 is connected with adder 1222 with 1226.Adder 1222 is connected with memory circuit 1218 with delay cell 1220.Memory circuit 1218 is connected with adder 1214.Selector unit 1216 offers multiplier 1006 by lead 1028 with control signal.

During work, multiplier 1200 receives I1 ' and 1/N so that I1 '/N is offered multiplier 1204, this multiplier calculate square value (I1 '/N) ², and this result offered adder 1208.Equally, multiplier 1202 receives Q1 ' and 1/N so that Q1 '/N is offered multiplier 1206, the square value that this multiplier calculates this result with will (Q1 '/N) ²Offer adder 1208.Adder with the result (I1 '/N) ²+ (Q1 '/N) ²Offer memory circuit 1212 and delay cell 1210.Adder 1208, delay cell 1210 and memory circuit 1202 on a period of time will (I1 '/N) ²+ (Q1 '/N) ²Numerical value add up.Equally, this time period is determined by the sample frequency corresponding with input signal I1 ', Q1 '.N refers to the sample size of being adopted (that is window size) equally.In case adopted the sample of correct number, memory circuit 1212 is with I1 ' as a result ²+ Q1 ' ²Offer adder 1214, wherein I1 ' ²And Q1 ' ²Be respectively I1 ' ²And Q1 ' ²Mean value on this time period.Equally, carry out identical calculating for I2 ', Q2 '.Also have, can repeat this circuit to I2 ', Q2 ' as shown in figure 12, perhaps can be by two signal I1 ', Q1 ' and I2 ', Q2 ' are carried out the next shared and corresponding circuit of I1 ', Q1 ' of time division multiplexing (time multiplexing).Therefore, the operation of adder 1222, delay cell 1220 and memory circuit 1218de be used for adding up on the window at the fixed time (I2 '/N) ²+ (Q2 '/N) ²Numerical value, this time window is determined by the sample frequency of I2 ', Q2 ' and N.Therefore, the result who offers adder 1214 is I2 ' ²+ Q2 ' ², I2 ' wherein ²And Q2 ' ²Be I2 ' ²And Q2 ' ²Mean value on this scheduled time window.Be noted that numerical value I1 ' ²+ Q1 ' ²And I2 ' ²And Q2 ' ²In, each is all corresponding to the power of corresponding signal I1 ', Q1 ' and I2 ', Q2 '.

To offer adder 1214 from the result of memory circuit 1212 and 1218, this adder is with these two I1 ' as a result ²+ Q1 ' ²And I2 ' ²And Q2 ' ²Between difference offer selector unit 1216.It is stronger and thus by lead 1028 these control signals of output which selector unit 1216 determines among signal I1 ', Q1 ' or I2 ', the Q2 '.If I1 ', Q1 ' are stronger signal, then the control signal by lead 1028 outputs allows MUX1026 can select I1 ', Q1 ' to send MUX1010 to by lead 1030 and 1032.But if selector unit 1216 is selected I2 ', the stronger signal of Q2 ' conduct, then MUX1006 exports to MUX1010 by lead 1030 and 1032 with I2 ', Q2 '.Therefore, selector unit 1216 can determine that signal has bigger power.For example, if the numerical value that offers selector unit 1216 from adder 1214 greater than 0, then power of this expression I1 ', Q1 ' is greater than I2 ', Q2 '.But if this difference is less than 0 (being negative), then power of this expression I2 ', Q2 ' is greater than I1 ', Q1 ', and selector unit 1216 is exported control signal thus.

Figure 13 demonstrates the part of multiplier 1012 according to an embodiment of the invention and the part of phase-locked loop and lock detecting circuit 1008.Multiplier 1012 comprises multiplier 1300,1302,1306 and 1310 and adder 1304 and 1308.Multiplier 1300 receives I1 ' and I2 ', and multiplier 1302 receives Q1 ' and Q2 '.The result of multiplier 1300 and 1302 is offered adder 1304, and the output of this adder is provided for phase-locked loop and lock detecting circuit 1008 by lead 1034.Equally, multiplier 1306 receives input I2 ' and Q1 ', and multiplier 1310 receives input Q2 ' and I1 '.Multiplier 1306 and 1310 outputs with them offer adder 1308, and this adder calculates the difference between these two numerical value, and by lead 1306 result are offered phase-locked loop and lock detecting circuit 1008.Therefore, during work, multiplier 1012 output I1 ', Q1 ' multiply by the complex conjugate result of I2 ', the Q2 ' of IM+jQM form, and wherein IM represents the real part by lead 1034 conduction, and QM represents the imaginary part by lead 1036 conduction.(referring to top equation 3)

Phase-locked loop comprises multiplier 1314 that is connected with adder 1312 and the multiplier 1320 that is connected with adder 1322 with lock detecting circuit 1008.Adder 1312 also is connected with lock detector 1324 with multiplier 1316.Adder 1322 also is connected with multiplier 1328 with multiplier 1318.Fader 1326 is connected with the output of lock detector 1324, and provides input to multiplier 1328.Multiplier 1328 is connected with delay cell 1330, and this delay cell is connected with adder 1334.Adder 1334 is connected with delay cell 1332 with counting circuit 1336.Delay cell 1332 provides value of feedback to adder 1334.Counting circuit 1336 proofreaies and correct 2 by lead 1038 output phases correction 1 and by lead 1040 output phases.Counting circuit 1336 also connects into to multiplier 1320,1318,1316 and 1314 input is provided.

During work, phase-locked loop and lock detecting circuit 1008 comprise a phase-locked loop (PLL) part, are used for estimating the phase difference numerical value of input signal IM+jQM.This is by adopting the phase-locked loop of being realized by fader 1326, multiplier 1328, delay cell 1330, adder 1334, delay cell 1332 and counting circuit 1336 to carry out.Phase-locked loop begins with the initial value of the Δ θ ' that inputs to counting circuit 1336, and wherein Δ θ ' represents the phase number of PLL.For example, initial value can be 0.During the iteration of PLL, regulate Δ θ ' and be locked on the phase number up to PLL.PLL locking when Δ θ ' is substantially equal to the corresponding Δ θ of IM+jQM.The same as will be described further below, lock detector 1324 determines whether PLL locks.Counting circuit 1336 receives numerical value Δ θ ', and the result of cosine and sinusoidal calculations is offered multiplier 1320,1318,1316 and 1314.

Multiplier 1314,1316,1320,1318 and adder 1312 and 1322 calculate the complex conjugate result who input signal IM+jQM be multiply by the phase delta θ ' that obtains from PLL, and this can be expressed as e ^{-j Δ θ}', wherein:

Equation 17:e ^{-j Δ θ}'=cos (Δ θ ')-jsin (Δ θ ')

The same shown in reference equation 4, the phase place of IM+jQM can be expressed as e ^{J Δ θ}Therefore, this result calculated can be expressed as follows:

Equation 18:e ^{J Δ θ}E ^{-j Δ θ}'=e ^{J (Δ θ-Δ θ ')}=cos (Δ θ-Δ θ ')+jsin (Δ θ-Δ θ ')

At the lead 1340 of the output of adder 1312 the real part cos (Δ θ-Δ θ ') of final calculation result is offered lock detector 1324, and adder 1322 offers multiplier 1328 with the imaginary part sin (Δ θ-Δ θ ') of final calculation result.If lock detector 1324 is determined also not locking (that is, Δ θ ' is inadequately near Δ θ) of PLL, then fader 1326 is regulated gain from the imaginary part of 1322 signal by multiplier 1328, and calculates the Δ θ ' of renewal.The Δ θ ' of this renewal is offered counting circuit 1336, and this counting circuit provides the cosine of Δ θ ' and sinusoidal numerical value so that once more the complex conjugate of this Δ θ ' be multiply by input signal IM+jQM to multiplier 1314,1316,1318,1320.This iterative process continues until determines that the real part that is offered the final calculation result of lock detector 1324 by adder 1312 provides the Δ θ ' that is in preset range with the difference of Δ θ.Because the real part of final calculation result is by cos (Δ θ-Δ θ ') expression, along with Δ θ ' near Δ θ because cos (0) so=1 this cosine result calculated is near 1.If lock detector 1324 determines that input signal surpasses lock threshold 1338 (promptly, Δ θ ' is fully near Δ θ), then locking signal is offered MUX1010 so that the output that merges can be exported as I, Q by lead 1042 and 1044 by lead 1046.Also have, in case lock detector by lead 1046 " establishments " locking signal, then this locking signal also is provided for fader 1326 so that the littler yield value of selection, so that PLL has bigger stability.That is to say that in case the PLL locking, then littler gain provides more stable system.

Figure 14 demonstrates an embodiment of the lock detector 1324 of Figure 13.By lead 1340 top real part with reference to the described final calculation result of Figure 13 is offered lock detector 1324 as the input of giving low pass filter 1400.This low pass filter is removed the noise section in the HFS of input signal.The output of this low pass filter 1400 is offered adder 1402, and this adder also receives lock threshold 1338.Adder 1402 find out from filter 1400 through the input of filtering and the difference between the lock threshold 1338, and this result offered locking determine circuit 1404, this circuit will be exported locking signal by lead 1046 and offer MUX1010.Locking determine circuit 1404 determine difference at the output of adder 1402 be greater than 0 or less than 0 so as to determine input signal be greater than or less than lock threshold 1338.If determine just being input as of circuit for locking, then locking determines that circuit " establishment " is decided signal 1046 so that select lead 1042 and 1044, thereby at the output of MUX1010 combined signal is provided as I, Q.But, negative if locking determines that circuit 1404 determines that adders 1402 are output as, " establishments " locking signal 1046 then not, so the output of selecting MUX1006 is to provide this signal as I, Q at the output of MUX1010 by lead 1030 and 1032.

Figure 15 demonstrate Fig. 3 the time dummy cell 302 an embodiment.The time dummy cell 302 both input signal I1 ', Q1 ' and I2 ', Q2 ' were carried out diversity and merged, also eliminate for resulting signal provides echo.The time dummy cell 302 provide the space to merge for input signal and provide time-domain filtering for resulting signal.The time domain part also can be known as carries out the equalizer part that echo is eliminated.(this equalizer part also can be called as sef-adapting filter 1530, and it comprises performance measurement and error signal generator 1522, multiplier 1512,1514 and 1516, adder 1520, tap renovator (taps updater) 1518 and delayer 1506,1508 and 1510.) by multiplier 1500 and 1502 and adder 1504 with input signal I1 ', Q1 ' and I2 ', Q2 ' merging.Give I1 ', Q1 ' weighting with the weighted factor W1 that inputs to multiplier 1500 from weighting renovator 1524.Equally, give I2 ', Q2 ' weighting by multiplier 1502 usefulness weighted factor W2,1502 places also provide W2 by weighting renovator 1524 at multiplier.Therefore, the result of weighting is offered adder 1504 to produce the weighted signal of merging, this signal is provided for delay cell 1506 and multiplier 1512 then.W1 and W2 represent plural number.The output of adder 1504 is propagated by delay cell 1506,1508 and 1510.With the output of adder 1504 and each delay cell for example 1506,1508 and 1510 output offer corresponding multiplier 1512,1514 and 1516, there these results be multiply by corresponding tap for example A1, A2 and AL.Then these outputs of multiplier 1512,1514 and 1516 are offered adder 1520 producing the output of eliminating through echo of merging, this output is provided for performance measurement and error signal generator 1522 and is provided for MUX306 and multipath echo detector and signal quality monitor 300 by lead 312.Performance measurement and error signal generator 1522 offer weighting renovator 1524 and tap renovator 1518 thus the numerical value of these weighted sum taps is upgraded with information.Be noted that these taps (tap) (A1, A2 and AL) also are expressed as plural number.Delay cell for example 1506 and 1508 and multiplier 1512 and 1514 and tap for example the number of A1 and A2 depend on number of taps in this equalizer part.

So select the weight (for example W1 and W2) of space combiner and the tap of equalizer (for example A1, A2 ..., AL), thereby make changes in amplitude minimum at the resultant signal of output of adder 1520.Also the number of taps in equalizer part is chosen as: decide according to application, and the needs of more hardware or software are traded off, improve resulting signal quality.Performance measurement and error signal generator 1522 carry out improved constant modulus algorithm to upgrade these weights and tap so that reduce the changes in amplitude of output in resulting signal in adder 1520.(therefore, in one embodiment, adopt with upgrade time domain in the identical criterion of sef-adapting filter tap upgrade weight in the spatial domain, as the general below with reference to as described in the equation 19-26.) time dummy cell 302 therefore can use the constant modulus feature of input FM signal.That is to say that the FM signal should keep constant amplitude.But, because the introducing of multipath echo and noise, so the amplitude of input FM signal can not keep constant.Therefore, adopt these weights and tap to reduce the changes in amplitude that causes by the multipath echo.It is also noted that, be not only applicable to receive two aerial signals, and can expand to and to merge from the signal of any amount antenna and to carry out echo and eliminate in the application shown in Figure 15.In this embodiment, each input signal before offering adder 1504 by the corresponding weighting factor weighting.Equally, equalizer part (that is, sef-adapting filter 1530) can design the tap of any amount.

Performance measurement and error signal generator 1522 adopt improved constant modulus algorithm to provide appropriate information to weighting renovator 1524 and tap renovator 1518, and this will describe with reference to following equation below.In this algorithm, cost function limits as follows:

Equation 19: $J=\frac{1}{4}E{[{\left|X\left(k\right)\right|}^2-1]}^2$

In the superincumbent equation, X (k) is a resulting signal after the output of adder 1520 is handled through space-time, and k represents by t=kT _sThe sampling time that provides, wherein T _sBe the sampling period.Top equation is expressed as the desired value of random process, because the signal that is received (for example I1 ', Q1 ' and I2 ', Q2 ') is for statistical rather than deterministic.The time dummy cell 302 a purpose be to reduce cost function J, this realizes that by changing weight and tap this will be described further below.

Be noted that and see also on received signal I1 ', Q1 ' and I2 ', the Q2 ' dependency and can be expressed as r _m(k), m=1 wherein, 2 ... N, N is the antenna amount in receiver, and k is by t=kT _sThe sampling time that provides.It is also noted that weights W 1 and W2 can be expressed as W1=W1 respectively _R+ jW1 _IAnd W2=W2 _R+ jW2 _ISubscript R is used for representing this real, and subscript I is used for representing imaginary part.Also have, they can be expressed as W on attribute _m(k), m=1 wherein, 2 ... N, N is the antenna amount in receiver, and k is a sampling time interval.Equally, A1, A2 ... AL can be expressed as A1=A1 _R+ jA1 _IDeng, perhaps on attribute, be expressed as An (k), n=1 wherein, 2 ... L, L are the number of taps of equalizer, and k is the sampling time.For example, in the equation that provides, can adopt different expression here.

Following equation is represented the combination from all signals of different antennae.This signal Y (k) at the output of adder 1504 is expressed as shown in the face equation:

Equation 20: $Y\left(k\right)=\underset{m=1}{\overset{N}{\mathrm{\&Sigma;}}}{r}_m\left(k\right)\&times;W_m\left(k\right)$

Top equation is the general formula at the situation of the antenna that any amount is arranged in this system.In having the embodiment as shown in figure 15 of two antennas, the equation that is used for Y (k) can be expressed as follows:

Equation 21

Y(k)＝(I1′+Q1′)·(W1 _R+jW1 _I)+(I1′+jQ2′)·(W2 _R+jW2 _I)

Therefore, the equalizing signal that obtains at the output of adder 1520 can be expressed as follows:

Equation 22: $X\left(k\right)=\underset{n=1}{\overset{L}{\mathrm{\&Sigma;}}}Y(k-n)\&times;A_n\left(k\right)$

In the superincumbent equation, the number of taps when L is illustrated in the equalizer of dummy cell 302 part.Y (k-n) expression has been changed the weighting combined signal (also referring to top equation 20) at the output of adder 1504 of time by delay cell 1506,1508,1510 etc.

For the minimum value of hoping for success this function J, cost function is set at 0 with respect to the complex conjugate partial derivative of these weights, just as cost function with respect to the complex conjugate partial derivative of these taps.Therefore, these equatioies are following provides:

Equation 23: $\frac{\&PartialD;J}{{{\&PartialD;W}_m}^{*}}=0$ m＝1，2，...N

Equation 24: $\frac{\&PartialD;J}{{{\&PartialD;A}_n}^{*}}=0$ n＝1，2，...L

Can use statistical gradient to find out separating of top equation.Therefore, following the drawing of renewal equation that is used for these weights and tap:

Equation 25:W _m(k+1)=W _m(k)-μ * (| X (k) | ²-1) * X (k) * A ₁ ^*(k) * r _m ^*(k),

M=1 wherein, 2 ... N

Equation 26:A _n(k+1)=A _n(k)-μ * (| X (k) | ²-1) * X (k) * Y (k-n),

N=1 wherein, 2 ... L

Two equatioies are in equation 25 and 26 in the above, and μ is the constant of expression step-length, and k represents sampling instant t=kT _sTherefore, top equation is represented the time average of these weights and tap.

As described in reference Fig. 3, the output of adder 1520 is fed back to multipath echo detector and signal quality monitor 300, whether the echo of the signal that is calculated to determine has been reduced to the predetermined threshold that is lower than the permission echo.If then the control signal that transmits by lead 320 selects lead 312 to be provided for lead 208 as Icomb, Qcomb through MUX306.But if echo detector and signal quality monitor 300 determine that echo still is higher than predetermined threshold value, dummy cell 302 carries out another time iteration with the multipath echo in the further reduction signal in the time of then, thereby repeats this process.

Figure 16 demonstrates the multipath echo detector that is used in Fig. 3 and 4 and an embodiment of signal quality monitor 300,402.If adopt the embodiment of Fig. 3, then modulus circuit 1600 is respectively by lead 314 and 316 receiving inputted signal I1 ', Q1 ' and I2 ', Q2 '.In the embodiment of Fig. 4, multipath echo detector and signal quality monitor 402 receives the I1 ', the Q1 ' that merge and I2 ', Q2 ' signal by lead 416.Modulus circuit 1600 calculates the modulus of digital complex numbers baseband signal then.It is desirable to, these results should equal constant numerical value.But in time dependent mobile channel, the signal that is transmitted can be subjected to the influence of fading channel.Yet in the FM radio system, the variation of channel is compared usually slower with the bandwidth of broadband FM signal.Therefore, the modulus that can adopt band pass filter 1602 to deduct to be caused by the multipath echo changes and ignores the slow variation of channel.Calculate the average signal strength of the output of band pass filter 1602 then by average signal strength detector 1604.Comparison circuit 1606 compares average signal strength and the numerical example such as the threshold intensity 1608 that preset then.Decision making according to comparative result then.If average signal strength is greater than threshold intensity numerical value 1608, signal I1 ', the Q1 ' that is then received or I2 ', Q2 ' or their combination need be carried out echo and eliminate processing.That is to say, in the embodiment of Fig. 3, with I1 ', Q1 ' and I2 ', when Q2 ' sends to dummy cell 302 to tackle the frequency selective attenuation channel.In the embodiment of Fig. 4, multipath echo detection signal quality-monitoring device 402 makes echo eliminator 406 to carry out echo to the signal that receives from diversity merge cells 404 before as Icomb, Qcomb and eliminate these results being exported to lead 208.

Be noted that each hardware cell of in present specification, describing and circuit can be reused or by each function sharing.For example, can be used for realizing a kind of state machine, be used for controlling the execution of other function recited above, and be not limited to only calculate weighted factor W1 and W2 at the circuit shown in Figure 17 1718.Embodiment of the present invention can be implemented in hardware, software or the two combination.For example, some embodiments may be embodied as finite state machine, and it has the control circuit with the execution of microcode control state machine.Perhaps, can adopt software code to realize top function.

In the superincumbent specification, describe the present invention with reference to specific embodiments.But it will be appreciated by one skilled in the art that under the scope of the invention situation that does not break away from defined in the claim below and can make various changes and variation.Therefore, this specification and accompanying drawing should be considered to be exemplary and not restrictive, and all these changes are all planned within the scope of the present invention.

Describe above with reference to the solution of specific embodiments to beneficial effect, other advantage and problem.But the solution of these benefits, advantage, problem and may make any benefit, advantage or solution occurs or the tangible more any element that becomes can not be taken as the key of any or all claim, desired or necessary feature or element.Employed here term " comprises ", " comprising " or other similar expression waies mean non-exclusive comprising, the technology, method, article or the equipment that for example comprise series of elements have more than and comprise those elements, but can comprise other clearly do not list or this technology, method, article or equipment intrinsic other element.

Claims (2)

1. one kind is used for and will merges to produce the method for a combined signal from first signal of first sensor and secondary signal from second transducer, and this method comprises:

Determine the phase difference between described first signal and the described secondary signal, wherein, determine that the step of described phase difference comprises:

With the complex conjugate of described first signal times, to produce an intermediate object program with described secondary signal;

To described intermediate object program filtering, to produce intermediate object program once filtering;

Utilize described intermediate object program to obtain described phase difference through filtering;

Based on one of at least determining first weights in the power of described first signal and the amplitude, wherein these first weights and described phase difference have nothing to do;

Based on one of at least determining second weights in the power of described secondary signal and the amplitude, wherein these second weights and described phase difference have nothing to do;

With described first signal times with described first weights to produce first weighted signal;

Described secondary signal be multiply by described second weights to produce second weighted signal; And

When being merged, described first weighted signal and described second weighted signal adopt described phase difference to proofread and correct at least one phase place in described first and second signals.

2. one kind is used for and will merges to produce the method for a combined signal from first signal of first sensor and secondary signal from second transducer, and this method comprises:

Determine first characteristics of signals of described first signal, wherein said first characteristics of signals be in power and the amplitude one of at least;

Determine the phase difference between described first signal and the described secondary signal, wherein, this step of determining phase difference comprises:

With the complex conjugate of described first signal times, to produce an intermediate object program with described secondary signal;

To described intermediate object program filtering, to produce intermediate object program once filtering;

Isolate described phase difference from described intermediate object program through filtering;

When described first signal and described secondary signal being merged when producing described combined signal, adopt described first characteristics of signals to come, and utilize at least one the phase place in described first and second signals of described phase difference correction to described first signal weighting.

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