TW580759B - Method to manufacture the floating gate having improved coupling ratio and flash memory - Google Patents

Abstract

The present invention discloses a method to manufacture the floating gate having improved coupling ratio and flash memory, which comprises the steps of: forming a tunneling dielectric layer, a conductive layer and an insulative layer on a semiconductor substrate; defining and etching the tunneling dielectric layer, conductive layer and insulative layer on a semiconductor substrate, so as to form two trenches on the semiconductor substrate; filling an insulative material into the two trenches, so that the surface of the insulative material is lower than the surface of the conductive layer, so as to form the isolation structure of shallow trench isolation (STI); removing the insulative layer; forming the conductive spacer on both sidewalls of the conductive layer, wherein the top of the conductive spacer does not exceed the surface of the conductive layer, and the conductive spacer and the conductive layer form the floating gate; and, after forming the floating gate, sequentially forming a gate inter-layer dielectrics and a control gate on the isolation structure and the floating gate, so as to form a flash memory.

Description

580759 V. Description of the invention (1) The technical field to which the invention belongs: For example, 5 :: Ming is related to the manufacturing method of a non-volatile memory element, "" V 1 except programmable read-only memory (EPR0M), can be Elimination process ^ 111 EPR0M) '^ ^ #. # .J ^ Λ, Yi 1 Er Han's gate and flash memory manufacturing method. ^ The first technology: = non-volatile memory application fields are non-current to the attention of semiconductor products a, and one of them :: a: low cost and small size of a memory cell. ^ When using ^ as non-volatile memory, if the traditional regional oxidation method is used 疋 The isolation oxide formed by this method has a large scale factor which limits the reduction of memory cells. In order to achieve the purpose of reducing the size, another isolation technology has been applied to the non-volatile memory chip slot: ionization method to replace the traditional regional oxidation method. & The method utilizes shallow trenches to isolate the active area, thereby effectively improving the component accumulation. However, ‘the element size = keeps shrinking, and the surface area of the floating gate will also shrink. In this way, the effective terminal between the floating gate and the control gate will be reduced, which will lead to a decrease in the capacitive coupling rati0. Capacitor closing ratio is a parameter used to describe the voltage applied to the control gate to the floating closed pole. Capacitance-intensive memory

And poor access speed. The definition of A A valley valley ratio (Cp) is as follows:

580759 V. Description of the invention (2) 〇 As

Ccf + Cfs — where Ccf represents the capacitance between the control gate and the floating gate; Cf s represents the capacitance between the floating gate and the substrate. In order to increase the programming and access speed of non-volatile memory, many methods have been proposed to increase the lightening rate. It can be known from the above equation that when the capacitance Ccf between the control gate and the floating gate increases, the capacitance handle ratio Cp also increases. Therefore, by increasing the capacitance area between the control gate and the floating interrogator, the capacitance value of Cc f can be increased to achieve the purpose of increasing the coupling rate Cp. U.S. Patent Nos. 6,171,9 09 and 6,261,903 disclose methods for forming a stacked gate of a flash memory cell by increasing the coupling rate of the stacked gates by forming conductive spacers. This conductive spacer is part of the floating gate and can increase the capacitance area between the floating gate and the control gate. The floating gates formed by the above 6, 2 61, 90 3 patents are shown in Figures ιA and 1β. 10 is a semiconductor substrate, 12 is a tunneling dielectric layer, 14 is a conductive spacer, and 1 8 is an insulating layer. For example, si N, etc., and 16 is the conductive layer of the polycrystalline stone. In the above structure, the conductive spacer 14 is the polycrystalline silicon layer 16 and the spacer next to the insulating layer in FIG. 1A, and the insulating layer 1 is removed. After 8, a protruding structure shown in FIG. 1B is formed. Although the capacitance area between the floating gate and the control gate can be increased, the protruding structure is prone to tip discharge, and in subsequent processes, It is easy for the protruding structure to break and cause particles

580759

V. Description of the invention (3) (particle) is generated, so this method will have the potential problem of particle conductor device pollution in the subsequent process. In addition, U.S. Patent No. 6,331,46 No. 4 also proposes a flash memory process for improving the coupling ratio for the above-mentioned increase in the capacitive coupling area. The #method is smoothed after forming a conductive spacer with a protruding structure. The tip of the conductive part prevents the tip from discharging. However, the method disclosed in this patent highlights the problem of microstructure contamination of semiconductor devices caused by structural fracture. SUMMARY OF THE INVENTION In view of this, in the present invention, a floating gate structure for avoiding dogs and an improved manufacturing process for forming the floating gate to form a non-surge gate are included. The steps include: an electrical layer, a conductive layer, and an insulating layer. And the insulating layer and the substrate form two trenches; an isolation structure is formed to make the surface of the insulating material low-slot (STI); and the side walls on both sides of the insulating layer are formed with leading ends not exceeding the conductive layers to form a floating gate. The invention also provides a manufacturing method, the steps of which include: a dielectric layer, a conductive layer, and a method for providing a gate electrode with microstructures formed by the structure at the same time. Remove the insulating layer from the surface of the conductive layer in the two grooves of the semiconductor substrate; the electrical spacer, the surface of which is floating, and the conductivity has the advantages of improving the coupling rate and problems. The method mainly uses the spacer to do In order to partially float, a tunneling dielectric layer is sequentially formed, to fill the semiconductor with an insulating material, and to form a shallow isolation trench, and a top spacer portion of the conductive spacer portion of the conductive layer and the The conductive layer has a flash memory with an improved coupling rate. A tunnel insulating layer is sequentially formed on a semiconductor substrate;

0516-8446 ™ F (nl); 91009; phoebe.ptd Page 7 580759 V. Description of the invention (4) The layer, the conductive layer, the insulating layer and the above-mentioned semiconductor substrate, the conductor substrate forms two trenches; in the above two The trench is filled with material and the surface of the insulating material is lower than the conductive layer to protect the isolation structure of the isolation trench (sn); the insulating layer is removed to form a conductive layer on the sidewalls on both sides of the layer Spacers, where the 'on " conductive end does not exceed the opening of continued Rong Mo Lei + ^ Γθ1 gap f5: and the conductive spacers and the conductive layer / contaminated gate, and the isolation structures and The floating formation; = the electric and / or a control gate to form a fast flash II. According to the above method, the present invention provides a floating gate directly · a semiconductor substrate; a tunnel through the Bayi ^ 1 your teeth;丨 a military layer formed on the semiconductor substrate 5 conductive layer formed on the tunneling dielectric layer; and-a pair of conductive spaces ^ topped on the side walls on both sides of the conductive layer, where the pair of conductive spaces _ conductive The surface of the layer, and the conductive layer and the pair of guide rolls ^ M ^ constitute a dirty gate. The above floating gate also includes two adjacent M / 9 spacer structures, and the tunneling dielectric layer is located in the pair of shallow trench isolations. The second description of the dirty gate structure is shown in Figure 2E. A tunneling dielectric layer 120 and a conductive layer 160 are formed on the semiconductor substrate 100, and a pair of conductive spacers 140 are formed on the sidewalls of the conductive layer, wherein the tops of the pair of conductive two sections 140 do not exceed these. On the surface of the conductive layer 16, the pair is conductive:. And the conductive layer constitute a floating gate, and there are two shallow trench isolation structures 21 on both sides of the floating gate. The invention provides < In Wenliang's floating gate area, the i = method 'can effectively improve the capacitive contact of the floating gate and improve the coupling rate, and can also avoid the floating structure with a prominent structure.

580759 V. Description of the invention (5) Therefore, f will cause the problem of particle contamination in the subsequent process. 旎 Improve product yield and ensure the stability of component performance. In order to let the above-mentioned objects, features and advantages of the present invention be described in detail, the preferred embodiments are described in detail in conjunction with the accompanying drawings. Embodiments_person = I f Figures 2A ~ 2F illustrate the present invention in detail The process of making a gate with an improved turn-on rate. As shown in FIG. 2A, a tunneling dielectric layer 110, a conductive layer 160, and an insulating layer 180 are sequentially formed on a semiconductor substrate 100. The tunneling dielectric layer is an oxide layer or an oxynitride layer. For example, the tunneling dielectric layer may be formed by, for example, thermal oxidation at a temperature of 750 to 950 C or by a conventional atmospheric or low pressure chemical vapor deposition method. The preferred thickness is 60 to 12 angstroms; the conductive layer is doped polycrystalline silicon, doped amorphous silicon, undoped polycrystalline silicon, undoped amorphous silicon, or polycide metal. For example, WSi, etc .: It is preferably doped polycrystalline silicon, and its thickness is preferably in the range of 5,000 to 3,000 angstroms, and the insulating layer is preferably a dielectric material such as si N by a deposition method. The formed thickness is preferably 1 200 to 2 500 angstroms. Then, a photoresist mask (not shown) is used to cover the subsequent areas where active elements are to be formed, and the tunneling dielectric layer 丨 2 〇, conductive layer 丨 6 〇, and the insulating layer 180 are dried. And then continue to etch the substrate along a contour of the etching to a predetermined depth to form a plurality of shallow trenches 2000 as shown in FIG. 2. After finishing the etching, remove the photoresist pattern, and then deposit it with high-density plasma.

0516-8446TWF (nl). 91009; phoebe.ptd

580759 V. Description of the invention (6) High density plasma deposition (HDPCVD) or low pressure chemical vapor deposition (LPCVD) fills the trench 200 with an insulating material such as an oxide 'Wherein the above oxide is oxidized stone. The excess oxide in the trench can be removed by etch back or chemical mechanical polishing (CMP), so that the surface of the oxide is lower than the surface of the conductive layer, and the insulating layer is removed at the same time 丨8 〇. Thus, a recessed shallow trench isolation region 210 is formed to isolate the plurality of conductive layers 160, as shown in FIG. 2C. Please refer to FIG. 2D, and then perform the key steps of the present invention to comprehensively cover the conductive layer 160 and the shallow isolation trenches 2 10 with a conductive material 220. The conductive material is doped polycrystalline silicon, doped amorphous silicon, undoped polycrystalline silicon, undoped amorphous silicon, or polycide metal (polysilide), such as WSi. Crystal silicon. Next, anisotropic (an i st ro pic) etching is performed on the sidewalls on both sides of the conductive layers 160 to form two conductive spacers 14 as shown in FIG. 2E to expose the shallow isolation trench. Oxide of the trench 210. The conductive layer 160 and the conductive spacers 140 constitute a floating gate. Next, as shown in FIG. 2F, a gate-to-gate dielectric layer 23 can be sequentially formed on the floating gate (160 and 140) and the shallow isolation trench 21O oxide surface in accordance with a conventional method. And a second conductive layer 24o as a control gate. The material of the inter-gate dielectric layer 23 0 is usually formed of silicon oxide / silicon nitride / silicon oxide μ (NO), silicon nitride / silicon oxide (NO), or a barium strontium titanium oxide (μτ). MM 'Μ', Ti03, where μ includes at least Ba, Sr, pb, etc., but

580759 V. Description of the invention (7) For example, BaxSrvxTi03, BaTi03, SrTi03 #. The material of the second conductive layer 240 is doped polycrystalline silicon, doped amorphous silicon, undoped polycrystalline stone, undoped amorphous silicon, and polycide. For example, WSi or self-aligned polycrystalline silicon silicide (Sa 1icide). Finally, the second conductive layer is defined as a control gate by a mask and a rest process, and a non-volatile memory with a floating gate with improved light-on ratio is formed. As can be seen from FIG. 2F, the non-volatile memory of the present invention includes at least two isolation structures 210 whose surfaces are lower than 100 of the semiconductor substrate. Two conductive spacers 14 are provided on the two side walls of the two isolation structures 210, which form the floating gate electrode with the conductive layer 160 formed previously. Since the conductive spacers 140 and the conductive layer 160 form a smooth surface structure, the disadvantages of the protruding structure can be avoided. In summary, the present invention provides a floating gate with an improved coupling ratio: a clever method that can increase the capacitance area of the floating gate and the control gate to increase the capacitance coupling ratio, which can be avoided. The shortcomings of the guide == the disadvantages of contaminated wafers caused by particle breakage in the process. Ξ Although the present invention has been disclosed in the preferred embodiment as above, the bran limits the present invention. When some changes and retouching can be made, the spiritual scope of = shall be determined by the scope of the attached patent application. Yuezhibao 580759 Brief Description of Drawings Figures 1A and 1B are cross-sectional views of floating gates made by conventional techniques. Figures 2A to 2F are cross-sectional views of a manufacturing process of a method for manufacturing a floating gate with improved coupling ratio according to an embodiment of the present invention. [Symbol description] 10, 100 ~ substrate; 12, 120 ~ tunneling dielectric layer; 14, 140 ~ conductive spacer; 16, 160 ~ conductive layer; 1 8, 1 0 ~ insulating layer; 2 1 0 ~ shallow Trench isolation; 2 2 0 ~ conductive material; 2 0 0 ~ trench; 2 3 0 ~ gate dielectric layer; 2 4 0 ~ control gate.

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Claims (1)

580759 VI. Application Patent Scope 1 · A method for manufacturing a floating gate with improved coupling ratio, including the following steps: sequentially forming a tunneling dielectric layer, a conductive layer, and an insulating layer on a semiconductor substrate; definition Etching the tunneling dielectric layer, the conductive layer, the insulating layer, and the semiconductor substrate to form grooves in the semiconductor substrate; and filling the two grooves with an insulating material so that the surface of the insulating material is lower than the conductive layer Forming a shallow isolation trench (STI) isolation structure on the surface of the layer; removing the insulating layer; and forming a pair of conductive spacers on the side walls on both sides of the conductive layer, wherein the tops of the pair of conductive spacers do not exceed A surface of the conductive layer, and the pair of conductive spacers and the conductive layer form a floating gate. 2 · The method for manufacturing a floating gate with improved coupling ratio as described in item 1 of the scope of the patent application, wherein the conductive layer is doped polycrystalline silicon, doped amorphous stone, and undoped complex Spar, non-doped amorphous or polycide. 3. The method for manufacturing a floating gate with improved surface area ratio as described in item 1 of the scope of the patent application, wherein the pair of conductive spacers are doped polycrystalline silicon, doped amorphous silicon, and undoped Polycrystalline silicon, undoped amorphous silicon, or polycrystalline silicon (ρ ο 1 ycide). 4. The method of manufacturing a floating gate with improved coupling ratio as described in item 1 of the scope of the patent application, wherein the tunneling dielectric layer is an oxide layer or an oxynitride. 0516-8446TWF (nl); 91009; phoebe.ptd Page 13 τ 饷 Patent scope_ 5 · If you apply for a floating gate, go to ① The manufacturing described in item 1 has an improvement 6. The insulating layer is a nitride layer. A semiconductor substrate · Coupling rate floating gate, which includes: a through-dielectric layer, a conductive sound, formed on the semiconductor substrate, a pair of conductors on the through-dielectric layer, and a pair of Lightning guides M are formed on the sides of the conductive layer S τ electrical spacers > The right electrical layer and the top of the pair of lightning guides ^ do not exceed the surface of the conductive layer. Set the gate. Gate, which has an improved structure as described in item 6 of the Minghuan range, and the second * also includes two adjacent shallow trench isolations (ST1 〇 ^. The dielectric layer is located in the pair of shallow trenches Isolation. The gate electrode is described in item 6 of the patent scope with improved handle undoped. The conductive layer is doped polycrystalline silicon, doped #, polycrystalline silicon, undoped. Amorphous silicon or polycrystalline gold silicide jw has an improved coupling as described in item 6 of the patent claim: poles, where the pair of conductive spacers are doped polycrystalline silicon, and the name is: undoped polycrystalline silicon Silicon, undoped amorphous silicon or polycrystalline jm 〇ίο. &Quot; Please refer to the patent scope of item 6 with an improved coupling gate, where the tunneling dielectric layer is an oxide layer or an oxynitride The gate with an improved surface name as described in item 6 of the scope of the patent application, wherein the insulating layer is a nitride layer. 12. A flash memory having an improved coupling rate is manufactured at the coupling rate ^, and the (Guidance> Float of rate) Float of the junction rate, L crystal fragmentation, Float of 〇 rate: Miscellaneous non-M gold gold 'Float rate' float method, 0516-8446TWF (nl); 91009; phoebe.ptd page 14, the scope of patent application includes the following steps ... and-a tunnel dielectric layer is sequentially formed on the conductor substrate,-the conductive layer is semiconducting and the above-mentioned pass-through dielectric The electrical layer, the electrical layer and the insulating layer and the above-mentioned "on the ground" are used to form two trenches in the semiconductor substrate; on the surface, the two trenches are filled with an insulating material, and the isolation structure of the insulating material is electrically conductive. A layer of shallow isolation trench (STI) is formed on the surface of the layer to remove the insulating layer; a pair of conductive spacers are formed on the sidewalls on both sides of the conductive layer, and the conductive spacer and the conductive layer form a floating gate Electrodes; and electrical debris sequentially forming an inter-gate intermediary q and a control gate on the isolation structures and the floating gate to form a flash memory. 13. The method for manufacturing a flash memory with improved coupling as described in item 12 of the scope of the patent application, wherein the dielectric layer between the gates is oxidized fossil / oxide oxidized (_) or Ta205 . 1 4 · The method for manufacturing a digital flash memory with improved coupling as described in item 12 of the scope of patent application, wherein the inter-gate dielectric layer is high-dielectric ^ 1 5 · As described in the scope of patent application No. 14 The method for manufacturing flash memory with improved coupling is described, wherein the high dielectric constant material is titanic acid; lock (BaxSri-xTi〇3), BaTi〇3, SrTi〇3 into MM, M ,, Ti 〇3, which contains less Ba, Sr or Pb. 1 6 · Method for manufacturing flash memory with improved coupling as described in item 2 of the scope of patent application 0516-8446TWF (nl); 91009; phoebe.ptd page 15 580759 6. Method for applying flash memory with the scope of patent application, where The control gate is doped with polycrystalline silicon, doped amorphous silicon, undoped ytterbium silicon, or polyc ide. 17. The manufacturing process is improved as described in item 12 of the scope of patent application. A method of flash memory with a high area ratio, wherein the tunneling dielectric layer is an oxide layer or an oxynitride. ， 的 盘 造 has an improved vehicle 18. As in the application for the scope of the patent application No. 12 gasification layer. Rate flash memory method, in which the insulation said ",, 0516-8446TWF (nl); 91009; phoebe.ptd page 16