TW201639001A - Memory device and method of fabricating the same - Google Patents

Abstract

Provided is a memory device including a plurality of bit lines, a plurality of capacitors, a plurality of contact plugs, and a plurality of semiconductor layers. The bit lines are located on a substrate. The capacitors are located on the substrate between the bit lines. The contact plugs are located between the capacitors and the substrate. The semiconductor layers are located between the contact plugs and the substrate.

Description

Memory element and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a memory device and a method of fabricating the same.

In general, the memory element is often filled with a doped poly (Doped Poly) into a storage node contact (Storage Node Contact) to electrically connect a storage capacitor (Storage Capacitor) and an active area (AA). However, with the rapid development of technology, it has become a trend to increase the accumulation of memory components and reduce the critical size. Therefore, in the case where the degree of integration of the memory element is increased and the critical size is reduced, the size of the contact window in the memory element is also gradually reduced, which leads to an increase in contact resistance between the storage node contact window and the active area in the memory element, resulting in an increase in contact resistance. The slower resistance-capacitance delay (RC Delay), which in turn affects the operating speed of the memory element. Therefore, how to reduce the resistance value between the storage node contact window and the active area to improve the operating speed of the memory element will become a very important issue.

The invention provides a memory element and a manufacturing method thereof, which can reduce the resistance value between the contact window and the active area of the storage node to improve the operating speed of the memory element.

The present invention provides a memory device comprising: a plurality of bit lines, a plurality of capacitors, a plurality of contact plugs, and a plurality of semiconductor layers. The bit line is on the substrate. The capacitor is located on the substrate between the bit lines. The contact plug is located between the capacitor and the substrate. The semiconductor layer is between the contact plug and the substrate. The material of the semiconductor layer includes germanium (SiGe), tantalum carbide (SiC), or a combination thereof.

In an embodiment of the invention, the semiconductor layer has a thickness of 5 nm to 30 nm.

In an embodiment of the invention, the material of the contact plug comprises tungsten (W).

In an embodiment of the invention, a plurality of barrier layers are further disposed between the contact plug and the semiconductor layer. The material of the barrier layer includes titanium (Ti), titanium nitride (TiN), or a combination thereof.

In an embodiment of the invention, a plurality of isolation structures are further included in the substrate below the bit line.

The present invention provides a method of manufacturing a memory element, the steps of which are as follows. A plurality of bit lines are formed on the substrate. A selective epitaxial growth process is performed to form a plurality of semiconductor layers on the substrate between the bit lines, wherein the material of the semiconductor layer comprises tantalum, tantalum carbide or a combination thereof. The semiconductor between the bit lines A plurality of contact plugs are formed on the layer. A plurality of capacitors are formed on the contact plug.

The present invention provides a method of manufacturing another memory element, the steps of which are as follows. A plurality of bit lines are formed on the substrate. A semiconductor layer is conformally formed on the substrate. The semiconductor layer covers a surface of the bit line, wherein a material of the semiconductor layer includes germanium, tantalum carbide, or a combination thereof. An etch back process is performed to remove a portion of the semiconductor layer to expose a top surface of the bit line. A plurality of contact plugs are formed on the semiconductor layer between the bit lines. A plurality of capacitors are formed on the contact plug.

In an embodiment of the invention, the semiconductor layer has a thickness of 5 nm to 30 nm.

In an embodiment of the invention, the material of the contact plug comprises tungsten.

In an embodiment of the invention, before the forming the contact plug, forming a plurality of barrier layers on the semiconductor layer, wherein the material of the barrier layer comprises titanium, titanium nitride or a combination thereof .

Based on the above, the present invention utilizes a selective epitaxial growth process to form a plurality of semiconductor layers on a substrate between bit lines or conformal formation of a semiconductor layer on a substrate between bit lines. The material of the semiconductor layer may be, for example, a low resistance value of tantalum, tantalum carbide or a combination thereof. Compared to the prior art doped polysilicon, the semiconductor layer of the present invention can reduce the resistance between the storage node contact window and the active region, resulting in a faster resistance-capacitance delay, thereby increasing the operating speed of the memory device.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧ openings

100‧‧‧Base

101‧‧‧Isolation structure

102‧‧‧ bit line

104‧‧‧gate dielectric layer

106‧‧‧Conductor layer

108, 120‧‧‧ barrier layer

110‧‧‧ conductor layer

112‧‧‧Top cover

114, 128‧‧‧ dielectric layer

116‧‧‧ spacer

118‧‧‧Semiconductor layer

118a‧‧‧Semiconductor structure

122‧‧‧Contact plug

124‧‧‧ capacitor

124a‧‧‧ lower electrode

124b‧‧‧ dielectric layer

124c‧‧‧Upper electrode

126‧‧‧Protective layer

1A to 1F are schematic cross-sectional views showing a manufacturing process of a memory element according to a first embodiment of the present invention.

2A to 2G are schematic cross-sectional views showing a manufacturing process of a memory element according to a second embodiment of the present invention.

1A to 1F are schematic cross-sectional views showing a manufacturing process of a memory element according to a first embodiment of the present invention.

Referring to FIG. 1A, a first embodiment of the present invention provides a method of fabricating a memory device, the steps of which are as follows. First, a substrate 100 (which may be, for example, an active region) is provided. In the present embodiment, the substrate 100 may be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (SOI) on the insulating layer.

Next, a plurality of bit lines 102 are formed on the substrate 100, and openings 10 are formed between the adjacent bit lines 102. In detail, the bit line 102 is sequentially stacked by the gate dielectric layer 104, the conductor layer 106, the barrier layer 108, the conductor layer 110, the cap layer 112, and the dielectric layer 114. In the present embodiment, the material of the gate dielectric layer 104 may be, for example, hafnium oxide, and the formation method may be a chemical vapor deposition method, a thermal oxidation method, or the like. The material of the conductor layer 106 may be, for example, doped polysilicon, undoped polysilicon or a combination thereof, and the formation method may be a chemical vapor deposition method. The material of the barrier layer 108 may be, for example, titanium (Ti), titanium nitride (TiN), or a combination thereof, which may be formed by chemical vapor deposition. guide The material of the bulk layer 110 may be, for example, tungsten (W), which may be formed by physical vapor deposition. The material of the cap layer 112 may be, for example, tantalum nitride, which may be formed by chemical vapor deposition. The material of the dielectric layer 114 may be, for example, ruthenium oxide, and the formation method thereof may be a chemical vapor deposition method, a thermal oxidation method, or the like. The bit line 102 has spacers 116 on both sides. The material of the spacers 116 may be, for example, hafnium oxide, tantalum nitride or a combination thereof, which is well known to those of ordinary skill in the art and will not be described in detail herein.

In addition, the present embodiment further includes forming the isolation structure 101 in the substrate 100 below the bit line 102. The material of the isolation structure 101 can be, for example, doped or undoped cerium oxide, high density plasma oxide, cerium oxynitride, spin-on yttria, low dielectric constant dielectric material, or a combination thereof. The isolation structure 101 can be, for example, a shallow trench isolation structure.

Referring to FIG. 1B, a selective epitaxial growth (SEG) process is performed to form the semiconductor layer 118 in the opening 10. In detail, since the selective epitaxial growth process is performed only on the surface of the exposed substrate 100, the semiconductor layer 118 is only on the substrate 100 between the bit lines 102. In the present embodiment, the material of the semiconductor layer 118 may be, for example, germanium (SiGe), tantalum carbide (SiC), or a combination thereof. The thickness of the semiconductor layer 118 may be between 5 nm and 30 nm. Taking 矽锗 as an example, since the resistance value of ruthenium is smaller than the resistance value of the doped polysilicon, this embodiment fills the semiconductor layer 118 having germanium into the opening 10, which can reduce the subsequent contact plug 122 and the substrate 100. The resistance value between (for example, the active region) produces a faster resistance-capacitance delay, which in turn increases the operating speed of the memory element. In another embodiment, a doped polysilicon layer may also be formed on the substrate 100 before the semiconductor layer 118 is formed. (not shown) such that the doped polysilicon layer is between the substrate 100 and the subsequently formed semiconductor layer 118.

Referring to FIG. 1B and FIG. 1C , a barrier layer 120 is conformally formed in the opening 10 , and the barrier layer 120 covers the surface of the semiconductor layer 118 . In this embodiment, the material of the barrier layer 120 may be, for example, titanium (Ti), titanium nitride (TiN), or a combination thereof, and the thickness thereof may be between 5 nm and 30 nm, and the formation method may be physical vapor deposition. law.

Next, referring to FIG. 1C and FIG. 1D, a contact plug 122 is formed in the opening 10. In detail, a layer of a conductor material (not shown) is formed on the substrate 100, and a layer of the conductor material is filled in the opening 10. The material of the conductor material layer may include a metal, which may be, for example, tungsten, which may be formed by physical vapor deposition. Thereafter, a layer of conductive material on the surface of dielectric layer 114 is removed by chemical mechanical polishing (CMP) to form contact plugs 122 in opening 10. In this embodiment, the contact plug 122 and the barrier layer 120 in each opening 10 can be regarded as a storage node contact window, which can be used to electrically connect the substrate 100 (which can be, for example, an active region), the semiconductor layer 118, and subsequent formation. Capacitor 124 (shown in Figure 1F below).

Referring to FIG. 1E and FIG. 1F, a plurality of capacitors 124 are formed on the contact plugs 122. In detail, the protective layer 126 is formed on the bit line 102 and the contact plug 122. In the present embodiment, the material of the protective layer 126 may be, for example, hafnium oxide, tantalum nitride or a combination thereof. Thereafter, a dielectric layer 128 is formed over the protective layer 126. The dielectric layer 128 may be, for example, hafnium oxide, tantalum nitride, borophosphoquinone glass (BPSG), or the like, which may be formed by chemical vapor deposition (as shown in FIG. 1E). Next, a capacitor 124 is formed in the protective layer 126 and the dielectric layer 128 (as shown in FIG. 1F). Specifically, each The capacitor 124 includes a lower electrode 124a, an upper electrode 124c, and a dielectric layer 124b. Each dielectric layer 124b is located between the lower electrode 124a and the upper electrode 124c. Each of the lower electrodes 124a is electrically connected to the corresponding contact plug 122. In an embodiment, the dielectric layer 124b may comprise a high dielectric constant material layer, the material of which may be, for example, hafnium oxide (HfO), zirconium oxide (ZrO), aluminum oxide (AlO), aluminum nitride (AlN), oxidation. Titanium (TiO), lanthanum oxide (LaO), yttrium oxide (YO), yttrium oxide (GdO), yttrium oxide (TaO), or a combination thereof. The material of the lower electrode 124a and the upper electrode 124c may be, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium tungsten (TiW), aluminum (Al), copper (Cu) or metal telluride. . The method of forming the lower electrode 124a, the upper electrode 124c, and the dielectric layer 124b is well known to those of ordinary skill in the art and will not be described in detail herein.

Referring to FIG. 1F , the memory device includes a plurality of bit lines 102 , a plurality of contact plugs 122 , a plurality of capacitors 124 , and a plurality of semiconductor layers 118 . The bit line 102 is located on the substrate 100, and the bit line 102 is sequentially stacked by the gate dielectric layer 104, the conductor layer 106, the barrier layer 108, the conductor layer 110, the cap layer 112, and the dielectric layer 114. Contact plugs 122 are located on substrate 100 between adjacent bit lines 102. The semiconductor layer 118 is located between the contact plug 122 and the substrate 100. The material of the semiconductor layer 118 may be, for example, tantalum, tantalum carbide or a combination thereof. Capacitor 124 is located on substrate 100 between bit lines 102 and contact plug 122 is located between capacitor 124 and substrate 100. In the present embodiment, a plurality of barrier layers 120 are further disposed between the contact plugs 122 and the semiconductor layer 118.

Since the semiconductor layer 118 having a low resistance value of the present embodiment is located between the contact plug 122 and the substrate 100, it can reduce the contact plug 122 and the substrate. A resistance value between 100 (which may be, for example, the active region) produces a faster resistance-capacitance delay, which in turn increases the operating speed of the memory element. In addition, the material of the semiconductor layer 118 in this embodiment may be, for example, tantalum, tantalum carbide or a combination thereof. Tantalum or tantalum carbide not only has a lower resistance value, it is close to the properties of the material of the substrate 100 (which may be, for example, the active region). Therefore, the semiconductor layer 118 having germanium or tantalum carbide can also reduce leakage current between the contact plug 122 and the substrate 100 compared to other metal materials.

2A to 2G are schematic cross-sectional views showing a manufacturing process of a memory element according to a second embodiment of the present invention.

In the following embodiments, the same or similar elements, members, and layers are denoted by like reference numerals. For example, bit line 102 of FIG. 1A is the same or similar component as bit line 102 of FIG. 2A. After that, they will not be repeated one by one.

Referring to FIG. 2A, a second embodiment of the present invention provides another method of fabricating a memory device, the steps of which are as follows. Because of the substrate 100, the isolation structure 101, the bit line 102, the gate dielectric layer 104, the conductor layer 106, the barrier layer 108, the conductor layer 110, the cap layer 112, the dielectric layer 114, and the spacers of FIGS. 1A and 2A The configuration, materials, and formation methods of 116 are similar, and will not be described herein.

Referring to FIG. 2B, a semiconductor layer 118 is conformally formed on the substrate 100. The semiconductor layer 118 covers the surface of the bit line 102. In detail, the semiconductor layer 118 covers the surfaces of the substrate 100, the spacers 116, and the dielectric layer 114. The material of the semiconductor layer 118 may be, for example, tantalum, tantalum carbide or a combination thereof, and may have a thickness of between 5 nm and 30 nm. In the present embodiment, the method of forming the semiconductor layer 118 can be, for example, The reaction gas is introduced into the Furnace at a reaction temperature of between 400 ° C and 550 ° C and is continued for 60 minutes to 600 minutes. Taking hydrazine as an example, the reaction gas includes at least a ruthenium-containing gas, a ruthenium-containing gas, or a combination thereof. The helium-containing gas may, for example, be methane, hydrazine or dichloromethane; the helium-containing gas may, for example, be decane.

Referring to FIG. 2B and FIG. 2C, an etch back process is performed to remove a portion of the semiconductor layer 118 to expose the top surface of the bit line 102. In detail, the etch back process exposes the surface of the dielectric layer 114 and the surface of a portion of the spacers 116 that cause the continuous semiconductor layer 118 to become a plurality of discrete semiconductor structures 118a. The semiconductor structure 118a is located on the substrate 100 between the bit lines 102 (i.e., in the opening 10). In this embodiment, the etch back process can be, for example, a dry etch process.

Referring to FIG. 2C and FIG. 2D, the barrier layer 120 is conformally formed on the substrate 100. The barrier layer 120 covers the dielectric layer 114, a portion of the spacers 116, and a surface of the semiconductor layer 118. In this embodiment, the material of the barrier layer 120 may be, for example, titanium, titanium nitride or a combination thereof, and the thickness thereof may be between 5 nm and 30 nm, and the formation method may be physical vapor deposition.

Next, referring to FIG. 2D and FIG. 2E, a contact plug 122 is formed in the opening 10. In detail, a layer of a conductor material (not shown) is formed on the substrate 100, and a layer of the conductor material is filled in the opening 10. The material of the conductor material layer may include a metal, which may be, for example, tungsten, which may be formed by physical vapor deposition. Thereafter, the conductive material layer on the surface of the dielectric layer 114 and the partial barrier layer 120 are removed by chemical mechanical polishing (CMP) to form the contact plugs 122 in the openings 10. In this embodiment, the contact plug 122 and the barrier layer 120 in each opening 10 can be regarded as a storage section. A point contact window can be used to electrically connect the substrate 100 (which can be, for example, an active region), the semiconductor layer 118, and a subsequently formed capacitor 124 (as shown in Figure 2G below).

Referring to FIG. 2F and FIG. 2G, a plurality of capacitors 124 are formed on the contact plugs 122. Specifically, a protective layer 126 and a dielectric layer 128 (shown in FIG. 2F) are sequentially formed on the bit line 102 and the contact plug 122. Next, a capacitor 124 is formed in the protective layer 126 and the dielectric layer 128 (as shown in FIG. 2G). Each capacitor 124 is electrically connected to a corresponding contact plug 122. The structure, material, and formation method of the protective layer 126, the dielectric layer 128, and the capacitor 124 of FIG. 2G are the same as those of the protective layer 126, the dielectric layer 128, and the capacitor 124 of FIG. 1F. I won't go into details.

In summary, the present invention utilizes a selective epitaxial growth process to form a plurality of semiconductor layers on a substrate between bit lines or conformal formation of a semiconductor layer on a substrate between bit lines. The material of the semiconductor layer may be, for example, a low resistance value of tantalum, tantalum carbide or a combination thereof. Compared to the prior art doped polysilicon, the semiconductor layer of the present invention can reduce the resistance between the storage node contact window and the active region, resulting in a faster resistance-capacitance delay, thereby increasing the operating speed of the memory device.

Further, since the semiconductor layer having germanium or tantalum carbide is close to the properties of the material of the substrate (which may be, for example, an active region). Therefore, the semiconductor layer of the present invention can also reduce the leakage current between the contact plug and the substrate compared to other metal materials.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of protection of the present invention It is subject to the definition of the scope of the patent application attached.

100‧‧‧Base

101‧‧‧Isolation structure

102‧‧‧ bit line

104‧‧‧gate dielectric layer

106‧‧‧Conductor layer

108, 120‧‧‧ barrier layer

110‧‧‧ conductor layer

112‧‧‧Top cover

114, 128‧‧‧ dielectric layer

116‧‧‧ spacer

118‧‧‧Semiconductor layer

122‧‧‧Contact plug

124‧‧‧ capacitor

124a‧‧‧ lower electrode

124b‧‧‧ dielectric layer

124c‧‧‧Upper electrode

126‧‧‧Protective layer

Claims (10)

A memory element comprising: a plurality of bit lines on a substrate; a plurality of capacitors on the substrate between the bit lines; a plurality of contact plugs between the capacitor and the substrate And a plurality of semiconductor layers between the contact plug and the substrate, wherein the material of the semiconductor layer comprises tantalum, tantalum carbide or a combination thereof. The memory element according to claim 1, wherein the semiconductor layer has a thickness of 5 nm to 30 nm. The memory element of claim 1, wherein the material of the contact plug comprises tungsten. The memory device of claim 1, further comprising a plurality of barrier layers between the contact plug and the semiconductor layer, wherein the material of the barrier layer comprises titanium, titanium nitride or combination. The memory element of claim 1, further comprising a plurality of isolation structures located in the substrate below the bit line. A method of fabricating a memory device, comprising: forming a plurality of bit lines on a substrate; performing a selective epitaxial growth process to form a plurality of semiconductor layers on the substrate between the bit lines, wherein a material of the semiconductor layer comprising germanium, tantalum carbide or a combination thereof; a plurality of contact plugs are formed on the semiconductor layer between the bit lines; A plurality of capacitors are formed on the contact plug. A method of fabricating a memory device, comprising: forming a plurality of bit lines on a substrate; conformally forming a semiconductor layer on the substrate, the semiconductor layer covering a surface of the bit line, wherein a material of the semiconductor layer Including ruthenium, tantalum carbide or a combination thereof; performing an etch back process, removing a portion of the semiconductor layer to expose a top surface of the bit line; forming a plurality of layers on the semiconductor layer between the bit lines Contact plugs; and forming a plurality of capacitors on the contact plugs. The method of manufacturing a memory device according to claim 6 or 7, wherein the semiconductor layer has a thickness of 5 nm to 30 nm. The method of manufacturing a memory device according to claim 6 or 7, wherein the material of the contact plug comprises tungsten. The method of manufacturing a memory device according to claim 6 or 7, further comprising forming a plurality of barrier layers on the semiconductor layer before forming the contact plug, wherein the barrier layer Materials include titanium, titanium nitride, or combinations thereof.