TW578177B - Trench capacitor and method for manufacturing thereof - Google Patents
Trench capacitor and method for manufacturing thereof Download PDFInfo
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- TW578177B TW578177B TW91134717A TW91134717A TW578177B TW 578177 B TW578177 B TW 578177B TW 91134717 A TW91134717 A TW 91134717A TW 91134717 A TW91134717 A TW 91134717A TW 578177 B TW578177 B TW 578177B
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578177 五、發明說明(l) —- [發明所屬之技術領域] 本發明是有關於一種半導體元件的製造方法,且特別 是有關於一種溝渠式電容器(Deep trench Capacit〇r)的 結構及其製造方法。 [先前技術] 在動態隨機存取記憶體(DRAM)中,電容器是其藉以儲 存訊號的心臟,如果電容器所儲存的電荷越多,在讀取資 料時越不易受雜訊影響(如幘所產生的軟錯K(s〇ft 、 Errors)),更可能會減低動態隨機存取記憶體之再生 (Refresh)頻率。 但是’當半導體製程進入深次微米(j)eep Sub-Micron)製程時,元件尺寸跟著逐漸縮小,對以往 動恶卩通機存取§己憶體結構而言,也代表著可做為電容号、 空間愈來愈小。所以如何保持電容器具有足夠的電容:,、 、憂成在0·25微米以下半導體製程之重要課題。 動態隨機存取記憶體(DRAM)電容器的結構主要八 種’其一為堆疊式電容器(Stack Capacitor),另一刀或兩 深溝渠式電容器(Deep Trench Capacitor),而不执B為 疊式電容器或是深溝渠式電容器,在半導體元件尺 的要求下,其製造的技術上均遭遇到越來越多的困難縮減 其中,堆疊式電容器技術是傳統半導體電容器製二 主要方法’目前普遍用於增加堆疊式電容器表面積的^的 有半球晶粒(Hemi-Spherical Grain,HSG)製程,以及去 變電容器結構,如冠狀(Crown)、鰭狀(Fin)、挺狀 改578177 V. Description of the invention (l) — [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a semiconductor element, and more particularly, to a structure and manufacturing method of a deep trench capacitor method. [Prior technology] In dynamic random access memory (DRAM), the capacitor is the heart of the signal. If the capacitor stores more charge, it is less susceptible to noise when reading data (such as generated by 帻). The soft errors K (sft, Errors)) are more likely to reduce the refresh frequency of the dynamic random access memory. However, when the semiconductor process enters the deep sub-micron (j) eep sub-micron process, the component size gradually decreases, which means that it can be used as a capacitor for the conventional memory access structure. No., space is getting smaller. So how to keep capacitors with sufficient capacitance: an important issue in semiconductor processes below 0,25 microns. There are mainly eight types of structures of dynamic random access memory (DRAM) capacitors. One is a stack capacitor, and the other is a deep-trench capacitor. The other is not a stack capacitor or a deep-trench capacitor. It is a deep trench capacitor. Under the requirements of the semiconductor element rule, its manufacturing technology has encountered more and more difficulties. Among them, stacked capacitor technology is the main method of traditional semiconductor capacitor manufacturing. The surface area of the capacitors includes the Hemi-Spherical Grain (HSG) process, as well as the capacitor structure, such as Crown, Fin, and stiff modification.
578177 五、發明說明(2) (Cyll=der)、或是延伸狀(Spread)等結構。 /然而’儘管堆疊式電容器的技術較為普遍,但對記憶 體兀件尺寸縮小的趨勢而言,其平坦化(Planarization) 的問題是必須要克服的。 另一方面’由於深溝渠式電容器是製造於基底之中, 因此不易產生平坦化的問題,而較有利於記憶體元件尺寸 縮小時的製作。 请參照第1圖,習知之溝渠式電容器1〇8係由位於基底 100中之下電極i 〇2、位於下電極1〇2之上的上電極丨〇6、以 及位於上電極106與下電極102之間的介電層104所構成。 。對於上述屢朱式電容器108而言,由於電容器log僅有 單一接面的介電層104作為電容之儲存使用,因此,電容 器1 08之電容儲存量仍然無法獲得大幅提昇。故在元件尺 寸設計的限制下,欲使用上述電容器來製造電容量為託6 百萬位元或甚至十億位元以上之電容器,仍然是一件相當 困難的事。 胃 [發明内容] 有鑑於此,本發明之一目的係提供一種溝渠式電容器 的結構及其製造方法,可以大幅增加電容器的表面積,^ 能夠得到電容量為256百萬位元或甚至十億位元以上之電 容器。 本發明之另一目的係提供一種溝渠式電容器的結構及 其製造方法,町以在元件尺寸縮小之際,仍可得到大 量的電容器。578177 V. Description of the invention (2) (Cyll = der), or extended (Spread) and other structures. / However, although the technology of stacked capacitors is more common, the problem of planarization of the memory elements must be overcome. On the other hand, since the deep trench capacitor is manufactured in the substrate, it is not easy to cause the problem of planarization, and it is more favorable for manufacturing when the size of the memory element is reduced. Please refer to FIG. 1. The conventional trench capacitor 108 is composed of a lower electrode i 02 located on the substrate 100, an upper electrode located above the lower electrode 102, and an upper electrode 106 and a lower electrode. It is composed of a dielectric layer 104 between 102. . For the above-mentioned repeated capacitor 108, since the capacitor log has only a single-layered dielectric layer 104 for storage of the capacitor, the storage capacity of the capacitor 108 cannot be greatly improved. Therefore, it is still very difficult to use the above capacitors to manufacture capacitors with a capacitance of 6 million bits or even more than one billion bits under the limitation of component size design. [Summary of the Invention] In view of this, one object of the present invention is to provide a trench capacitor structure and a manufacturing method thereof, which can greatly increase the surface area of the capacitor, and can obtain a capacitance of 256 million bits or even a billion bits. Capacitors above the yuan. Another object of the present invention is to provide a structure of a trench capacitor and a manufacturing method thereof, so that a large number of capacitors can be obtained even when the size of a component is reduced.
立、發明說明(3) 本發明提出一種溝渠时 於基底中形成一溝渠後,飞電=裔之製造方法,此方法係 區,且部分摻雜區;j系柚於溝渠底部之基底中形成一摻雜 形成第一介電層、第一、曾至溝渠側壁。接著於溝渠内依序 電層、第一導電層及層及第二介電層,其中第一介 除部分第二介電層、j $電層均未填滿溝渠。接著,移 於溝渠側壁上之筮-人一導電層及第一介電層,只留下位 之後,於溝渠側壁I二,=二第一導電層及第一介電層。 成第二導電層及第四介;f三介電層,並於溝渠内依序形 層均未填滿溝渠。接著,' :其中第二導電層及第四介電 層之頂面低於溝渠之頂面於溝渠内填入材料層,其中材料 介電層、第一導電層、後,移除咼於材料層的第一 電層及第四介電層。——;丨電層、第三介電層、第二導 壁及暴露之第二導電声i π f =材料層,再分別於溝渠側 之後,於溝渠内填入^一第五介電層及第六介電層。 導電層電性接简。、乐二v電層,其中第三導電層與第一 上述第一導電層、 式電容器之上電極:且、第四導電層構成溝渠 容器之下電極。@ ^ /一導電層及摻雜區構成溝渠式雷 電層)與多”出部第上分為上電極本體(第四導 且下電極可分為導電層、第三導電層)兩部分· 區、第二導極本體(溝渠底部之基底中的“, &、苐二導電層)兩部分。 伸至心側壁之換雜 極之突出部係交 八中上電極之突出部與下 互排列,而介電層(第-介電層、第:: 578177 五、發明說明(4)(3) The present invention proposes a method for manufacturing fly-by electricity after a trench is formed in a substrate. The method is a region and a partially doped region; j is formed in a substrate at the bottom of the trench. The first dielectric layer is doped to form a first dielectric layer. Then, an electrical layer, a first conductive layer and a layer, and a second dielectric layer are sequentially arranged in the trench, wherein the first dielectric part and the second dielectric layer and the j $ electric layer are not filled in the trench. Then, move the conductive layer and the first dielectric layer on the sidewall of the trench, leaving only a bit, and then on the sidewall of the trench I = 2, the first conductive layer and the first dielectric layer. To form a second conductive layer and a fourth dielectric layer; f three dielectric layers, and the layers are not filled in the trenches in sequence. Then, ': wherein the top surfaces of the second conductive layer and the fourth dielectric layer are lower than the top surface of the trench, and a material layer is filled in the trench, wherein the material dielectric layer, the first conductive layer, and the material are removed. A first electrical layer and a fourth dielectric layer. ——; 丨 the electrical layer, the third dielectric layer, the second conductive wall, and the exposed second conductive sound i π f = the material layer, and then after the trench side, fill in a fifth dielectric layer in the trench. And a sixth dielectric layer. The conductive layer is electrically connected. And Le Er v electric layer, wherein the third conductive layer and the first above-mentioned first conductive layer and the capacitor upper electrode: and the fourth conductive layer constitutes the electrode below the trench container. @ ^ / A conductive layer and a doped region constitute a trench-type lightning layer) and the upper part of the upper part is divided into an upper electrode body (the fourth and lower electrodes can be divided into a conductive layer and a third conductive layer). The second conductive body (", &, the second conductive layer in the substrate at the bottom of the trench). The protrusions of the replacement electrodes extending to the side wall of the heart are intersected, and the protrusions of the upper electrode of the middle are arranged next to each other, and the dielectric layer (the first dielectric layer, the first: 578177: V. Description of the invention (4)
電層、第三介電層、第四介電層、第五介電層、第六介 層)則形成於於上電極與下電極之間。由於,上電極之~突“ 出部與下電極之突出部彼此交叉排列,因此上電極與下&電 ,之間的面積增大了,而可以增加溝渠電容器的電荷儲量。 ,丁 而 於溝渠 於溝渠 第二導 層及第 介電層 形成第 第二導 介電層 形成第 驟,而 出部之 由 子層化 層之厚 具有多 之電容 且,在上 内依序形 内填入材 電層及第 四介電層 、第一導 二導電層 電層及第 、第一導 二導電層 可以形成 上電極所 於本發明 學氣相沈 度报薄, 個導電層 量。 述溝渠式電 成第二導電 料層之步驟 四介電層, 。然後,依 電層及第二 及第四介電 四介電層之 電層及第二 及第四介電 由具有多個 構成的溝渠 之溝渠式電 胃法所沈積 如此即可於 &介電層的 層及第四介電層之步 之前’進行蝕刻步驟 而只留下溝渠側壁之 序進行於溝渠内依序 介電層之步驟至於溝 層之步驟。接著重複 步驟、於溝渠内依序 介電層之步驟至於溝 層之步驟,再進行後 突出部之下電極與具 式電容器。 谷器的導電層及介電 而成,因此,各導電 元件尺寸設計之限制 電谷器,進而可以增 驟之後與 移除部分 第二導電 形成第一 渠内依序 移除部分 形成第一 渠内依序 續之步 有多個突 層係以原 層及介電 下,獲得 加電容器 由 本發明 下電極、 另提出一種溝渠式電容器 上電極與介電層所構成。The electrical layer, the third dielectric layer, the fourth dielectric layer, the fifth dielectric layer, and the sixth dielectric layer are formed between the upper electrode and the lower electrode. Because the protrusions of the upper electrode and the protrusions of the lower electrode are arranged crosswise to each other, the area between the upper electrode and the lower electrode is increased, and the charge storage capacity of the trench capacitor can be increased. Ding Eryu The trench is formed on the second conductive layer and the first dielectric layer of the trench, and the second conductive dielectric layer is formed on the trench. The thickness of the sublayer layer at the output portion has a large capacitance, and the material is sequentially filled in the upper and inner shapes. The electrical layer and the fourth dielectric layer, the first conductive second conductive layer, the first conductive first conductive layer, and the first conductive second conductive layer can form an upper electrode, and the vapor deposition of the present invention is thin, and the amount of conductive layers is described. Step 4 of forming a second conductive material layer, a dielectric layer. Then, the dielectric layer and the second and fourth dielectric layers of the fourth dielectric layer and the second and fourth dielectric layers have a plurality of trenches. The trench-type electrogastric method is so deposited that the etching step can be performed before the steps of the & dielectric layer and the fourth dielectric layer, leaving only the order of the sidewalls of the trench to be performed sequentially on the dielectric layers in the trench. As for the steps of the trench layer, then repeat the steps In the trench, the steps of the dielectric layer are sequentially followed by the steps of the trench layer, and then the electrodes and capacitors under the rear protrusion are performed. The conductive layer and the dielectric of the valley device are formed. Therefore, the size design of each conductive element is limited. The electric valley device can further remove the second conductive layer to form a first channel and then sequentially remove the second conductive layer to form a first channel. There are multiple protruding layers based on the original layer and the dielectric. The obtained capacitor is composed of a lower electrode of the present invention, another upper electrode of a trench capacitor and a dielectric layer.
’此溝渠式電容器是 下電極設置於基底 578177 五、發明說明(5) 中,且下電極是由下電極本體與多 ★ 筮一穿屮邱夕楚 r. 第 犬出部所構成。 第一“权第—末端連接下電極本體 二末端從下電極朝一第一方向延伸。上二,第 中,且位於從下電極朝第一方Θ 认置於基底 朝弟方向延伸的相對位置上。上電 ;ί土ΐΐϊίίίΓ個第二突出部所構成。第二突出部 m第:方向延伸。第二方向係與第-方向相 交互排列。介電層則設 反’且第二突出部係與第一突 置於上電極及下電極之間。 邱盥本ϊ明之溝渠式電容器中,上電極之多個突出 .^ — 大出邛係為父互排列的形式,因此,玎 =^加兀件尺寸之情形下’藉由改變前述突出部之尺寸 以掸r、番ί:大幅增加上電極與下電極之間的面積,而可 以增加溝渠電容器的儲存量。 韶且ί讓本發明之上述和其他目#、特徵、和優點能更明 : 下文特舉一較佳實施例,並配合所附圖式,作詳 細說明如下: [實施方式] a ί2圖至第11圖所纷示為本發明之一較佳實施例之溝 渠式電容器之製造流程剖面圖。 η /先、,、凊參照第2圖,提供一基底200,然後於基底 形成溝渠202及摻雜區2〇4。播雜區2〇4係形成於溝渠 底部的基底2〇〇巾,y 土 & z u u T 而且部分延伸至溝渠2 0 2側壁。 溝渠202之形成步騍例如是先於基底200表面形成一圖‘This trench capacitor has a lower electrode on the substrate 578177 5. In the description of the invention (5), and the lower electrode is composed of a lower electrode body and a plurality of ★ 一 穿 屮 Qiu Xichu r. No. Inu Chube. The first "right-end" is connected to the lower electrode body and the two ends extend from the lower electrode in a first direction. The upper two, the middle, and are located at the relative positions extending from the lower electrode toward the first side Θ to the direction of the base. Power on; ί 土 ΐΐϊίίΓ composed of two second protrusions. The second protrusions extend in the m-direction: the second direction is arranged alternately with the-direction. The dielectric layer is opposite and the second protrusions are And the first protrusion is placed between the upper electrode and the lower electrode. Qiu Xiben's Ming-type trench capacitor, the multiple protrusions of the upper electrode. ^ — The big out of the line is a form of parent arrangement, so 玎 = ^ 加In the case of the size of the element, by changing the size of the aforementioned protrusions to increase the area between the upper electrode and the lower electrode, the storage capacity of the trench capacitor can be increased. The above and other items #, features, and advantages can be made clearer: A preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: [Embodiment] a 2 to 11 are shown as A trench capacitor according to a preferred embodiment of the present invention A cross-sectional view of the manufacturing process of the device. Η / ,,,, and 凊 Refer to FIG. 2 to provide a substrate 200, and then form a trench 202 and a doped region 204 on the substrate. The doped region 204 is formed at the bottom of the trench. The substrate 200, y soil & zuu T and partly extends to the side wall of the trench 202. The formation step of the trench 202 is, for example, forming a picture before the surface of the substrate 200
578177 五、發明說明(6) 案化之罩幕層(未圖示),此圖案化之罩幕層之材質例如是 氮化矽,形成圖案化之罩幕層之方法例如是先以化學氣相 沉積法(Chemical Vapor Deposition,CVD)形成一罩幕層 覆蓋於基底2 0 0上,再進行一微影钱刻製程,以在此罩幕 層中形成圖案。然後,進行一触刻製程,以在基底2 〇 〇中 形成溝渠202。在基底200中蝕刻出溝渠202之方法,例如 是乾式钱刻法。溝渠202之寬度例如是2600埃左右,且在 下述之說明中,各構件之尺寸係溝渠2〇2之寬度為基準進 行說明。 紅 摻雜區2 0 4之形成步驟例如是在溝渠2 0 2内形成一層摻 雜絕緣層(未圖示),此摻雜絕緣層之材質例如是摻質為砷 離子之氧化矽層,形成摻雜絕緣層之方法例如是以臨場 (In-Situ)摻雜離子之方式,利用化學氣相沈積法以形成 之。然後,於溝渠2〇4底部形成一層光阻層(未圖示),豆 中光阻層並未填滿溝渠202 ’且光阻層之表面係位於基底 屏銘接者,移除高於光阻層之部分掺雜絕緣 ;氟:(1 ff =層之方法例如是濕式姓刻法,係以緩衝 圖示),間隙壁之材質二=之,上形成間隙壁(未578177 V. Description of the invention (6) The patterned mask layer (not shown). The material of the patterned mask layer is, for example, silicon nitride. The method of forming the patterned mask layer is, for example, chemical gas. The phase deposition method (Chemical Vapor Deposition, CVD) forms a mask layer to cover the substrate 200, and then performs a lithography process to form a pattern in the mask layer. Then, a one-touch etch process is performed to form a trench 202 in the substrate 2000. The method of etching the trench 202 in the substrate 200 is, for example, a dry money engraving method. The width of the trench 202 is, for example, about 2600 angstroms, and in the following description, the dimensions of each component are described based on the width of the trench 202. The step of forming the red doped region 204 is, for example, forming a doped insulating layer (not shown) in the trench 202, and the material of the doped insulating layer is, for example, a silicon oxide layer doped with arsenic ions. The method of doping the insulating layer is, for example, formed by in-situ doping ions and using a chemical vapor deposition method. Then, a photoresist layer (not shown) is formed at the bottom of the trench 204. The photoresist layer in the bean does not fill the trench 202 'and the surface of the photoresist layer is located on the substrate screen. Part of the barrier layer is doped with insulation; fluorine: (1 ff = layer method is, for example, a wet-type engraving method, which is illustrated by a buffer), and the material of the partition wall = 2 is formed on the partition wall (not
Ethyl Ortho S i 1 i Cate V ^ ^ ^ (Τβ ΪΓ3 用化學氣相沈積法所形成之氧)化:乳(〇3)為反應氣體源利 底200進行-熱製程,使推 移除光阻層後’對基 底㈣中而形成-摻雜S f。^層中;^質擴散進入基 A後’移除溝渠202内的摻Ethyl Ortho S i 1 i Cate V ^ ^ ^ (Tβ ΪΓ3 Oxygen formed by chemical vapor deposition): Milk (〇3) is a reaction gas source and bottom 200 is subjected to a thermal process, so that the photoresist layer is removed by pushing And then doped into the substrate to form-doped S f. In the layer; after the diffusion of the substance into the base A, the dopant in the trench 202 is removed.
578177 五、發明說明(7) 雜絕緣層與溝渠2 〇 2側壁上之間隙壁。移除摻雜絕緣層與 間隙壁之方法例如是濕式餘刻法,係以緩衝氫氟酸 (Buffer HF,BHF)或稀釋的氫氟酸(Diluted HF,DHF)為 I虫刻劑。 接著,請參照第3圖,於溝渠2 0 2内形成一層共形的第 一介電層206a,其材質例如是氮化物、氧化物。具體而 言,第一介電層206a之材質例如是氧化鋁或氮化矽。第一 介電層20 6a之形成方法例如是原子層化學氣相沈積法 (Atomic Layer Chemical Vapor Deposition ,ALCVD)或 低壓化學氣相沈積法(Low Pressure Chemical Vapor Deposition,LPCVD)。再者,第一介電層20 6a之厚度例如 是100埃至300埃左右。 之後,於第一介電層20 6a上形成一層共形的第一導電 層2 08a,其材質例如是抗氧化金屬化合物、抗氮化金屬化 合物’較佳者前述材質之耐熱溫度至少需高於攝氏12〇〇 度。具體而言,第一導電層20 8a之材質例如是氮化鈦。第 一導電層208a之形成方法例如是原子層化學氣相沈積法或 低壓化學氣相沈積法。再者,第一導電層2〇8a之厚度例如 是100埃至200埃左右。 接著,於第一導電層208a上形成一層共形的第二介電 層21 0a,其材質例如是氮化物、氧化物。具體而言,第二 介電層210a之材質例如是氧化紹或氮化石夕。第二介電層 21 〇a之形成方法例如是原子層化學氣相沈積法或低壓化學 氣相沈積法。再者,第二介電層2 1 0 a之厚度例如是5 0埃至578177 V. Description of the invention (7) The gap between the hetero insulation layer and the side wall of the trench 202. The method for removing the doped insulating layer and the spacer is, for example, a wet-etching method, which uses a buffer hydrofluoric acid (Buffer HF, BHF) or a diluted hydrofluoric acid (Diluted HF, DHF) as an insecticide. Next, referring to FIG. 3, a conformal first dielectric layer 206a is formed in the trench 202, and the material is, for example, nitride or oxide. Specifically, the material of the first dielectric layer 206a is, for example, aluminum oxide or silicon nitride. A method for forming the first dielectric layer 206a is, for example, an atomic layer chemical vapor deposition (ALCVD) method or a low pressure chemical vapor deposition (LPCVD) method. The thickness of the first dielectric layer 20 6a is, for example, about 100 to 300 angstroms. After that, a conformal first conductive layer 2 08a is formed on the first dielectric layer 20 6a. The material is, for example, an anti-oxidation metal compound or an anti-nitridation metal compound. 12,000 degrees Celsius. Specifically, the material of the first conductive layer 20 8a is, for example, titanium nitride. The method for forming the first conductive layer 208a is, for example, an atomic layer chemical vapor deposition method or a low-pressure chemical vapor deposition method. The thickness of the first conductive layer 208a is, for example, about 100 to 200 angstroms. Next, a conformal second dielectric layer 21 0a is formed on the first conductive layer 208a, and the material is, for example, nitride or oxide. Specifically, the material of the second dielectric layer 210a is, for example, oxide or nitride. The method for forming the second dielectric layer 21 oa is, for example, an atomic layer chemical vapor deposition method or a low-pressure chemical vapor deposition method. Furthermore, the thickness of the second dielectric layer 2 1 0 a is, for example, 50 Angstroms to
第12頁 578177Page 12 578177
150埃左右。 之後,請參照第4圖,移除部分第二介電層2丨〇a、第 一導電層208a及第一介電層2〇6a,只留下位於溝渠2〇2側 壁上之第二介電層210b、第一導電層2〇8b及第一介電層 20 6^)。其中,移除部分第二介電層以仏、第一導電層2〇8a 及第一介電層206a的方法包括非等向性蝕刻法,其例如是 電漿蝕刻法、反應性離子蝕刻法等。 一接著,請參照第5圖,於基底2 00上形成一層共形的第 二介電層212a,以覆蓋暴露之基底2〇〇、摻雜區2〇4、第一 介電層20 6b、第一導電層208b及第二介電層21〇b。第三介 電層21 2a之材質例如是氮化物、氧化物。具體而言,第三 介電層212a之材質例如是氧化鋁或氮化矽。第三介電層 2^1 2a之形成方法例如是原子層化學氣相沈積法或低壓化學 氣相沈積法。再者,第三介電層212a之厚度例如是5〇埃至 1 5 0埃左右。 之後’请參照第6圖,移除部分第三介電層2 1 2 a,只 留下位於溝渠202側壁上之第三介電層212b。其中,移除 4为第二介電層21 2 a的方法包括非等向性钱刻法,其例如 是電漿蝕刻法、反應性離子蝕刻法等。Around 150 Angstroms. After that, please refer to FIG. 4 to remove part of the second dielectric layer 20a, the first conductive layer 208a, and the first dielectric layer 206a, leaving only the second dielectric layer on the sidewall of the trench 202. The electrical layer 210b, the first conductive layer 208b, and the first dielectric layer 206b). Among them, a method of removing a part of the second dielectric layer with ytterbium, the first conductive layer 208a, and the first dielectric layer 206a includes an anisotropic etching method, such as a plasma etching method and a reactive ion etching method. Wait. Next, referring to FIG. 5, a conformal second dielectric layer 212a is formed on the substrate 200 to cover the exposed substrate 200, the doped region 204, the first dielectric layer 20 6b, The first conductive layer 208b and the second dielectric layer 210b. The material of the third dielectric layer 21 2a is, for example, a nitride or an oxide. Specifically, the material of the third dielectric layer 212a is, for example, aluminum oxide or silicon nitride. The method for forming the third dielectric layer 2 ^ 1 2a is, for example, an atomic layer chemical vapor deposition method or a low-pressure chemical vapor deposition method. The thickness of the third dielectric layer 212a is, for example, about 50 to 150 angstroms. After that, please refer to FIG. 6, and remove a part of the third dielectric layer 2 1 2 a, leaving only the third dielectric layer 212 b on the sidewall of the trench 202. Among them, the method of removing 4 as the second dielectric layer 21 2 a includes an anisotropic money engraving method, which is, for example, a plasma etching method, a reactive ion etching method, or the like.
接著,請參照第7圖,於基底2 00上形成一層共形的第 二導電層214a,以覆蓋暴露之基底2〇〇、摻雜區2〇4、第一 介電層206b、第一導電層2〇8b、第二介電層21 〇b及第三介 電層212b。第二導電層21 4a之材質例如是多晶矽等可氧化 (或可氮化)的材質。第二導電層21 6a之形成方法例如是Next, referring to FIG. 7, a conformal second conductive layer 214a is formed on the substrate 200 to cover the exposed substrate 2000, the doped region 204, the first dielectric layer 206b, and the first conductive layer. Layer 208b, second dielectric layer 212b, and third dielectric layer 212b. The material of the second conductive layer 21 4a is, for example, an oxidizable (or nitrided) material such as polycrystalline silicon. The method for forming the second conductive layer 21 6a is, for example,
第13頁 578177 五、發明說明(9) 原子層化子氣相/尤積法或低壓化學氣相沈積 二導電f214a之厚度例如是200埃至500埃左右。再者第 接著,於帛二導電層21 4a上形成一層共形❸第 :216a,其材質例如是氮化物、氧化物。 ^ 介電層216a之材質例如是氧化銘或氮化石夕。第:;電ί 氣相沈料。AJ 層化學氣相沈積法或低壓化學 〃沈積法再者,第四介電層21 6a之厚度例如是5〇埃 1 5 0埃左右。 J戈疋5 ϋ埃至 之後,於溝渠202内填入材料層218,且 …低於溝渠202之頂面(亦即,基底2〇〇之=8 )。此材料層218之材質例如是光阻 表面2 形成方法例如是先於第四介電層216a之上塗佈材二 (未圖不),i此光阻層填滿溝渠m,然後回曰 直到光阻頂面低於溝準2〇2之頂而盔u ^ ^ 4尤丨且 之材質也可以是其為當然,材料層218 層2二著第:i=b,移,除高於材料層218的第-介電 212b、第二導電層2Ua及第四 教I—電層 括非等向性餘刻法,复例如是雷。移除的方法包 刻法等。 八例如疋電漿蝕刻法、反應性離子蝕 21n ^ M 第9圖,砂咪矸科層218。移除材料層 f除部分光阻後,#以濕式_法移除殘留之光 專。接者,於溝渠202側壁形成第五介電層22〇以及於暴Page 13 578177 V. Description of the invention (9) Atomic layered layer gas phase / Euzo method or low pressure chemical vapor deposition The thickness of the second conductive f214a is, for example, about 200 angstroms to 500 angstroms. Furthermore, a conformal layer: 216a is formed on the second conductive layer 21 4a, and the material is, for example, nitride or oxide. ^ The material of the dielectric layer 216a is, for example, oxide or nitride. No .: Electricity ί Vapor sinker. Furthermore, the thickness of the fourth dielectric layer 21 6a is, for example, about 50 angstroms or 150 angstroms. After J Ge 疋 5 疋, the material layer 218 is filled in the trench 202, and is ... lower than the top surface of the trench 202 (that is, the base 200 = 8). The material of the material layer 218 is, for example, a photoresist surface 2. The method for forming the material layer 218 is, for example, coating material 2 (not shown) on the fourth dielectric layer 216a, i. The top surface of the photoresist is lower than the top of the groove standard 202 and the material of the helmet u ^ 4 can also be taken as a matter of course. The material layer 218 and the layer 2 are aligned: i = b, shift, except that it is higher than the material. The first dielectric layer 212b, the second conductive layer 2Ua, and the fourth electrode I-layer of the layer 218 include an anisotropic post-cut method, such as thunder. Removed methods include engraving. For example, the plasma etching method, reactive ion etching 21n ^ M FIG. 9, Samiaceae layer 218. After the material layer is removed, a portion of the photoresist is removed, and the remaining light is removed by a wet method. Then, a fifth dielectric layer 22 is formed on the sidewall of the trench 202 and
578177 五、發明說明(ίο) 路之第一導電層214b之表面形成第六介電層222。形成 五介電層220及第六介電層的方法例如是氧化法或氮化 法。此時,由於第一導電層208b係由抗氮化或抗氧化之耐 高溫材質所構成,且利用第一導電層2〇8b和第二導電層 214b之抗氮化或抗氧化的能力的差異,因而,在第一& 層2 08b之表面不易產生氮化物或氧化物,而可 之第三導電層224電性連接。 良, 尸然而,為了完全防止暴露之第一導電層2〇81)受到氧化 或氮化,而使第一導電層2〇8b無法與後續之第三導電層 224電性連接,也可進行一短時間的蝕刻步驟,利用電曰裝 蝕刻或反應性離子蝕刻法移除可能形成於 上之極薄的氧化層(或氮化層)。 憲 接著\請參照第圖,於溝渠202内填入第三導電層 224 ’其中第三導電層m之頂面低於溝渠2〇2之頂面(亦 即,基底200之表面2〇〇a),且第三導電層2 =電:接觸。此時,第三導電綱覆蓋有第一導導電電 22 V八二介電層21〇b、第三介電層212b、第六介電層 矽、金屬H層216b。帛三導電層224之材質例如是多晶 方法例如物、金屬化合物等。第三導電層224之形成 '|,疋化學氣相沈積法或物理氣相沈積法。 五介參照第11圖移除高於第三導電層224的第 雷芦2?η曰夕士、’以暴露出溝渠202側壁。其中,移除第五介 去例如是濕式姓刻法。接著,於呆露 202側壁上形成 接者於暴路之溝渠 Α乳化物層(Collar Oxide) 22 6。領氧化物 第15頁 578177 五、發明說明(11) 層2 2 6之形成方法例如疋熱氧化法或化學氣相沈積法。然 後,移除部分領氧化層226以暴露出第三導電層224之表 面,移除部分領氧化層2 2 6的方法包括非等向性蝕刻法, 其例如是電漿餘刻法、反應性離子敍刻法等。 接著,形成苐四導電層228填滿溝渠2〇2,其中第四導 電層228與第三導電層224電性接觸。第四導電層228之材 質例如是多晶矽、金屬矽化物、金屬化合物等。第四導電 層228之形成方法例如是化學氣相沈積法或物理氣相沈積 法。 之後,進行回蝕刻,移除溝渠2〇2外之第四導電層 2 2 8,並暴露出溝渠2 0 2頂部之部份側壁。接著,形成第五 導電層230填滿溝渠202,其中第五導電層23〇與第四導電 層2 2 8電性接觸。第五導電層2 3 〇之材質例如是多晶矽、金 屬矽化物、金屬化合物等。第五導電層23〇之形成方法例 如疋化學氣相沈積法或物理氣相沈積法。 由於,第一導電層2〇8b、第三導電層224、第四導電 層228、第五導電層230構成溝渠式電容器之上電極;且第 二導電層21 4b及摻雜區204構成溝渠式電容器之下電極。 7 ί為上電極本體(第四導電層228、第五導 ”夕個突出部(第一導電層2〇8b、第:導電層 224)兩部分;且下雪托可八决 禾一导电續 ^9ηη , ^ 下電極可刀為下電極本體(溝渠202底部基 伸至雀渠雜區2〇4、第二導電層214b)與多個突出部(延 魚壁之摻雜區204、第二導電層214b)兩部分。其 ,電極之突出部與下電極之突出部係交互排列,而介578177 V. Description of the Invention A sixth dielectric layer 222 is formed on the surface of the first conductive layer 214b of the circuit. The method of forming the fifth dielectric layer 220 and the sixth dielectric layer is, for example, an oxidation method or a nitride method. At this time, since the first conductive layer 208b is made of a high-temperature resistant material that is resistant to nitridation or oxidation, and uses the difference in the ability to resist nitriding or oxidation of the first conductive layer 208b and the second conductive layer 214b Therefore, it is difficult to generate nitrides or oxides on the surface of the first & layer 2 08b, and the third conductive layer 224 can be electrically connected. However, in order to completely prevent the exposed first conductive layer 2081) from being oxidized or nitrided, so that the first conductive layer 208b cannot be electrically connected to the subsequent third conductive layer 224, it is also possible to perform a In a short etching step, an extremely thin oxide layer (or nitride layer) that may be formed thereon is removed by electrical etching or reactive ion etching. Then, please refer to the figure, and fill the trench 202 with a third conductive layer 224 ', wherein the top surface of the third conductive layer m is lower than the top surface of the trench 200 (ie, the surface 200a of the substrate 200). ), And the third conductive layer 2 = electricity: contact. At this time, the third conductive platform is covered with the first conductive 22 V 822 dielectric layer 21 0b, the third dielectric layer 212b, the sixth dielectric layer silicon, and the metal H layer 216b. The material of the tri-conductive layer 224 is, for example, a polycrystalline method such as a substance, a metal compound, or the like. The third conductive layer 224 is formed by a chemical vapor deposition method or a physical vapor deposition method. Wujie refers to FIG. 11 to remove the first thunder, which is higher than the third conductive layer 224, to expose the sidewall of the trench 202. Among them, removing the fifth agent is, for example, a wet last name engraving method. Then, on the side wall of the dew 202, a oxidized layer of Collar Oxide A (Collar Oxide) 22 6 is formed. Colloidal Oxide Page 15 578177 V. Description of the Invention (11) The method for forming the layer 2 2 6 is, for example, a thermal oxidation method or a chemical vapor deposition method. Then, a part of the collar oxide layer 226 is removed to expose the surface of the third conductive layer 224, and a method of removing the collar oxide layer 2 2 6 includes an anisotropic etching method, such as a plasma etching method and a reactive property. Ion engraving and so on. Next, a trench 24 is formed to fill the trench 202, and the fourth conductive layer 228 is in electrical contact with the third conductive layer 224. The material of the fourth conductive layer 228 is, for example, polycrystalline silicon, metal silicide, metal compound, or the like. The method for forming the fourth conductive layer 228 is, for example, a chemical vapor deposition method or a physical vapor deposition method. After that, etch back is performed to remove the fourth conductive layer 2 2 8 outside the trench 20 2, and a part of the sidewall of the top of the trench 20 2 is exposed. Next, a fifth conductive layer 230 is formed to fill the trench 202, and the fifth conductive layer 230 is in electrical contact with the fourth conductive layer 228. The material of the fifth conductive layer 23 is, for example, polycrystalline silicon, metal silicide, metal compound, or the like. The fifth conductive layer 23 is formed by, for example, a chemical vapor deposition method or a physical vapor deposition method. Because the first conductive layer 208b, the third conductive layer 224, the fourth conductive layer 228, and the fifth conductive layer 230 constitute an electrode above the trench capacitor; and the second conductive layer 21 4b and the doped region 204 constitute a trench type The electrode below the capacitor. 7 is two parts of the upper electrode body (the fourth conductive layer 228, the fifth conductive layer) (the first conductive layer 208b, the first: the conductive layer 224); and the snow support can be conductive. ^ 9ηη, ^ The lower electrode can be the lower electrode body (the bottom of the trench 202 extends to the bird channel heterogeneous region 204, the second conductive layer 214b) and a plurality of protrusions (the doped region 204 of the fish wall, the second conductive Layer 214b). The protrusions of the electrode and the protrusions of the lower electrode are alternately arranged, and
第16頁 578177 五、發明說明(12) =(第-介入電層議、第二介電層2i〇b、第三介電層 212b、第四,丨電層216b、第五介 222 )則設置於上電極盥下雷代々卩日 主 电增 态之1私為=知技術者所週知在此不再贅述。 在上述實施例中,本發明之溝渠式電容器的導電層及 介電層係以原子層化學翁4日、士扯 i Φβ八Φ 虱相沈積法所沈積而成,因此,各 導電層及;!電層之厚度很薄,如此即可於元件尺寸設計之 限制下,形成由多個導電層及介電層組成的溝渠式電容 器,進而可以增加電容器之電容量。 而且,在上述實施例中,下電極係以形成四 為實例作說明,上電極係以形成三個突出部為實例作^ 明,當然本發明也可以在第7圖之步驟中,於基底2〇〇 :依 序形成一層共形的第二導電層21“與一層共形的第四介 層21 6a後,移除部分的第二導電層214a與第四介電層 216a(如第7圖所示區域a之第二導電層2Ha與第四介電層 216a)後,只留下位於溝渠2〇2側壁上之第二導電層2ι乜曰盘 第四介電層216a。其中,移除部分第二導電層21“與第= 介電層21 6a的方法包括非等向性蝕刻法,其例如是電漿蝕 刻法、反應性離子蝕刻法等。接著,進行第3圖至第7圖之 步驟。然後重複移除部分的第二導電層214a與第四介電 21 6a之步驟與進行第3圖至第7圖之步驟,再進行後續(第8 圖至第11圖)之步驟,·而可以形成包括具有四個以上突出 部之下電極與具有三個以上突出部之上電極的溝渠式電容 器0P.16 578177 V. Description of the invention (12) = (The first-interventional layer, the second dielectric layer 2iob, the third dielectric layer 212b, the fourth, the electrical layer 216b, the fifth dielectric 222) It is set at the upper electrode and the next generation of the main power increase state of the next day is known to those skilled in the art and will not be repeated here. In the above embodiments, the conductive layer and the dielectric layer of the trench capacitor of the present invention are deposited by the atomic layer chemical method and the Shih i Φ β Φ Φ phase deposition method, so each conductive layer and; !! The thickness of the electrical layer is very thin, so that a trench capacitor composed of multiple conductive layers and dielectric layers can be formed under the limitation of the component size design, which can increase the capacitance of the capacitor. Moreover, in the above embodiment, the lower electrode system is described by taking the formation of four as an example, and the upper electrode system is described by taking the formation of three protrusions as an example. Of course, the present invention can also be applied to the substrate 2 in the step of FIG. 〇〇: After forming a conformal second conductive layer 21 "and a conformal fourth dielectric layer 21 6a, remove part of the second conductive layer 214a and the fourth dielectric layer 216a (as shown in Fig. 7). After the second conductive layer 2Ha and the fourth dielectric layer 216a) in the area a, only the second conductive layer 2m on the sidewall of the trench 202 is left, and the fourth dielectric layer 216a is removed. Part of the method of the second conductive layer 21 "and the third dielectric layer 21a includes anisotropic etching, such as plasma etching, reactive ion etching, and the like. Next, the steps of FIGS. 3 to 7 are performed. Then repeat the steps of removing a part of the second conductive layer 214a and the fourth dielectric 21 6a and performing the steps of FIGS. 3 to 7 and then the subsequent steps (FIGS. 8 to 11). Forming a trench capacitor including an electrode having four or more protrusions and an electrode having three or more protrusions
578177 五、發明說明(13) 上述說明本發明溝渠是電容器之製造方法 本發明之溝渠式電容器之結構。 月 第1?圖2繪示為本發明之溝渠式電容器的結構剖面 圖。請爹照第1 2圖,在基底3〇〇中形成有本發明之 電容器。而本發明之溝渠式電容器是由下電極3〇2、:電 極304、與介電層306所構成。 下電極302設置於基底300中,其例如是由下電極本體 304a與多個突出部304b所構成。下電極本體3〇乜係設置於 基底300中。多個突出部3〇2b之一端與下電極本體3〇2&連 接,而多個突出部3〇2b之另一端則從下電極本體3〇2a往第 一方向延伸。且突出部302b之形狀例如是矩形、多邊形、 不規則形狀等的凸塊。 上電極304設置於基底3〇〇中,且位於從下電極3〇2朝 第一方向延伸的相對位置上,其例如是由上電極本體 3〇4a、導體層304c與多個突出部3〇 4b所構成。上電極本體 304a係設置於下電極302上方。導體層3〇4c係設置於上電 極本體304a上方且與上電極本體3〇4a連接。多個突出部 304b之一端與上電極本體3〇4a連接,而多個突出部3〇“之 另一端則從上電極本體304a往第二方向延伸,且第二方向 係為第一方向的相反方向。因此,上電極3〇4之突出部 304b係與下電極3〇2之突出部3〇2b交互排列。其中突出部 3 0 4 b之形狀例如是矩形、多邊形、不規則形狀等的凸塊。 介電層306則設置上電極304及下電極302之間。 在上述之溝渠式電容器中,上電極之多個突出部與下 第18頁 578177 五、發明說明^ ---- 電極之多個突屮卸 加元件尺寸ΐϊ;係為交互排列的形式,因此,可在不增 #, 形下,藉由改變前述突出部之尺寸及數 里,即口J大ψδ 4_祕又人 之儲户旦 ^ 5 U電谷器之表面積’進而大幅增加電容器 出部$ ^ ’在上述實施例中,下電極302係以具有四個突 之突it} j丨作σ兒明’當然也可視實際需要而設置不同個數 例作戈Γ °同樣的’上電極304係以具有三個突出部為實 部。兄月’當然也可視實際需要而設置不同個數之突出 限定:::發:月已以較佳實施例揭露如上,然其並非用以 和範“ = =者’在不脫離本發明之精神 範園當视後與潤飾_:因此本發明之保護 便附之申凊專利範圍所界定者為準。 578177 圖式簡單說明 第1圖所示係為習知溝渠式電容器之結構的剖面示意 圖, 第2圖至第1 1圖所示係為本發明之一較佳實施例之溝 渠式電容器製造流程的示意圖;以及 第1 2圖所示係為本發明之一較佳實施例之溝渠式電容 器之結構的剖面示意圖。 [圖式標示說明] 100、200、300 :基底 1 0 2、3 0 2 :下電極 104、30 6 :介電層 106、304 :上電極 1 0 8 :溝渠式電容器 200a :表面 202 :溝渠 2 0 4 :摻雜區 2 2 6 :領氧化物層 206a、206b :第一介電層 208a、208b :第一導電層 210a、210b :第二介電層 212a、212b :第三介電層 214a、214b :第二導電層 216a、216b :第四介電層 2 1 8 :材料層 220 :第五介電層578177 V. Description of the invention (13) The above description The trench of the present invention is a method for manufacturing a capacitor The structure of the trench capacitor of the present invention. Fig. 1 to Fig. 2 are cross-sectional views showing the structure of a trench capacitor of the present invention. Please refer to Fig. 12 for the capacitor of the present invention formed in the substrate 300. The trench capacitor of the present invention is composed of a lower electrode 302, an electrode 304, and a dielectric layer 306. The lower electrode 302 is provided in the substrate 300, and is formed of, for example, a lower electrode body 304a and a plurality of protruding portions 304b. The lower electrode body 300 is disposed in the substrate 300. One end of the plurality of protrusions 302b is connected to the lower electrode body 302, and the other end of the plurality of protrusions 302b extends from the lower electrode body 302a in the first direction. The shape of the protruding portion 302b is, for example, a bump having a rectangular shape, a polygonal shape, or an irregular shape. The upper electrode 304 is disposed in the substrate 300 and is located at a relative position extending from the lower electrode 3002 in the first direction. For example, the upper electrode 304 is composed of the upper electrode body 304a, the conductor layer 304c, and a plurality of protrusions 30. 4b. The upper electrode body 304a is disposed above the lower electrode 302. The conductive layer 304c is disposed above the upper electrode body 304a and is connected to the upper electrode body 304a. One end of the plurality of protrusions 304b is connected to the upper electrode body 304a, and the other end of the plurality of protrusions 304 "extends from the upper electrode body 304a to the second direction, and the second direction is opposite to the first direction Therefore, the protruding portion 304b of the upper electrode 304 is alternately arranged with the protruding portion 30b of the lower electrode 302. The shape of the protruding portion 3 0 4b is, for example, a convex shape such as a rectangle, a polygon, or an irregular shape. The dielectric layer 306 is provided between the upper electrode 304 and the lower electrode 302. In the above-mentioned trench capacitor, the plurality of protrusions of the upper electrode and the lower page 18 578177 V. Description of the invention ^ ---- The electrode The dimensions of multiple protrusions are added in an alternating arrangement, so you can change the size and number of the aforementioned protrusions without increasing the #, shape, that is, the mouth J 大 ψδ 4_ 秘 又 人The surface area of the depositor ^ 5 U electric valley device 'further increased the capacitor output $ ^' In the above embodiment, the lower electrode 302 is formed with four protrusions} Depending on the actual needs, different numbers of examples can be set to make the same 'upper electrode 304' It has three protruding parts as the actual part. Of course, Brother Yue 'can also set different number of protruding restrictions according to actual needs ::: 发: 月 has been disclosed as above with a preferred embodiment, but it is not used to converge "= = Those who do not depart from the spiritual garden of the present invention should consider and embellish the _: Therefore, the protection of the present invention is defined by the scope of the patent application. 578177 Brief description of the drawing Figure 1 shows a schematic cross-sectional view of the structure of a conventional trench capacitor. Figures 2 to 11 show the manufacturing process of a trench capacitor according to a preferred embodiment of the present invention. Schematic diagrams; and FIG. 12 is a cross-sectional diagram showing the structure of a trench capacitor according to a preferred embodiment of the present invention. [Illustration of diagrammatic symbols] 100, 200, 300: substrate 10, 2, 3 0 2: lower electrode 104, 30 6: dielectric layer 106, 304: upper electrode 108, trench capacitor 200a: surface 202: trench 2 0 4: doped region 2 2 6: collar oxide layers 206 a and 206 b: first dielectric layers 208 a and 208 b: first conductive layers 210 a and 210 b: second dielectric layers 212 a and 212 b: third dielectric layer 214a, 214b: second conductive layers 216a, 216b: fourth dielectric layer 2 1 8: material layer 220: fifth dielectric layer
第20頁 578177 圖式簡單說明 222 :第六介電層 224 :第三導電層 228 :第四導電層 230 :第五導電層 302a :下電極本體 302b 、 304b :突出部 304a :上電極本體 304c :導體層Page 578177 Brief description of the drawings 222: The sixth dielectric layer 224: The third conductive layer 228: The fourth conductive layer 230: The fifth conductive layer 302a: The lower electrode body 302b, 304b: The protruding portion 304a: The upper electrode body 304c : Conductor layer
第21頁Page 21
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