TW577139B - Method of using one lithography step to form alignment mark and shallow trench - Google Patents

Abstract

A method of using one lithography step to form alignment mark and shallow trench is disclosed in the present invention. At first, a silicon oxide layer, a silicon nitride layer, and a silicon-oxy-nitride layer are sequentially formed on a semiconductor substrate; and the positions of the alignment mark and the shallow trench are defined by using lithography technique. Then, the first anisotropic etching process is conducted to form the alignment mark and the shallow-layered shallow trench on the semiconductor substrate. After that, an etching barrier layer is formed on the alignment mark, and is followed by conducting the second anisotropic etching process onto the shallow-layered shallow trench to form the shallow trench.

Description

577139 V. Description of the invention (l) '---- Detailed description: Technical field: This issue is about a method for forming alignment marks and shallow trenches on a semiconductor substrate, especially a method using a lithography process at the same time. Method for forming alignment marks and shallow trenches. Background of the invention: The lithography process is one of the most important process steps in the entire semiconductor process. Second, the structure of all integrated circuit components, such as the pattern of each layer of film and the area of noise, are determined by the lithography process. . The traditional micro-manufacturing process uses a repeat and step (repeat_and-step) method to perform the process of performing this type of exposure method is called a stepper. However, after the integrated circuit has entered the deep sub-micron process, the characteristic dimension (CD) of the integrated circuit has been continuously reduced, so the requirements for the accuracy of the lithographic process have become higher and higher. The traditional stepper has been Unable to meet the needs of this process. In order to meet the feature size requirements of semiconductor processes from 0.5 microns to 1.3 microns, the integrated circuit industry has developed a scanner that replaces stepper machines. step-and-scan). In the integrated circuit manufacturing process, a wafer from the beginning of the wafer to the final wafer back grinding (b a c k g r n d i n g) must be completed in a layer-by-layer manner through more than a dozen or even more than 20 yellow lithography steps. Each level of the integrated circuit has its physical and electrical significance. Therefore, in the process of stacking, it must be ensured that the alignment of the level and the previous level is accurate and good, so that the product

5. Description of the invention (2) The quality of the invention is well controlled. In order to achieve this alignment, multiple alignment marks (A1 ignment Marks) must be added during the design and layout of the integrated circuit as a basis for alignment. Please refer to FIG. 1 first, which is a schematic cross-sectional view of a process for forming the alignment mark in the conventional art. First, a semiconductor substrate is provided, and an oxide chip layer 20 is formed on the semiconductor substrate 10 with a thickness of about 350 angstroms. Then, a photoresist 30 is coated on the silicon oxide layer 20, and the position of the alignment mark is defined by using a conventional photolithography technique (see FIG. 1A). Next, an anisotropic etching technique is used to successively etch the silicon oxide layer 20 and the semiconductor substrate 10 to form an alignment mark 40 'as shown in FIG. 1b. Finally, the silicon oxide layer 20 is removed to complete the process of the alignment mark, as shown in Figure 〆C. The resulting alignment mark 40 has a depth of about κοο. In addition, absolute electrical isolation must be formed between each two components to avoid mutual interference between telecommunications between the components. The traditional electrical isolation is formed by the local silicon oxide layer (LOCOS) technology. However, due to its huge Bird's beak effect, too much area of the semiconductor substrate is wasted. The technology of integrated circuits has entered the deep sub-micron field. No longer used. Currently generally used by the industry as electrical isolation is shallow trench isolation (Sha 1 1 〇w Trench Isolation; STI). ○ First of all, please refer to FIG. 2, which is a control profile for forming shallow trench isolation in conventional technology. Illustration. First, a P-type single crystal semiconductor substrate 10 is provided, and successively formed on the semiconductor substrate 10, a silicon oxide layer 50, a silicon nitride layer 60, and a silicon oxynitride layer 70, as shown in the figure. As shown in two A. Of which ^ / 7139

The thickness of ^ 50 is about 110 Angstroms, the thickness of the gasified rock is 60 Å, and the thickness of the silicon oxynitride layer 70 is about 3,200 Angstroms. Next, a layer of photoresist 80 is coated on the shadow stone dioxide layer 70, and the position of the shallow low trenches is drawn by using a conventional micro-B, as shown in Figure 2 (16 ^. Next) Using anisotropic etching technology to form a shallow trench 9 0 on the semiconductor substrate, as shown in Figure 2C. The ice of the shallow trench 9 0 is about 3 500 angstroms. From the above description, it can be known that the depth of the alignment mark 40 is about 2,000, and the depth of the shallow trench 90 is about 3500 angstroms. Because of the required depth of the two, ^ The process of the alignment mark and the process of the shallow trench are separately carried out separately. In this way, the deposition and micro-second: i engraved process must be repeated, which not only increases the cost of the process, but also makes the process Reducing the cost of the process and shortening the process time have become an important subject in the integrated circuit industry. Summary of the Invention: A method for using a lithographic process and the main purpose of the present invention is to provide a method for forming alignment marks and shallow trenches. Standard = = =; To provide a method for forming a semiconductor substrate Using the lithography step to form alignment marks and sha trench trenches, a silicon oxide layer, a silicon nitride layer, and- Layer of silicon oxynitride layer 'reuses lithography to define 577139

The position of the alignment mark and the shallow trench. Next, a first asymmetric etching process is performed to form the alignment marks and shallow trenches on the semiconductor substrate. Subsequently, an etching barrier layer is formed on the alignment mark, and then a second anisotropic etching process is performed to continue etching the shallow shallow trenches into the shallow trenches. For car owners, the etching barrier layer is a layer of local photoresist, and its thickness is between 15 Angstroms and 2500 Angstroms. A method of forming the local photoresist is to place the semiconductor substrate in a buffer reaction chamber, including a pre-alignment chamber or a cooling chamber. Preferably, the etching barrier layer system-clamp (e.g., the clampe) can form alignment marks and shallow trenches with different depths by using only one photomask, which can not only save the cost of making a photomask, but also Significantly shorten the duration of the process, which can greatly improve the competitiveness of the product. Jade, description of the invention (4), the present invention relates to a method for forming alignment marks and shallow trenches on a semiconductor substrate, and more particularly to a method for simultaneously forming alignment marks and shallow trenches using a lithography process.

First, please refer to FIG. 3 ′, which is a schematic cross-sectional view of forming a pad layer, a silicon nitride layer, and a silicon oxynitride layer in the process of the present invention. First, a p-type single crystal f-conductor substrate 100 is provided, and a layer of emulsified silicon layer 110, a layer of silicon nitride layer 120, and a layer of silicon oxynitride layer 130 are successively formed on the semiconductor substrate 100. Wherein, the silicon oxide layer n0 is formed by a thermal oxidation method (thermai 0 and 1 (1 to 1010 or a low pressure chemical vapor deposition method (1 ^ (^ 1))), and the thickness

577139 V. Description of the invention (5) The degree is between 90 angstroms and 130 angstroms, and the optimal thickness is 11 angstroms. The silicon nitride layer 120 is formed by a low-pressure chemical vapor deposition method (LpcvD). The thickness is between 14 Angstroms and 200 Angstroms, and the optimal thickness is about 6 2 5 Angstroms. The silicon oxynitride layer 130 is formed by a low-pressure chemical vapor deposition method (LpcVD). Its thickness is between 250 angstroms and 400 angstroms, and its optimum thickness is about 3 200 angstroms. Next, please refer to FIG. 4, a layer of photoresist 14 0 'is coated on the silicon oxynitride layer i 30 and the conventional lithography technology is used to simultaneously define alignment marks and shallow trenches (5). 1311〇 Trenches). This step is one of the key points of the present invention. It is necessary to redesign the mask. A mask can replace the alignment mark mask and shallow trench mask in the conventional art. This can save a lot of light I, which can greatly reduce Reduce process costs. ί I5 I: I ΐ 五 ’performing a first anisotropic etching process to form alignment marks and shallow shallow channels on the surface of the dead soil plate; 冓. The first engraving system is successively etched with the nitride stone layer 130, the polycrystalline silicon layer 120, the silicon oxide layer 110, and the semiconductor substrate 100 to form an alignment at the same time. Mark I60 and shallow shallow trench 150 have a depth between 1000 Angstroms and 140 Angstroms, and an optimal depth of 12 Angstroms. , /, Is called with reference to FIG. 6 and FIG. 7, which are schematic diagrams of the process of forming j and trench in the first embodiment of the present invention. First, the entire semiconductor substrate i 00 is set slowly. In a buffer chamber, a photoresist nozzle (not shown) is used to align the alignment mark 16 to align the alignment mark 16. A layer of local photoresist 17 is formed in 〇, and no photoresist is formed in the shallow shallow trench 150, as shown in FIG. Generally speaking, the alignment mark is located at a 55-degree angle on the semiconductor substrate 100, so it can be adjusted in advance.

577139 V. Description of the invention (6) " ----, the photoresist nozzle of the tube arranged in the reaction chamber is aligned with this position to form a local photoresist 170. The thickness of the local photoresist 17 is between 1 500 Angstroms and 2500 Angstroms. 1 The buffer reaction chamber can be a pre-al ignment chamber or a cooling chamber. Next, a second anisotropic etching process is performed, and the shallow shallow trench 150 is further etched into a shallow trench 15a, as shown in FIG. The depth of the shallow trench 1530 is between 300 angstroms and 4500 angstroms, and the optimal depth is 3500 angstroms. At this time, the local light is in the alignment mark 160. The resistance 170 is used as an etching protection layer, so the depth of the alignment mark 660 will not increase any more. In this way, only one mask can be used to form alignment marks 160 and shallow trenches 150a at different depths. Please refer to FIG. 8 and FIG. 9, which are schematic diagrams of a process for forming a shallow trench in the second embodiment of the present invention. Generally speaking, a rough alignment mark (not shown) is made on the semiconductor substrate i 00 to provide semiconductor process alignment. By aligning the rough alignment mark, the semiconductor substrate can be aligned. 1 0 0 Position accurately in the buffer reaction chamber to accurately define the position of the alignment mark 1 60. Therefore, by setting the position of the clamp 180 in advance, this clamp can be formed above the alignment mark 1 6 0, which is located above the alignment mark 1 6 0. And fixed on the photoresist i 4 0; as for the shallow shallow trench 15 0, no fixture is formed, as shown in FIG. Next, a second anisotropic etching process is performed, and the shallow shallow trenches 150 are further etched into shallow trenches 150a, as shown in FIG. The depth of the shallow trench 1 500a is between 3,500 angstroms and 4,500 angstroms, and the optimal depth is 3,500 angstroms. At this time, the misalignment 1 800 is taken as the alignment mark 16

577139 V. Description of the invention (7) The protective layer is etched, so the depth of the alignment mark 160 will not increase any more. In this way, only one mask can be used to form alignment marks 160 and shallow trenches 150a at different depths. In summary, both the first embodiment and the second embodiment of the present invention can use only one mask to form alignment marks and shallow trenches of different depths, which not only saves the cost of manufacturing the mask, but also greatly Shortening the duration of the process can greatly enhance the competitiveness of the product. The above description uses the preferred embodiments to explain the present invention in detail, but does not limit the scope of the present invention, and those skilled in the art will also understand that appropriate changes and adjustments will still be made without losing the essence of the present invention. Without departing from the spirit and scope of the invention.

Page 12 577139 Brief description of the diagram 9 0 _ shallow trench 11 0-silicon oxide layer 13 0_ silicon oxynitride layer 1 5 0-shallow shallow trench 1 7 0 _ partial photoresistor 100-semiconductor substrate 1 2 0 -Silicon nitride layer 1 4 0-photoresist 1 6 0-alignment mark 1 8 0-cooler

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Claims (1)

577139 6. Scope of patent application Patent scope: 1. A method of forming alignment marks and shallow trenches, the steps include: a. Forming a dielectric layer on a substrate; b. Define the positions of the alignment marks and the shallow trenches on the substrate; c · form the alignment marks and shallow shallow trenches on the substrate; d · on the alignment marks Forming an etch barrier layer; and e. Engraving the 'layer shallow trench' into the shallow trench. 2. The method according to item 1 of the patent application range, wherein the thickness of the dielectric layer is between 100 angstroms and 2000 angstroms. 3. The method according to item 1 of the scope of patent application, wherein said etching barrier layer is a layer of photoresist. 4. The method of claim 3, wherein the thickness of the photoresist is between 15 and 50 Angstroms. 5. The method of claim 3, wherein the method of forming the photoresist is to place the semiconductor substrate in a buffer chamber. 6. The method according to item 5 of the patent application, wherein the buffer reaction chamber is Page 15 577139 VI. Scope of patent application A pre-alignment chamber. 7. The method of claim 5 in which the buffer reaction chamber is a cooling chamber. 8. The method of claim 1, wherein the etch barrier layer is a jig. 9. The method according to item 1 of the patent application, wherein the depth of the alignment mark is between 100 angstroms and 140 angstroms. 10. The method according to item 9 of the scope of patent application, wherein the depth of the alignment mark is 12 Angstroms. 1 1. The method according to item 1 of the scope of patent application, wherein the depth of the shallow trench is between 300 angstroms and 450 angstroms. 12. The method according to item 11 of the scope of patent application, wherein the depth of the shallow trench is 3,500 angstroms. Page 16