05954twf2.doc/006 修正日期92.12.31 玖、發明說明： 本發明是有關於一種用於積體電路製程中的化學配 方，且特別是有關於一種用以形成銅膜的銅電鍍液配方。 隨著積體電路製程進入深次微米（Deep Sub-micron)世 代，積體電路中兀件的積集度（Integraty)也伴隨著大幅提 昇。然而，在提高積集度的過程中也會因爲元件的特性與 其材質而遇到一些問題，其中由於金屬內連線本身材質的 電阻値（Resistance)以及抗電致遷移（Electromigration Resistivity)等特性不能滿足深次微米製程的需求爲積體電 路製程當今最急需解決的問題。 在積體電路製程中，以鋁作爲金屬導線的技術已經發 展的相當成熟了。但是，由於鋁本身材質的電阻値太大(約 爲2.7mQ-cm)，且鋁容易產生電致遷移的現象而造成斷線 的情形，因此在深次微米的半導體製程中以電阻値較低(約 爲1·7ιηΩ -cm)且抗電致遷移能力較佳的銅來取代銘已經成 爲一種趨勢。因此，目前各大半導體製造公司，莫不投入 大量的人力與物力來從事銅製程的硏發。 由於金屬銅不容易被蝕刻，因此銅製程中的金屬導，線 大多都已金屬鑲嵌(Damascene)的技術來製作，也就是先形 成介電層之後，於介電層中形成暴露出欲連接導,線的區 05954twf2.doc/006 修正日期92.12.31 域，再形成塡滿開口的銅層以作爲導線及插塞。這樣的技 術雖然可以避免銅層不易蝕刻的問題’但是在形成銅層時 是否能夠將開口完全塡滿且沒有孔洞（Void)或縫隙 (Seam)，就成了製作銅層時最大的挑戰。 可用於形成銅層的方法包括了物理氣相沉積法 (Physical Vapor Deposition; PVD)、化學氣相沉積法（Chemical Vapor Deposition ; CVD)以及電鍍銅（Cu Electroplating)技術 等。其中，以物理與化學氣相沉積法來製作銅層不但成本 較高，且其所形成的銅層也將因爲塡洞能力不佳而造成銅 膜品質的低落。因此以電鍍銅技術來製作銅膜可以說是積 體電路製程中形成銅層的最佳選擇。 電鍍銅的塡洞能力，不但與進行電鍍的條件有關，其 所使用之電鍍液的成分更是一項不可或缺的因素。目前市 售的銅電鍍液其塡洞能力大約都只能達到毫米等級，無法 適用於設計規則(Design Rule)已經降到深次微米等級的積 體電路，因此提供一種具有絕佳塡洞能力的銅電鍍液就成 了積體電路製程中極需突破的一個課題。 因此’本發明之一目的就是在提供一種化學配方，可 以適用於積體電路製程中。 本發明的另一目的，就是在提供一種銅電鍍液配方， 576875 05954twf2.doc/006 修正曰期92.12.31 以使得形成於積體電路開口中的銅層具有較佳的品質且不 會產生孔洞或是縫隙。 本發明的又一目的是在提供一種銅電鍍液配方，藉著 在具有銅離子源、電解質以及界面活性劑的溶液中添加 (NH2OH)2 · H2S04，可以使銅電鍍液具有絕佳的塡洞能力。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉較佳實施例，並配合所附圖示，作詳細說明如下： 圖示之簡單說明 第1A圖至第1C圖繪示使用本發明所提供之銅電鍍液 進行銅電鍍的示意圖。 圖示標號說明： 100 :半導體基材 102 :介電層 104 :開口 106 :黏著層 108 :阻障層 110 :種子層 112 :銅層 05954twf2.doc/006 修正日期92.12.31 實施例 本發明所揭露之銅電鍍液配方中包括了銅離子源、電 解質、界面活性劑，並且添加了（NH2〇H)2 · H2S〇4以增強 其塡洞效果。其中，銅離子源比如爲CuS〇4 · 5H2◦，電解 質比如爲硫酸以及氯離子，界面活性劑則比如爲PEG (Polyethylene Glycol，M.W.=4000_8000)。而其各個成份的較 佳使用濃度則分述如下：硫酸銅大約爲60至150g/L，硫 酸大約爲80至150mL/L，氯離子大約爲50至150ppm，PEG 的濃度約爲50至200ppm，而用以增加此銅電鍍液之塡洞 效果的(ΝΗ2ΟΗ)2· H2S04其使用的濃度範圍則介於0.005至 5 g/L。 爲了更加淸楚的說明本發明所揭露的銅電鍍液之使用 方法，以下將說明進行銅電鍍的方法。 請參照第1A圖，首先提供一個半導體基材100 ’其中 此半導體基材100可以爲已經形成有半導體元件(未繪示於 圖中），或甚至是已經形成部分金屬導線結構（未繪示於圖 中）之半導體晶片。接著’於此半導體基材1〇〇上形成一層 介電層102，其中此介電層102的材質可以爲氧化物或是 其他具有介電特性的材質。之後，移除部分的介電層102， 以於介電層102中形成開口 1〇4，其中此開口 1〇4並且暴 05954twf2.doc/006 修正日期92.12.31 露半導體基材100的部分表面。此部份表面爲欲與銅導線 接觸的區域，比如爲半導體基材100中的元件或是部分的 導線接點。 請參照第1B圖，形成黏著層106覆蓋半導體基材100 與介電層102，其中黏著層106與半導體基材1〇〇及介電 層102所構成之結構共形。也就是說此黏著層106覆蓋了 開口 104的側壁及底部，同時此黏著層106也覆蓋了介電 層102的上表面。接著，形成與黏著層106共形的阻障層 108。其中，阻障層108的功能在於避免之後所形成之銅 層112(繪示於第1C圖中）擴散至介電層102中，而黏著層 106的作用則是在增進阻障層108與介電層102之間的附 著力。其中，黏著層106的材質比如爲鈦(Ti)、鉬(Ta)等與 介電層102之間附著力較強的導體，而阻障層108的材質 則可以爲氮化鈦(TiN)或氮化钽(TaN)等足以有效阻止銅質 擴散的的材質。 請參照第1C圖，形成與阻障層108共形的種子層11〇 覆蓋阻障層108,其作用在於增進電鍍時銅質沉積的效率 及品質。而阻障層108的材質可以爲銅。接著，形成銅層 112全面覆蓋半導體基材1〇〇並且塡滿開口 104。其中’形 成銅層112的方法比如爲將已經形成有種子層110的半導 05954twf2.doc/006 修正日期92.12.31 體基材100放入本發明之電鍍銅溶液中，並於溶液中造成 電流密度爲0.5至4A/dm2的條件進行電鍍。 以本發明所揭露的銅1電鍍、液配合上述的方法進行電 表产，可以將開口尺寸小且局寬比大的開口元全塡滿。如此 一來，以金屬鑲嵌技術1製作銅1導線就可以得：到與1^層元件 或導線接觸較佳、雜質較少且沒有孔、洞或縫隙的銅插塞’ 以達到製程所需的s求。 ，綜_h所述，雖然本發明已以較佳實施例揭露如上，然 其並非用以限定本發明’任何熟習此技藝者’在不脫離本 發明之精神和範圍內’當可作各種之更動與潤飾’因此本 發明之保護範圍當視後附之申請專利範圍所界定者爲準。05954twf2.doc / 006 Revised date 92.12.31 发明, description of the invention: The present invention relates to a chemical formulation used in the process of integrated circuit, and in particular to a copper plating solution formulation for forming a copper film. As the integrated circuit manufacturing process enters the deep sub-micron generation, the integration degree of the components in the integrated circuit has also increased significantly. However, in the process of increasing the accumulation, there are also some problems due to the characteristics of the components and their materials. Among them, the properties of the metal interconnects such as Resistance and Electromigration Resistivity cannot be used. Meeting the needs of deep sub-micron processes is the most urgent problem in integrated circuit manufacturing today. In the integrated circuit manufacturing process, the technology of using aluminum as a metal wire has been quite developed. However, because the resistance 材质 of aluminum itself is too large (about 2.7mQ-cm), and aluminum is easily disconnected due to electromigration, the resistance 値 is lower in deep submicron semiconductor processes. It has become a trend to replace copper with copper (about 1.7 μmΩ-cm) and better resistance to electromigration. Therefore, at present, major semiconductor manufacturing companies must invest a lot of manpower and material resources to engage in the development of copper processes. Because metallic copper is not easy to be etched, most of the metal conductors and wires in the copper process have been fabricated with Damascene technology. That is, the dielectric layer is formed first, and then the conductive conductors are exposed in the dielectric layer. The area of the wire 05954twf2.doc / 006 The date of revision 92.12.31 domain, and then a copper layer filled with openings is used as a wire and a plug. Although this technology can avoid the problem that the copper layer is not easily etched ', whether or not the openings can be completely filled without holes or seams when forming the copper layer has become the biggest challenge in the production of the copper layer. Methods that can be used to form the copper layer include Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), and Cu Electroplating. Among them, the physical and chemical vapor deposition methods are not only costly to produce the copper layer, but the copper layer formed by it will also cause the quality of the copper film to be degraded due to poor cavitation capabilities. Therefore, using copper electroplating technology to make the copper film can be said to be the best choice for forming a copper layer in the integrated circuit manufacturing process. The cavitation ability of electroplated copper is not only related to the conditions of electroplating, but the composition of the electroplating bath used is an indispensable factor. The currently available copper electroplating baths have cavitation capabilities of only about millimeters, which cannot be applied to integrated circuits whose design rule has dropped to the sub-micron level. Therefore, they provide an excellent cavitation capability. Copper electroplating solution has become a subject that needs to be broken in the integrated circuit manufacturing process. Therefore, one of the objects of the present invention is to provide a chemical formula which can be applied to the integrated circuit manufacturing process. Another object of the present invention is to provide a copper plating solution formula, 576875 05954twf2.doc / 006 amended date 92.12.31 so that the copper layer formed in the opening of the integrated circuit has better quality and does not generate holes. Or a gap. Another object of the present invention is to provide a copper electroplating bath formulation. By adding (NH2OH) 2 · H2S04 to a solution having a copper ion source, an electrolyte and a surfactant, the copper electroplating bath can have excellent cavities. ability. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following exemplifies a preferred embodiment and describes it in detail with the accompanying drawings as follows: Brief description of the drawings FIG. 1A to FIG. 1C A schematic diagram of copper plating using the copper plating solution provided by the present invention is shown. Description of icons: 100: semiconductor substrate 102: dielectric layer 104: opening 106: adhesive layer 108: barrier layer 110: seed layer 112: copper layer 05954twf2.doc / 006 Example of the invention The disclosed copper plating solution includes a copper ion source, an electrolyte, and a surfactant, and (NH2OH) 2 · H2S04 is added to enhance its cavitation effect. Among them, the copper ion source is CuS04-5H2, the electrolyte is sulfuric acid and chloride, and the surfactant is PEG (Polyethylene Glycol, M.W. = 4000_8000). The preferred concentration of each component is as follows: copper sulfate is about 60 to 150 g / L, sulfuric acid is about 80 to 150 mL / L, chloride ion is about 50 to 150 ppm, and the concentration of PEG is about 50 to 200 ppm. The concentration range of (NΗ2ΟΗ) 2 · H2S04 used to increase the pitting effect of this copper plating solution is 0.005 to 5 g / L. In order to more clearly explain the use method of the copper plating solution disclosed in the present invention, the method of performing copper plating will be described below. Please refer to FIG. 1A. First, a semiconductor substrate 100 is provided. The semiconductor substrate 100 may be a semiconductor element (not shown in the figure) already formed, or even a part of a metal wire structure (not shown in the figure). (In the figure). Next, a dielectric layer 102 is formed on the semiconductor substrate 100. The material of the dielectric layer 102 may be an oxide or other materials with dielectric properties. After that, a part of the dielectric layer 102 is removed to form an opening 104 in the dielectric layer 102, where the opening 104 is exposed to 59954twf2.doc / 006, and the revision date is 92.12.31. A part of the surface of the semiconductor substrate 100 is exposed. . This part of the surface is an area to be in contact with the copper wire, such as a component in the semiconductor substrate 100 or a part of a wire contact. Referring to FIG. 1B, an adhesive layer 106 is formed to cover the semiconductor substrate 100 and the dielectric layer 102. The structure formed by the adhesive layer 106 and the semiconductor substrate 100 and the dielectric layer 102 is conformal. In other words, the adhesive layer 106 covers the sidewall and the bottom of the opening 104, and at the same time, the adhesive layer 106 also covers the upper surface of the dielectric layer 102. Next, a barrier layer 108 conforming to the adhesive layer 106 is formed. The function of the barrier layer 108 is to prevent the copper layer 112 (shown in FIG. 1C) formed later from diffusing into the dielectric layer 102, and the role of the adhesive layer 106 is to improve the barrier layer 108 and the dielectric layer. Adhesion between the electrical layers 102. The material of the adhesive layer 106 is, for example, a conductor with strong adhesion between the titanium (Ti), molybdenum (Ta), and the dielectric layer 102, and the material of the barrier layer 108 may be titanium nitride (TiN) or Materials such as tantalum nitride (TaN) are sufficient to effectively prevent copper diffusion. Referring to FIG. 1C, a seed layer 11 conforming to the barrier layer 108 is formed to cover the barrier layer 108, and its role is to improve the efficiency and quality of copper deposition during electroplating. The material of the barrier layer 108 may be copper. Next, a copper layer 112 is formed to completely cover the semiconductor substrate 100 and fill the opening 104. The method for forming the copper layer 112 is, for example, to place the semiconductor 05954twf2.doc / 006 on which the seed layer 110 has been formed, the revision date 92.12.31. The substrate 100 is put into the electroplated copper solution of the present invention, and a current is caused in the solution. Electroplating is performed at a density of 0.5 to 4 A / dm2. With the copper 1 electroplating and liquid disclosed in the present invention combined with the above method for meter production, the openings with small opening size and large local width ratio can be fully filled. In this way, using copper inlay technology 1 to produce copper 1 wires can be obtained: copper plugs that have better contact with 1 ^ layer components or wires, less impurities, and no holes, holes or gaps, to achieve the required process s seeking. In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention to 'any person skilled in the art' without departing from the spirit and scope of the invention. Changes and Retouching 'Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.