TW575922B - Thick metal layer deposition for improving detection stability of chemical polishing process end point - Google Patents

Description

575922

V. Description of the invention (l) The technical field to which the invention belongs: The present invention relates to a method for enhancing, in particular, a pair of semi-final-point debt measurement stability formulas, and a multi-stage method for each opening in the material Chemical grinding method to avoid grinding cooking points ^ Correlation of the upper surface of the substrate after the electroplating process, i = stable ^ caused the metal layer to remain in the semiconductor. Previous technology: ^ In response to the needs of high-density circuit systems, miniaturization, Siliconization, co-frequency, integration, and compounding have become inevitable trends for the development of passive components. For example, 'the demand for global mobile phones has increased by approximately 50% per year in recent years, which has directly driven the market capacity and demand for passive components as a whole.' These components are chip resistors and chip capacitors of the size of 0.42 , Chip inductors and chip SAW filters are important passive components for high-frequency communication. Communication modules made of passive components integrated with high-frequency bipolars or transistors are hot key components. Resistance, capacitor and inductor are the three major components of passive components. The main function of inductor is to stabilize the current and remove noise. Therefore, it is used in information and consumer products, machinery, electronic distribution and suppression. Electromagnetic radiation is widely used. Due to the problem of electromagnetic radiation when electronic products are in use, all electronic products on the market must pass the electromagnetic radiation test specifications. As a result, the industry's demand for inductors is increasing. In addition, in order to cope with the thin and light functions driven by the emergence of the communications market, the application of chip inductors has become increasingly heavy.

575922 V. Description of the invention (2) Going to the outside 'and gradually replacing the traditional wire-wound inductor. The domestic inductor industry started in the late 1960s, and this traditional wire-wound inductor is a labor-intensive and technologically mature product. At the beginning, it was mainly based on home foundry and factory manufacturing. However, with the change of the times and the gradual increase of various production costs, domestic manufacturers have moved to regions with lower labor costs, which has caused the decline of traditional wound inductors. Instead, direct inductance has been replaced. A chip inductor formed in a wafer.

After statistics of the production of passive components in China over the years, it can be found that the production scale of capacitors is the largest. Judging from the output value calculated in 1999, the percentages of wafers are: resistors are 36%, capacitors are 47.8%, and inductors are 38%. However, the number of chip resistor suppliers accounts for about 10% of all resistors in the industry, the number of chip capacitor suppliers accounts for about 16% of all capacitor industries, and the number of chip inductor suppliers accounts for about all inductors. 40% of the industry is the highest proportion. From this result, it can be seen that the proportion of domestic manufacturers devoted to the production of chip inductors is increasing.

Please read the first picture, this picture reveals the manufacturing method of the chip inductor. First, an opening 12 is provided in the semiconductor substrate 10, and then a chemical plating process is performed to form a metal layer 14 on the upper surface of a portion of the semiconductor substrate 10, and filled in the opening 12. In a preferred embodiment, the depth of the opening 2 is within 3300 angstroms. Then, referring to the second figure, a CMP process is performed to remove a part of the metal layer 14 on the upper surface of the semiconductor substrate 10 to define the mosaic structure 16 in the opening pattern 12. It is worth noting that when performing the above-mentioned chemical mechanical polishing method, an optical emission spectrum analysis method using a method for detecting the end point of the polishing is used to

Page 6 ^ / jyzz. The detection of the semiconductor radio signal is a phenomenon of radio emission coming out of gold. After reaching the metal-free point detection, it should be semiconductive. The phase of the metal layer detection method is shown on the substrate. However, the original principle of the inlay body such as the semiconductor bottom layer remaining in the back is formed in the subsequent residual principle. The detection of the surface metal instrument is when the semiconductor bottom signal is ground and the semiconductor bottom structure is detected. The depth can be improved, and the semiconductor bottom grinding end point rate has increased significantly. V. Description of the invention (3) The final black that determines the grinding takes place when the light hits the reflection phenomenon. In this reverse grinding process, the semiconductor substrate is still exposed, so light will be transmitted. The procedure is currently in place, which can avoid the stable grinding end, so if you want to deepen the depth due to the structure, the layer will also become thicker and unstable5, which will cause the use of light *. When the layer is used, the light will be generated. The system will learn that the program continues until the material is transparent. When the system is used, the system stops the program. The upper surface of the material (that is, within 10,000 angstroms), and the metal detection of the upper surface of the inlaid junction material will become 0. Summary of the invention: The main purpose of the present invention is to provide an improved end point detection of the chemical grinding process. Method of stability. Another object of the present invention is to provide a method for reducing the residue of the metal layer.

Another object of the present invention is to provide a method for manufacturing a damascene structure, in particular, a multi-stage chemical plating process for openings in a semiconductor substrate is performed first. The surface metal layer is subjected to a chemical mechanical polishing method to prevent the polishing end point from being unstable and causing the metal layer to remain on the upper surface of the semiconductor substrate. '— 575922

First, the table covers the degree of coverage; the substrate is removed. Stable conductor semiconducting. A method for forming a surface uniformity. After the metal is used, the bottom surface of the substrate is detected to avoid openings with this process layer on the continuity surface. The upper end metal layer is on the semiconducting seed layer. The pre-positioned surface described above is in the surface of Qiantian body. Next, the top layer of the mechanical substrate of the chemical substrate is studied, and the thickness is set to an allowable thickness and filled with a part of the metal, in which the surface of the semi-conductive plating process, the grinding process is avoided, and the layer is stopped after the opening. The above table is in the order of the semiconductor substrate, and follows along with the electromechanical plating. The squared substrate that forms the most veneer is formed to form an opening. After the seed grinding process is performed, the structure and the opening structure are removed. When the predetermined thick surface-covered semiconductor layer is moved, it can cover half of the area. In the opening mode: The present invention discloses a method for preventing a metal layer from remaining on the upper surface of a semiconductor substrate. First, referring to the third figure, an opening 52 is formed in the semiconductor substrate 50. Wherein, the semiconductor substrate 50 may be a < 1〇〇 > 4 < m > crystalline monocrystalline or a silicon on insulator (SOI) on an insulating layer, and A seeding layer (not shown) is provided on the surface of the semiconductor substrate 50 and the opening 52. Next, a multi-stage deposition process is performed on the semiconductor substrate 50, and each stage of the deposition process includes two steps: First, a chemical plating (ECP) process is performed to form a metal layer 54 of a predetermined thickness on the semiconductor. The upper surface of the substrate 50 is covered along the surface of the opening 52, wherein, this page 8 > 75922 V. Description of the invention (5) Step 2 The semiconductor substrate 50 is placed on a chemical plating machine. 2: By connecting the seed layer's electrical property to the cathode of a power source, and filling the surface of the seed layer, and filling = reduction reaction ', to form a metal layer 54 on the crystal junction, @ "真 充 的 在 circle pattern 52. Formation of the metal layer 54. The second one is the chemical mechanical polishing (chemical mechanical polishing), which is used to remove the metal layer 54 on the semiconductor substrate 50. And to avoid the seed layer below it being removed, and the effect of electroplating of the metal layer 54 is reduced during the m-deposition process. Two more ..., the fourth to the ninth pictures, the six pictures reveal the three-stage deposition process = 、 晴 幵 y. First, as shown in the fourth figure, first perform the first chemical electricity ^ ^ "To form 4 the first metal layer 72 on the semiconductor substrate 70 and the opening surface ^ 7 π into the first chemical mechanical polishing method, remove part of the first metal layer 72 on the upper surface of the semiconductor substrate 70 to A thickness (as shown in the fifth figure, in the car and good example embodiment, this thickness is 300 to 500 angstroms, and the purpose of retaining the thickness is to protect the seed layer at ten (not shown in the figure). (Shown). Please refer to the sixth picture. After the first deposition process is completed, the plating process 4 is performed successively to form a second metal layer 74 on the surface of a portion of the first gold 3 72. Then As shown in the seventh figure, the second chemical machine: grind J sequence to remove part of this second metal layer? 4 to the same thickness as the first stage of chemical and mechanical laboratory sequence completion. Please refer to the last The eighth to the eighth figures, (2) the second electroless plating process, and the opening is filled with a third metal layer: (1) removing a part of the first metal 2 on the upper surface of the semiconductor substrate 70—the metal layer 74 and the first Three metal layers 76 to form a mosaic structure in the opening. 575922 V. Description of the invention (6) However, it is worth noting that For all the above-mentioned metal layers deposited by the chemical plating process, the predetermined thickness formed is that when the chemical mechanical polishing process is continued, the allowable thickness of the polishing end position can be stably detected, thereby effectively preventing the metal layer from remaining on the semiconductor substrate. Upper surface. In a preferred embodiment, the predetermined thickness is less than 2000 angstroms. In the present invention, a multi-stage deposition process is used to form a mosaic structure in an opening in a semiconductor substrate with the following advantages: (1) The accuracy of the end point detection of the chemical mechanical polishing can be improved; (2) The probability of the metal layer remaining on the upper surface of the semiconductor substrate is reduced; and (3) The process yield is increased. Although the present invention is explained above with a preferred example, it is not intended to limit the spirit and the inventive substance of the present invention, but only to this embodiment. Therefore, all modifications made without departing from the spirit and scope of the present invention should be included in the scope of patent application described below.

Page 575922 Brief Description of the Drawings The above description and the many advantages of this invention can be easily understood through the following detailed description combined with the attached drawings, where: The first figure is a cross-sectional view of a semiconductor wafer, showing the basis for Current industry technology: the step of forming a metal layer on the upper surface of a semiconductor substrate and filling it in the opening; the second figure is a cross-sectional view of a semiconductor wafer, showing the step of defining a mosaic pattern in the opening according to the current industry technology; the third figure is A cross-sectional view of a semiconductor wafer shows a step of forming a metal layer on the upper surface of a semiconductor substrate and filling it in an opening according to the present invention; a fourth view is a cross-sectional view of a semiconductor wafer showing the formation of an f-th metal layer according to the present invention. The step of filling the upper surface of the semiconductor substrate along the opening surface; the fifth figure is a cutaway view of the semiconductor wafer, showing the steps of the first chemical mechanical polishing process according to the present invention; the sixth figure is the cross section of the semiconductor wafer FIG. Shows a step of forming a second metal layer on the upper surface of the first metal layer according to the present invention; and FIG. A plan view showing the steps of performing the second chemical mechanical polishing process according to the present invention; the eighth view is a cross-sectional view of a semiconductor wafer showing the steps of forming a third metal layer and filling the opening according to the present invention; and the ninth view is A cross-sectional view of a semiconductor wafer, showing the steps of forming a mosaic structure in an opening according to the present invention.

Page 11 575922 The diagram briefly illustrates the semiconductor substrate 1 0 metal layer 1 4 semiconductor substrate 5 0 metal layer 5 4 first metal layer 72 third metal layer 76 opening 1 2 mosaic structure 1 6 opening 52 semiconductor substrate 70 Two metal layer 74

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Claims (1)

575922, application scope 1 twilight-a method to improve the stability of the end point detection of the chemical grinding process, which has an opening in the semi-sinking material, and the semiconductor substrate and the opening: the surface has a seed layer 'this The method includes at least the following steps: Including: performing a multi-stage deposition process, wherein each stage of the deposition sequence includes at least a. A chemical plating process is performed to form a metal screen of a predetermined thickness on the upper surface of the $ + conductor substrate, and along the The surface of the opening is covered; "the layer is on the b · chemical mechanical polishing method is performed to remove a part of the metal layer on the surface of the semi-conductive sculpture, and-straight in the center The layer is removed; the allowable thickness of the end position is detected stably; the multi-stage deposition process is stopped when the grinding process fills the opening; the part of the metal layer on the upper surface of the semiconductor substrate is removed to structure the Into the opening. Into the inlay 2 · as in the method of claim 1 of the scope of the patent application, and φ I. L. ^ ^ < H in the above-mentioned predetermined thickness / / equal to 15 0 0 0 0 Angstrom. With small 3 For example, the method of applying for the patent scope of the patent, in which any combination of the above predetermined is less than or equal to 15 0 0 angstroms. And 彳 4. A method of reducing the residue of the metal layer, wherein the semiconductor substrate has a mouth, and A seed sweat layer has been deposited on the surface of the semiconductor substrate and the open σ first. The method includes at least the following steps: 575922 6. The scope of the patent application is a multi-stage deposition process, where each stage of the deposition process includes at least: a. A chemical plating process is performed to form a metal layer having a thickness of less than or equal to 15 0 0 angstroms on the upper surface of the semiconductor substrate And cover along the opening surface; b. Performing a chemical mechanical polishing method to remove a portion of the metal layer located on the upper surface of the semiconductor substrate, and to prevent the seed layer located below it from being removed; After the opening, the multi-stage deposition process is stopped; and a portion of the metal layer on the upper surface of the semiconductor substrate is removed to form a mosaic structure in the opening. (5. The method according to item 4 of the scope of patent application, wherein the above thicknesses can be any combination of less than or equal to 15,000 angstroms. 6.-A method for making a mosaic structure, the method includes at least the following steps: A. Forming an opening in the semiconductor substrate 'and having a seed layer on the upper surface of the semiconductor substrate and the opening surface; B. performing a chemical plating process to form a metal layer of a predetermined thickness on the upper surface of the semiconductor substrate, and Cover along the surface of the opening; ie, B C. implement a chemical mechanical polishing process to remove the portion of the metal layer on the upper surface of the semiconductor substrate to a protective thickness to prevent the layer below it from being removed; D Repeating steps B and C above, wherein the electroless plating process stops after covering the upper surface of the semiconductor substrate and filling the opening; and Page 14 575922 6. Scope of patent application E. Remove a part of the metal layer on the upper surface of the semiconductor substrate to form a mosaic structure in the opening; wherein the predetermined thickness is when the chemical mechanical polishing method is subsequently performed, , Stable detection of the allowable thickness of the end position. 7. The method according to item 6 of the scope of patent application, wherein the above-mentioned predetermined thickness is 15,000 angstroms or less. 8. The method according to item 6 of the scope of patent application, wherein the predetermined thickness mentioned above can be any combination of 15,000 angstroms or less. Page 15