TW575838B - Automatic recovery method of BIOS memory circuit in memory apparatus containing dual BIOS memory circuits - Google Patents

Automatic recovery method of BIOS memory circuit in memory apparatus containing dual BIOS memory circuits Download PDF

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TW575838B
TW575838B TW89126127A TW89126127A TW575838B TW 575838 B TW575838 B TW 575838B TW 89126127 A TW89126127 A TW 89126127A TW 89126127 A TW89126127 A TW 89126127A TW 575838 B TW575838 B TW 575838B
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memory circuit
computer program
circuit
basic input
output system
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TW89126127A
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Chinese (zh)
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Huo-Yuan Lin
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Giga Byte Tech Co Ltd
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Abstract

An automatic recovery method of defective BIOS memory circuit in a computer system having memory apparatus containing dual BIOS memory circuits is disclosed in the present invention. A computer system contains a memory apparatus that includes a main BIOS memory circuit and a recovery BIOS memory circuit, which respectively store the first BIOS program and the second BIOS program for starting the operation of computer system. In addition, the main BIOS memory circuit or the safe recovery BIOS memory circuit even contains a BIOS flash utility such that, when the computer system is boosted, the chip enable circuit in the computer system first enables the recovery BIOS memory circuit and uses an error detection circuit to check and find if there is any error contained in the first BIOS program stored in the main BIOS memory circuit. If the first BIOS program stored in the main BIOS memory circuit contains error, the content of safe recovery BIOS memory circuit is used to program the main BIOS memory circuit via the BIOS flash utility. Then, the chip enable circuit disable the safe recovery BIOS memory circuit and enable the main BIOS memory circuit so as to continue the boosting procedure of computer system from main BIOS memory circuit.

Description

575838 五、發明說明(l) 發明領域 的記憶裝 回復一主 作發生錯 本案係有關於在一具有包含雙3丨0S記憶電路 置的電,系統中,以一安全回復B I 0S記憶電路來 B I OS z丨思電路,避免電腦系統的開機時的啟始運 誤而導致電腦開機失敗的結果。 發明背景 在現今電腦的架構中,所謂的基本輸入輸出系統 (ba^lc lnput〜〇utput system,BI〇s)乃是電腦基本操 中取基砧的軟體。BI〇s主要是由電腦低階的指令隼所组 yn腦運作時最基本的硬體測試、$義電腦的特性 的工作。比如:當電腦開機時,執行電腦的開 值#笼笙:銓釋鍵盤所發出的訊號,與連接埠間資訊的 、遞##。因此,電腦一開機時初始的運作, 昭 BIOS的内容來執行運作。倘若M〇s出現問題,電腦一 開機便無法執行如記憶體(RAM)、硬碟(HD)、 處理 器(CPU) #的測試,貝,j電腦便無法順利的開機。 也因為BIOS纟電腦系統具備了如此重要的地位,一 般而言我們皆會將BIOS的程式指令集燒錄在一個可以長 久不需電源的記憶體中,如Flash R〇M、pR〇M、EpR〇M、 EEPROM等,並將此類BIOS記憶體内建於電腦的主機板或放 入電腦系統的晶片組中,使其内容不受電源供應影響而可 永久保存其内容。 · 然而,B I 0S記憶體的内容卻非是完全沒有錯誤的。當 B I 0S記憶體的電路結構隨著時間而產生退化 575838 五、發明說明(2) (degradation) 或是受到不可預剛 可能會流失或產生錯誤,導致電月遂 集時產生失誤,因而導致電腦無法 職是之故,吾人乃經悉心的試 不捨的研究精神,終創造出本案之 路的記憶裝置中之BIOS記憶電路自 為本案的說明。 發明概述575838 V. Description of the invention (l) The memory device in the field of the invention restores a masterpiece error. The case is related to a system with a dual 3S0S memory circuit. In the system, a safe recovery BI 0S memory circuit is used to BI. OS z 丨 thinking circuit, to avoid computer system startup failure caused by computer startup failure. BACKGROUND OF THE INVENTION In the architecture of today's computers, the so-called basic input-output system (BA ^ lc ~ putput system, BI0s) is software for obtaining basic anvils in basic computer operations. BIOs is mainly composed of the computer's low-level instructions. The basic hardware test during the operation of the yn brain, and the characteristics of the computer. For example: when the computer is turned on, execute the on value of the computer # 笼 盛 铨: interpret the signal sent by the keyboard, and ## between the port information. Therefore, as soon as the computer starts up, the contents of the BIOS are used to perform the operation. If there is a problem with M0s, once the computer is turned on, tests such as memory (RAM), hard disk (HD), and processor (CPU) # cannot be performed, and the computer cannot be started smoothly. Because the BIOS and computer system have such an important status, generally, we will burn the BIOS program instruction set in a memory that can not need power for a long time, such as Flash ROM, pROM, EpR 〇M, EEPROM, etc., and built such BIOS memory in the computer's motherboard or into the computer system's chipset, so that its content is not affected by the power supply and can permanently save its content. · However, the contents of the B I 0S memory are not completely error-free. When the circuit structure of BI 0S memory degenerates with time 575838 V. Description of the Invention (2) (degradation) or unpredictable rigidity may be lost or cause errors, resulting in errors in the collection of electricity and the computer. The reason for the incompetence is that I have carefully studied the spirit of perseverance and finally created the BIOS memory circuit in the memory device of the road of this case. Summary of invention

本案之-曰ΑΛ» I 士, ^ 目的在於發展一自動 方法,用以在目去 ^ D 任具有一包含主BIOS 1己 BIOS記憶電路夕二l 匕 之5己憶晶片的電腦系 §己i思電路回彳I古 ^ ^ A有缺陷的主BIOS記怜 電路啟始電腦$ k 包如糸統的運作。 根據本宰m ^ , 構想,本案之自動安 的方法,乃杲少 ^ 裝置具有—第—:電腦系統中’提 輪入輸出系统;;本輸入輸出系統 路與該第二義:=電路,該第一基 腦程式與本:入輸出系統記憶The purpose of this case is to say, ΛΛ »I, ^ The purpose is to develop an automatic method for the purpose of ^ D any computer system with a main BIOS 1 BIOS memory circuit and 5 5 memory chips § Ji i Think of the circuit back to ancient times ^ ^ A defective main BIOS memory circuit starts the computer's $ k package operation. According to the concept of Benjamin m ^, the automatic safety method of this case is that the device has-the first-: the computer's' lift wheel input and output system; this input and output system and the second meaning: = circuit, The first basic brain program and the book: input and output system memory

程式係用腦程式,該第S 機時,該第该電腦系統的運作 剛該第-基:;本輸入輸出系統記 彳9 π A:本輪入輸出系統記憶電 读 # ^。若偵測該第一電 第二基本輪Λ ^ ~輸出系統記憶電路所 之操作的影響,其内容 開機執行BIOS程式指令 完成開機的程序。 驗與研究,並秉持鍥而 在一包含雙BIOS記憶電 動安全回復方法。以= 回復BIOS記憶電路的 憶電路與一安全回復 統中,以安全回復B I 〇 $ 電路,再以主BIOS記憶 全回復BIOS 供一記憶裝 記憶電路與 本輪入輪出 電路分別儲 電腦程式與 。當該電腦 憶電路被致 路所包含之 腦程式包含 铸存之第二 記憶電路 置,該記憶 一第二基本 糸統記憶電 存一第一電 該第二電腦 系統電源開 能,接著偵 第一電腦程 錯誤’以該 電腦程式再The program is a brain program. When the computer is running, the computer system operates just as the base-; this input-output system records 彳 9 π A: the current input-output system memory reads # ^. If the effect of the operation of the first electric second basic wheel Λ ^ ~ output system memory circuit is detected, its contents boot and execute the BIOS program command to complete the boot process. Examine and research, and insist on a safe recovery method that includes dual BIOS memory power. It is to restore the BIOS circuit of the BIOS memory circuit and a security recovery system to safely restore the BI 〇 $ circuit, and then use the main BIOS memory to fully restore the BIOS for a memory-mounted memory circuit and this round-in-round circuit to store computer programs and . When the computer memory circuit is set by the brain program included in the way, the memory includes a second memory circuit, the memory is a second basic system memory, the first computer power is turned on, and the second computer system A computer program error 'with the computer program again

第6頁 575838 五、發明說明(3) ^ f化邊第一基本輸人輸出 基本輪入輪出系統記憶電c電路,以回復該第一 紗根據上述構想,該第之該第-電腦程式。 二存之第—電腦程式與該第二A 輪出系统記憶電路所 儲存之該第二電腦程式可二入輪出系統記憶電路 驟,3”能該^基本輪者: 電腦系Γ u提供一晶片致能控制端的曰Μ °己k電路的步 制端i i開機時,以該晶片致能電路::致能電路’當該 之晶片;;;二基本輸入輪出系統記憶電致能控 叫來達:制端係利用--般用途輸-輪i::二述 而侦測該第一電腦程式 —錯誤偵測 =3錯誤的步驟,乃是利 ,資料值,電腦程式所包含之-錯誤 (CRcV^^[arity check)^^^^A-Tm^ ^ 、為了能夠對誃# 馨 ^化,該第—:::基本輸入輪出系統記憶電路進行再 ^輪出系統記_ +輪入輪出系統記憶電路或該$ -Ά # 再“以更=燒錄程式,:以 根據本案另—^第一基本輸入輸出系統記憶電路。 p運作的方法,::的構想,本案提出-種啟始—電腦 5亥記憶裝置係、j ^包含以下步驟:#供一記憶裝 j_______ 基本輪入輸出系統記憶電路 第7頁 575838 五、發明說明(4) .Page 6 575838 V. Description of the invention (3) ^ f The first basic input and output basic round-in-round-out system memory electrical c circuit to restore the first yarn. According to the above concept, the first-the-th computer program . The second stored—computer program and the second A round-out system memory circuit. The second computer program can be stored in the round-out system memory circuit. 3 ”can be used for the basic round: computer system Γ u provides a When the step end ii of the M ° k circuit of the chip enable control end is turned on, the chip enable circuit is enabled by the chip :: enable circuit 'when the chip is ;; two basic input wheel-out system memory electric enable control call Laida: The end system uses-general purpose input-round i :: second description to detect the first computer program-error detection = 3 error steps, it is profit, data value, computer program contains- Error (CRcV ^^ [arity check) ^^^^ A-Tm ^ ^ In order to be able to 誃 # 馨 ^, the first — ::: Basic input wheel-out system memory circuit for re- ^ out system record_ + Turn-in-round-out system memory circuit or the $ -Ά # Then "to change = programming program": In accordance with this case-^ the first basic input and output system memory circuit. The method of p operation: The conception of :: This case proposes-a kind of beginning-the computer 5H memory device system, j ^ contains the following steps: # 给 一 记忆 装 j_______ Basic wheel input and output system memory circuit page 7 575838 V. Invention Explanation (4).

與一第二基本輸入輸出系統記憶電路,該第一基本輸入輸 出系統記憶電路與該第二基本輸入輸出系統記憶電路分別 儲存一第一電腦程式與一第二電腦程式,其中該第一電腦 程式與該第二電腦程式係用以啟始該電腦系統的運作。當 該電腦糸統開機時’致能該第二基本輸入輸出糸統記憶電 路,並偵測該第一電腦程式是否包含錯誤。當偵測該第一 電腦程式包含錯誤,以該第二電腦程式再程式化該第一基 本輸入輸出系統記憶電路。接著,致能該第一基本輸入輸 出系統記憶電路而失能該第二基本輸入輸出系統記憶電 路。最後,以該第一基本輸入輸出系統記憶電路啟始該電 腦系統的運作。 根據以上構想,該第一基本輸入輸出系統記憶電路所 儲存之該弟一電腦程式與該第二基本輸入輸出糸統記憶電 路所儲存之該第二電腦程式可為相同或互異者。And a second basic input-output system memory circuit, the first basic input-output system memory circuit and the second basic input-output system memory circuit respectively store a first computer program and a second computer program, wherein the first computer program And the second computer program is used to start the operation of the computer system. When the computer system is turned on, the second basic input-output system memory circuit is enabled, and it is detected whether the first computer program contains an error. When detecting that the first computer program contains an error, the second computer program is used to reprogram the first basic input-output system memory circuit. Then, the first basic input-output system memory circuit is enabled and the second basic input-output system memory circuit is disabled. Finally, the first basic input-output system memory circuit starts the operation of the computer system. According to the above concept, the first computer program stored in the first basic input output system memory circuit and the second computer program stored in the second basic input output system memory circuit may be the same or different.

其中致能該第二基本輸入輸出系統記憶電路的步驟, 乃是以提供一晶片致能控制端的晶片致能電路,當該電腦 系統開機時,以該晶片致能電路之該晶片致能控制端致能 該第二基本輸入輸出系統電路來完成。上述之晶片致能控 制端係利用一一般用途輸入輸出接腳(G P I 0 p i η )來達成。 而偵測該第一電腦程式是否包含錯誤的步驟,乃是利 用一錯誤偵測電路來檢查該第一電腦程式所包含之一錯誤 偵測資料值,以供判斷該第一電腦程式是否包含錯誤。 上述之錯誤偵測資料值係可為一檢查總和(checksum)資’ 料值、一同位檢查(parity check)資料值或為一循環多The step of enabling the memory circuit of the second basic input output system is to provide a chip enable circuit of a chip enable control terminal. When the computer system is turned on, the chip enable control terminal of the chip enable circuit is used. The second basic input-output system circuit is enabled to complete. The aforementioned chip enable control terminal is achieved by using a general-purpose input-output pin (G P I 0 p i η). The step of detecting whether the first computer program contains an error is to use an error detection circuit to check an error detection data value included in the first computer program to determine whether the first computer program contains an error . The above-mentioned error detection data value can be a checksum data value, a parity check data value, or a cycle multiple.

第8頁 575838 五、發明說明(5) 餘檢查(CRC)資料值。Page 8 575838 V. Description of the invention (5) Remainder check (CRC) data value.

2 了能夠對該第一基本輸入輸出系統記憶電路進行再 王 > ’該第一基本輸入輸出系統記憶電路或該塗—A 輸入輸出系統記憶電路更包含一燒錄程式:;^本 " 式再程式化該第一基本輸入輸出系統記憶電路。 本水之優點與特徵,得藉由下奋之實施例的二,、 明,俾得-更深入之瞭解。 七細况 簡單圖示說明 ^立圖一為根據本案之一較佳實施例之具有包含雙B I⑽ a己fe電路的B丨〇S記憶裝置之電腦系統功能方塊圖;以及 圖二為根據本案之一較佳實施例之一電腦系統中的 βI〇s化丨思電路自動安全回復方法流程圖。 較佳貫施例說明 請參見圖一,根據本案之一較佳實施例,本案之具有 包含雙BIOS記憶電路(141,142)的61〇3記憶晶片 ς 系統10包含了 一中央處理單元^,一記憶體12,—曰,= 能電路13 ’ 一錯誤偵測電路15,以及具有雙BI〇s記Z帝2 It is possible to re-king the memory circuit of the first basic input-output system > 'The first basic input-output system memory circuit or the Tu-A input-output system memory circuit further includes a programming program: ^ 本 " Reprogramming the first basic input output system memory circuit. The advantages and characteristics of this water can be obtained through the second embodiment of the following examples, and it is clear that-a deeper understanding. Seven detailed descriptions with simple illustrations ^ Figure 1 is a functional block diagram of a computer system having a B 丨 memory device including a dual B I ⑽ a fe circuit according to a preferred embodiment of the present case; and Figure 2 is based on the present case; One preferred embodiment is a flowchart of a method for automatically responding to a beta circuit in a computer system. For a description of a preferred embodiment, please refer to FIG. 1. According to a preferred embodiment of the present invention, the system has a 6103 memory chip including dual BIOS memory circuits (141, 142). The system 10 includes a central processing unit ^, A memory 12, ie, = capable circuit 13 ', an error detection circuit 15, and a dual BIOs record Z emperor

1 4 1與1 4 2的B I 〇s記憶裝置1 4。該B I 0S記憶裝置1 4係將S B I 0S記憶e體整合在一起而成為一顆特殊用途積體電路 (ASIC)晶片,使得該電腦系統1〇 個^〇§ 該B I 0S記憶裝罟! j #达 | 1刀 而 UPR0M)或電ί 4 = 一可抹除可程式化唯讀記憶體 組成。 末除可程式化唯讀記憶體(EEPR0M)所 5亥Β I 0 S記憶步菩1 心、夏丨4所包含之兩Β丨〇s記憶電路,其一為1 4 1 and 14 2 B Ios memory device 14. The B I 0S memory device 14 integrates the S B I 0S memory e into a special-purpose integrated circuit (ASIC) chip, which makes the computer system 10 ^^ § The B I 0S memory device! j # 达 | 1 blade and UPR0M) or electric 4 = a composition of erasable and programmable read-only memory. In addition to the programmable read-only memory (EEPR0M), there are two B 丨 〇s memory circuits included in the 5 Β I 0 S memory step 1 heart, Xia 丨 4

第9頁 575838 五、發明說明(6) 主BIOS記憶電路(main BIOS memory circuit)142,另一 個為安全回復BIOS記憶電路(safe recovery BIOS memory circuit)141。主BIOS 記憶電路142與安全回復 BIOS記憶電路141所儲存的BIOS程式·可為相同的BIOS程 式’也可為相異的B I 0 S程式。而兩者所儲存的b I 〇 s程式皆 是由用以啟始電腦系統1 〇的運作之電腦程式指令集所組 成。為了要能夠在主BIOS記憶電路142所儲存的BIOS程式 被偵測包含錯誤時,能夠回復主B丨0S記憶電路丨42所儲存 的B I 0 S私式’主B I 0 S記憶電路1 4 2或安全回復b I 〇 S記憶電 路141更包含一燒錄程式(fiash utility),用以將安全回 復BIOS記憶電路141所儲存的BIOS程式再程式化主BI0S記 憶電路142,藉以回復主BI0S記憶電路142的内容。 该晶片致能電路1 3具有一晶片致能控制端j 3 1,如以 一般用途輸入輸出接腳(Gpi〇) 131來完成,用以送出 一致能訊號至主BIOS記憶電路丨42的晶片致能(CE)接腳 1421與安全回復BI0S記憶電路141的晶片致能(CE)接腳 1 4 11,來切換欲致能的b丨〇s記憶電路。 而本案之一較佳實施例之一電腦系統中的BIOS記憶電 T自動安全回復方法,可由圖二的流程圖得到充份的了 %。請爹見圖二。由步驟21開始,當電腦系統開機後(步 驟22),晶片致能電路的“1〇接腳便會使得安全回復“⑽ t己憶電路致能(步驟23)。此時,電腦的錯誤偵測電路便合 去檢查儲存於主BIOS記憶電路中的BI〇s程式是否包含錯等 (判斷式24)。而錯誤偵測的技術,可以利用檢查位於主 575838 五、發明說明(7) B I 0 S記憶電路之一^』 資料值或同位檢查(pa^ c憶位址t檢查總和(checksum) (CRC)資料值是否正確來Uh3eck)貢料值或循環多餘檢查 包含錯誤。若沒有债測到:广否主M〇Sf£憶電路的内容 誤,則晶片致能電路的GPl〇=:,^^^ 憶電路失能而使主BI0S$ ft接腳便會使安全回復61仍記 的運作#由電路致能(步驟26),電腦開機 到主BIOS Θ + t圮憶電路來繼續進行(步驟27)。若偵測 回ίΒ Ϊ: 包含錯誤,主BI〇S記憶電路或安全 =口二電ς路中所儲存的燒錄程式則會被執行,以便 Β〇=ΐΓ記憶電路所儲存的麗程式再程式化主 25 =電路’藉以回復细〇3記憶電路的内容(步驟Page 9 575838 V. Description of the invention (6) Main BIOS memory circuit 142, the other is safe recovery BIOS memory circuit 141. The BIOS programs stored in the main BIOS memory circuit 142 and the secure recovery BIOS memory circuit 141 may be the same BIOS program 'or different B I 0 S programs. The b I 0 s programs stored by both are composed of a computer program instruction set used to start the operation of the computer system 10. In order to be able to restore the main B 丨 0S memory circuit 丨 42 stored BI 0 S private 'main BI 0 S memory circuit 1 4 2 or when the BIOS program stored in the main BIOS memory circuit 142 is detected to contain errors The security recovery b I 0S memory circuit 141 further includes a flash utility for reprogramming the BIOS program stored in the security recovery BIOS memory circuit 141 to the main BIOS memory circuit 142, thereby restoring the main BIOS memory circuit 142. Content. The chip enabling circuit 13 has a chip enabling control terminal j 3 1. For example, it is completed by a general-purpose input / output pin (Gpi〇) 131, and is used to send a uniform energy signal to the main BIOS memory circuit 42. The CE (CE) pin 1421 and the chip enable (CE) pin 1 4 11 of the safety recovery BI0S memory circuit 141 are used to switch the b 丨 0s memory circuit to be enabled. However, the BIOS memory automatic automatic recovery method in a computer system, which is one of the preferred embodiments of the present case, can be fully obtained from the flowchart in FIG. 2. Please see figure two. Starting from step 21, after the computer system is turned on (step 22), the "10 pin of the chip enable circuit will make the safety reply" ⑽ the memory circuit is enabled (step 23). At this time, the computer's error detection circuit will check whether the BIOs program stored in the main BIOS memory circuit contains errors, etc. (decision 24). The error detection technology can be used to check the location of the main 575838. V. Description of the invention (7) One of the BI 0 S memory circuits ^ "data value or parity check (pa ^ c memory address t checksum) (CRC) Whether the data value is correct. Uh3eck) Tribute value or cycle redundant check contains errors. If no debt is detected: whether the content of the main M0Sf memory circuit is wrong, then the chip GP10 = :, ^^^ The memory circuit is disabled and the main BI0S $ ft pin will make a safe reply 61still the operation # is enabled by the circuit (step 26), the computer boots to the main BIOS Θ + t memory circuit to continue (step 27). If it is detected that ίΒ Ϊ: Contains an error, the burning program stored in the main BI0S memory circuit or the safety = port two electrical circuits will be executed, so that the program reprogram stored in the B0 = ΒΓ memory circuit化 主 25 = circuit 'to restore the details of the memory circuit (steps

So。:,憶電路被回復後,晶…^So. :, After the circuit is restored, Jing ... ^

記情電路腳級便处%使牛女全回復M〇S記憶電路失能而使主BI0S α心電路致此(步驟26),電腦開機的運作 憶電路來繼續進行(步W27)。石士 .卞使由主BIOS 5己 便可;: 一來,電腦的開機程序 =,利地元成,絲毫不受到主^⑽記憶電路的内 有包含錯誤的影響。 综上所述,本案將兩個…⑽記憶電路整 途積體電路USIC)晶片裡,且利用其中一個鱼主=殊用 =路分別儲f —BI〇s程式之安全回復_記憶電路來做 …田主B 10S記憶電路被偵測出錯誤時的安全回復電路,並 且將燒錄程式一併儲存於主BIOS記憶電路或安=回復bi〇1 言士己憶電路中,使得iBI0S記憶電路的内容被偵測出錯误 ^ ’執行該燒錄程式以安全回復BI0.S電路所儲存的βι^' 第11頁 575838 五、發明說明(8) 式來回復主B I 0S記憶電路的内容。如此的方法可以避免 B I 0S 程式執行時發生錯誤而導致電腦無法開機的結果, 使電腦的啟始運作得以順利繼續進行,實為一具有實用性 的商業創作。 ’ 是以,本案得由熟習此技藝之人士任施匠思而為諸般 修飾,然皆不脫如附申請專利範圍所欲保護者。The footsteps of the memory circuit caused the female to fully restore the MOS memory circuit and caused the main BI0S α heart circuit to do so (step 26). The computer starts the operation of the memory circuit to continue (step W27). Shi Shi. You can do it from the main BIOS 5 .: First, the computer's booting procedure =, Li Di Yuan Cheng, is not affected by the error contained in the main memory circuit. In summary, in this case, two ... ⑽memory circuits are integrated in the integrated circuit (IC) chip, and one of them is used to store the safety recovery of the F_BI0s program. … Tianzhu B 10S memory circuit is a safety recovery circuit when an error is detected, and the burning program is stored in the main BIOS memory circuit or Ann = Restore bi〇1 memory memory circuit, making the iBI0S memory circuit An error was detected in the content ^ 'Run this programming program to safely restore the βι ^ stored in the BI0.S circuit'. Page 11 575838 V. Description of the invention (8) Formula to restore the content of the main BI 0S memory circuit. This method can avoid the error that the B I 0S program executes and the result that the computer cannot be turned on, so that the initial operation of the computer can continue smoothly, which is a practical commercial creation. Therefore, this case may be modified by anyone who is familiar with this skill, but it is not inferior to those who want to protect the scope of the patent application.

第12頁 575838 圖式簡單說明 圖一為根據本案之一較佳實施例之具有包含雙B I OS 記憶· 電路的B I 0S記憶裝置之電腦系統功能方塊圖;以及 圖二為根據本案之一較佳實施例之一電腦系統中的B I 0S記 憶電路自動安全回復方法流程圖。Page 575838 Brief Description of Drawings Figure 1 is a functional block diagram of a computer system having a BI 0S memory device including dual BI OS memories and circuits according to a preferred embodiment of the present case; and FIG. 2 is a preferred embodiment of the present case. A flowchart of a method for automatically recovering a BI OS memory circuit in a computer system according to one embodiment.

第13頁Page 13

Claims (1)

575838 申請專利範圍 用以回復一基本輸入輸出系統 記憶電路的方法,該方法係包含下列步驟: 提供一包含一第一基本輸入輸出系統記憶電路與一第 電路的記憶裝置,該第一基本輸 第二基本輸入輸出系統記憶電路 分別儲存一第一電腦程式與一第二電腦程式,其中該第一 電腦程式與該第二電腦程式係用以啟始該電腦系統的運 作; 當該電腦糸統開機時 記憶電路; 偵測該第一電腦程式 當偵測該第一電腦程 再程式化該第一基本輸入 2 .如申請專利範圍第1項 式與該第二電腦程式係為 3. 如申請專利範圍第1項 式與該第二電腦程式係為 4. 如申請專利範圍第1項 本輸入輸出系統記憶電路 1. 種在'一電腦糸統中 二基本輸入輸出系統記憶 入輸出系統記憶電路與該 致能該拿二基本輸入輸出系統 提供一具有一晶片致 當該電腦糸統開機時 片致能控制端致能該第二 5 .如申請專利範圍第4項 制端係為 般用途輸入 是否包 式包含 輸出系 所述之 相同者 所述之 互異者 所述之 的步驟 能控制 ?以該 基本輸 所述之 輸出接 含錯誤;以及 錯誤,以該第二電腦程式 統記憶電路。 方法,其中該第一電腦程 〇 方法,其中該第一電腦程 〇 方法,其中致能該第二基 係包含下列步驟: 端的晶片致能電路;以及 晶片致能電路裝置之該晶 入輸出系統記憶電路。 方法,其中該晶片致能控 腳(G P I 0 p i η ) 〇575838 The scope of the patent application is for a method for restoring a memory circuit of a basic input-output system. The method includes the following steps: A memory device including a memory circuit of a first basic input-output system and a first circuit is provided. Two basic input-output system memory circuits respectively store a first computer program and a second computer program, wherein the first computer program and the second computer program are used to start the operation of the computer system; when the computer system is turned on Time memory circuit; detecting the first computer program and reprogramming the first basic input 2 when detecting the first computer program. If the scope of the patent application is the first formula and the second computer program is 3. If the patent is applied for The first item of the scope and the second computer program are 4. If the patent application scope of the first item is the memory circuit of the input-output system 1. It is a kind of memory system of the two basic input-output systems in the 'one computer system and the input-output system memory circuit and The enabling and taking two basic input / output system provides a chip having a chip enabling the chip enabling control terminal to enable the first when the computer system is turned on. 5. If the 4th system of the scope of the patent application is for general use, whether the input includes a package type and the output is controlled by the same steps as described by the different ones, can the steps described above be controlled? Including errors; and errors, using the second computer program to memorize the circuit. Method, wherein the first computer program method, wherein the first computer program method, wherein enabling the second base system comprises the following steps: a chip enabling circuit at the end; and the crystal input and output system of the chip enabling circuit device Memory circuit. Method, wherein the chip enables a control pin (G P I 0 p i η). 第14頁 575838 六、申請專利範圍 ’ 6. 如申請專利範圍第1項所述之方法,其中偵測該第一電 腦程式是否包含錯誤的步驟係包含下列步驟: 提供一錯誤偵測電路; 以該錯誤偵測電路檢查該第一電腦程式所包含之一錯 誤偵測資料值,以供判斷該第一電腦程式是否包含錯誤。 7. 如申請專利範圍第6項所述之方法,其中該錯誤偵測資 料值係包含一檢查總和(c h e c k s u m )資料值。 8. 如申請專利範圍第6項所述之方法,其中該錯誤偵測資 料值係包含一同位檢查(parity check)資料值。Page 14 575838 6. Scope of patent application 6. The method as described in item 1 of the scope of patent application, wherein the steps of detecting whether the first computer program contains errors include the following steps: providing an error detection circuit; The error detection circuit checks an error detection data value included in the first computer program to determine whether the first computer program contains an error. 7. The method as described in item 6 of the scope of patent application, wherein the error detection data value includes a check sum (c h e c k s u m) data value. 8. The method according to item 6 of the scope of patent application, wherein the error detection data value includes a parity check data value. 9. 如申請專利範圍第6項所述之方法,其中該錯誤偵測資 料值係包含一循環多餘檢查(CRC)資料值。 10. 如申請專利範圍第1項所述之方法,其中該第一基本 輸入輸出系統記憶電路更包含一燒錄程式,用以將該第二 電腦程式再程式化該第一基本輸入輸出系統記憶電路。 11. 如申請專利範圍第1項所述之方法,其中該第二基本 輸入輸出系統記憶電路更包含一燒錄程式,用以將該第二 電腦程式再程式化該第一基本輸入輸出系統記憶裝置。·9. The method according to item 6 of the scope of patent application, wherein the error detection data value includes a cyclic redundant check (CRC) data value. 10. The method according to item 1 of the scope of patent application, wherein the first basic input-output system memory circuit further comprises a programming program for reprogramming the second computer program to the first basic input-output system memory. Circuit. 11. The method according to item 1 of the scope of patent application, wherein the second basic input-output system memory circuit further includes a programming program for reprogramming the second computer program to the first basic input-output system memory. Device. · 12. —種用以啟始一電腦系統運作的方法,該方法係包含 下列步驟: 提供一包含一第一基本輸入輸出系統記憶電路與一第 二基本輸入輸出系統記憶電路的記憶晶片,該第一基本輸 入輸出系統記憶電路與該第二基本輸入輸出系統記憶電路 分別儲存一第一電腦程式與一第二電腦程式,其中該第一 電腦程式與該第二電腦程式係用以啟始該電腦系統的運12. A method for starting the operation of a computer system, the method includes the following steps: providing a memory chip including a first basic input output system memory circuit and a second basic input output system memory circuit, the first A basic input-output system memory circuit and the second basic input-output system memory circuit respectively store a first computer program and a second computer program, wherein the first computer program and the second computer program are used to start the computer. Systematic operation 第15頁 575838 六、申請專利範圍 作; 當該電腦系統開機時,致能該第二基本輸入輸出系統 記憶電路; 偵測該第一電腦程式是否包含錯誤; 當偵測該第一電腦程式包含錯誤,以該第二電腦程式 再程式化該第一基本輸入輸出系統記憶電路; 致能該第一基本輸入輸出系統記憶電路而失能該第二 基本輸入輸出系統記憶電路;以及 以該第一基本輸入輸出系統記憶電路啟始該電腦系統 的運作。 13. 如申請專利範圍第1 2項所述之方法,其中該第一電腦 程式與該第二電腦程式係為相同者。 14. 如申請專利範圍第1 2項所述之方法,其中該第一電腦 程式與該第二電腦程式係為互異者。 15. 如申請專利範圍第1 2項所述之方法,其中致能該第二 基本輸入輸出系統記憶電路的步驟更包含下列步驟: 提供一具有一晶片致能控制端的晶片致能電路;以及 當該電腦糸統開機時^以該晶片致能電路裝置之該晶 片致能控制端致能該第二基本輸入輸出系統記憶電路。 16. 如申請專利範圍第1 5項所述之方法,其中該晶片致能 控制端係為--般用途輸入輸出接腳(G P I 0 p i η )。 17. 如申請專利範圍第1 2項所述之方法,其中偵測該第一 電腦程式是否包含錯誤的步驟更包含下列步驟: 提供一錯誤偵測電路;Page 15 575838 6. The scope of patent application is enabled; when the computer system is turned on, the second basic input-output system memory circuit is enabled; detecting whether the first computer program contains an error; when detecting that the first computer program contains Error, reprogramming the first basic input output system memory circuit with the second computer program; enabling the first basic input output system memory circuit while disabling the second basic input output system memory circuit; and using the first The basic input output system memory circuit starts the operation of the computer system. 13. The method as described in item 12 of the scope of patent application, wherein the first computer program and the second computer program are the same. 14. The method as described in item 12 of the scope of patent application, wherein the first computer program and the second computer program are different from each other. 15. The method according to item 12 of the scope of patent application, wherein the step of enabling the memory circuit of the second basic input-output system further comprises the following steps: providing a chip enabling circuit having a chip enabling control terminal; and when When the computer system is powered on, the chip enable control terminal of the chip enable circuit device enables the second basic input output system memory circuit. 16. The method according to item 15 of the scope of patent application, wherein the chip enable control terminal is a general-purpose input / output pin (G P I 0 p i η). 17. The method according to item 12 of the scope of patent application, wherein the steps of detecting whether the first computer program contains errors further include the following steps: providing an error detection circuit; 第16頁 575838 六、申請專利範圍 以該錯誤偵測電路檢查該第一電腦程式所包含之一錯 誤偵測資料值,以供判斷該第一電腦程式是否包含錯誤。 18. 如申請專利範圍第1 7項所述之方法,其中該錯誤偵測 資料值係包含一檢查總和(c h e c k s u m )資料值。 19. 如申請專利範圍第1 7項所述之方法,其中該錯誤偵測 資料值係包含一同位檢查(p a r i t y c h e c k )資料值。 20. 如申請專利範圍第1 7項所述之方法,其中該錯誤偵測 資料值係包含一循環多餘檢查(CRC)資料值。Page 16 575838 6. Scope of patent application Use the error detection circuit to check an error detection data value included in the first computer program for judging whether the first computer program contains an error. 18. The method according to item 17 of the scope of patent application, wherein the error detection data value includes a check sum (c h e c k s u m) data value. 19. The method as described in item 17 of the scope of patent application, wherein the error detection data value includes a parity check (p a r i t y c h e c k) data value. 20. The method as described in item 17 of the scope of patent application, wherein the error detection data value includes a cyclic redundancy check (CRC) data value. 21. 如申請專利範圍第1 2項所述之方法,其中該第一基本 輸入輸出系統記憶電路更包含一燒錄程式,用以將該第二 電腦程式再程式化該第一基本輸入輸出系統記憶電路。 2 2.如申請專利範圍第1 2項所述之方法,其中該第二基本 輸入輸出系統記憶電路更包含一燒錄程式,用以將該第二 電腦程式再程式化該第一基本輸入輸出系統記憶電路。21. The method as described in item 12 of the scope of patent application, wherein the first basic input-output system memory circuit further includes a programming program for reprogramming the second computer program to the first basic input-output system. Memory circuit. 2 2. The method according to item 12 of the scope of patent application, wherein the memory circuit of the second basic input-output system further comprises a programming program for reprogramming the second computer program to the first basic input-output System memory circuit. 第17頁Page 17
TW89126127A 2000-12-07 2000-12-07 Automatic recovery method of BIOS memory circuit in memory apparatus containing dual BIOS memory circuits TW575838B (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI411959B (en) * 2008-03-21 2013-10-11 Asustek Comp Inc Computer system with dual boot-program area and method of booting the same
TWI414996B (en) * 2008-04-14 2013-11-11 Asustek Comp Inc Computer system
CN103678018A (en) * 2012-09-04 2014-03-26 联想(北京)有限公司 Method and device for recovering data
CN104932968A (en) * 2014-03-18 2015-09-23 微星科技股份有限公司 System and method for informing abnormal information in real time and eliminating abnormal state

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI411959B (en) * 2008-03-21 2013-10-11 Asustek Comp Inc Computer system with dual boot-program area and method of booting the same
TWI414996B (en) * 2008-04-14 2013-11-11 Asustek Comp Inc Computer system
CN103678018A (en) * 2012-09-04 2014-03-26 联想(北京)有限公司 Method and device for recovering data
CN104932968A (en) * 2014-03-18 2015-09-23 微星科技股份有限公司 System and method for informing abnormal information in real time and eliminating abnormal state
CN104932968B (en) * 2014-03-18 2018-07-10 微星科技股份有限公司 System and method for informing abnormal information in real time and eliminating abnormal state

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