TW573330B - A light-emitting semiconductor device with a flip-chip package structure - Google Patents

A light-emitting semiconductor device with a flip-chip package structure Download PDF

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Publication number
TW573330B
TW573330B TW91105514A TW91105514A TW573330B TW 573330 B TW573330 B TW 573330B TW 91105514 A TW91105514 A TW 91105514A TW 91105514 A TW91105514 A TW 91105514A TW 573330 B TW573330 B TW 573330B
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Taiwan
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light emitting
white light
semiconductor device
layer
item
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TW91105514A
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Chinese (zh)
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Ming-Der Lin
Kwang-Ru Wang
Chi-Tang Chuang
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Highlink Technology Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Led Devices (AREA)
  • Led Device Packages (AREA)

Description

573330573330

【發明領域】 本發明儀關於一種發光丰導體裝置, 用霜曰夕4+壯+丄裡知尤午导篮表置特別係指一锸4丨丨 用覆日日之封裝方#所製成之自光發光二極體裝置:種利 【習知 白 品。白 長色光 之白光 式來產 等優點 習 晶粒上 物質產 混合而 習知技 技術】 光發光二極體(LED)是LED產業中最被看好沾如 Φ 的混合,例如:藍色光加黃色光,可得二 \曰波人 ;或採用藍色光、綠色光與紅色光三原色混^ ^ ^ 生白光。由於白光led具省電、環保與操作"壽°^長 ,未來甚具發展潛力。 知之白光LED之發光方式主要係在封裴時,在藍色 塗佈一層YAG螢光物質,利用藍光LED照射此一1"螢光 生的黃光與藍光LED本身所發出的藍光,二者相互 得出白光;美國第5, 998, 92 5號專利案即揭露此類 術。 圖1係用以顯示在美國第5, 998, 925號專利案中,一習 知白光LED之封裝結構的示意圖。 如圖1所示,在該習知技術中,一白光發光二極體裝 置100包含一發光二極體晶粒102、一基座導線1〇5、以及 一側導線106,其中’基座導線105又分成杯形基座i〇5a與 導線105b兩部分。將發光二極體晶粒1〇2安裝在杯形基座 105a之凹處中後’再對杯形基座105a填充一含有特定螢光 劑(phosphor)之樹脂層101,如此,即可將發光二極體晶[Field of the invention] The present invention relates to a light-emitting conductor device, which is made of Frost eve 4 + Zhuang + Bali Zhiyou lunch basket table, especially refers to a 4 丨 丨 made by the encapsulating party ## Self-Light Emitting Diode Device: Kind of Lee [Xi Bai Bai Pin. White long-color light, white light production, and other advantages. Learn the technology of mixing materials on the grain. Known technology] Light-emitting diodes (LEDs) are the most promising mix in the LED industry, such as blue light and yellow Light, you can get two \ Yebo people; or use the three primary colors of blue light, green light and red light mixed ^ ^ ^ white light. Because white light LEDs have power saving, environmental protection, and longevity, they have great potential for development in the future. The light-emitting method of the known white LED is mainly when coating a layer of YAG fluorescent material in blue, and using this blue LED to illuminate the yellow light generated by the fluorescent light and the blue light emitted by the blue LED itself. White light; US Patent No. 5,998, 92 5 discloses such a technique. FIG. 1 is a schematic diagram showing a conventional white LED packaging structure in US Pat. No. 5,998,925. As shown in FIG. 1, in the conventional technology, a white light emitting diode device 100 includes a light emitting diode die 102, a pedestal lead 105, and a side lead 106. 105 is further divided into a cup-shaped base 105a and a lead 105b. After the light emitting diode crystal 102 is installed in the recess of the cup-shaped base 105a, the cup-shaped base 105a is filled with a resin layer 101 containing a specific phosphor, so that the Light emitting diode

第7頁 573330 五、發明說明(2) 粒1 0 2模鑄於樹脂層1 〇 1之中。然後,發光二極體晶粒 102之正電極與負電極(未顯示)則以焊線103分別連接至基 座導線105與侧導線1〇6,最後,發光二極體晶粒1〇2、以 及部分之基座導線105與側導線1〇6則會進一步被包覆在一 具保護作用之塑模材料1 〇4中。Page 7 573330 V. Description of the invention (2) The pellets 102 are molded in the resin layer 101. Then, the positive electrode and the negative electrode (not shown) of the light-emitting diode die 102 are connected to the base lead 105 and the side lead 106 by bonding wires 103, respectively. Finally, the light-emitting diode die 102, And part of the base wire 105 and the side wire 106 are further coated in a protective molding material 104.

在操作上述白光發光二極體裝置1〇〇時,由發光二極 體晶粒102發出之部分光線會激發包含在樹脂層1〇1中之 營光劑而產生與發光二極體晶粒1 〇2所發出光線不同波長 之光。因此,當發光二極體晶粒1 〇 2所發出之光線和螢光 劑受到藍光二極體激發所產生的混合光一起射出發光二極 體裝置1 0 0外時,此由兩不同波長所構成之混合光即形成 人眼可視的白光。 圖2係用以顯示習知發光二極體晶粒1 〇 2結構之示意 圖。 習知之發光二極體晶粒102可如圖2所示,其係一種以 氮化録(GaN)為主之發光二極體。在圖2中,發光二極體 20 0包含一藍寶石(sapphire)基板2〇1與一層狀結構,該層 狀結構至少包含一沉積在藍寶石基板2〇1上之n型氮化鎵半 導體層202、以及沉積其上之p型氮化鎵半導體層2〇3。然 後’利用蝕刻方式形成一N型氮化鎵半導體裸露表面2〇6, _ 其上並設有一N型電極205 ;在P型氮化鎵半導體層2〇3之表 面上則形成有一透明電極204 ;接著在透明電極2〇4上定義 出一P型電極區域(未顯示)’使該區域裸露出p型氮化鎵半 導體層,並於該區域之P型氮化鎵半導體層2〇3上形成p型When the above-mentioned white light emitting diode device 100 is operated, part of the light emitted by the light emitting diode crystal grains 102 will excite the light-emitting agent contained in the resin layer 101 to generate and emit light emitting diode crystal grains 1 〇2 light of different wavelengths. Therefore, when the light emitted by the light-emitting diode grains 102 and the mixed light generated by the fluorescent agent excited by the blue light-emitting diode are emitted out of the light-emitting diode device 100 together, this is caused by two different wavelengths. The composed mixed light forms white light visible to the human eye. Fig. 2 is a schematic diagram showing the structure of a conventional light emitting diode crystal 102. A conventional light emitting diode crystal grain 102 can be shown in FIG. 2, which is a kind of light emitting diode mainly composed of nitride (GaN). In FIG. 2, the light emitting diode 200 includes a sapphire substrate 201 and a layered structure. The layered structure includes at least one n-type gallium nitride semiconductor layer deposited on the sapphire substrate 201. 202, and a p-type gallium nitride semiconductor layer 203 deposited thereon. Then, an N-type gallium nitride semiconductor bare surface 206 is formed by etching, and an N-type electrode 205 is provided thereon; a transparent electrode 204 is formed on the surface of the P-type gallium nitride semiconductor layer 203. ; Next, a P-type electrode region (not shown) is defined on the transparent electrode 204, so that the region exposes the p-type gallium nitride semiconductor layer on the P-type gallium nitride semiconductor layer 203 in the region. P-type

573330 五、發明說明(3) 電極2 07,並使其與透明電極204形成電性連接,如此即完 成整個習知發光二極體晶粒的製程。 上述之傳統的白光發光半導體裝置1〇〇雖可有效地產 生白光,然而,卻存在一些截至目前為止,在製程上或結 構上仍然無法克服的問題。 一·如圖2所示,白光發光二極體裝置1〇〇所產生之光 線必須經過透明電極204透射出去,此電極雖因厚度極薄 而具有一定之透光率,然而實際上為使電極與其下之半導 體層間具有良好的歐姆接觸,其厚度一般皆無法做到極 薄,因此,造成發光二極體200所產生之光仍有一部份會 受到透明電極2 0 4之阻擋或吸收。 曰 二.如圖1所示,發光二極體晶粒1〇2所發出的光於 穿過混合有螢光劑之樹脂層101時會有所衰減,這些原因 會減弱發光二極體裝置100的輸出亮度; 一 一三·白光發光二極體裝置100所發出的白光,係由發 ,二極體晶粒1 0 2所發出之光線與樹脂層丨〇 i中之螢光劑 受激而產生之光線的混合光,因此要混合出恰當的白光, 除了需要控制好塗佈之樹脂層101的厚度,並且得控制好 每次特定螢光劑(phosphor)在樹脂層101中的混合比例, 這在大量生產時,是一個滿大的挑戰。 口 四·利用習知技術製成的白光led b , 右要檢驗其所發 出的光線是否為所設定的白光時,通常得等到完成整個 裝製程以後才能做檢驗,如此二來,即使可以檢驗出發先 波長不合所需的白光LED,可是已經無法再做其它補救"的573330 V. Description of the invention (3) Electrode 20 07 and make it electrically connected with the transparent electrode 204, so as to complete the whole process of the conventional light-emitting diode grains. Although the above-mentioned conventional white light emitting semiconductor device 100 can effectively generate white light, there are still some problems that cannot be overcome in terms of process or structure so far. 1. As shown in Figure 2, the light generated by the white light emitting diode device 100 must be transmitted through the transparent electrode 204. Although this electrode has a certain light transmittance due to its extremely thin thickness, it is actually used to make the electrode There is a good ohmic contact with the underlying semiconductor layer, and its thickness is generally not extremely thin. Therefore, a part of the light generated by the light emitting diode 200 will be blocked or absorbed by the transparent electrode 204. Said two. As shown in FIG. 1, the light emitted by the light-emitting diode crystal grains 102 will attenuate when passing through the resin layer 101 mixed with a fluorescent agent. These reasons will weaken the light-emitting diode device 100. The output brightness of the white light emitting diode device 100 is caused by the light emitted by the diode crystal 102 and the fluorescent agent in the resin layer. The mixed light of the generated light should be mixed to produce appropriate white light. In addition to controlling the thickness of the coated resin layer 101 and controlling the mixing ratio of a specific phosphor in the resin layer 101 each time, This is a big challenge in mass production. Mouth 4. White light led b made by the conventional technology. When you want to check whether the light emitted is the set white light, you usually have to wait until the entire assembly process is completed before you can do the inspection. White LEDs with different wavelengths are required first, but other remedies are no longer available

第9頁 573330 五、發明說明(4) 製程;這樣的特性,你媒 裝檢驗,在大量製造時ί類LED經常只能進行事後的封 驗,而形成材料=的因為無法做到即時的檢 m 5 # ^/袓的/良費,尤有甚者,事後檢驗的結 所有產品。心,很可能就會損失一整個製造批號相同的 -極ί ·奘ίΛΓ:面所述的缺點以夕卜,由於傳統的白光發光 C例如·雙波長混合型的ώ 曰i 的白先發光二極體,即利用藍色光 所』生=&忠、Γ1所發出的波長,與藍光照射到螢光粉後 昭射ί丨罄古I混0而成白光。由於利用短波長的藍光, 而激發出長波長的黃光,基本上是能量轉換 主但是這種型式的能量轉換(短波長藍光轉 ΐΐΐΐ '光)效率,很難達到百分之百。根據能量 寸疋的觀念,無法百分之百轉換的部份能量便會透過 熱能的方式釋放出來,而且傳統的白光發光二極體裝置 (如美國第5,998,925號與5,962,97 1專利案),由於晶粒都 是密封在透明(指相對於發光波段為透明)的材料中(例 如:樹脂(resin or epoxy)或聚醯亞胺(p〇lyimide)), 熱量極難透過適當的管道排散到外界;而且,大多數的白 光發光二極體裝置,螢光粉多是置於封裝材料中,而且離 發光二極體晶粒的上表面很近,這樣的結構使得晶粒離熱 源(螢光粉層;因能量轉換不完全而產生的熱)很近,而且 也因發光二極體晶粒的主動層離上表面很近,當熱量在晶· 片上表面累積到某種程度時,會使得白光發光二極體裝置 573330 五、發明說明(5) 變得不穩定·,同時,也間接影響到白光發光二極體裝置的 操作壽命。 【發明概要】 本發明之目的即在改善上述之缺點,並針對上述習知 之白光發光二極體裝置,提出一具有熱阻絕性能優異(利 用藍寶石基板阻絕晶粒和榮光層間的熱傳)、散熱佳、亮 度高、製造良率高、以及製造成本低廉之等優點的白光發 光半導體裝置,該裝置之特色在於·· 一、 採用覆晶(flip chip)之方式來進行白光發光半 導體之固晶製程。 二、 於晶粒的製造過程中採用精密塗佈製程,嚴密控 制塗佈樹脂層的厚度與特定螢光劑(phosph〇r )在樹脂層中 的混合比例。 二、採用整片式檢測方式(wafer - level probing)做 線上的即時檢驗,以減少不良的發生與快速的分類;此種 方式,即使遇到不良的產品,也可做到即時的補救 (on-time rework processing)。 四、利用藍寶石基板導熱不良的特性,做為隔絕晶粒 與螢光層之間的熱傳導,避免傳統白光發光二極體裝置, 因為熱所導致的元件可靠度不佳與壽命過短的問題。 , 本發明之具有覆晶(flip chip)封裝結構之白光發光 半導體裝置,包含:一封裝基被、局部覆蓋於該封裝基板 表面之一第一絕緣層、以覆晶之方式連接至該封裝基板之Page 9 573330 V. Description of the invention (4) Manufacturing process; With such characteristics, when you inspect the media, in the case of mass manufacturing, LEDs can often only be tested afterwards, and the material is formed because it is impossible to perform instant inspection. m 5 # ^ / 袓 / good fee, especially if all products are inspected after the fact. Heart, it is likely to lose a whole manufacturing batch with the same lot number-pole ί · 奘 ίΛΓ: the disadvantages described above are due to the traditional white light emission C, such as the dual-wavelength hybrid type of white first luminescence II The polar body, that is, the wavelength emitted by "blue light" and "Zhong, Γ1", is irradiated with blue light and fluoresces into white powder. The use of short-wavelength blue light to excite long-wavelength yellow light is basically energy conversion. However, this type of energy conversion (short-wavelength blue light to light) efficiency is difficult to reach 100%. According to the concept of energy scale, part of the energy that cannot be converted 100% will be released through thermal energy, and traditional white light-emitting diode devices (such as US Patent Nos. 5,998,925 and 5,962,97 1), due to crystal grains All are sealed in transparent (referring to transparent light-emitting band) materials (such as resin or epoxy or polyimide), and it is extremely difficult to dissipate heat to the outside through appropriate pipes; Moreover, in most white light emitting diode devices, the phosphor is mostly placed in the packaging material and is close to the upper surface of the light emitting diode grains. This structure makes the grains away from the heat source (the phosphor layer). ; Heat due to incomplete energy conversion) is very close, and also because the active layer of the light-emitting diode grains is close to the upper surface, when heat is accumulated to a certain extent on the upper surface of the crystal, the white light will emit light Diode device 573330 5. Description of the invention (5) becomes unstable. At the same time, it also indirectly affects the operating life of the white light emitting diode device. [Summary of the Invention] The purpose of the present invention is to improve the above-mentioned shortcomings, and in view of the conventional white light emitting diode device described above, to propose an excellent thermal insulation performance (the sapphire substrate is used to block the heat transfer between the crystal grain and the glory layer), and the heat dissipation White light emitting semiconductor device with the advantages of good, high brightness, high manufacturing yield, and low manufacturing cost. The characteristics of this device are: 1. Using a flip chip method to perform the solid-state crystal manufacturing process of white light emitting semiconductors. . 2. In the manufacturing process of the crystal grains, a precise coating process is used to closely control the thickness of the coating resin layer and the mixing ratio of the specific phosphor (phosphor) in the resin layer. Second, the use of wafer-level probing method (wafer-level probing) for online real-time inspection to reduce the occurrence of bad and rapid classification; this way, even if you encounter bad products, you can achieve immediate remedy (on -time rework processing). Fourth, use the sapphire substrate's poor thermal conductivity to isolate the heat conduction between the crystal grains and the fluorescent layer to avoid the traditional white light emitting diode device, because of the poor reliability and short life of the components caused by heat. The white light emitting semiconductor device with a flip chip package structure according to the present invention includes: a package base, a first insulating layer partially covering a surface of the package substrate, and connected to the package substrate in a flip-chip manner. Of

第11頁 573330 五、發明說明(6)Page 11 573330 V. Description of the invention (6)

一發$二極體’及塗佈於該發光二極體之基板底部表面之 螢光層’其中’此發光二極體包含·· 一基板、形成於該 基板之表面之一第一型態半導體層、形成於該第一型態半 導體層之部分表面之一第一電極、形成於該第一型態半導 體層之表面,,但不會覆蓋該第一電極之一主動層、形成於 該^動層表面之一第二型態半導體層,以及形成於該第二 型態半導體層之表面之一第二電極。此白光發光半導體裝 置更包含位於該第一絕緣層上之一第一焊接隆起部、位於 ,封裝基板未覆蓋該第一絕緣層之區域之一第二焊接隆起 4 ’以及位於該第一焊接隆起部與該第二焊接隆起部間之 成凸塊狀之一第二絕緣層。其中,此發光二極體係透過該 ,電極與該第一焊接隆起部之連接、該第二電極與該第 =焊接隆起部之連接,而接合至該封裝基板之上,且該第 —絕緣層係用以間隔該第一電極與該第二電極。 【實施例】 、 參見圖3a及圖4,圖3a為本發明第1實施例之白光發光 半導體裝置之橫剖面圖,圖4則為本發明第}實施例之白光 發光半導體裝置之俯視圖。 如圖3a所示,根據本發明之較佳實施例,一具有覆晶 封襄結構之白光發光半導體裝置3〇〇包含一封裝基板3〇1以 及一發光二極體302。其中,封裝基板3〇1係一導電之 石夕基板’其上並形成有一二氧化矽之絕緣層3 〇 3。類似於 圖2之發光二極體200,可產生藍光之發光二極體3〇2包含 有一藍寶石基板304、沉積在藍寶石基板3〇4上之N型氮化Yifa $ diode 'and a fluorescent layer coated on the bottom surface of the substrate of the light-emitting diode', where 'This light-emitting diode includes a first form of a substrate formed on the surface of the substrate A semiconductor layer, a first electrode formed on a part of the surface of the first type semiconductor layer, and a surface of the first type semiconductor layer, but an active layer that does not cover the first electrode is formed on the semiconductor layer A second type semiconductor layer on the surface of the movable layer, and a second electrode formed on the surface of the second type semiconductor layer. The white light emitting semiconductor device further includes a first solder bump on the first insulation layer, a second solder bump 4 ′ located on an area of the package substrate that does not cover the first insulation layer, and the first solder bump. A second insulating layer formed in a bump shape between the portion and the second solder bump portion. Wherein, the light-emitting diode system passes through the connection between the electrode and the first solder bump, the connection between the second electrode and the first solder bump, and is bonded to the package substrate, and the first insulating layer It is used to separate the first electrode from the second electrode. [Embodiment] Referring to FIG. 3a and FIG. 4, FIG. 3a is a cross-sectional view of a white light emitting semiconductor device according to the first embodiment of the present invention, and FIG. 4 is a top view of the white light emitting semiconductor device according to the} th embodiment of the present invention. As shown in FIG. 3a, according to a preferred embodiment of the present invention, a white light emitting semiconductor device 300 having a flip-chip encapsulation structure includes a package substrate 300 and a light emitting diode 302. Among them, the package substrate 3101 is a conductive Shixi substrate 'and an insulating layer 3 of silicon dioxide is formed thereon. Similar to the light-emitting diode 200 of FIG. 2, the blue-emitting light-emitting diode 302 includes a sapphire substrate 304 and N-type nitride deposited on the sapphire substrate 304.

573330573330

鎵半導體層305、沉積在N型氮化鎵半導體層3〇5上之主動 層306、以及一沉積在主動層3〇6上之p型氮化鎵半導體層 307。其中,主動層306之作用係用以發光,而N型氮化^ 半導體層305與P型氮化鎵半導體層3〇7之化學組成係為一 四元素半導體InxAlyGai_x_yN,且莫耳分數x、y須滿足〇 $ 1、0 Sy S 1、與x + y = l之條件。主動層之材料亦為一四 元素半導體InxAlyGa^yN,且莫耳分數x、y須滿足〇 ‘ 1、0 S 1、與x + y = l之條件。此外,絕緣層3〇3之材料可 代之以氧化石夕(SiOx)、氮化石夕(SiNx)、氧化銘(ai2〇3)、二 氧化鈦(Ti02)、氧化鈕(Ta2 05 )、 23 TEOS(Tetra-Ethyl-Ortho-Silicate)、環氧樹脂 (epoxy)、與聚醯亞胺(polyimide)其中之一。 在本發明之實施例中,藍寶石基板304之上係先配置 一層N型氮化鎵半導體層305及主動層3〇6,然後再於其上 配置一層P型氮化鎵半導體層307。但是,亦可於藍、寶石基 板3 04上,先沉積一層p型氮化鎵半導體層,然後再依序沉 積主動層與N型氮化鎵半導體層;此時,封裝基板3〇1則 用P型矽基板。 類似於圖2之發光二極體200,本實施例之發光二極體 302在N型氮化鎵半導體層305上形成有一電極3〇8,在?型 氮化鎵半導體層307上則形成有一透明電極3〇9,且透明電 極309上並設有一導電反射層314。同時,電極3〇8與透明 電極之間係設置一聚醯亞胺絕緣層3丨5。 本發明之最大特色在於螢光層313係塗佈於發光二極A gallium semiconductor layer 305, an active layer 306 deposited on the N-type gallium nitride semiconductor layer 305, and a p-type gallium nitride semiconductor layer 307 deposited on the active layer 306. Among them, the function of the active layer 306 is to emit light, and the chemical composition of the N-type nitride semiconductor layer 305 and the P-type gallium nitride semiconductor layer 307 is a four-element semiconductor InxAlyGai_x_yN, and the Mohr fractions x, y The conditions of $ 0, 0 Sy S 1, and x + y = l must be met. The material of the active layer is also a four-element semiconductor InxAlyGa ^ yN, and the Mohr fractions x and y must satisfy the conditions of 0 ′ 1, 0 S 1, and x + y = l. In addition, the material of the insulating layer 303 can be replaced by SiOx, SiNx, ai203, titanium dioxide (Ti02), oxide button (Ta2 05), 23 TEOS ( Tetra-Ethyl-Ortho-Silicate), epoxy, and polyimide. In the embodiment of the present invention, an N-type gallium nitride semiconductor layer 305 and an active layer 306 are disposed on the sapphire substrate 304, and then a P-type gallium nitride semiconductor layer 307 is disposed thereon. However, it is also possible to deposit a p-type gallium nitride semiconductor layer on the blue and sapphire substrate 300, and then sequentially deposit an active layer and an n-type gallium nitride semiconductor layer; at this time, the packaging substrate 300 is used P-type silicon substrate. Similar to the light-emitting diode 200 of FIG. 2, the light-emitting diode 302 of this embodiment has an electrode 3 08 formed on the N-type gallium nitride semiconductor layer 305. A transparent electrode 309 is formed on the type GaN semiconductor layer 307, and a conductive reflective layer 314 is provided on the transparent electrode 309. At the same time, a polyimide insulation layer 3 丨 5 is arranged between the electrode 308 and the transparent electrode. The biggest feature of the present invention is that the fluorescent layer 313 is coated on the light emitting diode

573330 五、發明說明(8) -- 體302之藍寶石基板3〇4的底表面上,依據不同顏色的發光 二極體晶粒與激發螢光粉後所產生的色光混合成白光。與 習知白光發光二極體裝置相比較,其具有下列幾項優點Y (1)螢光層313所產生的熱,可以有效地為藍寶石基板所 隔絕。在習知技術中,螢光層313係設置於晶粒上方,由 於封裝材料(例如:res in或epoxy)和晶粒表層(例如: bonding pad和TCL)的熱膨脹係數不同,於白光發光二極 體裝置的操作過程中所產生的熱,極易於晶粒上方產生應 力’加以晶粒表面又離主動層很近,所以極易影響到元件 整體的穩定性與操作壽命。本發明之設計則可避免此一缺 點;(2 )具有背面出光的特性。本發明將可避免如習知 白光發光二極體裝置使用正面出光之方式,而產生陰影的 問題。 上述發光二極體302係以覆晶(flip chip)之封裝方式 設置在封裝基板301之上,且係透過二焊接隆起部(solder bump)310與311使發光二極體302接合於封裝基板3 01上。 其接合方式係先將焊接隆起部31 〇與311分別設置在封裝基 板301上,再將電極3〇8與焊接隆起部310、以及導電反射 層314與焊接隆起部311相焊接而使發光二極體302固定於 封裝基板3 01上;絕緣層303上並設有一與焊接隆起部310 相連接之焊墊312,以使電極308能導通於外部電源;同 時,電極308與透明電極之間係設置一聚醯亞胺絕緣層 315,其目的係用以避免因為採‘用覆晶(fl ip chip)封裝方 式,而造成元件表面漏電流過大、電極短路與定位不良的573330 V. Description of the invention (8)-On the bottom surface of the sapphire substrate 304 of the body 302, light-emitting diode crystals of different colors are mixed with colored light generated after the phosphor is excited into white light. Compared with the conventional white light emitting diode device, it has the following advantages Y (1) The heat generated by the fluorescent layer 313 can be effectively isolated from the sapphire substrate. In the conventional technology, the fluorescent layer 313 is disposed above the die. Due to the different thermal expansion coefficients of the packaging material (such as resin or epoxy) and the die surface layer (such as bonding pad and TCL), it is used for white light emitting diodes. The heat generated during the operation of the bulk device is very easy to generate stress above the crystal grains, and the surface of the crystal grains is very close to the active layer, so it can easily affect the overall stability and operating life of the device. The design of the present invention can avoid this disadvantage; (2) It has the characteristics of back light emission. The present invention can avoid the problem of shadows caused by the conventional method of using white light emitting diode devices to emit light from the front. The light-emitting diode 302 is provided on the package substrate 301 in a flip chip package, and the light-emitting diode 302 is bonded to the package substrate 3 through two solder bumps 310 and 311. 01 on. The bonding method is to firstly mount the solder bumps 31 o and 311 on the package substrate 301, and then solder the electrode 308 to the solder bump 310 and the conductive reflective layer 314 to the solder bump 311 to make the light-emitting diodes. The body 302 is fixed on the packaging substrate 301; the insulation layer 303 is provided with a solder pad 312 connected to the solder bump 310 so that the electrode 308 can be connected to an external power source; at the same time, an electrode 308 is disposed between the transparent electrode A polyimide insulation layer 315 is used to avoid the excessive leakage current on the surface of the component, the short circuit of the electrode and the poor positioning due to the use of fl ip chip packaging.

573330 五、發明說明(9) 問題。 根據上述之結構,發光二極體302之電極3G8可透過焊 接隆起部310與焊墊312而外接至一負電極’而透明電極 309則透過焊接隆起部311而導通於可導電之封裝基板 301,進而外接至一正電極,故相較於傳統封裝製程皆需 要兩道正負電極之打線製程,本實施例之一大優點即在於 可省去傳統封裝製程中之焊線製程。 此外,如前所述,本發明之另一優點是具有較佳的亮 度,相較於圖1所示之發光二極體晶粒102,發光二極體 302所發出之光並不會受到電極3〇8、透明電極3〇9、以及 焊塾312等之吸收或阻擋,此係因其於主動層3〇6所產生之 光線可朝上出射於藍寶石基板3〇4,而藍寶石基板3〇4則具 有極佳的透光率,因此,其所產生之大部分光線皆能有效 地出射於藍寶石基板3〇4,故可獲致極佳的亮度。除此之 外,如圖3a所示,尚可在透明電極3〇9之上形成上述之導 電反射層314,其可選用金、鋁、鎳、鈦、銀、鉻、鉑等 金屬材料或氧化辞(Zn0)、二氧化錫(511〇2)、鎘錫氧化物 (CTO)/銦辞氧化物(IZ〇)、氧化鎳(Ni〇)、氧化鎘、 氧化物(CdSn2〇4)、銦鎘氧化物(Cd2Sn〇4)、鋅錫氧化物 丁 = 辞氧化物(GZ〇)、铭辞氧化物(AZ0)、氮化欽 # \ ®氧化物(IT〇)等介電材料,配合發光元件的出 此Ϊ恰當的材料,以單層、多層或混合多層的方 ί發光波段的高反射層。其作用即在於有效地, 反射從主動層3〇6朝封裝基板301所發出之光線, 些573330 V. Description of Invention (9) Problem. According to the above structure, the electrode 3G8 of the light-emitting diode 302 can be connected to a negative electrode through the solder bump 310 and the solder pad 312, and the transparent electrode 309 can be conducted to the conductive packaging substrate 301 through the solder bump 311. Furthermore, it is externally connected to a positive electrode. Therefore, compared with the conventional packaging process, a wire bonding process of two positive and negative electrodes is required. One of the great advantages of this embodiment is that the wire bonding process in the traditional packaging process can be omitted. In addition, as mentioned above, another advantage of the present invention is that it has better brightness. Compared with the light-emitting diode grains 102 shown in FIG. 1, the light emitted by the light-emitting diode 302 is not affected by the electrode. The absorption or blocking of 308, the transparent electrode 309, and the solder pad 312, etc., is because the light generated by the active layer 306 can be emitted upward from the sapphire substrate 300, and the sapphire substrate 30. 4 has excellent light transmittance. Therefore, most of the light generated by it can be effectively emitted from the sapphire substrate 304, so it can obtain excellent brightness. In addition, as shown in FIG. 3a, the above-mentioned conductive reflective layer 314 can also be formed on the transparent electrode 309, which can be selected from metal materials such as gold, aluminum, nickel, titanium, silver, chromium, platinum, or an oxide. (Zn0), tin dioxide (511〇2), cadmium tin oxide (CTO) / indium oxide (IZ〇), nickel oxide (Ni〇), cadmium oxide, oxide (CdSn204), indium Dielectric materials such as cadmium oxide (Cd2Sn〇4), zinc tin oxide, butadiene oxide (GZ〇), inscription oxide (AZ0), nitride # \ ® oxide (IT〇), etc. The appropriate material for the component is a highly reflective layer with a single-layer, multi-layer, or mixed-multi-layer square-band emission band. Its role is to effectively reflect the light emitted from the active layer 306 towards the package substrate 301.

ΗΙΙΙΗί 第15頁 573330 五、發明說明(ίο) 光線朝藍寳石基板304反射,如此更可增進白光發光半導 體裝置3 0 0之輸出亮度。 根據上述之實施例,本發明之另一優點是散熱性佳, 此係因為上述諸如以矽製成之封裝基板3〇1本身即具有極 佳的散熱性,所以發光二極體3〇2於操作中所產生之熱量 即可透過焊接隆起部31〇與311而導熱於封裝基板3 〇1,所 以,白光發光半導體裝置300之耐熱性與操作壽命即可大 為增進。 參見圖5,其係用以說明本發明第1實施例之白光發光 半導體裝置之一製程剖面示意圖。本發明另一優點即為螢 光層之塗佈較諸習知裝置之製程,將可節省較多的螢光劑 ^料與製程時間。如圖5所示,連續排列之複數個白光發 光=導體裝置300可同時進行螢光層313之塗佈,因而可大 ,卽省製程所耗費的時間,使得白光發光半導體裝置3〇〇 =有利於大量製造。而且,在進行塗佈時,並可用遮罩 4〇〇遮住各發光二極體,裝置3〇〇之焊墊部位,因為這些部位 豐本即會遮住發光二極體3〇2所產生之光,所以其實並不 =塗佈螢光劑,&此,更可節省製程中所耗費的螢光劑 县’更重要的’這樣的製造方式,極可能是目前所知可 以最均勻塗佈螢光材料的方法。 參見圖3b, 導體裝置之橫剖 圖中顯示本發明第2實施例之白光發光半 面圖。 3 2 0。如圖儿所不,此發光二極體30 2之一側面係為一斜面 如此’由主動層306所發出之光線在出射於發光二極 573330 五、發明說明(π) 體302側面時較不容易於斜面320產生全反射,亦即,盡可 能讓這些光線可以相當容易地從發光二極體3 0 2之側面透 射出去。同時,其封裝基板可具有一梯形截面,且其可為 一透光基板。 此外,由於本發明之最上層係發光二極體之基板,該 基板通常皆為不導電之材料所製成,如上述實施例中所使 用之藍寶石基板304 ’所以’其相較於習知裝置尚具有靜 電放電(ESD)之防護作用。 圖3 c係用以顯示本發明之第3實施例之白光發光半導 體裝置之橫剖面圖。 如圖3c所示,本發明之第3實施例極類似於前述之第i 實施例’其中’ 一具有覆晶封裝結構之白光發光半導體裝 置500包含一封裝基板501以及一發光二極體502。其中, 封裝基板501係一導電之N型石夕基板,其上並形成有一二氧 化石夕之絕緣層503。類似於圖2之發光二極體2〇〇,發光二 極體502包含有一藍寶石基板5〇4、沉積在藍寶石基板5〇4 上之N型氮化鎵半導體層5〇5、沉積在n型氮化鎵半導體層 5 0 5上之主動層506、以及一沉積在主動層506上之p型氮化 鎵半導體層507。發光二極體502 在N型氮化鎵半導體層5〇5 上形成有一 N型電極5 08,在p型氮化鎵半導體層5〇7上則形 成有一 P型電極5 09,而且,在藍寶石基板5〇4底表面上並 塗佈有一螢光層513。 曰與第1實施例及第2實施例相同,發光二極體5 〇 2係以, 覆晶之封裝方式設置在封裝基板5〇1之上,其接合方式則ΗΙΙΙΗί Page 15 573330 V. Description of the invention (ίο) The light is reflected toward the sapphire substrate 304, which can further improve the output brightness of the white light emitting semiconductor device 300. According to the above-mentioned embodiment, another advantage of the present invention is that the heat dissipation is good. This is because the package substrate 301 made of silicon, for example, has excellent heat dissipation, so the light emitting diode 302 is The heat generated during the operation can be conducted to the package substrate 3 001 through the solder bumps 31 and 311, so the heat resistance and operating life of the white light emitting semiconductor device 300 can be greatly improved. Referring to FIG. 5, it is a schematic cross-sectional view illustrating a process of a white light emitting semiconductor device according to a first embodiment of the present invention. Another advantage of the present invention is that the coating of the fluorescent layer can save more fluorescent materials and processing time than the manufacturing processes of conventional devices. As shown in FIG. 5, a plurality of white light emitting diodes arranged in a row = the conductor device 300 can simultaneously coat the fluorescent layer 313, so that it can be large and save time in the manufacturing process, making the white light emitting semiconductor device 300 = favorable For mass production. In addition, during coating, a mask 400 can be used to cover each light-emitting diode, and the pad portion of the device 300 can be installed, because these parts will be covered by the light-emitting diode 300. Light, so it is not actually = coating the fluorescent agent, & this can save the fluorescent agent used in the manufacturing process, and the "more important" manufacturing method is probably the most uniform coating known so far. Method for distributing fluorescent materials. Referring to Fig. 3b, a cross-sectional view of a conductor device shows a white light emitting half view of a second embodiment of the present invention. 3 2 0. As shown in the figure, one side of the light-emitting diode 302 is an inclined plane, so that the light emitted by the active layer 306 is emitted from the light-emitting diode 573330. 5. The invention (π) side of the body 302 is less It is easy to generate total reflection on the inclined surface 320, that is, to make these lights transmit as easily as possible from the side of the light emitting diode 320. At the same time, the package substrate may have a trapezoidal cross-section, and it may be a light-transmitting substrate. In addition, since the uppermost layer of the present invention is a substrate of a light-emitting diode, the substrate is usually made of a non-conductive material, such as the sapphire substrate 304 used in the above embodiment, so it is compared with conventional devices. Still has the protective function of electrostatic discharge (ESD). Fig. 3c is a cross-sectional view showing a white light emitting semiconductor device according to a third embodiment of the present invention. As shown in FIG. 3c, the third embodiment of the present invention is very similar to the i-th embodiment described above, wherein a white light emitting semiconductor device 500 with a flip-chip packaging structure includes a packaging substrate 501 and a light emitting diode 502. Among them, the package substrate 501 is a conductive N-type stone substrate, and an insulating layer 503 of silicon dioxide is formed thereon. Similar to the light-emitting diode 200 of FIG. 2, the light-emitting diode 502 includes a sapphire substrate 504, an N-type gallium nitride semiconductor layer 505 deposited on the sapphire substrate 504, and an n-type. An active layer 506 on the gallium nitride semiconductor layer 505 and a p-type gallium nitride semiconductor layer 507 deposited on the active layer 506. The light-emitting diode 502 has an N-type electrode 508 formed on the N-type gallium nitride semiconductor layer 505, and a P-type electrode 509 is formed on the p-type gallium nitride semiconductor layer 507. A fluorescent layer 513 is coated on the bottom surface of the substrate 504. In the same way as in the first embodiment and the second embodiment, the light emitting diode 502 is mounted on the package substrate 501 with a flip-chip packaging method, and the bonding method is

573330573330

係透過二焊接隆起部(s〇lder bump)510與511來達成。亦 即’P型電極509係與焊接隆起部511相接合而固定在封袭 基板501上,絕緣層503上則設有一與焊接隆起部51〇相連 接之焊墊512,並將N型電極5 08與焊接隆起部510相接合而 固定在封裝基板501上。 本實施例與第1實施例之差別僅在於其P型電極5 〇 9並 不需要為一透明電極,且在P型氮化鎵半導體層5〇7上亦不 具有如第1實施例中之導電反射層3 1 4,故相較第1實施例 中之透明電極309,P型電極509之厚度可較大,以獲致較 佳的歐姆接觸特性。 以上藉由實施例所做之描述,係為方便說明本發明之 内容,而非將本發明狹義地限制於該實施例。凡未背離本 發明之精神所做之任何變更,皆屬本發明申請專利之範 圍0This is achieved through two solder bumps 510 and 511. That is, the 'P-type electrode 509 is bonded to the solder bump 511 and fixed on the sealing substrate 501. The insulating layer 503 is provided with a solder pad 512 connected to the solder bump 51, and the N-type electrode 5 08 is bonded to the solder bump 510 and fixed on the package substrate 501. The difference between this embodiment and the first embodiment is only that the P-type electrode 509 does not need to be a transparent electrode, and the P-type gallium nitride semiconductor layer 507 does not have the same as that in the first embodiment. The conductive reflective layer 3 1 4 has a thicker P-type electrode 509 than the transparent electrode 309 in the first embodiment, so as to obtain better ohmic contact characteristics. The descriptions made by the embodiments above are for the convenience of explaining the content of the present invention, rather than limiting the present invention to the embodiment in a narrow sense. Any changes that do not depart from the spirit of the present invention are within the scope of the present invention.

第18頁 573330 圖式簡單說明 圖1為一習知之白光發光二極體封裝結構之示意圖。 圖2為一習知發光二極體晶粒1〇2結構之示意圖。 圖3a為本發明之第1實施例之白光發光半導體裝置之 橫剖面圖。 圖3b為本發明第2實施例之白光發光半導體裝置之橫 剖面圖。 圖3 c為本發明第3實施例之白光發光半導體裝置之横 剖面圖。 圖4為本發明第1實施例之白光發光半導體裝置之俯視 圖。 圖5為本發明第1實施例之白光發光半導體裝置之製程 剖面示意圖。 【圖式編號】 100〜白光發光二極體裝置 1 0 1〜樹脂層 1 0 2〜發光二極體 1 0 3〜焊線 104〜塑模材料 105〜基座導線 1 0 5a〜基座 105b〜導線 106〜侧導線 - 200〜發光二極體Page 18 573330 Brief description of drawings Figure 1 is a schematic diagram of a conventional white light emitting diode package structure. FIG. 2 is a schematic diagram of a conventional light emitting diode crystal structure 102. FIG. Fig. 3a is a cross-sectional view of a white light emitting semiconductor device according to a first embodiment of the present invention. Fig. 3b is a cross-sectional view of a white light emitting semiconductor device according to a second embodiment of the present invention. Fig. 3c is a cross-sectional view of a white light emitting semiconductor device according to a third embodiment of the present invention. Fig. 4 is a plan view of the white light emitting semiconductor device according to the first embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a manufacturing process of the white light emitting semiconductor device according to the first embodiment of the present invention. [Figure number] 100 ~ white light emitting diode device 1 0 1 ~ resin layer 1 0 2 ~ light emitting diode 1 0 3 ~ bonding wire 104 ~ mold material 105 ~ base wire 1 0 5a ~ base 105b ~ Lead 106 ~ Side lead-200 ~ Light emitting diode

第19頁 573330 圖式簡單說明 2 0 1〜藍寶石基板 202〜N型氮化鎵半導體層 203〜P型氮化鎵半導體層 204〜透明電極 205〜N型電極 20 6〜半導體裸露表面 20 7〜P型電極 30 0〜白光發光半導體裝置 301〜封裝基板 302〜發光二極體 3 0 3〜絕緣層 304〜藍寶石基板 30 5〜N型氮化鎵半導體層 3 0 6〜主動層 30 7〜P型氮化鎵半導體層 3 0 8〜電極 309〜透明電極 31 0〜焊接隆起部 3 11〜焊接隆起部 312〜焊墊 313〜螢光層 314〜導電反射層 315〜聚醯亞胺層 320〜斜面Page 19 573330 Schematic description 2 0 1 ~ Sapphire substrate 202 ~ N-type GaN semiconductor layer 203 ~ P-type GaN semiconductor layer 204 ~ Transparent electrode 205 ~ N-type electrode 20 6 ~ Semiconductor bare surface 20 7 ~ P-type electrode 30 0 to white light emitting semiconductor device 301 to package substrate 302 to light emitting diode 3 0 3 to insulating layer 304 to sapphire substrate 30 5 to N-type gallium nitride semiconductor layer 3 0 6 to active layer 30 7 to P Type gallium nitride semiconductor layer 3 0 8 to electrode 309 to transparent electrode 31 0 to solder bump 3 11 to solder bump 312 to pad 313 to fluorescent layer 314 to conductive reflective layer 315 to polyimide layer 320 to Bevel

第20頁 573330 圖式簡單說明 4 0 0〜遮罩 50 0〜白光發光半導體裝置 501〜封裝基板 50 2〜發光二極體 5 0 3〜絕緣層 504〜藍寶石基板 50 5〜N型氮化鎵半導體層 5 0 6〜主動層 507〜P型氮化鎵半導體層 508〜N型電極 50 9〜P型電極 51 0〜焊接隆起部 51卜焊接隆起部 512〜焊墊 513〜螢光層P.20 573330 Brief description of the drawings 4 0 0 to mask 50 0 to white light emitting semiconductor device 501 to package substrate 50 2 to light emitting diode 5 0 3 to insulating layer 504 to sapphire substrate 50 5 to N-type gallium nitride Semiconductor layer 5 0 6 to active layer 507 to P-type gallium nitride semiconductor layer 508 to N-type electrode 50 9 to P-type electrode 51 0 to solder bump 51 b solder bump 512 to pad 513 to fluorescent layer

第21頁Page 21

Claims (1)

573330 六、申請專利範圍 — * ^ w一種具有覆晶(flip chiP)封裝結構之白光發光半導體. 罝’其包含: ~封裝基板; :第一絕緣層,係局部覆蓋於該封裝基板表面; 包冬.發光二極體,係以覆晶之方式連接至該封裝基板,· 一基板; 一第 _ _ 型 態 半 導 體 層 , 係 形 成 於 該 基 板之 表 面 J 分表面; ~第 電 極 5 係 形 成 於 該 第 — 型 態 半 導體層 之 部 面,伯Τ 一主 動 層 9 係 形 成 於 該 第 一 型 態 半 導 體層 之 表 m不 會覆 蓋 該 第 一 電 極 及 一第 二 型 態 半 導 體 層 5 係 形 成 於 該 主 動層 表 面 9 面; 一第 二 電 極 9 係 形 成 於 該 第 二 型 態 半 導體 層 之 表 =第—焊接隆起部,位於該第一絕緣層之上;573330 VI. Scope of patent application-* ^ w A white light emitting semiconductor with flip-chip packaging structure. 罝 'It includes: ~ package substrate;: a first insulation layer, which partially covers the surface of the package substrate; Winter. The light-emitting diode is connected to the package substrate in a flip-chip manner, a substrate; a _ _ type semiconductor layer is formed on the surface of the surface of the substrate; and the fifth electrode is formed on A part of the first type semiconductor layer, an active layer 9 is formed on the surface of the first type semiconductor layer, and the first electrode and a second type semiconductor layer 5 are not formed on the surface. The surface of the active layer has 9 faces; a second electrode 9 is formed on the surface of the second type semiconductor layer = the first solder bump, and is located on the first insulating layer; 緣層:ί二焊接隆起部,位於該封裝基板^覆蓋該第 、區域; 隆起部2 一絕緣層,位於該第一焊接隆起部與該第二焊接 二^間’且呈凸塊狀;及 上;一螢光層,係塗佈於該發光二極體之基板底部表面Edge layer: two solder bumps are located on the package substrate and cover the first and second regions; bump 2 is an insulating layer located between the first solder bump and the second solder bump and is in the shape of a bump; and On; a fluorescent layer is coated on the bottom surface of the substrate of the light emitting diode 第22頁 573330Page 573 330 其中,該發光二極體係透過該第一電極與該第一焊接隆起 部之連接、該第二電極與該第二焊揍埠之連接,而接合至 該封裝基板之上,且利用該第二絕緣層間隔該第_ ^與 該第二電極。 … 2.如申請專利範圍第1項之白光發光半導體裝置,其中., 該封裝基板係一導電基板。 3·如申請專利範圍第2項之白光發光半導體裝置,其中, 該封裝基板係一 N型矽基板。 八 4·如申請專利範圍第2項之白光發光半導體裝置,其中, 該封裝基板係一 P型矽基板。 〃 5·如申請專利範圍第1項之白光發光半導體裝置,其中, 該封裝基板係一陶瓷基板。 6·如申請專利範圍第1項之白光發光半導體裝置,其中, 遠發光二極體之基板係一藍寶石基板。 7. 如申請專利範圍第1項之白光發光半導體裝置,其中, 該發光一極體具有一呈斜面之一側面。 8. 如申請專利範圍第1項之白光發光半導體裝置,其中, 該封裝基板具有一梯形剖面且為一透光基板。 9·如申請專利範圍第1項之白光發光半導體裝置,其中, 該第一絕緣層之材料係為二氧化矽(si〇2) '氧化石夕 (SiOx)、氮化矽(SiNx)、氧化鋁(A 1 203)、二氧化鈦 (Ti02)、氧化鈕(Ta205)、 TEOS(Tetra-Ethy卜Ortho-Silicate)、環氧樹脂(ep〇Xy) 或聚醢亞胺(poly imide)其中之一。Wherein, the light-emitting diode system is connected to the packaging substrate through the connection between the first electrode and the first solder bump, and the connection between the second electrode and the second solder bump, and the second substrate is used. The insulating layer is spaced from the first electrode and the second electrode. … 2. The white light emitting semiconductor device according to item 1 of the scope of patent application, wherein the packaging substrate is a conductive substrate. 3. The white light emitting semiconductor device according to item 2 of the patent application scope, wherein the package substrate is an N-type silicon substrate. 8. The white light emitting semiconductor device according to item 2 of the patent application scope, wherein the package substrate is a P-type silicon substrate. · 5. The white light emitting semiconductor device according to item 1 of the patent application scope, wherein the package substrate is a ceramic substrate. 6. The white light emitting semiconductor device according to item 1 of the application, wherein the substrate of the far-emitting diode is a sapphire substrate. 7. The white light-emitting semiconductor device according to item 1 of the patent application scope, wherein the light-emitting polar body has a side surface with an inclined surface. 8. The white light emitting semiconductor device according to item 1 of the application, wherein the package substrate has a trapezoidal cross section and is a light-transmitting substrate. 9. The white light emitting semiconductor device according to item 1 of the scope of patent application, wherein the material of the first insulating layer is silicon dioxide (SiO2), silicon oxide (SiOx), silicon nitride (SiNx), oxide One of aluminum (A 1 203), titanium dioxide (Ti02), oxide button (Ta205), TEOS (Tetra-Ethy or Ortho-Silicate), epoxy resin (epoxy), or polyimide. 第23頁 573330 六、申請專利範圍 10·如申請專利範圍第1項之白光發光半導體裝置,其中, 該第二絕緣層之材料係為聚醯亞胺(P 01 y i m i d e )。 11·如申請專利範圍第1項之白光發光半導體裝置,其 中,該發光二極體更具有一導電反射層,其係形成於該第 二電極之上且具有反射光線之效果。 12.如申請專利範圍第11項之白光發光半導體裝置,其 中’該第二電極係一透明電極。 13·如申請專利範圍第11項之白光發光半導體裝置,其 中’該導電反射層之材料係為金、鋁、鎳、鈦、銀、鉻或 始其中之一。 14·如申請專利範圍第11項之白光發光半導體裝置,其 中,該導電反射層之材料係為氧化鋅(Zn〇)、二氧化錫 (Sn〇2)、鎘錫氧化物(CT〇)、銦鋅氧化物(lz〇)、氧化鎳 5 = 、氧化鎘(cd〇)、錫鎘氧化物(CdSn2〇4)、銦鎘氧化物 (二Sn04)、鋅錫氧化物(Zn2Sn〇4)、鎵鋅氧化物(gz〇)、鋁 一化物(AZ0)、氮化鈦(TiN)或銦錫氧化物(ιτ〇)其中之 1中5 專利範圍第11項之白光發光半導體裝置 “Π;!射層之材料係利用金m銀、鉻 踢氧;匕物(CT0、以及:氧化辞(Zn〇)、:氧化錫(Sn〇2)、鎘 鋅氧化物(Iz。)、氧化鎳(刚)’氧化 (AZOf Λ4鎵鋅氧花物⑽)、鋁鋅氧化物 (_、亂化鈦(TiN)或銦錫氧化物(ιτ〇)其中之一形成多Page 23 573330 6. Scope of patent application 10. The white light-emitting semiconductor device according to item 1 of the patent scope, wherein the material of the second insulating layer is polyimide (P 01 y i m i d e). 11. The white light emitting semiconductor device according to item 1 of the application, wherein the light emitting diode further has a conductive reflective layer formed on the second electrode and having an effect of reflecting light. 12. The white light emitting semiconductor device according to item 11 of the application, wherein 'the second electrode is a transparent electrode. 13. The white light emitting semiconductor device according to item 11 of the application, wherein the material of the conductive reflective layer is gold, aluminum, nickel, titanium, silver, chromium, or one of them. 14. The white light emitting semiconductor device according to item 11 of the application, wherein the material of the conductive reflective layer is zinc oxide (Zn〇), tin dioxide (Sn〇2), cadmium tin oxide (CT〇), Indium zinc oxide (lz〇), nickel oxide 5 =, cadmium oxide (cd〇), tin cadmium oxide (CdSn204), indium cadmium oxide (di Sn04), zinc tin oxide (Zn2Sn〇4), Gallium zinc oxide (gz〇), aluminum monolith (AZ0), titanium nitride (TiN), or indium tin oxide (ιτ〇) 1 of 5 5 of the patent scope of the white light emitting semiconductor device "Π ;! The material of the radiation layer uses gold, silver, and chromium to kick oxygen; darts (CT0, and: oxide (Zn〇) ;: tin oxide (Sn〇2); cadmium zinc oxide (Iz.); Nickel oxide (rigid ) 'Oxidation (AZOf Λ4 gallium zinc oxide flower ⑽), aluminum zinc oxide (_, disordered titanium (TiN) or indium tin oxide (ιτ〇) 第24頁 573330 六、申請專利範圍 層之堆疊構造。 16·如申請專利範圍第1項之白光發光半導體裝置,其 中,該第:型態半導體層與該第二型態半導體層之成分係 一四兀素半導體1nxAlyGa卜"N,且莫耳分數X、y須滿足〇 $ 、與 x + y = l 之條件。 17·如申请專利範圍第16項之白光發光半導體裝置,其 中,該第一型態半導體層為一N型氮化鎵半導體層,該第 二半導體層為一P型氮化鎵半導體層。Page 24 573330 6. Scope of patent application Stacked structure of layers. 16. The white light emitting semiconductor device according to item 1 of the scope of the patent application, wherein the composition of the first type semiconductor layer and the second type semiconductor layer is a four element semiconductor 1nxAlyGab " N, and the mole fraction X and y must satisfy the conditions of 0 $ and x + y = l. 17. The white light emitting semiconductor device according to item 16 of the application, wherein the first type semiconductor layer is an N-type gallium nitride semiconductor layer, and the second semiconductor layer is a P-type gallium nitride semiconductor layer. 18·如申請專利範圍第16項之白光發光半導體裝置,其 中’該第一型態半導體層為一p型氮化鎵半導體層,該第 二半導體層為一N型氮化鎵半導體層。 19. 一種形成具有覆晶(flip chip)封裝結構之白光發光 半導體裝置之方法,包含下列步驟: 局部覆蓋一第一絕緣層於一封裝基板之上; 形成一發光二極體,此發光二極體包含: 一基板; 一第一型態半導體層,係形成於該基板之表面; 一第一電極,係形成於該第一型態半導體層之表 一主動層,係形成於該第一型態半導體層之表 面、但不致覆蓋該第一電極; 一第二型態半導體層,係形成於該主動層表面; 及 ‘ 一第二電極,係形成於該第二型態半導體層表18. The white light emitting semiconductor device according to item 16 of the application, wherein 'the first type semiconductor layer is a p-type gallium nitride semiconductor layer, and the second semiconductor layer is an N-type gallium nitride semiconductor layer. 19. A method for forming a white light emitting semiconductor device with a flip chip package structure, comprising the following steps: partially covering a first insulating layer on a package substrate; forming a light emitting diode, the light emitting diode The body includes: a substrate; a first type semiconductor layer formed on the surface of the substrate; a first electrode formed on the surface of the first type semiconductor layer; an active layer formed on the first type; A second type semiconductor layer is formed on the surface of the active layer; and a second electrode is formed on the surface of the second type semiconductor layer 第25頁 573330Page 573 330 於該第一絕緣層之上形成一第一焊接隆起部; 於該封裝基板上未覆蓋該第一絕緣層之區 二焊接隆起部,· 成一第 於該第一焊接隆起部與該第二焊接隆起部 - 凸塊狀之第二絕緣層; 风成 將該發光二極體以該第一電極連接至該第一焊接隆起 部,該第二電極連接至該第二焊接隆起部之方式,接合至 該封裝基板之該第一絕緣層上,其中,該第二絕緣層係用 以間隔該第一電極與該第二電極;以及 於該發光二極體之基板底部表面上塗佈一螢光層。 20·如申請專利範圍第19項之白光發光半導體裝置之形成 方法,其中,該封裝基板係一導電基板。 21·如申請專利範圍第20項之白光發光半導體裝置之形成 方法,其中,該封裝基板係一N型矽基板。 22·如申請專利範圍第2〇項之白光發光半導體裝置之形成 方法,其中,該封裝基板係一P型矽基板。 23·如申請專利範圍第19項之白光發光半導體裝置之形成 方法’其中,該封裝基板係一陶瓷基板。 24·如申請專利範圍第19項之白光發光半導體裝置之形成 方法,其中,該發光二極體之基板係一藍寶石基板。 25·如申請專利範圍第19項之白光發光半導體裝置之形成 方法,其中,該發光二極體係具有呈斜面之一侧面。 26·如申請專利範圍第19項之白光發光半導體裝置之形成Forming a first solder bump on the first insulating layer; forming a second solder bump on the package substrate that is not covered by the first insulating layer; forming a first solder bump on the first solder bump with the second solder Bulge-a second insulating layer in the shape of a bump; Fengcheng joins the light-emitting diode in such a manner that the first electrode is connected to the first soldered bump, and the second electrode is connected to the second soldered bump. To the first insulating layer of the packaging substrate, wherein the second insulating layer is used to separate the first electrode from the second electrode; and coating a fluorescent light on the bottom surface of the substrate of the light emitting diode Floor. 20. The method for forming a white light emitting semiconductor device according to item 19 of the application, wherein the package substrate is a conductive substrate. 21. The method for forming a white light emitting semiconductor device according to item 20 of the application, wherein the package substrate is an N-type silicon substrate. 22. The method for forming a white light emitting semiconductor device according to item 20 of the application, wherein the package substrate is a P-type silicon substrate. 23. The method for forming a white light emitting semiconductor device according to item 19 of the application, wherein the package substrate is a ceramic substrate. 24. The method for forming a white light emitting semiconductor device according to item 19 of the application, wherein the substrate of the light emitting diode is a sapphire substrate. 25. The method for forming a white light emitting semiconductor device according to item 19 of the application, wherein the light emitting diode system has a side surface having an inclined surface. 26. Formation of white light emitting semiconductor devices such as the scope of application for item 19 573330 六、申請專利範圍 方法,其中,該封裝基板具有一梯形剖面且為一透光基 板。 2 7 ·如申請專利範圍第1 9項之白光發光半導體裝置之形成 方法,其中,該苐一絕緣層之材料係為二氧化梦(S i 〇 2 )、 氧化梦(SiOx)、氮化矽(SiNx)、氧化鋁(A12〇3)、二氧化 鈦(Ti〇2)、氧化鈕(Ta205)、 TE0S(Tetra-Ethyl-Ortho-Silicate)、環氧樹脂(epoxy) 或聚醯亞胺(polyimide)其中之一。 28·如申請專利範圍第19項之白光發光半導體裝置之形成 方法其中,該第一絕緣層之材料係為聚酿亞胺 (polyimide) 〇 29·、如申請專利範圍第19項之白光發光半導體裝置之形成 方法,其中,該發光二極體更具有一導電反射層,其係形 成於該第二電極之上且具有反射光線之效果。 30·如申請專利範圍第29項之白光發光半導體裝置之形成 方法,其中,該第二電極係一透明電極。 31·如申請專利範圍第29項之白光發光半導體裝置之形成 方法,其中,該導電反射層之材料係為金、鋁、鎳、鈦、 銀、絡或翻其中之一。 32.如申明專利範圍第29項之白光發光半導體裝置之形成 方法’其中,該導電反射層之材料係為氧化鋅(Zn〇)、二 氧化錫(Sn〇2)、鎘錫氧化物(CT〇)、銦鋅氧化物(ιζ〇)、氧 化鎳(Nl())、氧化録(Cd〇)、錫鎬氧化物(CdSn2〇4)、銦鎘氧. 化物(Cd2Sn04)、鋅錫氧化物(Zn2Sn〇4)、鎵辞氧化物573330 6. Method for applying for a patent, wherein the package substrate has a trapezoidal cross section and is a light-transmitting substrate. 27. The method for forming a white light-emitting semiconductor device according to item 19 of the scope of the patent application, wherein the material of the first insulating layer is dream dioxide (SiO 2), dream oxide (SiOx), silicon nitride (SiNx), aluminum oxide (A12〇3), titanium dioxide (Ti〇2), oxide button (Ta205), TEOS (Tetra-Ethyl-Ortho-Silicate), epoxy resin or polyimide one of them. 28. The method for forming a white light emitting semiconductor device according to item 19 of the patent application, wherein the material of the first insulating layer is polyimide. 29. The white light emitting semiconductor according to item 19 of the patent application. The device forming method, wherein the light emitting diode further has a conductive reflective layer formed on the second electrode and having an effect of reflecting light. 30. The method for forming a white light emitting semiconductor device according to item 29 of the application, wherein the second electrode is a transparent electrode. 31. The method for forming a white light emitting semiconductor device according to item 29 of the application, wherein the material of the conductive reflective layer is one of gold, aluminum, nickel, titanium, silver, copper, or aluminum. 32. The method for forming a white light emitting semiconductor device according to claim 29 of the patent scope, wherein the material of the conductive reflective layer is zinc oxide (Zn〇), tin dioxide (Sn〇2), cadmium tin oxide (CT 〇), indium zinc oxide (ιζ〇), nickel oxide (Nl ()), oxidation log (Cd〇), tin pick oxide (CdSn204), indium cadmium oxide (Cd2Sn04), zinc tin oxide (Zn2Sn〇4), gallium oxide 573330 六、申請專利範圚 * —___ (GZ0)、麵鋅氧 ^ (ΙΤ0)其中之一。物()、乳化鈦(ΠΝ)或銦錫氧化物 33·如申清專利範第gg項 方法,其中,該導電反射層之2光發光半導體裝置之形成 欽、銀、鉻或鉑豆φ 一 7、枒料係利用金、鋁、鎳、_ 錫(Sn02)、鎘锡氧化物(c 二 ' 乳化 (NiO)、氧化鎘(Cd0)、錫糕 > 銦鋅虱化物(IZ0)、氧化鎳 (Cd SnO ) }锡知乳化物(CdSn204 )、銦鎘氧化物 j ^ 、錫氧化物(Zn2Sn〇4)、鎵鋅氧化物(GZ0)、鋁 鋅乳化物(AZ0)、氮化鈦(TiN)或銦錫氧化物(ΙΤ0)其中之 一形成多層之堆疊構造。 、 34·如申請專利範圍第19項之白光發光半導體裝置之形成 方法’其中,該第一型態半導體層與該第二型態 之成分係-四元素半導體InxAlyGai_x,yN,且莫耳分== 須滿足〇 Sx 、〇 Sy 、與x + y=l之條件。 35·、如申請專利範圍第34項之白光發光半導體裝置之形成 方法其中該第一型態半導體層為一N型氮化鎵半導體 層’該第二半導體層為一 p型氮化鎵半導體層。 如Γΐ專利範圍第34項之白光發光半導曰體裝置之形成 法,/、 ·該第一型態半導體層為一 Ρ型氮化鎵半導體 曰’該第二半導體層為一 Ν型氮化鎵半導體層。573330 VI. One of the patent application scopes * — ___ (GZ0) and zinc zinc oxide (ΙΤ0). Material (), emulsified titanium (ΠN) or indium tin oxide 33. As described in the method of item gg of the Shen Qing patent, wherein the light-emitting semiconductor device of the conductive reflective layer is formed of silver, silver, chromium or platinum 7. The material is made of gold, aluminum, nickel, tin (Sn02), cadmium tin oxide (c di'emulsification (NiO), cadmium oxide (Cd0), tin cake> Indium zinc lice (IZ0), oxidation Nickel (Cd SnO)} Tin Emulsion (CdSn204), Indium Cadmium Oxide j ^, Tin Oxide (Zn2Sn〇4), Gallium Zinc Oxide (GZ0), Aluminum Zinc Emulsion (AZ0), Titanium Nitride ( TiN) or indium tin oxide (ITO) to form a multilayer stack structure. 34. The method for forming a white light emitting semiconductor device according to item 19 of the patent application 'wherein the first type semiconductor layer and the first type semiconductor layer Type II composition system-four-element semiconductor InxAlyGai_x, yN, and Morse = = must meet the conditions of 0Sx, 0Sy, and x + y = 1. 35. White light emission such as the 34th in the scope of patent application Method for forming a semiconductor device, wherein the first type semiconductor layer is an N-type gallium nitride semiconductor layer The conductor layer is a p-type gallium nitride semiconductor layer. For example, a method for forming a white light emitting semiconductor device in the 34th patent scope of the Γΐ patent, /, The first type semiconductor layer is a p-type gallium nitride semiconductor. 'The second semiconductor layer is an N-type gallium nitride semiconductor layer.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI449201B (en) * 2004-04-07 2014-08-11 Gelcore Llc High reflectivity p-contact for ingan leds
US9559265B2 (en) 2014-03-21 2017-01-31 Mao Bang Electronic Co., Ltd. Flip-chip LED, method for manufacturing the same and flip-chip package of the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI449201B (en) * 2004-04-07 2014-08-11 Gelcore Llc High reflectivity p-contact for ingan leds
US9559265B2 (en) 2014-03-21 2017-01-31 Mao Bang Electronic Co., Ltd. Flip-chip LED, method for manufacturing the same and flip-chip package of the same

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