TW571183B - Address decoding device - Google Patents

Abstract

An address decoding device is suitable for addressing a word line based on a first address signal, a second address signal and an internal clock signal, which includes: a pre-decoding circuit for receiving the first address signal, and decoding the first address signal as a global address signal; a reset circuit for receiving the internal clock signal and outputting a reset signal when the clock cycle of the internal clock signal ends; a global address latching circuit coupled to the reset circuit for latching the global address signal and outputting a first latching signal based on the internal clock signal, and resetting the first latching signal when receiving the reset signal; a global decoding circuit coupled to the global address latching circuit for decoding the first latching signal as a global word line address signal; a local address latching circuit coupled to the reset signal for latching the second address signal and outputting a second latching signal, and resetting the second latching signal when receiving the reset signal; and a local decoding circuit coupled to the global decoding circuit and the local address latching circuit for outputting a word line address signal to the word line based on the first latching circuit and the second latching signal.

Description

571183 V. Description of the invention (1) The invention of the invention relates to an address decoding device, in particular to an address decoding device that pre-calibrates the address signal of the previous cycle when an address word line is used. Other bits first introduce the current traditional addressing decoding circuit. Refer to Figure i :: The factory does not pass the block diagram of the 10-address addressing decoding circuit. As shown in the figure i = is used to amplify the strength of the address signal, and the amplified address ϊ = to: first decode the circuit 2, where the address signal is A 0 ~ 'H / first input After the address signal is arranged, it is given as above, κ to ^ 17 + Ί! Liezi roughly describes the operation of the pre-decoding circuit 2. f & 〇 立 / 止 L is A0 ~ A9, so the pre-decoding circuit 2 decodes the address as heart [〇], χ21⑴: χϋq. For example, decode A1 and A2 as x43 [i], x43mw ϋ; L and A4 are decoded as X43 [0], corresponding to the word line WL Γ and 4 can find the way 5 according to the above X signal, and its action will be later The re-addressing signal is input to the area address latch. ^ ^ Ί't; 11;; ^ ^ ^ ^ ^ ^ ^-The signals GCLK are input to people respectively. The clock bluffs GCLK. Internal clock lock circuit 5. i, enter the r domain lock circuit 4 and the area address pin GCLK and the latch is received from the king 5 address latch circuit 4 according to the internal clock signal-the latch signal XρΓ all from: = the address of the circuit 2 Signal and provide the first circuit 5 according to the internal time; the same 'area address latch two latch signal XG to CLK n CLK while latching the address signal A0 and output the ^ kth domain decoding circuit 4 and area address latch The function of circuit 5 is on Wang Yu's address latching circuit 571183 V. Description of the invention (2) = The level is not disturbed by external noise. Then, the second latch signal xp of the global decoding circuit can obtain the global word line address mwl, and the global word line address MWL of \ kang and the second X are used. At the same time, it is input to the regional decoding circuit 7, * 2 = the address muscle of the word line of the message decoding domain and used to record the path 7: address " ia number XQ and accurately select the correct position. Addressing solution; the operation bit ... the corresponding character ㈣ is completed, s〆ί and L in the above operation 'the first of each clock cycle-the latching Hx suspension will be delayed to the next cycle and cause the addressing operation Figure 2 of the calcium shows the determination of Xi * technology? ? Figure 2 Figure 2 shows the production in the pre-cycle. If xp does not follow the end of the previous period, the 桂 -laurus signal cycle will continue to maintain the high level ill, with 、, 芑 芑 ', and the signal at the current address continues to exist in the current cycle. The period bit decoding circuit 7 receives the pre-period MWL bit 'and will cause the area address signal X. , And therefore output a sudden j5 as well as the addressed character line of the current cycle being addressed by the addressing decoding device η wave will cause the previous download, the addressing decoding device must select a character line currently under normal conditions at this time. In the above situation, the element line, that is, another operation logic error occurs, so that the k will be an address decoding device, which results in an error in the system operation. The factory writes the wrong unit. ”The current traditional solution is to delay the second latch signal XG to avoid logical operation with the second number output by the circuit. However, the MWL of the first eight cycles Address letter ~ No. 571183 output by the lock detection circuit V. Description of the invention (3) ^ Latching signal X. Delaying will cause a delay, which in turn will reduce the requirement for the entire system to run faster and faster. In addition, the above-mentioned foot is currently used for system operation due to timing drift in the operating procedure, and the inability to grasp the various installation methods will reduce the stability of the system. In order to solve the above problem, in order to provide an address decoding device, the main purpose of the present invention is to complete the above-mentioned global address latch circuit 4 and the pulse period at the end of the pulse period. The pick-up signal created by the overlap of the periodic signals and the next time to achieve the above purpose, = ... It is suitable for addressing a word line according to the first address signal, the _th type of address decoding device, the signal,-彳 5 彳 and an internal clock of the above-mentioned first address signal, and solving the above-mentioned solution. It is used to receive the address signal; a reset circuit is used to receive :: the code is a global j; the above = the clock period of the clock signal; the time: the pulse: the number, and bluff, the global address latch circuit , J output—resets the internal clock signal and locks it; the reset circuit, according to the lock signal, and receives =; =: = output—the first pin "number, a global decoding circuit, coupled The first latch is used to decode the first latch signal into one bit: latch circuit, =% of the domain address latch power, which is consumed by the heavy line; address signal; out-second When the latch signal is set to 1 mouth, the above is reset-without sighing to the above-mentioned younger one technology lock #bluff; and an area decoding signal

0503-6030TW.ptd Page 7 571183

According to above and philosophy, the above-mentioned global decoding circuit and area address latch circuit 'are combined with the lock detection signal and the second latch signal to output a word line address h to the above word line. Brief description of the drawings: In order to make the present invention, μ, +, „M and ± d and the above-mentioned purposes, features and advantages can be more clearly understood, the following examples are given in conjunction with the attached drawings: The detailed description is as shown in the figure:: Ξ: is a block diagram of the traditional addressing decoding circuit of T. The 3m / 糸 display ^ the clock diagram of the addressing and decoding device of the conventional technology. The block diagram ^. When the address decoding circuit according to the embodiment of the present invention = 1, the figure shows the symbol description of the fixed code device according to the embodiment of the present invention: 1, 3 1 ~ buffer, 32 ~, 33 ~, 34 ~, 35 ~ 、 3 6 ～ Pre-decoding circuit Internal clock generator Global address latch circuit Area address latch circuit Global decoding circuit 571183

7, 3 7 ~ area decoding circuit 38 ~ reset circuit Embodiment: Firstly, the address decoding circuit according to the embodiment of the present invention is described. "Quan Lei Xi Xi" map shows the address decoding diagram according to the embodiment of the present invention. As shown in Figure 3, the buffer 31 is used to amplify the address, 3; The input to the pre-decoding circuit takes the address signal A0 ~ A9 as an example. The pre-decoding circuit 32 first = arranges the input address signal after it is' # decoded. The following is to describe the operation of the pre-decoding circuit 32. = 9 'Therefore, the pre-decoding circuit 32 decodes the address signal from ί21 i L & Α4 into X43m, [1], ^ [2], and the X signal of the second address Un ▲ ## corresponding word line WL .: Then the input is input to the area address pick-up circuit 35, and its action is provided later by the circuit (not shown) to generate an internal clock signal into the global address latch circuit 34 internal clock generator 33 The external clock and control signals are combined with GCLK. The internal clock signal GCLK is input to the area address latching circuit 35. In the embodiment of the present invention, an internal clock generator 33 is provided to receive the clock. ,, eight are coupled to the internal clock signal GCLK at the clock cycle end ^ ^ Signal GCLK 'and in the month, when the mouth fruit, round out a reset signal

5. Description of the invention (6) RSET. Then, enter the g GCLK and the latch is received from the pre-JJ. According to the internal clock signal-the latch signal to the global decoding circuit 3.2 address signal, and provide the 35th path based on the internal time, the regional address latch electrical check lock The signal to the area 222 lock ^ Road 34 and the area address latch _ 2 domain address latch immediately reset the first latch error when the reset signal RSET, that is, the above first error. Chastity Xp and the second latch-up signal X. , Also low level. Here, the function of f and p and the second latch signal XG are reduced from a high level to the function of the lock circuit 35: = Circuit 34 and area address plug noise interference. The chastity address is made ’so that its level is not affected by the outside.

And the address MWL circuit of the global character line γ, the address 4 and the address 仏 are simultaneously input to the regional decoding address data, but the address 7 is decoded according to the address MWL of the global character line. And the operation of recording the line WL, ^ j ^ #uXq to accurately select the characters corresponding to the address signal, which is an address decoding operation. Address decoding: The main picture of the dagger map is shown in FIG. 4 as the timing chart according to the embodiment of the present invention. As shown in Fig. 4, the first lock detection signal Xρ generated in the previous-period end reset signal RSET = ^ period is set to a low level by the last name of the previous period from 1, and at the same time, the previous period is therefore Goes low when avoidable # _,, Ό, 时. In this way, as shown in FIG. 4, at the clock cycle, the latch signal X, the address signal MWL overlaps with the ^ LOCK 彳 & number \, so that the word 571183 previously addressed is included. V. Description of the invention ( 7) The surge generated by the element line in the current cycle will be eliminated to avoid errors in the logical operation of the regional decoding circuit 37. Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the scope of the present invention. Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

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Claims (1)

571183 VI. Application patent scope 1-Two address signals of an addressing decoding device and an internal clock based on the first address signal and the first pre-decoding circuit for addressing a word line, including: The above first address signal is decoded into a first address signal, and a reset circuit is used to receive the address signal; the end of the clock cycle of the internal clock signal = the internal clock signal, The address latching circuit, = ', turns out a reset signal; latches the above-mentioned internal clock signal into the above reset circuit, according to the locking signal, and upon receiving the above =: address signal and outputting A first bolt signal; 彳 " No. 'reset the above-mentioned first latch-global decoding circuit, coupled to decode the above-mentioned first latch signal into a two == full-lock circuit, use lock ten to describe the second Address signal and output-a second pin, which is used to reset the above-mentioned second latch signal and receive the address latch when the above-mentioned set signal is received. Regional bit output—word line address signal to the above character . — 裎 锁 #bluff 2. The addressing solution described in item 丨 of the scope of patent application-Buffer 'is lightly connected to the aforementioned pre-decoding circuit to amplify the more-bit address signal. The above-mentioned address decoding according to item 3 of the scope of the patent application includes an internal clock generator for generating the internal clock signal according to an external circuit, a dagger, and a control signal. u, the clock is 0503-6030TTptd page 12