TW569402B - Method of forming an embedded memory - Google Patents

Abstract

A wafer has a substrate defined with a first region and a second region. An ONO layer, a first silicon layer and a silicon nitride layer are formed on the substrate in sequence. Then the ONO layer, the first silicon layer and the silicon nitride layer disposed on the second region are removed. At least one gate oxide layer is formed on the second region and a second silicon layer is deposited on the wafer. After that, a photo-etching process is performed to remove the second silicon layer and the silicon nitride layer on the first region. At least a third silicon layer is formed on the wafer. Photo-etching processes and a plurality of ion implantation processes are then performed to form a gate, a drain and a source of each MOS transistor on the substrate.

Description

569402 V. Description of the invention (1) Technical field to which the invention belongs-The present invention provides a method for manufacturing an embedded memory, especially a method for manufacturing an embedded memory containing a flash memory structure. With the continuous improvement of process integration in the prior art, the current trend of making semiconductor integrated circuits is to integrate memory cell arrays with other circuit elements, such as a memory cell array and high-speed logic circuit elements ( high-speed l0gic circuit elements) are simultaneously fabricated on a chip (ch ip) to form an embedded memory that combines both a memory array and a logic circuit (10gicci rcu its) to greatly save area and speed up signals Processing speed. Please refer to FIG. 1 to FIG. 5, which are schematic diagrams of a method for fabricating a MOS transistor of a random type memory in a semiconductor wafer. The semiconductor day-to-day film 10 includes a silicon substrate 12 and a surface has been previously defined on the surface of the stone substrate 12. A memory array region 20 and a peripheral circuit region ( periphery circuit region) 30. Among them, the memory array region 20 and the peripheral circuit region 30 respectively include a doping region 16, a second doped region 18, and a third doped region 19 '. The plurality of doped regions are used as each Element wells, P-wells, P-wells, and N-wells, and each area is 569402. V. Description of the invention (2) Shallow trench isolation, STI) region 14 is separated. As shown in FIG. 1, a conventional method for making embedded memory is to sequentially form a bottom oxide layer 21, a silicon nitride layer 22, and An oxide layer (top oxide layer) 24, the three layers are collectively referred to as an oxide-nitride-oxide (0N0) layer 26. Then, as shown in FIG. 2, a first yellow light and etching process is performed to remove the ON0 dielectric layer 26 above the peripheral circuit area 30, and to remove the residual photoresist layer on the surface of the semiconductor wafer 10 and the peripheral circuit area 3. After the native oxide layer on the 0 surface, a thermal oxidation process is performed to form at least one gate oxide layer 28 on the surface of the peripheral circuit area 30. Subsequently, as shown in FIG. 3, a chemical vapor deposition (CVD) process is performed to form a polycrystalline silicon layer 32 to cover the memory array region 20 and the peripheral circuit region 30. Then, the polycrystalline silicon layer 32 is subjected to a The second yellow light and etching process is to form the control gate of each nitride memory in the memory array area 20, and to form the gate of each MOS transistor in the peripheral circuit area 30, as shown in Figure 4 It is shown that a first gate 34, a second gate 36, and a third gate 38 are formed in the memory array region 20 and the peripheral circuit region 30, respectively. Finally, as shown in FIG. 5 ′, the appropriate mask layer is then used, and several ion distribution processes are performed to shape the first gate 34, the second gate 36, and the third gate 38, respectively.

Page 8 569402 V. Description of the invention (3) The corresponding doped region is used as the source / drain of each MOS transistor. Due to the characteristics of nitride memory, the nitrogen stone layer in the underlying 0 N 0 dielectric layer is used as a charge trapping medium, and the high density of the nitrogen silicon layer is used to tunnel through the MOS transistor ( The electrons that tunneling into the azolite layer trap, thereby forming a non-uniform concentration distribution, and thereby changing the distribution range of the initial voltage to produce the effect of memory. Therefore, for a nitride memory, the quality of the formed 0N0 dielectric layer has a direct and sensitive effect on its electrical performance. However, in the conventional manufacturing method of embedded memory, in order to fabricate various circuit elements in the peripheral circuit area, such as forming a gate oxide layer on the surface of the peripheral circuit area (as shown in FIG. 2), multiple cleanings are often required. , Money engraving, or thermal oxidation processes, and these processes will cause a loss of the thickness of the 0N0 dielectric layer on the 20 surface of the memory array region, or damage the quality of the 0N0 dielectric layer, and then seriously affect the electrical performance of the nitride memory. , Reducing the stability and reliability of the embedded memory. Therefore, how to develop an embedded memory manufacturing method to improve the shortcomings of known technologies and improve product reliability has become an important issue at present. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide an embedded memory.

569402

The manufacturing method of MOS transistor is to solve the above problems. A secondary object of the present invention is to provide an electrically erasable and erasable codeable read-only memory of nitride (s0N0s).

Programmable read-only memory (EEPR0M), flash memory and other embedded non-volatile memory manufacturing methods. In a preferred embodiment of the present invention, a method for manufacturing a MOS transistor of an embedded memory is disclosed. The method first provides a semiconductor wafer, wherein the semiconductor wafer includes a substrate, and a first region and a second region have been defined on the surface of the substrate, and then an oxide-nitridation layer is sequentially formed on the surface of the semiconductor wafer— An oxide layer, a first silicon layer, and a silicon nitride layer, and then the oxide-nitridation-oxide layer, the first chip layer, and the silicon nitride layer above the first region are removed, and are deposited on the surface of the substrate The second region is formed to a gate oxide layer, a second stone layer 1 is formed on the surface of the semiconductor wafer, and a second yellow light and etching process is performed to remove the second silicon from the surface of the first region. Layer and the nitrogen silicon layer, and then formed on the surface of the semiconductor wafer = one less third silicon layer covers the surface of the semiconductor wafer, and then a yellow light engraving process is performed to form the first region and the second region respectively The gate of each # crystal, and then the ion distribution process is performed on the first region to form the source of each MOS transistor in the first region; and the pole, and then the ion distribution is performed on the first region Process' to form this Each of the power source transistor within the second region with no electrode pole.

569402 V. Description of the invention (5) The present invention is to form a stone layer and a dielectric layer over the oxidation-nitriding-oxidation (0N0 layer) as a protective layer to protect the 0N0 dielectric layer from subsequent processes. Affecting the 'cause' can effectively increase the reliability of the post-entry memory. Embodiments Please refer to FIG. 6 to FIG. 10, which are schematic diagrams of a method for fabricating a pile-up MOS transistor of an embedded memory according to the present invention. As shown in FIG. 6, the method for manufacturing a stacked MOS transistor with embedded memory according to the present invention is to first provide a semiconductor wafer 110, and a silicon region 11 2 on the surface of the semiconductor wafer 110 has a first region 12 0 and A second region 130 is used as a memory array region and a peripheral circuit region of the embedded memory of the present invention, and each region has a plurality of shallow trenches. Isolate them. Next, a plurality of N-type ion disposition processes and a P-type ion disposition process are performed to form a plurality of doped regions on the surface of the silicon substrate 112, wherein the first region 12 and the second region 130 respectively contain at least Cell

well 116, a deep P-well 117, a deep N-well 119, a p weii H8, and an n wel 1 122 . Next, an oxidation process is used to form a bottom oxide layer on the surface of the silicon substrate n 2 and a low pressure vapor deposition (LPCVD) process is performed on the bottom oxide layer.

569402

A nitrogen-silicon layer is deposited on the surface, and an a-pressure vapor deposition process is used to form a: L electron layer, and then a lower layer, an upper oxide layer, and an upper oxide layer are formed on the nitrogen-silicon layer. Among them, the bottom oxide layer and the silicon nitride vapor deposition process are sequentially performed as the dielectric layer i24. Then it is formed with a chemical 12-like and an H layer ^-the first Shixi layer. & / U8, covering the first area 120 and the second area 130. 〃 In addition, in a preferred embodiment of the present invention, the thicknesses of the bottom oxide layer, the nitrogen silicon layer, and the upper oxide layer in the 0N0 dielectric layer are about 20, 50, and 45 angstroms. Floor! 26 can be a polycrystalline silicon layer or an amorphous silicon layer with a thickness of about 300 to 80 Angstroms, and a nitrogen silicon layer 128 has a thickness of about 150 to 250 Angstroms. Subsequently, as shown in FIG. 7, a first yellow light and etching process is performed first to remove the nitrogen silicon layer 1 2 8, the first silicon layer 126 and the ONO in the second area 1 3 0 on the surface of the semiconductor wafer 1 10. The dielectric layer 124 is then subjected to at least one cleaning process and at least one thermal oxidation process to form at least one gate oxide layer 132 on the surface of the second region 130 of the silicon substrate 112, and then a low-pressure chemical vapor phase is performed. A deposition process is performed to form a second silicon layer 134 with a thickness of about 300 to 800 angstroms on the surface of the semiconductor wafer u. Among them, the nitrogen silicon layer 12 8 and the first stone layer 1 2 6 that cover the memory array ^ above the first region 120 are used to protect the on 0 dielectric layer 124 below to avoid ON. The 0 dielectric layer 1 24 was damaged or injured during the above-mentioned cleaning, thermal oxidation process and subsequent processes. As shown in Figure 8, a second yellow light and etching process is then performed to

569402 Description of the invention (7) ΪΪί: the second stone layer 134 and the nitrogen stone layer above the area 120, 28, a chemical vapor deposition process for the semiconductor wafer 13〇 ^ \ a third silicon layer 136 It covers the first area 120 and the second area /, and then can be used to make a selective selective process according to the needs of the product. Core 2: Layer ^ on the "order formation"-metal ^ ^ 2 / dielectric layer 142m hair Layer and-Shi Xi oxygen layer, and the second silicon layer 134 and the third silicon layer 136 are also the same as the above < IIi I26, which can be a doubly stone layer or an amorphous stone layer. Invention = In a preferred embodiment, the dielectric layer 1 42 is composed of a silicon oxide layer and a silicon nitride layer: stacked, the thickness of the second stone layer i 34 and the third stone layer 136 are approximately 30 0 to 800 angstroms, and the metal silicide layer 138 is composed of a tungsten sulfide (wsi) with a thickness of about 500 angstroms. Then, as shown in FIG. 9, a third yellow light and etching is performed. In the manufacturing process, a patterned photoresist layer (not shown) is formed on the surface of the dielectric layer 142 to define the positions of the gate electrodes in the first region 120 and the second region 130. Then, an etching process is further performed, and etching is performed along the pattern of the photoresist layer to form a plurality of first gate structures 1 4 4 in the first region 120 and the second region 130 respectively. Two gate structures 1 4 6 and third gate structures 1 4 8. Each of the first gate structures 1 4 4 includes two stacked first silicon layers 1 2 6 and a third stone layer 1 3 6, and the second gate structure 1 4 6 and the third gate structure 1 4 8 each include two stacked second silicon layers 1 3 4 and a third silicon layer 3 6 (metal silicide layer 1 3 8 And the dielectric layer 1 4 2 is selective design).

569402 V. Description of the invention (8) As shown in FIG. 10, an ion distribution process is performed in the first region to form a plurality of doped regions around each of the first gate structures 1 4 4 in the first region 1 2 0. , Which are used as the source electrode 160 and the non-pole electrode 150 respectively to form a stacked M0S transistor with each of the first gate structures 1 44 for use as a nitride flash memory (S0N0S flash memory). ) Or nitride can electronically erase the memory cell (memory ce 1 1) that can encode only the memory cell (S0N0S EEPR0M). Among them, the pole 150 is extended along a bit line and connected to the drain of an adjacent flash memory cell, and is used as a bit line of nitride flash memory (SON OS flash memory). The source 160 is a common source of two adjacent memory cells. Subsequently, a second area ion distribution process is performed, and a sidewall substructure 195 formed around each gate and a plurality of N-type and P-type ion processes are formed to form an N-type light around the second gate structure 1 4 6 Doped drain (nty pe 1 i gh t doped drain, N-LDD) 170 and N-type source / drain 175, and a p-type lightly doped drain (p ^) is formed around the third gate structure 1 4 8 y pe 丨 丨 gh t doped drain (P-LDD) 1 8 0 and p-type source / drain i 85. Since all processes in this part are standard CMs processes commonly used in the industry, they should be familiar. The item artist is well-known, so I won't repeat it here. ^ As described in the above embodiment, the first area 12 is used as a memory array area, and the second area 130 is used as a peripheral circuit area, that is, a logic (10 gic )region. However, the manufacturing method of the present invention is not limited to this, but can be applied to the integration of other types of circuit components, such as

569402 V. Description of the invention (9) The second area 130 may also be a static random access memory (SRAM) area or a dynamic random access memory (DRAM) area. Compared with the conventional method for fabricating a metal oxide semiconductor transistor of an embedded memory, the present invention forms a first silicon layer 12 6 and a nitrogen silicon layer 12 8 after forming the ONO dielectric layer 1 24. After that, the fabrication of circuit elements on the peripheral circuit area will be performed later. Therefore, the ON0 dielectric layer 124 will be protected from the subsequent processes of cleaning, oxidation, and etching. Therefore, the ON0 dielectric formed can be effectively controlled. Layer quality to increase the reliability of the memory components. In addition, since the gate structures 144, 146, and 148 on the surface of the memory array area and the peripheral circuit area are all formed by two stacked silicon layer structures (the first silicon layer 126 and the third silicon layer 136, the first The second silicon layer 134 and the third layer i3 6). This gate structure 1 4 4, 1 4 6 and Η 8 can avoid doping (such as boron) caused by increasing the gate ^ value = degree (reducing the resistance value). Penetration through gate oxidation 1: = The current level of the gate oxide is damaged or the gate's initial voltage is shifted, which improves the reliability of the memory process. The patent ^ ΐ described is only a preferred embodiment of the present invention. ‘Every application according to the present invention = equal changes and modifications made should be covered by the patent of the present invention.

569402 Brief description of the diagrams Brief description of the diagrams: Figures 1 to 5 are schematic diagrams of the conventional method for making M0S transistors of embedded memory. Figures 6 to 10 are schematic diagrams of a method for making a MOS transistor of an embedded memory according to the present invention. Explanation of symbols: 10 semiconductor wafer 12 silicon substrate 14 shallow trench isolation region 16 first doped region 18 second doped region 19 third doped region 20 memory array region 21 bottom oxide layer 22 nitrogen silicon layer 24 Oxide layer 26 0 N 0 Dielectric layer 28 Gate oxide layer 30 Peripheral circuit area 32 Polycrystalline silicon layer 34 First gate 36 Second gate 38 Third gate 110 Semiconductor wafer 112 Silicon substrate 114 Shallow trench 1¾ Isolation area 116 Single Cell 117 Deep P-well 118 P-well 119 Deep N-well 120 First region 122 N-well 124 0 N 0 Dielectric layer 126 First silicon layer 128 Nitrogen silicon layer 130 Second region

Page 569402 Brief description of the drawings 132 Gate oxide layer 134 Second silicon layer 136 Third silicon layer 138 Metal oxide layer 142 Dielectric layer 144 First gate 146 Second gate 148 Third gate 150 Drain 160 source 170 N-type lightly doped drain 175 drain 180 P-type lightly doped drain 185 source 190 silicon nitrogen layer 195 sidewall

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Claims (1)

569402 VI. Application Patent Scope 1. A method for manufacturing a MOS transistor with embedded memory, the method includes the following steps: providing a semiconductor wafer, the semiconductor wafer includes a substrate, and a surface of the substrate A first region and a second region have been defined; an oxide-nitride-oxide layer (0N0 layer), a first stone layer and a first dielectric layer are sequentially formed on the surface of the semiconductor wafer; A yellow light and etching process to remove the first dielectric layer, the first silicon layer, and the oxidation-nitriding-oxide layer on the second region; forming at least one on the second region of the substrate surface A gate oxide layer; forming a second silicon layer on the surface of the semiconductor wafer; performing a second yellow light and etching process to remove the second silicon layer and the first dielectric layer on the surface of the first region; A third silicon layer is formed on the surface of the semiconductor wafer; a third yellow light and etching process is performed to form a gate of each MOS transistor in the first region and the second region; and an ion distribution system in the first region is performed. To form the source of each of the transistors M0S the first region and the drain electrode; and a second region for an ion value process is performed to form the source and drain of each transistor M0S region within the second electrode. 2. The method according to item 1 of the patent application scope, wherein the method further comprises the following steps before implementing the third yellow light process: forming a metal silicide layer on the third silicon layer; and the metal stone A second dielectric layer is formed on the material layer. Page 569402 3. The method of claim 1, wherein the second dielectric layer comprises a silicon nitride compound or a silicon oxide. 4. The method according to item 1 of the patent application scope, wherein the first area includes a flash memory area or an electronically erasable code read-only memory (EEPROM) area. '5. The method of claim 1, wherein the second area includes a logic area, a static random access memory (SRAM) area, or a dynamic random access memory (DRAM) area. 6. The method according to item 1 of the patent application, wherein the first silicon layer, the second chipping layer and the third chipping layer comprise a polysilicon material or an amorphous stone. us silicon) material 0 = · —a method of manufacturing an embedded memory, the manufacturing method includes the following steps: providing a semiconductor wafer, the substrate surface of the semiconductor wafer has a human-memory array area defined, and A peripheral circuit area, and the memory array area includes at least one cell-well, and the peripheral circuit area includes at least one N-wel 1 and at least one P-well (P-wel 1); 569402 6. The scope of the application for a patent sequentially forms an oxide-nitride-oxide layer (0N0 layer), a first silicon layer and a first dielectric layer on the surface of the semiconductor wafer, covering the memory array area and the periphery. A side circuit region; performing a first yellow light and etching process to remove the first dielectric layer, the first silicon layer, and the oxidation-nitridation-oxide layer in the peripheral circuit region; Forming at least one gate oxide layer in the peripheral circuit region; performing a chemical vapor deposition process to form a second silicon layer to cover the surface of the semiconductor wafer; and performing a second yellow light and etching process to remove the memory array region Forming the second silicon layer and the first dielectric layer therein; forming at least a third silicon layer on the surface of the semiconductor wafer to cover the memory array region and the peripheral circuit region, and performing a third yellow light and etching process to A first gate, a second gate, and a third gate are formed above each of the single cell well, each of the N-type well, and each of the P-type well; a first ion distribution process is performed to On each side of the first gate Do not form a first source and a first drain; perform a second ion layout process to form a second source and a second drain on each side of each second gate; and perform a A third ion layout process is used to form a third source electrode and a third drain electrode on each side of each third gate electrode. 8. The method of claim 7 in the scope of patent application, wherein the method is implemented in the Page 20, 569402 6. Scope of patent application --- Before the second process, the process of forming a full line on the third silicon layer is additionally included: A first-on-a dielectric layer is formed on the metal silicide layer. 9 · For example, the method of applying for a patent Fan Yuan 箆 7j§ μ + ... you target target, in which the first dielectric layer 3 has a silicon compound or a silicon oxide compound. 10. The method of claim 7 in the scope of patent application, wherein the first silicon layer, the second stone layer, and the third silicon layer include a polysi 1 material or an amorphous stone (am 〇rph〇us silicon) material. 11. The method according to item 7 of the patent application, wherein the embedded memory system is a SOON flash memory, and the first gate, the first source, and the The first drain electrode constitutes a stacked MOS transistor, which is used as a memory cell of the nitride flash memory (SONOS flash memory). 1 2 · The method according to item 丨 丨 of the patent application, wherein the first drain is used as a bit line of the nitride flash memory ($ 〇N 〇sf 1 ashmem 〇ry), and the The first source is a common source. U. For example, the method of item 7 of the Qing Patent Scope, wherein the embedded memory is a gaseous, electronically erasable, codeable read-only memory (S0N0S Page 21 569402 6. Application scope of patent (EEPR0M), and the first gate electrode, the first source electrode and the first drain electrode constitute a stacked M0S transistor, which is used as the nitride to be electronically erasable. A memory cell capable of encoding a read-only memory (SONOS EEPR0M) 0 1 4. The method according to item 13 of the scope of patent application, wherein the first drain is used as the nitride electronically wipeable Except for the bit lines of the codeable read-only memory (S0N0S EEPR0M), the first source is a common source. Page 22