TW569347B - Method for selectively removing metal compound dielectric layer with high dielectric constant - Google Patents
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569347569347
【發明領域】 、本發明係有關於一種蝕刻方法,且特別是 選擇性移除具高介電常數之金屬化合物介電層 有關於一 的餘刻方 種 【發明背景】 傳統的半導體技術係以二氧化石夕做為金屬氧化半 metal oxlde semiconduct〇ie ,M〇s)電晶體 電 層:而”元件尺寸愈來愈小的趨勢,二氧化石夕層 =須跟者降⑻,以使閘極和通道區之間可以維持相同^ ,谷H氧切層厚度的減少會發生嚴重的穿遂電流 (tunnelmg current )。即使氧化矽層沒有缺陷不純μ 的物質或者在理想配比(st〇ichi〇metry)上的差異但 當厚度小於3奈米(nm )時,氧化梦層仍然會大量的漏^ 。只要在厚度上有幾個埃值(A)的變化,通道電流就 以好幾個位數的數量改變。更複雜的是,氧化矽層品質— 般都不完美’ 0此造成了另一種電流傳輸機制,不只增加 漏電流並且加速閘極氧化石夕層的失效。 鑑於氧化矽層薄化所帶來的問題,一些具有高介電常 數的介電材料已被應用至電晶體的閘極介電層,這些高介 電常數的介電材料係為一些金屬氧化物,例如二氧化鍅 (Zr〇2 )或二氧化铪(Hf〇2)等。這類物質的介電常數大 約為20〜25左右,大約為二氧化矽的5〜6倍。因此,使用這 類金屬氧化物介電材質做為閘極介電層時,若厚度為5〜6 奈米(nm) ’其等效氧化層厚度(e(luivalent 〇xide[Field of the Invention] The present invention relates to an etching method, and particularly to the selective removal of a metal compound dielectric layer with a high dielectric constant. [Background of the Invention] Traditional semiconductor technology is based on As the metal oxide half metal oxlde semiconductor (M0s) transistor layer: the "element size is getting smaller and smaller, the dioxide layer = must be lowered to make the gate The same can be maintained between the electrode and the channel region. The reduction of the thickness of the oxygen cut layer in the valley H will cause a severe tunneling current (tunnelmg current). Even if the silicon oxide layer is free of defects and impurities, or at an ideal ratio (st〇ichi) 〇metry) difference, but when the thickness is less than 3 nanometers (nm), the oxide dream layer will still leak a lot ^. As long as there are a few angstrom values (A) changes in thickness, the channel current will be in several bits The number of the number changes. More complicated is that the quality of the silicon oxide layer is generally imperfect. 0 This causes another current transfer mechanism, which not only increases the leakage current and accelerates the failure of the gate oxide layer. Given the thin silicon oxide layer Turn into The problems caused by this are that some dielectric materials with high dielectric constant have been applied to the gate dielectric layer of transistors. These dielectric materials with high dielectric constant are some metal oxides, such as hafnium dioxide (Zr 〇2) or hafnium dioxide (Hf〇2), etc. The dielectric constant of this kind of material is about 20 ~ 25, about 5 ~ 6 times that of silicon dioxide. Therefore, this type of metal oxide dielectric material is used When used as a gate dielectric layer, if the thickness is 5 to 6 nanometers (nm) ', its equivalent oxide thickness (e (luivalent 〇xide
569347 五、發明說明(2) thickness,EOT)約為1·〇奈米左右。 在目刚互補氧化金屬半導體(c〇mplementary metai oxide semiconductor,CMOS )之金屬氧化物閘極介電層 的製程中’必須選擇性地移除源極/沒極區的閘極介電 層,以進行隨後之金屬矽化物製程。然而傳統使用乾蝕刻 製程來移除金屬氧化物閘極介電層的方法,因為需要大量 的物理性餘刻或錢鑛,故對石夕基底缺少足夠的選擇性。此 外金屬氧化物介電層無法用濕式餘刻順利地移除。當使 用濃縮的HF溶液來蝕刻金屬氧化物介電層時,其蝕刻相當 低,且蝕刻後的均勻性相當差,而且濃縮的HF溶液會蝕刻 暴露出的隔離結構,再者,亦會造成閘極電極下做為閘極 介電層之金屬氧化物介電層的底切。 因此,需要開發移除金屬氧化物介電層且不會傷害 他元件的方法。 、 【發明的目的及概要】 ^有鑑於此,本發明的目的在於提供一種選擇性移除具 尚介電常數之金屬化合物介電層的方法,所使用的蝕刻劑 其金屬化合物介電層對矽材質層具有良好的蝕刻選擇比, 且對金屬化合物介電層的餘刻速率快。 本發明用以蝕刻金屬化合物介電層的蝕刻氣體為含鹵 素氣體,所適用的金屬化合物介電層包括氧化铪(Hf〇 ) '氧化* (zr〇2 )、氧化铭ul2〇5 )、氣氧化給 化錯、碎酸給、和碎酸錯。 上述用以蝕刻金屬化合物介電層的蝕刻氣體為含鹵素569347 V. Description of the invention (2) Thickness (EOT) is about 1.0 nm. In the fabrication of metal oxide gate dielectric layers of complementary metal oxide semiconductors (CMOS), the gate dielectric layers of the source / dead regions must be selectively removed in order to The subsequent metal silicide process is performed. However, the traditional method using a dry etching process to remove the metal oxide gate dielectric layer lacks sufficient selectivity to the Shixi substrate because it requires a large amount of physical relief or money deposits. The additional metal oxide dielectric layer cannot be removed smoothly with a wet finish. When a concentrated HF solution is used to etch the metal oxide dielectric layer, its etching is relatively low, and the uniformity after etching is quite poor, and the concentrated HF solution will etch the exposed isolation structure, and it will also cause a gate Undercuts of the metal oxide dielectric layer under the gate electrode serve as the gate dielectric layer. Therefore, methods to remove the metal oxide dielectric layer without harming other components need to be developed. [Objective and Summary of the Invention] In view of this, the object of the present invention is to provide a method for selectively removing a metal compound dielectric layer with a high dielectric constant. The etchant used has a metal compound dielectric layer pair. The silicon material layer has a good etching selection ratio and has a high remaining rate for the metal compound dielectric layer. The etching gas used for etching the metal compound dielectric layer of the present invention is a halogen-containing gas, and the applicable metal compound dielectric layer includes hafnium oxide (Hf〇) 'oxidation * (zr〇2), oxidized oxide (ul205), gas Oxidation errors, acid breaks, and acid breaks. The above-mentioned etching gas for etching the metal compound dielectric layer is halogen-containing
569347 五、發明說明(3) 氣體和惰性氣體(i n e r t g a s )。 上述用以蝕刻金屬化合物介電層的蝕刻氣體為含齒 氟體、惰性軋體(i n e r t g a s)和氧化劑氣體。 、 上述之含齒素氣體可為cf4、chf3、cM2、(:H3F、569347 V. Description of the invention (3) Gas and inert gas (i n e r t g a s). The etching gas used to etch the dielectric layer of the metal compound is a fluorine-containing tooth, an inert rolled body (iner t g a s), and an oxidant gas. The above-mentioned tooth-containing gas may be cf4, chf3, cM2, (: H3F,
Cl2、BC13、Br2、HF、HC1、斷、HI、NF3、sFe 或其混合。 上述之惰性氣體可為He、Ar、Xe、n2或其混合。 上述之氧化劑氣體可為&、C〇或其混合。 ^發明並提供將上述選擇性移除具高介電常數之金 化合物介電層的方法應用於製造電晶體的製程,其步驟如 下Ϊ达i於半導體基底上形成一金屬化合物介電層,並於 金,化::介電層上形成一閘極電極。接著,㈣極電極 兩貝i半導體基底中進行一淡離子摻雜。之後,於閘極電 隙壁。繼續對未為閘極電極和間陈壁覆蓋 之+導體基底中進行—漠離子摻雜’藉以形成—具有淡推 ::極二LDD)結構之源極/汲極。之後,使用上述含齒素 氣體對金屬化合物介電層進行乾式電漿姓刻, 以移除未為閘極電極和間隙壁覆蓋之金屬化合物介電層, J =出:原極/汲極之表面’以利於源極/汲極表面形成一 金屬矽化物層,藉以降低源極/汲極 【發明詳細說明】 J移Ϊί”的高介電常數之金屬化合物介電層的情 'β,本發明提出一種金屬化合物介電層對矽具有高選 亥!方法,在選擇性移除露出表面的金屬化合 "電層時’不會影響隨即暴露出的石夕材質㊆(例如:矽Cl2, BC13, Br2, HF, HC1, broken, HI, NF3, sFe, or a mixture thereof. The above inert gas may be He, Ar, Xe, n2 or a mixture thereof. The aforementioned oxidant gas may be &, Co or a mixture thereof. ^ Invented and provided the method for selectively removing a gold compound dielectric layer with a high dielectric constant as described above in a process for manufacturing a transistor, the steps of which are as follows: i. Forming a metal compound dielectric layer on a semiconductor substrate; and In gold, chemical: a gate electrode is formed on the dielectric layer. Next, a light ion doping is performed on the semiconductor electrodes on the semiconductor electrodes. After that, at the gate gap wall. Continue to perform in the + conductor substrate that is not covered by the gate electrode and the interstellar wall—by the formation of a dopant ion dopant—to form a source / drain with a faded :: pole two LDD) structure. After that, the metal compound dielectric layer was dry-etched using the above-mentioned tooth-containing gas to remove the metal compound dielectric layer that is not covered by the gate electrode and the spacer. J = Out: "Surface" facilitates the formation of a metal silicide layer on the source / drain surface, thereby reducing the source / drain [Detailed description of the invention] Jshift Ϊ "high dielectric constant metal compound dielectric layer 'β, this The invention proposes a metal compound dielectric layer with high selectivity for silicon! Method, when selectively removing the exposed surface metal compound " electrical layer 'will not affect the immediately exposed material of the stone 夕 (for example: silicon
569347 五、發明說明(4) 基底、淺溝槽隔離結構等)。 接著’配合第1 A圖至第1 D圖所繪示之不同製程階段的 基底剖面圖,來詳細說明本發明。 首先請參照第1A圖,在此基底剖面圖中,淺溝槽隔離 結構105已利用已知的半導體製造技術形成於半導體基底 100中。此半導體基底100通常為單晶矽或基他半導體材質 ,亦可為石夕層置於絕緣層上的結構(silic〇n —⑽一 insulator structure,SOI structure)。淺溝样隔離社569347 V. Description of the invention (4) Substrate, shallow trench isolation structure, etc.). Next, the present invention will be described in detail with reference to the cross-sectional views of the substrates at different process stages shown in Figs. 1A to 1D. First, please refer to FIG. 1A. In this cross-sectional view of the substrate, the shallow trench isolation structure 105 has been formed in the semiconductor substrate 100 using known semiconductor manufacturing techniques. The semiconductor substrate 100 is usually made of single crystal silicon or other semiconductor materials, and can also be a silicon on-insulator structure (SOI structure). Shallow trench
構m的材質通常為氧切(Si〇2)或氮切(iH 之後’在半導體基底100上形成一層具高介電常數之 金屬化合物介電層101,此具高介電常數之金屬化合物介 電層101係為含金屬元素的介電材質,適合的金屬元素為 铪(Hf)、錯(Zr)和鋁(A1),含這些金屬元素的介電 材質例如為與氧(〇 )化合的氧化铪(Hf 〇2 )、氧化錯 (Zr02 )、以及氧化鋁(ai2〇5 ),亦可為與氮(N )和氧 (0 )化合的氮氧化銓、以及氮氧化錯,或是為與石夕酸根 (S i 03 )化合的矽酸铪、以及矽酸鍅。 此金屬化兮物介電層1〇1的介電常數高於傳統利用熱 氧化法形成之&極氧化層的介電常數。此金屬化合物介電 層101的介電常數大致為1〇〜40左右。其形成方法為化學氣 相沈積(CVD )法。在此實施例中,此金屬化合物介電層 101係做為電晶體的閘極介電層’其厚度約為〜2〇埃左 右0 接著在金屬化合物介電層1 0 1上形成一閘極電極堆整The material of the structure m is usually oxygen cut (Si02) or nitrogen cut (after iH) to form a metal compound dielectric layer 101 with a high dielectric constant on the semiconductor substrate 100. The metal compound with a high dielectric constant The electrical layer 101 is a dielectric material containing a metal element, and suitable metal elements are hafnium (Hf), zirconium (Zr), and aluminum (A1). The dielectric material containing these metal elements is, for example, compounded with oxygen (〇). HfO2, Zr02, and alumina (ai205) can also be hafnium oxide combined with nitrogen (N) and oxygen (0), and nitrogen oxide, or Samarium silicate and hafnium silicate combined with lithium sulphate (S i 03). The dielectric constant of this metallized dielectric layer 101 is higher than that of the & polar oxide layer formed by the traditional thermal oxidation method. Dielectric constant. The dielectric constant of the metal compound dielectric layer 101 is approximately 10 to 40. The formation method is a chemical vapor deposition (CVD) method. In this embodiment, the metal compound dielectric layer 101 is As the gate dielectric layer of the transistor, its thickness is about ~ 20 angstroms. Then the metal compound dielectric layer A gate electrode stack is formed on 1 0 1
0503-8564TKf ; TSMC2002-0405 ; Amy.ptd 第 7 頁 569347 五、發明說明(5) '—^—-- 層104,此閘極電極堆疊層1〇4例如是雙層的閘極電極堆 疊。在此實施例中,此閘極電極堆疊層丨〇4包括依序形 於金屬化合物介電層101上之第一閘極電極層1〇2和第二閘 極電極層(蓋層,capping layer )1〇3,其形成方法 學氣相沈積(CVD )法。 適合第一閘極電極層1〇2的材質包括氮化鈦(ηΝ)、 氮化鎢(WN)、、矽鍺(SiGe)等,適合第二閘極電極層 103的材質包括複晶石夕(poiysiHcon)、石夕鍺(SiGe)、 鎢(W )等。 ' 上述之閘極電極堆疊層1〇4亦可為其他型態的昼層, 例如第一閘極層102為導電材質,第二閘極層1〇2為絕θ緣材 質。在本發明中,並不限定閘極電極堆疊層丨〇4的型態。 接著請參照第1B圖,在金屬化合物介電層1〇1上形成 閘極電極201,並暴露出部份金屬化合物介電層1〇ι的表面 203。閘極電極201的形成通常包括使用具有閘極圖案的罩 幕層,對閘極電極堆疊層1 〇4進行蝕刻,以定義出閘極電 極2 01。之後’於閘極電極2 〇 1的側壁形成間隙壁2 〇 2。 在形成間隙壁202之前更包括對半導體基底1〇〇進行一 淡離子摻雜,在形成間隙壁2〇2之後更包括對半導體基底 100進行一濃離子摻雜,以形成具有淡摻雜汲極結構 (lightly doped drain structure ,LDD structure)的 源極/汲極204。 接著請參照第1C圖,在形成源極/汲極2〇4之後,為了 降低電晶體元件之源極/汲極2〇4的寄生電阻(sheet0503-8564TKf; TSMC2002-0405; Amy.ptd page 7 569347 V. Description of the invention (5) '-^ --- layer 104, the gate electrode stack layer 104 is, for example, a double-layered gate electrode stack. In this embodiment, the gate electrode stack layer 104 includes a first gate electrode layer 102 and a second gate electrode layer (capping layer) sequentially formed on the metal compound dielectric layer 101. 10), its formation method is a vapor deposition (CVD) method. Suitable materials for the first gate electrode layer 102 include titanium nitride (ηN), tungsten nitride (WN), and silicon germanium (SiGe), and suitable materials for the second gate electrode layer 103 include polycrystalline stone. (PoiysiHcon), SiGe, tungsten (W), and the like. 'The above-mentioned gate electrode stacking layer 104 may also be a daylight layer of other types. For example, the first gate layer 102 is a conductive material, and the second gate layer 102 is an insulating θ edge material. In the present invention, the type of the gate electrode stack layer 104 is not limited. Next, referring to FIG. 1B, a gate electrode 201 is formed on the metal compound dielectric layer 101, and a part of the surface 203 of the metal compound dielectric layer 100 is exposed. The formation of the gate electrode 201 generally includes etching the gate electrode stacking layer 104 using a mask layer having a gate pattern to define the gate electrode 201. After that, a spacer 002 is formed on the side wall of the gate electrode 201. Before forming the spacers 202, a light ion doping is further performed on the semiconductor substrate 100, and after the spacers 200 are formed, a dense ion doping is further performed on the semiconductor substrate 100 to form a lightly doped drain electrode. A source / drain 204 of a lightly doped drain structure (LDD structure). Next, referring to FIG. 1C, after forming the source / drain 204, in order to reduce the parasitic resistance of the source / drain 204 of the transistor element (sheet
569347 五、發明說明(6) resistance ) Rs與Rd,因而必須在源極/汲極204的表面形 成一層金屬石夕化物層(metal silicide layer)。是故, 在源極/汲極204的表面形成金屬矽化物層前,必須移除暴 露出表面203的金屬化合物介電層ι〇1。 經發明人的研究發現,使用含齒素氣體之蝕刻氣體對 金屬化合物介電層1 〇 i進行乾式電漿蝕刻,可以有效地移 除暴露出的金屬化合物介電層101,而不對隨後暴露出的 半導體基底100和淺溝槽隔離結構i 05造成傷害。 上述蝕刻氣體中,含鹵素氣體可為含氟(F)的氣 體,例如:CF4、CHF3、CH2F2、CH3F、HF、NF3、或SF6。含 齒素氣體亦可為含氣(Cl)的氣體,例如:ci2、BC13、或 HC1。含自素氣體亦可是含溴()的氣體,例如·· βΓ2、 或HBr。此外,含鹵素氣體還可以是含碘(I )的氣體,例 如:HI。而且,上述之各種含邊素氣體還可做任意之混 合’而做為餘刻金屬化合物介電層1 〇 1的製程氣體。 另外,上述蝕刻氣體除了包括含鹵素氣體外,更包括 惰性氣體(inert gas),此惰性氣體可以是氦(He)、 氬(Ar )、氙(xe )、氮氣(& )或是其混合。 而且,上述#刻氣體更可以包括氧化劑氣體,亦即此 蚀刻氣體的組成為含鹵素氣體、惰性氣體以及氧化劑氣體 。其中,氧化劑氣體可以是氧氣(〇2 )、一氧化碳(CO ) 或是其混合。 接著請參照第1D圖,移除源極/汲極2〇4的表面的金屬 化合物介電層1 〇 1後,則繼續進行金屬矽化物製程,以於569347 5. Description of the invention (6) resistance Rs and Rd. Therefore, a metal silicide layer must be formed on the surface of the source / drain 204. Therefore, before the metal silicide layer is formed on the surface of the source / drain 204, the metal compound dielectric layer ιo exposed on the surface 203 must be removed. The inventor's research found that dry plasma etching of the metal compound dielectric layer 10i using an etching gas containing a tooth element gas can effectively remove the exposed metal compound dielectric layer 101 without subsequent exposure. The semiconductor substrate 100 and the shallow trench isolation structure i 05 cause damage. Among the above etching gases, the halogen-containing gas may be a gas containing fluorine (F), for example, CF4, CHF3, CH2F2, CH3F, HF, NF3, or SF6. The tooth-containing gas can also be a gas containing Cl (C1), for example: ci2, BC13, or HC1. The autogen-containing gas may also be a gas containing bromine (), such as βΓ2, or HBr. In addition, the halogen-containing gas may be a gas containing iodine (I), such as HI. In addition, the above-mentioned various element-containing gases can also be arbitrarily mixed 'to be used as a process gas for the remaining metal compound dielectric layer 101. In addition, the etching gas includes an inert gas in addition to a halogen-containing gas, and the inert gas may be helium (He), argon (Ar), xenon (xe), nitrogen (&), or a mixture thereof. . In addition, the #etching gas may further include an oxidant gas, that is, the composition of the etching gas is a halogen-containing gas, an inert gas, and an oxidant gas. The oxidant gas may be oxygen (02), carbon monoxide (CO), or a mixture thereof. Next, referring to FIG. 1D, after removing the metal compound dielectric layer 101 on the surface of the source / drain 204, the metal silicide process is continued, so that
0503-8564THVf . TSMC2002-0405 · Amy.ptd 第9頁 5693470503-8564THVf. TSMC2002-0405Amy.ptd Page 9 569347
五、發明說明(7)V. Description of Invention (7)
L面形成金屬矽化物層4〇1,其材質可為 、矽化鎳(NiSi )、矽化鈷(CoSi2 )或 以下特舉例一、例二和例三等三個用以蝕刻金屬矽化 物的餘刻條件之例子,並同時列出蝕刻金屬矽化物對複晶 矽的蝕刻結果。 待#刻的金屬矽化物層為氧化铪(Hf 02 )。 餘刻倏β : 餘刻氣體的組成為CF4/CH2F2,流量比為40 / 80 (單 位··標準立方公分,sccm ),壓力為5 m Torr,變壓耦式 電漿(transformer coupled plasma , TCP)的功率為600 瓦(W ),偏壓為200瓦(W )。 餘刻結果: (a) 氧化給(Hf02)的姓刻速率為343A/min (埃/分 ),均勻度為3. 8 % ; (b) 複晶碎的餘刻速率為l55A/min,均勻度為14 °/〇 ; (c) 氧化給(Hf02 )對複晶矽的蝕刻選擇比為2. 2。 例二 待蝕刻的金屬矽化物層為氧化铪(Hf02 )。 蝕刻條件: 蝕刻氣體的組成為CF4/CHF2/02,流量比為30 / 6〇 / 10 (seem ),壓力為5 m Torr,變壓輕式電漿(Tcp )的A metal silicide layer 401 is formed on the L surface, and the material can be nickel silicide (NiSi), cobalt silicide (CoSi2), or the following special examples 1, 2, and 3 for etching the metal silicide. An example of the conditions is also listed, and the results of the etching of the polycrystalline silicon by the etching metal silicide are also listed. The metal silicide layer to be etched is hafnium oxide (Hf 02). I 倏 β: I 气体 gas composition is CF4 / CH2F2, flow rate is 40/80 (unit ·· standard cubic centimeter, sccm), pressure is 5 m Torr, transformer coupled plasma (TCP ) Has a power of 600 watts (W) and a bias voltage of 200 watts (W). Remaining results: (a) The lasting rate of oxidation to (Hf02) was 343A / min (Angstroms / minute), and the uniformity was 3.8%; (b) The remaining rate of the polycrystalline fragment was l55A / min, uniform The degree is 14 ° / 〇; (c) The etching selectivity ratio of the oxide to (Hf02) to the polycrystalline silicon is 2.2. Example 2 The metal silicide layer to be etched is hafnium oxide (Hf02). Etching conditions: The composition of the etching gas is CF4 / CHF2 / 02, the flow ratio is 30/60/10 (seem), the pressure is 5 m Torr, and the pressure-variable light plasma (Tcp)
0503-8564TWf : TSMC2002-0405 : Amy.ptd 第10頁 569347 五、發明說明(8) 功率為600瓦(W),偏壓為200瓦(W)。 蝕刻結果: (a) 氧化铪(Hf02)的蝕刻速率為3〇6A/min (埃/分 ),均勻度為5 · 7 % ; (b) 複晶石夕的餘刻速率為98A/min,均勻度為14.7 % ; (c) 氧化铪(H f 〇2 )對複晶矽的餘刻選擇比為3 · 1。 例三 待餘刻的金屬矽化物層為氧化铪(jj f 〇2 )。 餘刻條件·· 蚀刻氣艘的組成為CF4/02/Ar,流量比為5 / 200 / 100 (seem),壓力為20 m Torr,變壓耦式電漿(TCP) 的功率為600瓦(W),偏壓為100瓦(w)。 餘刻結果: (a) 氧化給(Hf02)的蝕刻速率為138A/min (埃/分 )’均勻度為5.8 % ; (b) 複晶矽的蝕刻速率為8〇 A/min,均勻度為1〇 0/〇 ; (c) 氧化給(H f 〇2 )對複晶矽的蝕刻選擇比為丨· 7。 綜上所述,本發明所提供之用於蝕刻金屬化合物介電 層的蝕刻劑,有三種主要組成配方,第一種是由含齒素氣 體所組成,第二種是由含齒素氣體和惰性氣體所組成,第 三種是由含齒素氣體、惰性氣體和氧化劑氣體所組成。此 蝕刻劑其金屬化合物介電層對矽材質層具有良好的蝕刻選 擇比,可達2以上,而且此蝕刻劑對金屬化合物介電層的0503-8564TWf: TSMC2002-0405: Amy.ptd Page 10 569347 V. Description of the invention (8) The power is 600 watts (W) and the bias voltage is 200 watts (W). Etching results: (a) the etching rate of hafnium oxide (Hf02) is 306A / min (Angstroms / minute), and the uniformity is 5.7%; (b) the remaining rate of polycrystalline stone is 98A / min, The uniformity is 14.7%; (c) The remaining selection ratio of hafnium oxide (H f 〇 2) to polycrystalline silicon is 3.1. Example 3 The metal silicide layer to be etched is hafnium oxide (jj f 〇 2). Remaining conditions ·· The composition of the etching gas vessel is CF4 / 02 / Ar, the flow rate is 5/200/100 (seem), the pressure is 20 m Torr, and the power of the transformer voltage plasma (TCP) is 600 watts ( W) with a bias of 100 watts (w). The remaining results: (a) The etching rate of oxidation to (Hf02) is 138A / min (Angstroms / minute) 'uniformity is 5.8%; (b) The etching rate of polycrystalline silicon is 80A / min, and the uniformity is 100 / 〇; (c) The etching selectivity of the polycrystalline silicon by oxidation to (H f 〇 2) is 丨 · 7. To sum up, the etchant for etching a metal compound dielectric layer provided by the present invention has three main composition formulas, the first is composed of a tooth-containing gas and the second is composed of a tooth-containing gas and Composed of inert gas, the third is composed of tooth element gas, inert gas and oxidant gas. The metal compound dielectric layer of this etchant has a good etching selection ratio to the silicon material layer, which can reach 2 or more, and the etchant has a good effect on the metal compound dielectric layer.
0503-8564TW ; TSMC2002-0405 : Amy.ptd 第11頁 569347 五、發明說明(9) 触刻速率快。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限制本發明,任何熟習此項技藝者,在不脫離本發明之精 神和範圍内,當可做更動與潤飾,因此本發明之保護範圍 當事後附之申請專利範圍所界定者為準。0503-8564TW; TSMC2002-0405: Amy.ptd Page 11 569347 5. Description of the invention (9) The touch rate is fast. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the patent application.
0503-8564TWf ; TSMC2002-0405 ; Amy.ptd 第12頁 569347 圖式簡單說明 為讓本發明之上述目的、特徵及優點能更明顯易懂, 下文特舉一較佳實施例,並配合所附圖式,作詳細說明如 下: 第1 A圖至第1 D圖係繪示之不同製程階段的基底剖面 圖。 【符號說明】 半導體基底〜100 ; 金屬化合物介電層〜101 ; 第一閘極電極層〜102 ; 第二閘極電極層〜103 ; 閘極電極堆疊層〜104 ; 淺溝槽隔離結構〜105 ; 閘極電極〜201 ; 間隙壁〜2 0 2 ; 金屬化合物介電層暴露出的表面〜203 ; 源極/汲極〜204 ; 金屬矽化物層〜4 0 1。0503-8564TWf; TSMC2002-0405; Amy.ptd Page 12 569347 The diagram is briefly explained in order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible. The following exemplifies a preferred embodiment in conjunction with the accompanying drawings The detailed description is as follows: Figures 1A to 1D are cross-sectional views of the substrate at different stages of the process. [Symbol description] Semiconductor substrate ~ 100; metal compound dielectric layer ~ 101; first gate electrode layer ~ 102; second gate electrode layer ~ 103; gate electrode stack layer ~ 104; shallow trench isolation structure ~ 105 Gate electrode ~ 201; bulkhead ~ 202; exposed surface of metal compound dielectric layer ~ 203; source / drain ~ 204; metal silicide layer ~ 401.
0503-8564TWf ; TSMC2002-0405 ; Amy.ptd 第13頁0503-8564TWf; TSMC2002-0405; Amy.ptd page 13
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