TW569238B - Noise-immune memory - Google Patents

Abstract

The present invention provides an noise-immune memory, which recognizes the accuracy of data content and the timing for an external system to capture the data by inspecting whether the predetermined signal preset in the memory is correct when the data in the memory is being read. The present invention comprises: a word line decoder, a bit line decoder, a memory cell array, a sensing amplifier unit and a control unit, which is characterized in further comprising a preset signal unit for providing a set of 2<m> preset signals for being transmitted to the control unit via the sensing amplifier unit. The control unit determines the accuracy of the data outputted from the sensing amplifier unit by detecting the preset signal and generates an output signal to notify the external system of such, wherein the parameter m is a positive integer larger than 0 and represents the bit number of the memory cells in the memory cell array.

Description

569238 V. Description of the invention (1) Field of the invention: The present invention relates to a memory reading device μ, especially to an anti-noise memory that can use the correctness of a preset signal to ensure the correctness of data. Background of the Invention: In digital systems, the correctness of data has always played a very important role. However, in the current environment, noise interference is unavoidable, so how can the system more efficiently detect the interference due to interference early? It is the goal of all R & D personnel to cause the wrong information and improve the performance of the system. In general, when reading memory data, the system often operates abnormally due to noise, interference, or other factors. Therefore, in order to solve the problem of incorrect data, the parity bit is designed in the circuit and added. At the end of the data is the most common method. This error detection technique is called parity checking. This method is to set the number of "1" in a piece of data with parity as odd or even. In general, when the number of "1" in the data is determined to be odd, it is called odd parity, and when the number of "1" in the data is set to even, it is called even parity. However, using parity check only Can detect whether the number of "1" in the data is odd or even, so when an even number of bits in the data are wrong at the same time, the wrong data will be misjudged as correct data. In addition, parity check is used. At the time, each piece of data must be added with the same bit, because

Page 4 569238 V. Description of the invention (2) ----- Later transfer of assets with the same bit;-2: c bit, but cost. And it takes a lot of time to put the system into operation: Therefore, the benefits of the present invention are: When processing a large amount of data, the data with the same bit is sent to each bit.本 .A # 11 t I pair has the same cost as the A two -...-~~ circuit. Therefore, the present invention provides _ false energy or not to ensure the correctness of the data: :: using the correct force of the preset signal, and further "Miscellaneous" to improve the system "Purpose of the invention The present invention is described by the preset letter, whether it is true or not, the memory data is issued by the parity of the device. Line access: 2 The main purpose is to provide the correctness of the anti-noise recorder T number, w &gt; μ A ^ body, which can be borrowed to achieve the purpose of anti-noise, Wen Wen stopped the resistance provided by the invention Miscellaneous can be further pre-defined; the output of the data is positive function "understand" and then achieve the correct reading of the record another provides a kind of anti-noise record 愔 #

Ming Erji also does not require additional calculations and storage space; ",, the correctness of Xu Ming, g, J, with n a kind of anti-noise memory, by the notification system for proper processing. Correspondence; memory, can be preset by judgment. Letter, Yiting For the purpose of anti-noise, the device includes an array of characters, two devices, a memory cell array'-position sensing amplifier, a control unit, which is 569238. The word in the description of the invention (3) A meta-line decoder generates an address parameter, which decodes the address through a character line; and according to the decoded address input by the external system; where the record (ce 1 1) is used to store the data first; The first memory data and the bit data; wherein the sensing puts the second memory data, and the unit generates a reading signal with a sense amplifier. The unit number is used to provide a group to the control unit, the control amplifier. The unit outputs data to the external system, and the correctness of the external system. If a preset signal change is made, the present invention can take advantage of noise interference, and allow the external system to properly decode the main bit through the word line to decode the bit. Somatic cell The column receives the word line, the bit line, and the pass line decoding unit, which is based on the decoder produced by the external system to further generate a decoder for decoding. The number is then used to generate a bit line. The memory unit decodes the address, and the gate array is used to receive and read to generate a third memory data; its unit is connected, and its main special preset signal is used to control the correctness of the unit by detecting the material and by testing the number The external noise is detected by detecting the preset to notify the external strain. And generating a receiving signal and generating a second memory fetching signal and controlling the receiving a reading parameter and sign including a preset signal by sensing and amplifying the preset signal to generate an output preset signal to judge interference After pre-signaling, it is learned that the system data is not a unit, the signal is sent, the signal is sensed, and the signal is set to change the data. The data can be correct. Detailed descriptions and preferred embodiments are provided. Regarding the present invention, the technology, Means and specific structural features, here is a preferred and feasible embodiment, and by

Page 6 569238 V. Description of the invention (4) The illustration is further revealed and illustrated, as detailed below. Please refer to the schematic diagram of the structure of FIG. 1. The present invention provides an anti-noise memory, which can achieve the purpose of anti-noise by presetting the correctness of the signal. The device includes a word line decoder 1 1. A bit line decoder 1 2, a memory cell array 1 3, a bit line access gate array 1 4, a sense amplifier unit 15, a control unit 16, wherein the word line decoder 1 1 It is used for decoding. When an address parameter 10 generated by an external system is decoded by the word line decoder 11 and a word line decoding address 1 1 1 is further generated, wherein the bit line decoder 12 is used for decoding, and a bit line decoding address 1 2 1 is generated according to an address parameter 1 0 input from an external system; wherein the memory cell array 13 is mainly composed of a memory unit (mem 〇 ryce 1 1) is used to receive the word line decoding address 1 1 1 and generate a first memory data 1 3 1; wherein the bit line pass gate array 14 is used to receive the first memory Data 1 3 1 and the bit line decode address 1 2 1 and generate a second memory data 1 4 1; The sense amplifier unit 15 is configured to receive the read signal 16 1 and the second memory data 1 4 1 and generate a third memory data 1 5 1; wherein the control unit 16 and the sense amplifier unit 1 5 connection for receiving a reading parameter 1 6 4 and generating the reading signal 1 6 1 of which a preset signal unit 18 is used to provide a state of "1" and another state of "0" The preset signal, where the preset signal 17 is disturbed and changed to other states, indicates that the third memory data 1 5 1 may have an error. The preset signal 17 is transmitted to the control unit 16 through the sense amplifier unit 15 The control unit 16 determines whether it is disturbed by noise by detecting the preset signal 17 and generates an output signal 1 6 2 notification

Page 7 569238 V. Description of the invention (5) The external system, so the external system can judge the correctness of the data by the result of the preset signal 17. If the preset signal is disturbed by external noise, the preset signal is changed. By detecting the preset signal, it can be known that the data may be disturbed by noise, and then notify the external system that the data is not correct and painful, so that the external system can respond appropriately, such as re-reading the data. In addition, the control unit of the present invention may further include a data capture signal 1 6 3, and when the third memory data 1 5 1 is ready for use by an external system, the control system may generate a data capture signal 1 6 3 to notify the external system, The external system can receive the data capture signal 1 6 3 to read the third memory data 1 5 1 ′ of the present invention, thereby improving the data reading speed and improving the traditional external system to read the data after staying for a specific time. characteristic. In other words, when the external system needs to read the data of the present invention, the external system can send a reading parameter 16 to the control unit 16 and the external system sends a bit = parameter 1 to the word line decoder.丨 丨 and bit line decoder i 2 to select the required reading data. When the control unit 丨 6 receives the reading parameter 164, it sends out a reading signal 161 to notify the sense amplifier unit 15. The controller unit 15 can transmit the preset signal to the control unit 16 to obtain the second and second line exhaustion device 11 and the bit line decoder 12, and the selected reading unit 2 controls the unit 16 by receiving the preset signal 7 63 63 notification externalities, the present invention may further include the memory data of the data capture platform, to read the selected memory cell display 1 3 ^ Figure 2 Another preferred embodiment of the present invention, This invention provides

569238 5. Description of the invention (6) An anti-noise memory, which can achieve the purpose of anti-noise by presetting the correctness of the signal. The device includes a word line decoder and a bit line decoder. 2 2. A memory cell array 2 3. A bit line pass gate array 2 4. A sense amplifier unit 2 5. A control unit 26. The word line decoder 21 is used for decoding. An address parameter 20 generated by an external system is decoded by the word line decoder 21 and a word line decoding address 2 1 1 is further generated; wherein the bit line decoder 2 2 is used for decoding According to an address parameter 20 inputted from an external system, a one-bit line decoding address 2 2 1 is generated; wherein the memory cell array 23 is mainly composed of a memory unit (mem 0ryce 1 1) To receive the word line decoded address 2 1 1 and generate a first memory data 2 3 1; wherein the bit line pass gate array 24 is used to receive the first memory data 2 3 1 and the The bit line decodes the address 2 2 1 and generates a second memory data 2 4 1. 2 5 is used to receive the read signal 2 6 1 and the second memory data 2 4 1 and generate a third memory data 2 5 1; wherein the control unit 26 is connected to the sense amplifier unit 25, and In order to receive a reading parameter 2 6 4 and generate the reading signal 2 6 1, in this embodiment, a preset signal unit 2 8 is used to provide a preset signal 2 7, which includes “0 0” and “0 1 "," 0 1 "," 1 1 "status, the preset signal 2 7 is transmitted to the control unit 2 6 through the sense amplifier unit 2 5 unit, and the control unit 2 6 detects the status of the preset signal 2 7 It determines whether the noise is disturbed by noise and generates an output signal 2 6 2 to notify the external system. If the preset signal is disturbed by external noise, the preset signal of the preset signal changes, indicating that the data may also be interfered by noise, so the external system is notified that the data is incorrect.

Page 9 569238 V. Description of Invention (7) to allow external systems to respond appropriately. In addition, the control unit of the present invention may further include a data capture signal 2 6 3. When the third memory data 2 5 1 is ready for use by an external system, the control system may generate a data capture signal 2 6 3 to notify the external system. The external system can read the third memory data 2 51 of the present invention by receiving the data capture signal 2 6 3, thereby improving the data reading speed and improving the traditional external system to read the data after staying for a specific time. Characteristics. In other words, when the external system needs to read the data of the present invention, the external system can transmit a read parameter 2 64 to the control unit 26, and the external system transmits a bit address parameter 20 to the word line decoder 2 1 and bit line decoder 2 2 to select the required reading data, and when the control unit 2 6 receives the reading parameter 2 6 4, it sends out a reading signal 2 6 1 to notify the sense amplifier unit 2 5, The sense amplifier unit 25 can then transmit the preset signal to the control unit 2 6 and output the selected read data from the word line decoder 21 and the bit line decoder 2 2, of which the control unit 26 borrows The correctness of the output data is detected by receiving the preset signal 27. The present invention may further include a data capture signal 2 6 3 to notify an external system to read the memory data in the selected memory cell array 23.

The composition unit of the preset signal unit of the present invention can have different implementations, as long as it can provide a preset signal, it is applicable. The use of a memory cell is the most direct and convenient method, and FIG. An embodiment in which the memory element provides a preset signal in a preset 彳 55 tiger early element. As shown in FIG. 3, this structure includes a voltage dividing circuit 3 composed of a transistor (τ 丨) 3 3, a first resistor (Rl) 3 1 and a first resistor (R2) 3 2.

Page 10 569238 5. Description of the invention (8), the voltage dividing circuit is coupled to a voltage source (VCC) and a ground terminal (GND), wherein the voltage dividing circuit 30 has an intermediate node &gt; (N 1 ) 34, which is coupled to the transistor, wherein the partial voltage of the intermediate node is: K. In the present invention, the conduction characteristics of the memory cells can be controlled by controlling the partial voltage of the intermediate node, so the present invention can control the memory by Cell conduction characteristics and control of related parameters in the transistor, such as: aspect ratio (W / L rat io), further control the logic level, current level and anti-noise sensitivity of the preset signal 17 generated. 1. The preset signal unit in the present invention has at least the following implementations. The preset signal unit includes a complex array memory unit, and a group of memory units includes at least one memory unit, for example, a memory cell. Preferably, the memory cell array forms a memory cell array. Each group of memory cells corresponds to each character line. 2. The preset signal unit includes a group of memory units, and the group of memory units includes at least one memory unit, such as a memory cell or the structure shown in FIG. From the above, the preset signal unit of the present invention can generate a set signal to be transmitted to the control unit via the sense amplifier unit, and the control unit judges the correctness of the output data of the sense amplifier unit by detecting the preset signal and generates An output signal informs the external system, where the parameter m is a positive integer greater than 0 and is the number of bits represented by the memory cell in the memory cell array. The preset signal units 1 8 and 2 8 of the present invention can be stored by memory

569238 V. Description of the invention (9) The unit stores data, and the column 1 3, 2 3; among them, the preset resistance is used to simulate the storage of a small transistor and at least one for further improvement. The unit should be located in the memory position or the Memory cells Therefore, the present invention improves the correctness of the preset signal. It is said that the accuracy provided by the present invention can be reduced by unnecessary circuits. Therefore, the present invention can signal and does not transmit circuit complexity. Capture data within the output time. The digital circuit completed by Level Design F1ow c has the characteristics of false signals. Therefore, in the design of directly using the preset signal system, it is beneficial. The present invention "anti-noise record has excellent practicality, novelty, and can be The preset signal unit can also be a memory cell array signal. The unit can be coupled to a material by a transistor and can also be composed of at least a transistor circuit or a resistor. The sensitivity to noise of the invention is preset Signal somatic cell array is easy to be disturbed by noise in the array. Provides an anti-noise memory, which can be used to achieve the purpose of anti-noise by judging, and further anti-noise memory. The positive sign of the output data shows that it is not necessary to use the parity bit to reduce the effect of improving performance. According to the needs of the system, a set of 2 ^ preset data is changed to change the preset signal. The reduction can also be reduced by Judging that the output capture signal is the shortest. The circuit of the present invention can be completely composed of logic gates and is also suitable for High-designed with HDL. Besides, the present invention can detect errors and is very suitable for application. The memory read device judges the correctness of the data. Therefore, the range of use in the digital system will be very broad. In summary, the memory "is a reasonable and perfect invention, not only an unprecedented innovation in design, but also Completed by digital circuits of logic gate level

Page 12 569238 V. Description of invention (ίο) Further achieving the anti-noise function is also a high invention that breaks through the conventional technology. It is not a simple application that can be easily considered and is progressive. Therefore, this case has already met the invention patent. It is my sincere prayer that the bureau should scrutinize the various application requirements and grant the patents it deserves. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Anyone familiar with the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application

Page 13 569238 Brief description of the drawings: Figure 1 is a schematic diagram of an anti-noise memory architecture according to an embodiment of the present invention; Figure 2 is a schematic diagram of an anti-noise memory architecture according to another embodiment of the present invention; And FIG. 3 illustrates the composition of the preset signal unit according to the present invention. Explanation of main component symbols: -η,-17, -12, -161 -13 ^ -3 21 27 22 261 23 word line decoder ----- preset signal --------- bit Line Decoder ----- Read Signal --------- Memory Cell Array--Memory Cell (ce 1 1) Bit Line Gate Array--14 '24 Transistor (Τ1) ------- ---- 33 sense amplifier unit ---- --- 15 ^ 25 first resistor (R1) ----- --- 31 control unit --- 16 '26 Second resistor (R2) ----- --- 32 address parameter--10, 20 voltage divider circuit-30 word line decoding address-111, • 21 Middle point (N1)- --- --- 34 ♦

Page 14 569238 The diagram briefly explains the bit line decoding address ---- 121 &gt; 221 First memory resource bucket ----- ---- 13 Bu 231 Second memory resource # --- ----- 14 Bu 241 Third memory data ------ ---- 15 Bu 251 Read parameters ---- 164, 264 Data capture signal ------ 163, 263 output signal ---- 162, 262 preset signal unit ---- 18, 28

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Claims (1)

569238 6. Scope of patent application1. One word address, one decode, one record, memory data, one sense data, one control, and other special signal elements, zoom in 2. According to the letter 3. The signal is "4. The signal Memory element line deduplication element line decomposition address; memory body is detailed for data; one is enlarged with the position measurement, and the number of production units and production characteristics is that the special application number of the controller unit includes the application department. Two 1 ". The application department consists of four, including: encoder—according to the cell array, receiving the word bit line through the element line decoder unit, generating a third, and sensing the reading which includes a set signal through the unit according to the output data The 2m data of the range of interest is used to generate a word line decoder for the address parameter constructed by the state of the range of interest. The bit line is generated according to the address parameter and is decoded by the memory line (mem 0ryce 1 1). Address and generate a first gate array for receiving the first memory address and generate a second memory data; for receiving a read signal and the second memory memory data; and connecting the amplifier unit, It is used for receiving a read signal. A preset signal unit is used to provide whether the preset signal transmitted from the sense amplifier unit to the control unit is correct to determine the correctness of the sensing. The memory of item 1, wherein the set of pre, m is a positive integer greater than or equal to zero. The memory described in item 1, wherein the preset state is "0" in one state, and the memory described in item 1 in the other state, wherein the preset states "00", "01", "10", "11" Page 16 569238 Fan Fan Li Special Application Please apply for 6 N 1 A Fan C Fan Li Li and one special. Please go to Cheng Shenyou's system to rely on the 5 institutions D to remember the record, the} R in the ο, C, the gate body or the memory as little as the description, control and control its meaning. Items written by the group description &gt; item τ 1 ο Nth gate of the C gate, please refrain from applying for evidence and presume its body memory according to the 6th assumption 己-words to get 之 grab households Η items 1 The first perimeter student Fan Lili stepped in to apply for the Shenyuan bill, according to the group's electric circuit, Jingdian, the first shouwei sheet to Fancheng Youli, the special order, and the application number is believed to be based on the 8th body. The item in the description of 〇 is set to the Yuandan # of the group, which includes package position 1 and the voltage distribution of the body crystal group is set to be set in the paragraph of the body. According to Cheng Yi, this is expected. The location and interference of the bit are so complicated that it is easy to be included in the bit number of the system. It is specifically described in the description of it. According to the report, it is mixed with the bit of the system f. Di Wei Fan rnj Spear specially requested the code according to the code solution set by Jtub letter. The detailed description of the preset It It * νδ to the coping style Fan Li special request the application according to the order &amp; | ° letter set should be set by the letter set to pre-produce the cells of the institute, Body memory memory ο 生 之 之 定 定 项 中 中 元 元 元 元 元 元 元 元 元 元 元 元 3 3 3 3 3 3 3 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 所述 所述 所述 所述 所述 所述 所述 所述 所述 所述 所述 所述 所述 所述 所述 所述 所述 所述 所述 所述 in the first paragraph of the scope of the patent application, wherein the preset signal unit is through the memory unit (mem 〇ryce 1 1) Stored data ο 1 4. According to the memory described in item 7 of the scope of patent application, wherein the preset Page 17 569238 6. Scope of patent application The composition of the signal unit is a memory cell array. 1 5. According to the memory described in item 1 of the scope of the patent application ... wherein the preset signal unit is coupled to a voltage divider circuit by a transistor to simulate storing a data.