TW567600B - A package with a heat sink - Google Patents

A package with a heat sink Download PDF

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Publication number
TW567600B
TW567600B TW091125099A TW91125099A TW567600B TW 567600 B TW567600 B TW 567600B TW 091125099 A TW091125099 A TW 091125099A TW 91125099 A TW91125099 A TW 91125099A TW 567600 B TW567600 B TW 567600B
Authority
TW
Taiwan
Prior art keywords
heat dissipation
substrate
package
dissipation member
scope
Prior art date
Application number
TW091125099A
Other languages
Chinese (zh)
Inventor
Sung-Mao Wu
Original Assignee
Advanced Semiconductor Eng
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Publication date
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Priority to TW091125099A priority Critical patent/TW567600B/en
Application granted granted Critical
Publication of TW567600B publication Critical patent/TW567600B/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

A package with a heat sink, is suited for disposing on a motherboard. The package includes a substrate, a first package module, multiple second package modules, a heat sink and solders. The substrate has a first surface and a second surface, the first package module is disposed on the fist surface and the second package module is disposed on the second surface. The heat sink is disposed on the first package module, and has a first portion and a second portion. The first portion is located on the first package module, and the second portion is vertical to the first portion and trends toward the substrate and some area of the second portion is faced to the sidewalls of the substrate. The solders are disposed on the first surface of the substrate, and the substrate is electrically coupled to the motherboard by the solders.

Description

567600567600

是有關於一種且右私為碰& 一 # 1 1 /、有政熱構件之封裝結構,且特 種具有散熱構件配置在底部封裝模組上的封 體產業中,積+ 貝篮電路(Integrated Circu 1 ts, ,主要分為三個階段··裸晶片(die)的製造、積 、、=作以及積體電路(IC)的封裝(Package) 棵晶片係經由晶圓(Wafer)製作、電路設計、 及切割晶圓等步驟而完成,而每一顆由晶圓切 裸晶片,經由裸晶片上之焊墊(B〇nding Pad) 電性連接後’再以封膠材料將裸晶片包覆著, 的在於防止裸晶片受到濕氣、熱量、雜訊的影 裸晶片與外部電路,比如與印刷電路板 Ucuit Board, PCB)或其他封裝用基板之間電 介’如此即完成積體電路的封裝(Package)步 本發明 別是有關於 裝結構。 在半導 ic)的生產 體電路(1C) 等。其中, 光罩製作以 割所形成的 與外部訊號 其封裝之目 響,並提供 (Printed C 性連接的媒 驟0 為了連接上述之裸晶片和封裝用基板,通常會使用導 線(W i r e )及/或焊球(b u m p )作為接合之媒介。其中,覆晶 接合技術(Flip chip Interconnect Technology)即是在 裸晶片之焊墊上以陣列排列的方式形成焊球,接著再將晶 片翻覆之後,利用晶片上之焊球分別對應連接至封裝用基 板上的接點,使得晶片可經由焊球而電性連接至封裝用基 板’再經由封裝用基板之内部線路及表面之接點而與外部 訊號電性連接。因此,隨著晶片的積集度的增加,晶片的 封裝結構也是越來越多樣化,利用上述的覆晶接合技術之It is related to a type of packaging structure with a right-handed & a # 1 1 /, a thermal structure of a political component, and a special package industry with a heat dissipation component configured on the bottom packaging module. Circu 1 ts, is mainly divided into three stages: Bare wafer (die) manufacturing, fabrication, fabrication, and packaging of integrated circuit (IC) packages. Chips are produced through wafers and circuits. The design and cutting of the wafer are completed, and each of the bare wafers is cut from the wafer, electrically connected through the bonding pad on the bare wafer, and then the bare wafer is covered with a sealing material. The purpose is to prevent the bare chip from being exposed to moisture, heat, and noise. The dielectric between the bare chip and external circuits, such as the printed circuit board (Ucuit Board, PCB) or other packaging substrates, thus completes the integrated circuit. Package Step The present invention is particularly related to a package structure. Production of semiconductor circuits (1C) in semiconductor (ic). Among them, the photomask is formed by cutting and forming a package with external signals, and provides (Printed C-type media. In order to connect the bare chip and the packaging substrate described above, wires and wires are usually used.) / Or bump (bump) as the bonding medium. Among them, Flip chip Interconnect Technology (Flip chip Interconnect Technology) is to form solder balls in an array arrangement on the pads of the bare wafer, and then use the wafer after flipping the wafer The solder balls on the substrate are correspondingly connected to the contacts on the packaging substrate, so that the chip can be electrically connected to the packaging substrate through the solder balls, and then electrically connected to the external signals through the internal circuit and surface contacts of the packaging substrate. Therefore, with the increase of the accumulation degree of the chip, the package structure of the chip is also becoming more and more diversified.

10037twf1.ptc 第6頁 567600 -- 案號91125099_年月日__ 五、發明說明(2) 晶片封裝結構,其具有縮小晶片封裝面積及縮短訊號傳輸 路径等優點,目前已經廣泛應用於晶片封裝領域,例如晶 片尺寸構裝(Chip Scale Package, CSP)、球格陣列封裝 (Ball Grid Array, BGA)以及多晶片模組封裝 (Multi-Chip Module, MCM)等型態的封裝模組,均是覆晶 接合技術所應用的範疇。其中,多晶片模組封裝係例如將 數個晶片尺寸封裝(CSP)之型態的封裝模組,以覆晶接合 技術構裝且集合在一塊基板上,且封裝模組之間藉由基板 而彼此電性連接,以構成一具有不同功能的多封裝模組之 封裝結構。 以動態隨機存取記憶體(dynamic random access memory ,DRAM)以及中央處理器(CPU)為例,利用多晶片模 組封裝(MCM)的封裝結構可將多個DRAM以及中央處理曰曰、 (CPU)封裝在同一個基板上,如此不僅提高構裴六 态 少空間需求,也降低了封裝模組之間訊號延遲〜的^又、減 達到高速處理的目的,因此廣泛被應用在通万現象,以 子產品中。 攜帶式電 第1 A圖繪示習知具有多封裝模組之封裝結 母板1 0的側視示意圖。請參照第丨A圖,其包括一配置於一 1 0 0、一第一封裝模組丨丨〇以及多個第二封骏模矣基板 中基板1 0 0之二表面丨〇 2、i 〇 4上分別具有多個、接且1 2 〇 ,其 10 3b,用以作為基板1〇()之輸出入媒介。此外,gl〇3a、 模組1 1 0以及第二封裝模組丨丨2分別配置於基板1 〇 ~封骏 面102、104,而第一封裝模組iiq例如為中央處王之一表10037twf1.ptc Page 6 567600-Case No. 91125099_year month day__ V. Description of the invention (2) Chip package structure, which has the advantages of reducing chip package area and shortening signal transmission path, etc., has been widely used in chip packaging Fields, such as Chip Scale Package (CSP), Ball Grid Array (BGA), and Multi-Chip Module (MCM) packages Applications of flip-chip bonding technology. Among them, the multi-chip module package is, for example, a package module of a plurality of chip size packages (CSP), which is configured by flip-chip bonding technology and is integrated on a substrate, and the package modules are separated by the substrate. They are electrically connected to each other to form a packaging structure of a multi-package module with different functions. Taking dynamic random access memory (DRAM) and central processing unit (CPU) as examples, a multi-chip module package (MCM) package structure can be used to integrate multiple DRAMs and central processing units (CPUs). ) Encapsulated on the same substrate, this not only increases the space requirement of the six-state structure, but also reduces the signal delay between the packaging modules ~ and reduces the high-speed processing. Therefore, it is widely used in the Tongwan phenomenon. To sub products. FIG. 1A shows a schematic side view of a conventional package junction motherboard 10 having a multi-package module. Please refer to FIG. 丨 A, which includes a two-side surface of the substrate 100, which is disposed on a 100, a first package module, and a plurality of second-sealed substrates. Each of 4 has a plurality of, 12 and 10, 10 3b, which is used as the input and output medium of the substrate 10 (). In addition, gl03a, module 1 10, and the second package module 丨 2 are respectively arranged on the substrate 10 to the seal surface 102, 104, and the first package module iiq is, for example, one of the central kings.

567600 _案號 91125099_年 Ά__g___修正__ 五、發明說明(3) " (CPU) ’其位於基板100之下表面102的中央區域上,而第 二封裝模組1 1 2例如為動態隨機記憶體(D R A M ),其分佈於 基板100之上表面104的區域上。另外,第一、第二封裝模 組1 1 0、1 1 2例如藉由焊球1 〇6來電性連接基板丨〇〇之二表面 1 0 2、1 0 4的接點,且每一封裝模組丨〇 〇、丨丨2與基板1 〇 〇之 間’除了利用焊球1 〇 6來連接之外,還有填充材料 1 08( Underfill)填入於封裝模組10()、112'與基板1〇〇之 間,並包覆焊球106,用以分散焊球106之熱應力,以避免 封裝模組與基板之間因兩者的熱膨脹係數(c 〇 e f f丨c丨e n t of Thermal Expansion, CTE)不同所產生的拉伸應力,而 導致焊球1 06因疲勞破壞(fat igUe )而產生隙縫,並影響 封裝模組與基板之間的訊號傳輸效能。 曰 請參考第1 B圖,其繪示第1 a圖之封裝結構的下視示意 圖’‘知封裝結構之第一封封裝模組1 1 〇如中央處理器 (C P U )係電性連接於基板i 〇 〇之下表面丨〇 2的接點丨〇 3 a,且 ,板1 2 0之下表面丨〇 2還具有多個陣列排列的接點丨〇 3 b,其 藉由焊塊1 0 5與母板1 〇電性連接,用以作為基板丨〇 〇連接母 板1 0之輸出入媒介。 值得注意的是,當第一封裝模組1 1 0内部之晶片在高 頻運作下’由於晶片會產生介電耗損而產生大量的熱量, 如此將導致晶片之本身的溫度逐漸升高。當晶片之本身的 溫度一旦超出其正常的工作溫度範圍時,晶片之内部電路 I能會發生運算錯誤的現象,或是暫時性地失效。然而, 習知之第一封裝模組丨丨〇如中央處理器僅透過其表面以及567600 _Case No. 91125099_year __g___ amendment __ 5. Description of the invention (3) " (CPU) 'It is located on the central area of the lower surface 102 of the substrate 100, and the second package module 1 1 2 is dynamic, for example Random memory (DRAM) is distributed on a region of the upper surface 104 of the substrate 100. In addition, the first and second package modules 1 10 and 1 12 are electrically connected to the substrate 10 and the contacts on the surface 10 2 and 104 by the solder ball 1 06, and each package Modules 丨 〇〇, 丨 丨 2 and the substrate 1 〇 'In addition to the use of solder balls 〇 06 to connect, there are filler materials 1 08 (underfill) filled in the packaging module 10 (), 112' And the substrate 100, and the solder ball 106 is coated to disperse the thermal stress of the solder ball 106 to avoid the thermal expansion coefficient between the package module and the substrate (c oeff 丨 c 丨 ent of Thermal Expansion (CTE) produces different tensile stress, which causes solder ball 106 to produce gaps due to fatigue failure (fat igUe), and affects the signal transmission performance between the package module and the substrate. Please refer to FIG. 1B, which shows a schematic view of the package structure of FIG. 1a. `` The first package module 1 1 of the known package structure, such as a central processing unit (CPU), is electrically connected to the substrate. i 〇〇 the bottom surface 丨 〇2 contact 丨 〇 3 a, and the board 1200 below the surface 〇 02 also has a plurality of array array of contacts 丨 〇 3 b, by the solder bump 1 0 5 is electrically connected to the motherboard 10, and is used as a base board for connecting the input and output media of the motherboard 10. It is worth noting that when the chip inside the first package module 110 is operated at high frequency, a large amount of heat is generated due to the dielectric loss of the chip, which will gradually increase the temperature of the chip itself. When the temperature of the chip itself exceeds its normal operating temperature range, the internal circuit I of the chip may have a calculation error phenomenon, or may temporarily fail. However, the conventional first package module, such as the CPU, only penetrates through its surface and

10037twf1.ptc 第8頁 567600 _案號91125099_年月曰 修正_ 五、發明說明(4) 經由基板1 0 0之側壁將熱量散溢至外界,或是透過母板1 〇 來對中央處理器散熱,但此種散熱方式無法提供更大範圍 的散熱面積,導致晶片所產生之熱量無法有效散溢至外 界。 有鑑於此,本發明的目的在提出一種具有散熱構件之 封裝結構,其中散熱構件具有較大的散熱面積,而封裝結 構内部之晶片所產生的熱量可藉由散熱構件之傳導,而有 效地將熱量散溢到外界。 本發明的另一目的在提出一種散熱構件,適於配置在 多封裝模組之封裝結構上,其中散熱構件係可連接於封裝 模組之表面以及基板之側壁,如此晶片所產生的熱量可經 由封裝模組之表面以及基板之側壁,而傳導至散熱構件, 並將熱量透過散熱構件之表面而散溢至外界。 為達本發明之上述目的,提出一種具有散熱構件之封 裝結構,適於配置在一母板上,此具有散熱構件之封裝結 構主要包括一基板、一第一封裝模組、多個第二封裝模 組、散熱構件以及多個焊塊,其中基板具有一第一表面以 及對應之一第二表面,第一封裝模組係配置在基板之第一 表面上,而第二封裝模組係配置在基板之第二表面上。此 外,散熱構件係配置在第一封裝模組上,且散熱構件具有 一第一部份以及一第二部分,其中第一部份係位於第一封 裝模組上,而第二部分垂直於第一部份且第二部分的延伸 方向係朝向基板,且第二部分之部份區域係面向該基板之 側壁。另外,焊塊係配置在基板之第一表面上,藉由焊塊10037twf1.ptc Page 8 567600 _Case No. 91125099_ Year and Month Revision_ V. Description of the invention (4) The heat is dissipated to the outside through the side wall of the substrate 100, or to the CPU through the motherboard 10. Heat dissipation, but this heat dissipation method cannot provide a larger area of heat dissipation, resulting in the heat generated by the chip cannot be effectively dissipated to the outside world. In view of this, the object of the present invention is to provide a packaging structure having a heat dissipation member, wherein the heat dissipation member has a large heat dissipation area, and the heat generated by the chip inside the package structure can be efficiently conducted by the heat dissipation member. The heat escapes to the outside world. Another object of the present invention is to provide a heat dissipation member suitable for being arranged on a packaging structure of a multi-package module. The heat dissipation member can be connected to the surface of the packaging module and the side wall of the substrate. The surface of the package module and the side wall of the substrate are conducted to the heat dissipation member, and the heat is diffused to the outside through the surface of the heat dissipation member. In order to achieve the above object of the present invention, a packaging structure with a heat dissipation member is provided, which is suitable for being disposed on a motherboard. The packaging structure with the heat dissipation member mainly includes a substrate, a first packaging module, and a plurality of second packages. A module, a heat dissipation member, and a plurality of solder bumps, wherein the substrate has a first surface and a corresponding second surface, the first package module is disposed on the first surface of the substrate, and the second package module is disposed on On the second surface of the substrate. In addition, the heat dissipation member is disposed on the first package module, and the heat dissipation member has a first portion and a second portion, wherein the first portion is located on the first package module and the second portion is perpendicular to the first package module. The extending direction of one part and the second part is toward the substrate, and part of the area of the second part faces the side wall of the substrate. In addition, the solder bumps are arranged on the first surface of the substrate,

10037twf1.ptc 第9頁 567600 _案號91125099_年月曰 修正_ 五、發明說明(5) 可將基板與母板接合並與母板電性連接。 依照本發明一較佳實施例,第一封裝模組例如位在基 板之第一表面的中央區域上,而散熱構件之第一部份例如 為一條狀形的構件,或是由二條狀構件所構成之一十字形 的樣式,且十字形的交叉區域係配置在第一封裝模組上。 另外,散熱構件之第二部份例如透過一焊料與基板之側壁 接合。 為讓本發明之上述目的、特徵、和優點能更明顯易 懂,下文特舉一較佳實施例,並配合所附圖式,作詳細說 明如下: 圖式之標示說明: 1 0 :母板 1 0 0、2 0 0、3 0 0、3 0 0 a、3 0 0 b :基板 102 、202 、302 、302a > 302b :第一表面 1 0 3 a、1 0 3 b、2 0 3 a、2 0 3 b、··接點 104 、 204 、 304 :第二表面 1 0 5 :焊塊 1 0 6、2 0 6 :焊球 1 0 8、2 0 8 :填充材料 1 1 0、2 1 0、3 1 0、3 1 0 a、3 1 0 b ··第一封裝模組 1 1 2、2 2 0、3 2 0 :第二封裝模組 207 :晶片 2 3 0、3 3 0、3 3 0 a :散熱構件 232、332 :第一部份10037twf1.ptc Page 9 567600 _Case No. 91125099_ Year Month Amendment _ V. Description of the invention (5) The substrate can be bonded to the motherboard and electrically connected to the motherboard. According to a preferred embodiment of the present invention, the first package module is, for example, located on a central region of the first surface of the substrate, and the first part of the heat dissipation member is, for example, a strip-shaped member, or is formed by two strip-shaped members. A cross-shaped pattern is formed, and the cross-shaped crossing area is disposed on the first package module. In addition, the second portion of the heat dissipation member is bonded to the side wall of the substrate, for example, by a solder. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Marking description of the drawings: 1 0: Motherboard 1 0 0, 2 0 0, 3 0 0, 3 0 0 a, 3 0 0 b: substrates 102, 202, 302, 302a > 302b: first surface 1 0 3 a, 1 0 3 b, 2 0 3 a, 2 0 3 b, ... contact 104, 204, 304: second surface 1 0 5: solder bump 1 0 6, 2 0 6: solder ball 1 0 8, 2 0 8: filling material 1 1 0, 2 1 0, 3 1 0, 3 1 0 a, 3 1 0 b ·· First package module 1 1 2, 2 2 0, 3 2 0: Second package module 207: Chip 2 3 0, 3 3 0, 3 3 0 a: heat dissipation members 232, 332: first part

10037twf1.ptc 第10頁 567600 案號 91125099 曰 修正 五、發明說明(6) 234 、 334 236 240 250 252 338 P : ^ 3 3 6 : 、3 4 0、 > 3 5 0 : :槽道 、3 3 8 a 接合處 第二 焊料 3 4 0 a 側壁 份 3 4 0 b :焊塊 父叉區域 第 •實施例 第2 A圖繪示本發明第一實施例之一種具有散熱構件之 封裝結構配置於一母板丨〇的側視示意圖以及接合處'p美 ^側,的放大圖。第2B緣示本發明第2 A圖裝土 其:考第2A圖,此具有散熱構件之封裝】:主 括一基板2 0 0、一第一封裝模組2 i 〇、 r #2r" ^ ^24°5 ^ ^ ϊΐ 么且η一彳對應之一第二表面2 0 4,而第一封裝模 —夺面1尺寸構裳(CSP),其配置在基板2 0 0之第 尺4構f (CSP中)ΐ域上,而第二封裝模組22〇例如為晶片 卜,f ft Sp),/、配置在基板20◦之第二表面2 0 4的區域 接點2 0 3土板Γ丄之第—、二表面2〇2、2〇4上分別具有多個 接點2〇=、2〇3_b,用以作為基板2 0 0之輸出入媒介。 9 η 7 ,、,企/卜//第一、第二封裝模組2 1 0、2 2 0例如具有—晶片 9 η η φ认!個焊球2 〇 6,而藉由焊球2 0 6可使晶片2 0 7與基板 電,連接,用以分別電性連接基板2〇〇之第一、二表面 〇4的接點2 0 3a ’且每一封裝模組21 〇、22〇與基板10037twf1.ptc Page 10 567600 Case No. 91125099 Amendment V. Description of Invention (6) 234, 334 236 240 250 252 338 P: ^ 3 3 6:, 3 4 0, > 3 5 0:: channel, 3 3 8 a Second solder at the joint 3 4 0 a Side wall portion 3 4 0 b: Parent fork area of the solder bumps Embodiment 2A illustrates a packaging structure having a heat dissipation member according to the first embodiment of the present invention. A schematic side view of a mother board, and an enlarged view of the joint side. Figure 2B shows the installation of Figure 2A of the present invention. Consider Figure 2A. This package has a heat dissipation component.]: It includes a substrate 2 0 0, a first package module 2 i 〇, r # 2r " ^ ^ 24 ° 5 ^ ^ ϊΐ and η corresponds to one of the second surface 2 0 4 and the first packaging mold—the surface 1 size structure (CSP), is arranged on the substrate 4 0 4th structure f (in CSP), and the second package module 22 is, for example, a wafer chip, f ft Sp), and / or is disposed on the second surface 2 0 4 of the substrate 20 and the area contact 2 0 3 is a soil plate. The first and second surfaces of Γ 丄 have a plurality of contacts 20 =, 203_b on the two surfaces 202 and 204 respectively, which are used as the input and output medium of the substrate 200. 9 η 7 ,,, / / / / the first and second package modules 2 1 0, 2 2 0, for example, has a chip 9 η η φ recognizes a solder ball 2 0, and by the solder ball 2 0 6 The chip 2 07 can be electrically connected to the substrate, and is used to electrically connect the contacts 2 0 3a of the first and second surfaces 0 4 of the substrate 2000, and each package module 21 0, 22 0 and Substrate

567600 月 修正 曰 皇號911250卯 五、發明說明(7) 2 〇 0之間,除了利用焊球2 〇 6來連接之外,還有填充材料 208(UnderfiU)填入於晶片207與基板2〇〇之間,且包覆著 焊球2 0 6。 ^ π f 請同時參考第2A以及2B圖,其中第一封裝模組21〇例 t為中ί處理器(CPU),而第二封裝模組2 2 0例如為動態隨 機圮憶體(DRAM),且散熱構件2 3 0例如配置在第一封裝模 組2 1 上,其係由第一封裝模組2丨〇的兩側向外延伸,用以 ,收第一封裝模組2 1 〇如中央處理器所產生之熱量,並將 熱量透過散熱構件2 3 0向外料,而由散熱構件23〇之表面 =及兩側將熱量散逸至外界。因&,散熱構件2 3 Q可提供 ^ 一封裝模組2 1 0較大的散熱面積,且散熱性佳,使得熱 量不會過度集中在第一封裝模組2丨〇如中央處理器上,而 造成晶片之溫度超出其正常的工作溫度範圍。此外,散熱 構件2 3 0之材質例如為鋁、鋼或是其他散熱性佳的材質, 因此可迅速地將熱量由散熱構件23〇的表面散逸,藉以提 高中央處理器的散熱效能。 同樣請參考第2 A以及2 B圖,散熱構件2 3 〇例如具有一 第一部份2 3 2以及一第二部份2 3 4,其中第一部份232例如 為一條狀形的構件,其係由第一封裝模組2丨〇之兩側向外 延伸至大約與基板2 0 0之寬度相當,用以將第一封裝模組 210如中央處理器所產生的熱量,經由第一部份2 3 2之表面 以及兩端散逸。此外,第二部份2 34例如垂直於第一部份 232且連接於第一部份2 3 2之兩端,並且第二部份2 34係由 第-部份2 3 2之兩端向基板2〇0之側壁25〇延伸,以構成一In the month of 567600, the emperor 911250 was revised. 5. Description of the invention (7) 2000. In addition to the solder ball 206 for connection, a filler material 208 (UnderfiU) was filled in the wafer 207 and the substrate 2 〇, and covered with solder balls 206. ^ π f Please refer to Figures 2A and 2B at the same time, where the first package module 21 is a CPU and the second package module 2 2 0 is, for example, a dynamic random memory (DRAM). The heat dissipating member 2 3 0 is, for example, configured on the first packaging module 2 1, and it is extended outward from both sides of the first packaging module 2 丨 0, so as to receive the first packaging module 2 1 〇 The heat generated by the central processing unit passes the heat to the outside through the heat dissipation member 230, and the surface of the heat dissipation member 23 and the two sides dissipate the heat to the outside. Because of &, the heat dissipation member 2 3 Q can provide a large heat dissipation area of a package module 2 1 0 and good heat dissipation, so that the heat will not be excessively concentrated on the first package module 2 such as a central processing unit. , And the temperature of the chip exceeds its normal operating temperature range. In addition, the material of the heat dissipating member 230 is, for example, aluminum, steel, or other materials with good heat dissipating properties, so heat can be quickly dissipated from the surface of the heat dissipating member 23o, thereby improving the heat dissipation efficiency of the CPU. Please also refer to FIGS. 2A and 2B. The heat dissipation member 2 3 0 has a first portion 2 3 2 and a second portion 2 3 4. The first portion 232 is, for example, a strip-shaped member. It extends outward from both sides of the first packaging module 2 丨 0 to approximately the width of the substrate 200, and is used to pass the heat generated by the first packaging module 210, such as a central processing unit, through the first section. The surface and ends of part 2 3 2 are scattered. In addition, the second part 2 34 is, for example, perpendicular to the first part 232 and is connected to both ends of the first part 2 3 2, and the second part 2 34 is directed from both ends of the first part 2 3 2 The side wall 25 of the substrate 200 is extended to form a

10037twf1.ptc 第12頁 567600 _ 案號91125099 车 η pi 修正 五、發明說明(8) 倒门字型的散熱構件2 3 0,可以使散熱構件2 3 0之散熱面積 再加以延伸,使得散熱構件2 3 0具有更佳的散熱效果。另 外’焊塊2 4 0係配置在基板2〇〇之第一表面2 0 2上,且連接 第一表面2 0 2之接點2 0 3b,藉由焊塊2 4 0可將基板2 0 0與母 板1 0接合並與母板1 0電性連接。 再者,請參考第2A圖中接合處p之基板2 0 0側壁的放大 圖,基板2 0 0之側壁2 5 0可為一平坦的表面或基板2 0 0之側 壁2 5 0具有一槽道2 5 2,而散熱構件2 3 0之第二部份2 3 4可透 過一焊料2 3 6與基板2 0 0之側壁2 5 0接合。在製作過程上, 係先將焊料2 3 6塗佈在側壁2 5 0的表面上及槽道2 5 2中,再 將散熱構件2 3 0裝配到基板2 0 0上及第一封裝模組2 1 〇上, 其中散熱構件2 3 0的第二部份2 3 4會藉由焊料2 3 6與基板200 之側壁2 5 0黏合。接著,再進行迴焊的步驟,使得散熱構 件2 3 0之第二部份2 3 4藉由焊料2 3 6可以與基板2〇〇之側壁 2 5 0緊密接合。然而,在較佳的情況下,基板2 〇 〇之側壁 2 5 0要配置有槽道2 5 2,其可以增加焊料2 3 6與基板2 〇 〇之側 壁2 5 0間的接觸面積,並且焊料2 3 6會填入於槽道2 5 2中, 使得焊料2 3 6會形成多個凸起(未繪示)以卡入"到槽道2 5 2’ 中’而能夠提高散熱構件2 3 0之第二部份2 3 4盥美^ 側壁25G間的接合性。 ”基板m之 由上述之說明可知,第一封裝模組2丨〇所 可傳導至散熱構件2 3 0之第一部份2 3 2,並读、M * …、里 2 3 0之第一部份2 3 2可傳導至母板1 0上及散妖=政熱構件 二部份2 3 4上,使得熱量可以由散熱構件23〇、件2 3 0之第 丹1干W U之第一部份10037twf1.ptc Page 12 567600 _ Case No. 91125099 Car η pi Correction V. Description of the invention (8) Inverted door type heat dissipation member 2 3 0 can extend the heat dissipation area of the heat dissipation member 2 3 0 so that the heat dissipation member 2 3 0 has better heat dissipation effect. In addition, the solder bump 2 40 is arranged on the first surface 202 of the substrate 200, and the contact 2 0 3b connected to the first surface 202 is connected to the substrate 2 0 by the solder bump 2 4 0. 0 is bonded to the motherboard 10 and electrically connected to the motherboard 10. Furthermore, please refer to the enlarged view of the side wall of the substrate 200 in the joint p in FIG. 2A. The side wall 2 50 of the substrate 200 may be a flat surface or the side wall 2 50 of the substrate 200 has a groove. The second part 2 3 4 of the heat dissipation member 2 3 0 can be connected to the side wall 2 5 0 of the substrate 2 0 through a solder 2 3 6. In the manufacturing process, the solder 2 3 6 is first coated on the surface of the side wall 2 50 and the channel 2 5 2, and then the heat dissipation member 2 3 0 is mounted on the substrate 2 0 and the first packaging module. On 2 10, the second part 2 3 4 of the heat dissipation member 2 3 0 is bonded to the side wall 2 50 of the substrate 200 by the solder 2 3 6. Next, a re-soldering step is performed, so that the second part 2 3 4 of the heat dissipation member 2 30 can be tightly bonded to the side wall 2 50 of the substrate 200 by the solder 2 3 6. However, in a better case, the side wall 250 of the substrate 2000 is provided with a channel 2 52, which can increase the contact area between the solder 2 36 and the side wall 250 of the substrate 200, and The solder 2 3 6 will be filled in the channel 2 5 2, so that the solder 2 3 6 will form a plurality of protrusions (not shown) to be snapped into the channel 2 5 2 'to improve the heat dissipation member. The second part of 2 3 0 2 3 4 ^ United States ^ joint between the side wall 25G. From the above description of the substrate m, it can be known that the first package module 2 丨 〇 can be conducted to the first part 2 3 2 of the heat dissipation member 2 3 0, and read, M * ..., the first of 2 3 0 Part 2 3 2 can be transmitted to the mother board 1 0 and the demon = the thermal component two parts 2 3 4, so that the heat can be dissipated by the heat dissipation member 2330, the 2nd 3rd of the Dan 1 dry WU, the first Part

10037twf1.ptc 第13頁 567600 五、發明說明(9) 2 32之表面、第二部份234之表面以及母板1〇散逸至 另外,第一封裝模組210及第二封裝模組22〇傳導至. 之側登2 5 0的熱量’亦可傳導至第二部份川,並^過 第一部份234之表面而將熱量散逸至外界。 第二實施例 ’ 第3 A圖繪示本發明第二實施例之一種且有 吉構的側視示意圖。第3B繪示 :J牛 圖考第,,此… 封裝模組3 2 0、散土孰構件33。以及,/模組310、多個第二 〇Πη θ . 狀…稱仔以u以及多個焊塊3 4 0,其中美抬 封裝杈組310例如為晶片尺寸構阳弟 3〇〇之第-表面3 0 2的中央區域上裝J f配置在基板 如為晶片尺寸構裝(c /上,而苐二封裝模組3 2 0例 3 〇 4的區域上。此^卜, 在基板3〇〇之第二表面 3,如具有一第一部;』2以例巧 一部份3 3 2例如由二鉻此樓此a 第一部伤3 34,其中第 式,而十字形的交叉〃區 j構成,類似十字形的樣 並且散熱構件3 3 0之第一\ _位在第一封裝模組310上, 四個側邊向外延伸至大約盥其/會由第一封裝模組3 1 〇之 第一封裝模組310所產生的埶土量反3〇0之寬度相當,用以將 以及十字形之外端散逸。…里,經由第一部份3 3 2之表面 ^ 此外,第二部份3 3 4例如番古## 第一部份3 3 2之十字形的 ^於第—部份3 3 2且連接於 幻卜^ 並且第二部份3 3 4係由第—10037twf1.ptc Page 13 567600 V. Description of the invention (9) The surface of 32, the surface of the second part 234, and the motherboard 10 are dissipated to the other, and the first and second packaging modules 210 and 22 are conducted To the side of the heat of 2 50 'can also be transmitted to the second part of the stream, and ^ across the surface of the first part 234 to dissipate the heat to the outside world. Second Embodiment ′ FIG. 3A is a schematic side view of a second embodiment of the present invention with a gyroscope. Drawing 3B: J Niu Tukoudi, this ... Package module 3 2 0, loose soil concrete member 33. And, / module 310, a plurality of second 0Πη θ.... Is called u and a plurality of solder pads 3 4 0, where the US packaging package group 310 is, for example, the chip size of the Yangtze 300th- The central area of the surface 3 0 2 is mounted on the substrate. If the substrate is mounted on a substrate (c /), the second package module 3 2 is the area of the case 3 0 4. This is on the substrate 3 0. 〇 the second surface 3, if there is a first part; "2 for example, a part of 3 3 2 for example by the two chromium this building this a first injury 3 34, of which type, and the cross-shaped crossing 〃 The area j is formed like a cross shape and the first heat dissipation member 3 3 0 is located on the first packaging module 310, and the four sides extend outward to about 15 mm from the first packaging module 3 The amount of soil generated by the first package module 310 of 10 is equivalent to the width of 300, which is used to dissipate and the outer end of the cross shape...., Through the surface of the first part 3 3 2 ^ In addition, The second part 3 3 4 For example 番 古 ## The first part 3 3 2 is cross-shaped ^ in the first part-3 3 2 and is connected to the magic Bu ^ and the second part 3 3 4 is made by the first-

567600 案號 91125099 曰 修一 五、發明說明(10) 部份3 3 2之外端向基板3 0 0之側壁延伸,進而可以使散熱構 件2 3 0之散熱面積再加以延伸,使得散熱構件3 3 0具有更佳 的散熱效果。另外,又可將第二部份3 3 4透過一焊料3 3 6而 與基板3 0 0之側壁3 5 0接合,其第二部份3 3 4與基板3 0 0之側 壁3 5 0接合的結構如第一實施例所述,在此便不再贅述。 如此,第一封裝模組3 1 0及第二封裝模組3 2 0傳導至基板 3 0 0之側壁的熱量,可透過第二部份3 3 4之表面而將熱量散 逸至外界。再者,焊塊340係配置在基板3〇〇之第一表面月 302上,且連接第一表面302之外接點303,藉由焊塊340可 將基板3 0 0與母板1 〇接合並與母板丨〇電性連接。 請參考第4 A.以及4 B圖,其綠示另一種具有散熱構件之 封裝結構的底部示意圖。其中第一封裝模組3丨〇 a、3丨〇 b 可配置在如第4A以及4B圖之基板3 0 0 a、3〇〇b之第一表面/、 3 0 2 a、3 0 2 b的邊緣中間區域或角落區域上,因此散熱 3 3 0 a之第一部份3 3 2 a在外形上例如為了形或[形,而且第一 部份3 3 2 a之二條狀形結構會接合在一交叉區域3 3 8 a, 3 係對應於基板3〇〇a、3〇(^之 $ ϋΐί杜同樣位在第一封裝模組31〇a、310b上。另Ϊ ί 第二部份3 34a例如垂直於第一部份3 3 2a且 3 34a係由第一部份3 3 2a之外迪::^,並且第一 *份 伸,進而可以使散埶構件向f板3〇〇a、3〇〇13之側壁延 得散埶槿彳: f件33〇a之政熱面積再加以延伸,使 付政…構件3 3 0 a具有更佳的散熱效果。 便 綜上所述,本發明之1女μ & 。 月之具有散熱構件之封裝結構至少具567600 Case No. 91125099, Rev. 15th, Description of the Invention (10) The outer end of the part 3 3 2 extends to the side wall of the substrate 3 0 0, which can further extend the heat dissipation area of the heat dissipation member 2 3 0, so that the heat dissipation member 3 30 has better heat dissipation effect. In addition, the second part 3 3 4 can be joined with the side wall 3 50 of the substrate 3 0 through a solder 3 3 6, and the second part 3 3 4 can be joined with the side wall 3 5 0 of the substrate 3 0 0 The structure is as described in the first embodiment, and will not be repeated here. In this way, the heat transmitted to the side wall of the substrate 300 by the first package module 310 and the second package module 320 can dissipate the heat to the outside through the surface of the second portion 34. In addition, the solder bump 340 is arranged on the first surface 302 of the substrate 300, and is connected to the contact point 303 outside the first surface 302. The solder bump 340 can join the substrate 300 and the mother board 100. Electrically connected to the motherboard. Please refer to Figures 4 A. and 4 B, which show the bottom diagram of another package structure with heat dissipation components in green. The first package modules 3 丨 〇a, 3 丨 〇b can be arranged on the first surfaces of the substrates 300a, 300b as shown in Figures 4A and 4B /, 3002a, 300b On the edge of the middle area or corner area, so the first part 3 3 2 a of heat dissipation 3 3 0 a is in shape, for example, to shape or [shape, and the stripe structure of the first part 3 3 2 a will be joined In a crossing area 3 3 8 a, 3 corresponds to the substrates 300a, 30 (^ ϋΐ), and is also located on the first package modules 31〇a, 310b. In addition, the second part 3 34a is, for example, perpendicular to the first part 3 3 2a and 3 34a is outside the first part 3 3 2a: ^, and the first * part is extended, so that the scattered member can be directed to the f-board 300a. The side walls of 3,0013 are scattered too much: the political thermal area of f piece 33〇a is further extended, so that the fu ... member 3 3 0 a has better heat dissipation effect. As mentioned above, this The invention of 1 female μ &. The packaging structure of the moon with a heat dissipation member has at least

567600 _案號91125099_年月日__ 五、發明說明(Π) 有下列優點: 1 .本發明之具有散熱構件之封裝結構,其中散熱構件 具有較大的散熱面積,且散熱性佳,而封裝結構内部之晶 片所產生的熱量可藉由散熱構件之傳導,而有效地將熱量 散溢到外界。 2 .本發明之具有散熱構件之封裝結構,其中散熱構件 之第一、第二部份係可分別連接於封裝模組之表面以及基 板之側壁,藉以延伸封裝模組之散熱面積,如此晶片所產 生的熱量可經由封裝模組之表面以及基板之側壁,而傳導 至散熱構件之第一、第二部份以及母板上,並將熱量透過 第一、第二部份之表面以及母板而散溢至外界。 雖然本發明已以一較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精 神和範圍内,當可作各種之更動與潤飾,因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。567600 _Case No. 91125099_year month__ V. The description of the invention (Π) has the following advantages: 1. The packaging structure of the present invention having a heat dissipation member, wherein the heat dissipation member has a large heat dissipation area and good heat dissipation, and The heat generated by the chip inside the package structure can be conducted by the heat dissipation member to effectively dissipate the heat to the outside. 2. The packaging structure with a heat dissipation component of the present invention, wherein the first and second parts of the heat dissipation component can be connected to the surface of the packaging module and the side wall of the substrate, respectively, so as to extend the heat dissipation area of the packaging module. The generated heat can be transmitted to the first and second parts of the heat dissipation member and the mother board through the surface of the packaging module and the sidewall of the substrate, and the heat can be transmitted through the surfaces of the first and second parts and the mother board. Spill to the outside world. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

10037twf1.ptc 第16頁 567600 _案號91125099_年月曰 修正_ 圖式簡單說明 第1 A圖繪示習知具有多封裝模組之封裝結構的側視示 意圖, 第1 B圖繪示第1 A圖之封裝結構的仰視示意圖; 第2 A圖繪示本發明第一實施例之一種具有散熱構件之 封裝結構配置於一母板的側視示意圖以及接合處P之基板 側壁的放大圖; 第2 B繪示本發明第2 A圖之封裝結構的仰視示意圖; 第3 A圖繪示本發明第二實施例之一種具有散熱構件之 封裝結構的側視示意圖; 第3 B繪示本發明第3 A圖之封裝結構的仰視示意圖;以 及 第4A以及4B圖繪示另一種具有散熱構件之封裝結構的 底部示意圖。10037twf1.ptc Page 16 567600 _Case No. 91125099_ Year Month Revision _ Brief Description of Drawings Figure 1 A shows a schematic side view of a conventional packaging structure with multiple package modules, and Figure 1 B shows 1 A schematic bottom view of the packaging structure in FIG. A; FIG. 2A illustrates a schematic side view of a packaging structure with a heat dissipating member disposed on a mother board and an enlarged view of a sidewall of the substrate P at the joint P according to the first embodiment of the present invention; 2B is a schematic bottom view of the packaging structure shown in FIG. 2A of the present invention; FIG. 3A is a schematic side view of a packaging structure having a heat dissipation member according to the second embodiment of the present invention; 3A is a schematic bottom view of the packaging structure; and FIGS. 4A and 4B are bottom schematic views of another packaging structure having a heat dissipation member.

10037twf1.ptc 第17頁10037twf1.ptc Page 17

Claims (1)

567600 _案號91125099_年月曰 修正_ 六、申請專利範圍 1 . 一種具有散熱構件之封裝結構,適於配置在一母 板上,該具有散熱片之封裝結構至少包括: 一基板,具有一第一表面; 一第一封裝模組,係配置在該基板之該第一表面 上; 一散熱構件,配置在該第一封裝模組上,該散熱構 件具有一第一部份及一第二部份,該第二部份係大致上垂 直於該第一部份,該第二部份係由該第一部份向該基板延 伸,該散熱構件之該第一部份係位在該第一封裝模組上, 並且該散熱構件之該第二部份係與該基板之該側壁接合; 以及 複數個焊塊,配置在該基板之該第一表面上,藉由 該些焊塊,該基板可以與該母板接合並與該母板電性連 接。 2 .如申請專利範圍第1項所述之具有散熱構件之封裝 結構,還包括至少一第二封裝模組,而該基板還具有一第 二表面,係與該第一表面相對應,該第二模組係配置在該 基板之該第二表面上。 3. 如申請專利範圍第2項所述之具有散熱構件之封裝 結構,其中該第二封裝模組係為晶片尺寸構裝的形式。 4. 如申請專利範圍第2項所述之具有散熱構件之封裝 結構,其中該第二封裝模組包括: 一晶片,以及 複數個焊球,該些焊球係介於該晶片與該基板之該567600 _Case No. 9125099_Amended in January / August 6, Application scope 1. A package structure with a heat dissipation member is suitable for being arranged on a motherboard. The package structure with a heat sink includes at least: a substrate with a A first surface; a first package module disposed on the first surface of the substrate; a heat dissipation member disposed on the first package module, the heat dissipation member having a first portion and a second Part, the second part is substantially perpendicular to the first part, the second part extends from the first part to the substrate, and the first part of the heat dissipation member is located in the first part A package module, and the second portion of the heat dissipation member is bonded to the side wall of the substrate; and a plurality of solder bumps are arranged on the first surface of the substrate, and through the solder bumps, the The substrate may be bonded to the motherboard and electrically connected to the motherboard. 2. The package structure with a heat dissipation component as described in item 1 of the scope of the patent application, further comprising at least a second packaging module, and the substrate also has a second surface corresponding to the first surface. Two modules are disposed on the second surface of the substrate. 3. The package structure with a heat dissipation component as described in item 2 of the scope of the patent application, wherein the second package module is in the form of a chip-size package. 4. The packaging structure with a heat dissipation component as described in item 2 of the scope of the patent application, wherein the second packaging module includes: a wafer and a plurality of solder balls, the solder balls are between the wafer and the substrate The 10037twf1.ptc 第18頁 567600 _案號 91125099_年月日__ 六、申請專利範圍 第二表面之間,藉由該些焊球使該晶片與該基板電性連 接。 5 .如申請專利範圍第1項所述之具有散熱構件之封裝 結構,其中該第一封裝模組係為晶片尺寸構裝的形式。 6 .如申請專利範圍第1項所述之具有散熱構件之封裝 結構,其中該第一封裝模組包括: 一晶片,以及 複數個焊球,該些焊球係介於該晶片與該基板之該 第一表面之間,藉由該些焊球使該晶片與該基板電性連 接。 7. 如申請專利範圍第1項所述之具有散熱構件之封裝 結構,其中該散熱構件之該第二部份係透過一焊料與該基 板之該側壁接合。 8. 如申請專利範圍第7項所述之具有散熱構件之封裝 結構,其中該側壁具有至少一槽道,該焊料係容納於該側 壁之該槽道中。 9 .如申請專利範圍第1項所述之具有散熱構件之封裝 結構,其中該散熱構件之該第一部份具有二條狀結構,該 二條狀結構會交叉,其交叉的部份係定義為一交叉區域, 該第一部份之該交叉區域係位在該第一封裝模組上。 1 0 .如申請專利範圍第1項所述之具有散熱構件之封 裝結構,其中該散熱構件之該第一部份係為條狀形的樣 式。 1 1 .如申請專利範圍第1項所述之具有散熱構件之封10037twf1.ptc Page 18 567600 _Case No. 91125099_ Month and Day__ VI. Scope of patent application Between the second surface, the chip and the substrate are electrically connected by the solder balls. 5. The package structure with a heat dissipation component as described in item 1 of the scope of the patent application, wherein the first package module is in the form of a chip-size package. 6. The packaging structure with a heat dissipation component as described in item 1 of the scope of the patent application, wherein the first packaging module includes: a wafer and a plurality of solder balls, the solder balls being between the wafer and the substrate Between the first surface, the chip and the substrate are electrically connected by the solder balls. 7. The package structure with a heat dissipation member as described in item 1 of the scope of the patent application, wherein the second portion of the heat dissipation member is bonded to the side wall of the substrate through a solder. 8. The package structure with a heat dissipation member according to item 7 of the scope of the patent application, wherein the side wall has at least one channel, and the solder is received in the channel of the side wall. 9. The packaging structure with a heat dissipation component as described in item 1 of the scope of the patent application, wherein the first portion of the heat dissipation component has two strip-shaped structures, the two strip-shaped structures will cross, and the crossing portion is defined as a The cross region, the cross region of the first part is located on the first package module. 10. The packaging structure with a heat dissipation member as described in item 1 of the scope of the patent application, wherein the first portion of the heat dissipation member is a strip-shaped pattern. 1 1. Seal with heat dissipation component as described in item 1 of the scope of patent application 10037twf1.ptc 第19頁 567600 _案號91125099_年月曰 修正_ 六、申請專利範圍 裝結構,其中該第一封裝模組係位在該基板之該第一表面 的中間區域上。 1 2 .如申請專利範圍第1項所述之具有散熱構件之封 裝結構,其中該散熱構件係接觸該母板。10037twf1.ptc Page 19 567600 _Case No. 91125099_ year month revision 六 、 Patent application scope The mounting structure, wherein the first package module is located on the middle area of the first surface of the substrate. 12. The package structure with a heat dissipation member as described in item 1 of the scope of patent application, wherein the heat dissipation member is in contact with the motherboard. 10037twf1.ptc 第20頁10037twf1.ptc Page 20
TW091125099A 2002-10-25 2002-10-25 A package with a heat sink TW567600B (en)

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