TW567501B - Serial input/output testing method - Google Patents

Abstract

A serial I/O testing method is performed by a testing system for testing a memory device having a first pin, a second pin, and a third pin. The testing method includes a step of inputting a clock into the memory device through the first pin, followed by a step of inputting a serial address into the memory device through the second pin synchronized with the clock. The method further includes a step of inputting a command into the memory device and a step of, when the command is a read command, outputting from the third pin a serially-written data synchronized with the clock. When the command is a program command, the method includes inputting an initial data serially through the third pin synchronized with the clock, and programming the initial data into the memory device before outputting it on the third pin as programmed data from the memory device synchronized with the clock. The serially-written data, in the case of read command, or the programmed data, in the case of a program command, is then compared with an original or expected data.

Description

567501 V. Description of the invention (1) The present invention relates to a test of adding memory elements to a test of speed sound parts, and particularly, has a large-scale integrated circuit (mi) = collar mounting f. The manufacturing process is intended to produce larger sections of the 5A memory chip. The A5 body array is the same as the U5. 1 (semiconductor wafer). Unfortunately, the size of the J-times is smaller and the number of components on the wafer increases; the difficulty of k and body components is tested over time. 'Growth' therefore requires a greater amount of resources and requirements Ϊ t: density 丨 The manufacturing of the merit array makes most of the manufacturing process 2 :: Ϊ memory queue 1. Therefore, the 'test maker has established the same Automatic test system for testing memory components in Si Temple. The test can be performed on the memory components when the memory is completed but still on the silicon wafer ^, or after packaging into a wafer, or here Both stages are carried out. For the packaged chip, it is easier to design an automatic test machine, but if this chip is tested earlier, the management cost can be reduced because the trappable memory components are discarded to avoid spending extra resources. The memory testing machine used for multiple memory elements is generally tested on the body elements and the output results of those memory elements are compared to the standard or expected value. The machine can be used to place memory chips for testing. “Up” and start the electrical contact between the memory element and the external test device of the memory test machine. The external circuit of the memory test machine is generally designed to be integrated, and each module is related to one of the endpoints of the memory device. In one test, Wen-model based on the role of San modes, i.e., each module can send data, receive data, or to maintain the inter-position. Executed between the lines tested by the test station memory and the memory device

^ 554twf.ptd Page 6 567501 V. Description of the invention (2) _____ Signal exchange. The input position of the memory element is generated and sent to the memory element for testing. The input signal can be sent to the memory element by the test machine. ^ Pin ’, once the data pin is sent before the test data element sends out the output data. The signal in the memory element is sent to the memory element in accordance with the path: = f pieces of data input and output. When compared with the memory test machine, the memory area is compared. Whether the selected memory area in this case is suitable for p 2 is on time, which means that memory element 1 can be output and stored in the defect analysis record. When the defect is tested, the logical index is used. The defect analysis memory only stores missing blocks made by the relevant address signals, and is omitted.曰 圯 圯 memory block, and the general practice is to use parallel (para11 ka ,; 1 ^ l / o > ^ to the memory element, the memory element to be tested; ^ / 则 j 机 =, check out. The I / O test machine ’s next reading of the rain signal can be: than the established standard. If this value matches the output system, it can be operated normally. ⑴ ° Hidden body parts are treated as parallel to the 0 test machine. The frame structure has several fall-grip operation modes, the "reading" mode, which is recorded by the record = Zake mode *. The data is received by the parallel I / O test machine and read out with the standard ... 70, Formula " Write •, mode, where some values are written to T to the target ratio. Second, read back and compare with the standard value. For example, the logical value \ ZZ file, and the test machine write All the memory from the human to the memory element is 5 units. 'Parallel = ”Each memory bit is read back by the parallel I / O test machine and the unit 5 ~ The memory content is consistent with the previously determined standard. 疋 No. The second test mode is 567501 V. Description of the invention (3); r 4 + r * test the memory element when using h and parallel 1 / 〇 test machine The number of probes required is generally the same as the number of memory cells in the second place = plus. This phenomenon is because the number of address bits and ί / 〇: 2: = increase, so the number of pins also increases. #Measurement is required. When the quantity increases, the number of pins with the same number of pins is equal to the number of two-pieces / function. ”Try a smaller number of yuan games. For example, when using traditional 42 ^ ;; "::;;^;^; &Quot; μ office place 栝 23 input pins,] 6 output pins, one pin to the moon dagger pin, one turn out to enable the sun and the sun m / o, ι ^ „, , t, ^ 42 ^ ^ ^ memory components. / Hugh Needle Wood tried this note a larger number of pins can be provided in parallel 1/0 test = multiple memory components, but this architecture will be convenient? Can it be advantageous :! = 所If necessary, time, without the need to increase the relevant reduction of two :: bulk semiconductor elements' more need to the present invention is to meet these needs, by = memory element method, which uses the tandem heart = ί ·! =: String The serial communication includes the test system and the cascade flood system synchronized to the clock signal.

567501 V. Description of the invention (4) _ However, fewer pins are required to measure the clock gt> a heterogeneity (for example, the number of test probes c :): and: the complexity of the test system of the complex components of the test system ϋ) There may be ίί 少. Each memory under test can be tested at 4 times per day, and ΛΑ “degree reduction” allows the test system to

牯, then there are more S memory elements. Human 1 J ^ I / 0 ^ ^ ^ Φ element. The test method includes the following steps: testing a memory device; then, a memory device is tested; then, V. Input a timing signal to the record, ^ ^ input a serial address to the memory device in series, To the US position, 70 pieces of M ° w body were transferred from the test system in synchronization with the timing signal. The memory position of the memory unit is then accessed using the address, and the data is output from the memory bit serially in synchronization with the timing signal. In one embodiment of the present invention, a command is input to the memory element to indicate that the memory element is a read command or a programmed command. In another f embodiment, the instruction further indicates whether the memory element is required to execute a wipe ^ ^ When the violation instruction is a read instruction, the access step and the output step are performed, and the method further includes comparing the string Steps to write data and two original data. On the other hand, when the instruction is a stylized instruction, the access step continues: inputting an initial data serially in synchronization with the timing signal; and programming the initial data into the memory element; The method further includes a step of comparing the output data with an original data. According to another aspect of the present invention, a tandem I / 0 test method is provided, which is executed by a test system to test a memory element, the memory element having a first pin and at least one additional pin. The test method includes the following

567501 V. Description of the invention (5) Steps: Passing through the extra connection to the tandem bit line: When a one-finger instruction is entered, the data is synchronized, and the tandem of the is written to the memory. In another embodiment, the pin is written in series; wherein, the serial writing data is input to the first pin and an address is synchronized to the memory and the data is written in series in the clock. In the case of the component, in the tb example, the finger means that the additional serial address material is input from the first and serial input of the clock body component from the amount of data. The input is lost through the three-pin one-time address; the external correlation includes the line through the pulse to the input 0 and when the caster is stored: when writing additional memory memory, the method body component; component, which then enters, 5 The Haicai θ command is a read-line write memory device that outputs a string of data in which the read data and instructions have been input with an original pin. A second pin and a third pin are connected to the second pin for input and should be output. When the instruction is a stylized instruction, the test method includes the step of inputting an initial data serially through the third pin, wherein the initial data is synchronized to the clock; the initial data is programmed to The memory element; and outputting the programmed initial data from the memory element through the third pin, wherein the programmed initial data is synchronized to the clock and output. The stylized initial data can be compared with an original data.

The memory element further includes a fourth pin, a fifth pin, and a sixth pin, and the method further includes the following steps: inputting a chip enable signal to the memory element through the fourth pin. A step of inputting an output enable signal to the memory element through the fifth pin; and a step of inputting a write enable signal to the memory element through the sixth pin.

9554twf.ptd Page 10 567501 V. Description of the invention (6) In the above viewpoint, the present invention provides a method for testing at least one memory element, which uses serial input and output communication of the memory element, wherein the communication Is synchronized to a clock applied to the memory element. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below and described in detail with reference to the accompanying drawings. Explanation of symbols: 17: Parallel I / O test machines 19, 19 ', 19 π: Memory elements 21, 23, 26, 28, and 30: Conductors 32, 34' 36'26 > 28 and 30: Pad / Pin 3 5: Additional pin 3 7: Clock probe 38: Semiconductor wafer 40: Load mechanism 4 2 · Serial I / O test system 44: Probe 4 7: Clock probe 4 9: Address Probe 50: Tandem I / O Probe 5 1: I / 0 Probe 53: Output Enable Probe 5 5: Wafer Enable Probe 5 7: Write Enable Probe

9554twf.ptd Page 11 567501 V. Description of the invention (7) 60: Tandem I / 0 buffer 62: I / 0 gate circuit 64 ·· Row decoder 68: Column decoder 70: Clock input 73: Processing Generator 75: Morph generator 77. Timing generator 79: Waveform 81: Morphological comparator 84: Defective memory 87. Read instruction 89: Stylized instruction 91: Erase instruction 94: Clock signal 96: Tandem input cycle I 0 0: Extra cycle 102: Data output cycle 106: Data polling mode 107, 109, 111, 113: Memory element II 5, 1 1 7, 1 1 9, 1 2 1: Process comparison The preferred embodiment is described with reference to the accompanying drawings. FIG. 1 is a conventional parallel I / O testing machine 17 connected to a memory element 19 to be tested. Side-by-side I / 0 test bench 1 7 includes connection to memory

9554twf.ptd Page 12 567501

Probes or other components related to the plural i / o pins of the body element 19. In the i-th, the memory το member 19 includes 42 I / O pins, which include 16 output pins D0-D15, 23 input pins D16-D38, one write enable pin, and one chip enable. Pin E and an output enable pin 0. Memory component 9—Generally includes additional pins, such as power pins. Parallel 1/0 test machine 17 series, connected to input pins D16-D38 via conductor 21; connected to output pins D0-D15 via conductor 23; connected to write enable via conductor 26, "and ⑽ Pin W, chip enable pin E, and output enable pin 0. For example, the signals of the address and data signals pass through the conductors 2 丨 and 23 in a parallel manner and pass through the memory element 19 and the parallel I / 〇 Test machine 丨 7. For example, for "read" test, appropriate chip enable pin £ and output enable pin 〇 must be driven by parallel I / O test machine 17 via conductors 21 and 23 . The column I / 0 testing machine 17 can start reading requirements by placing addresses on the conductor 2 in a side-by-side manner. In response to the read request of the parallel 丨 / 〇 test machine 丨 7, the memory element 19 outputs 16 bits of data in parallel to the if-out pin DO-D15. As described above, the communication on the memory element 19 is parallel. The parallel I / O test machine 7 must be constructed with a sufficient number of probes to connect to the 421 / 〇 pins 〇0-〇38 of the memory element 19? , £ and 〇. More specifically, the 'parallel I / O test machine 17 must be constructed with 42 or more pins, 1 pin = 19 for testing this memory element. Testing this number of probes for a single memory device will increase the manufacturing time and cost of the memory device. The second figure is a tandem type 1 / 〇 tears & 51 series 2 ° load mechanism 40 series connected to a memory element IC19 on a half-rule wafer (according to an embodiment of the present invention) Extends from the tandem 1 / () test system 42 and includes 567501 V. Description of the invention (9) includes a plurality of probes 44 whose frame constitutes a 19 'pad (or pin). Negative. Volume two is sufficient to contact the memory element. Electrically connected to the first 塾 3 2 and / Λ probes 4 and 4 are established as shown. The extra pad includes a second pad 34: No .: Amount: Bu〗. In this embodiment, up. As early as the 9-point contact point, it is still located on the semiconductor wafer 38 and the probe 44-and then is fed back to the tandem 1/0 test system 42. Therefore, in the embodiment of the Office- # diagram, only 6 or fewer probes 4 4 are used to electrically connect the memory complex 2:19 'to the tandem 1/0 test system 42 for testing: 1 phase Than the first! The 42 connections required for the architecture of the graph are quite I> '. Although the system shows 6 probes 4 4, the number of probes 4 4 can be reduced to ν. For example, 2 probes include only one clock probe and one 丨 / 〇 probe. 5,5 memory body element 19 'can be tested at two points in its manufacturing process. That is, the 'memory element 19' can be broken and tested on the silicon wafer that has been manufactured but is still on the silicon wafer 'as shown in Figure 2; or after being packaged, as shown in Figure 3a and Flutter. Pins and pads can be used interchangeably here, because in this embodiment, these terms essentially represent the same meaning, "pads" are used for memory elements still on Shi Xi wafers, and "pins" ; Used for memory components that have been packaged. As mentioned, the memory element 19 may include random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), read-only memory (ROM), Programmable Read-Only Memory (opt ROM), Multiple Programmable Read-Only Memory (MPT ROM), Erasable Programmable Read-Only Memory

567501 V. Description of the Invention (EPROM), electrically erasable stylized read-only memory (EEpR0 flash memory or similar structure. Figure 3a shows a connection to another embodiment of the present invention. Block diagram of the in-line i / o test system 42 of the packaged memory element 19. As shown, the memory element 19 'is connected via conductors " pins of the inline I / O test system 42. In Figure 3a, the memory element 19 has been packaged, and the final formed wafer is used to accept the serial 1 / 〇 test system 42. The body element 19 includes the first pin 32 and at least one additional connection. = Example In addition, the second pin 34 and the third pin 36 are included. As shown, the memory element 19 series includes the fourth pin 26 and the fifth pin 30. This is implemented here In the example, the real pins 32, 34,% /, 28, and 30 are 1/0 pins of the original memory components. Therefore, the 36, 34, 36, 26, 28, and 30 pins can be used as memory. Element 19, the traditional 丨 / 〇 = tandem: the test mode is from the tandem 1/0 test system 仏, medium to> two pins, in The examples are all pins 32, 26, 28, and 30 act to facilitate the tandem 1/0 test system. As shown, pins 32, 34, 36, 26, 28, and 30 are divided.蠖, JI / O probe 51, address probe 49, clock probe 47, write enable tilt detection, i is connected to I by 57, chip enable probe 55, and output enable probe 53 / O testing system 42. Figure 3b of Jiaxi J shows another embodiment, in which the tandem 1/0 test system includes a clock probe 37 and an additional probe, in this case the tandem 丨 / Needle 50. In this embodiment, the tandem 1 / 〇 probe 50 is essentially executed: the combined function of the I / O probe 51 and the address probe 49. The memory of the first flutter picture ^

9554twf.ptd Page 15 567501 V. Description of the invention (11) The component 19 'includes a first pin 32 and an additional pin 35. In this example, it is essentially the same as the second pin 34 and the third pin 36. Features. A simplified description of several functional elements of the DRAM element 19 'is connected to the serial I / O test system 42 of the present invention to be tested, and is shown in FIG. In this embodiment, the location of the memory address is divided into a column address and a row address, as is conventional. The address, which may include the column address and the row address, are input from the serial probe I / 0 test system 4 2 of Figure 3 a to the address probe 4 9 to the memory element 1 9 " serial 1 ^ 0 buffer 60. The address transmitted by the address probe 49 is synchronized with the clock signal of the clock probe 47, and the clock signal 47 is received by the clock input 70 of the memory element 19 " for the memory element " Synchronization. In this embodiment, the column address in the address transmitted by the address probe 49 is decoded by the column demaser 68, which then starts the word line related to the column address. The serial number is sent through the 1/0 gate circuit 62 and sent to the column 1/0 I / O order buffer H64. It is decoded by the 1/0 inter-circuit 62 and sent to the application t ι test. The content of the address is located in the second output of the memory. The content of the address in question is output from the serial time λ λ 'in tandem and synchronized to the input to the clock input = clock ..., input to the tandem FIG. 5 is a tandem piece according to the present invention. If the tandem # I Μ 、 目 肀 ”formula 1 / U, then the function of the system 4 2 is called. Design and Engineering Principles to Change _, Mouth | 丨 Liyue Dagger can be used to sell the original shell! To change * As long as the obtained serial I / O test

9554twf.ptd Page 16 567501 V. Description of the Invention (12) 1 ~~~ System 4 2 series 忐 Test uses a serial address and a memory element of the type I / 0 signal synchronized with the timing signal. In this embodiment, the processor 73 is used for the operation of the serial I / O test system 42. The processor 73 provides a pattern signal, which is sent to the pattern generator 75. Shape generation < 75 then adds timing data and waveform data, and sends these items to the 1 sequence generator 77 and the wave shaper 79 in order. For certain data signals (such as address and initial data) to communicate with the memory element under test ^, the output of the rectifier 79 is synchronized with the signal sent to the memory element 19, Pulse signal. # The pattern, timing and waveform data are also sent to the pattern comparator 81. The above test data is passed through the wave rectifier 7 9 and sent to the memory element 9 9. In the " reading example ', the reading order is output by the rectifier 79, so that the memory is one piece 19 to output serial data from the memory position. The serial data output by the memory component 9 is then compared with the shape of the shape comparator 8 丨. If the data tested makes the test fail (for example, the serial data read is different from the expected or original data), the defect address is stored in defect memory 8 4 for further processing. Fig. 6 is a flowchart of testing a single memory element according to an embodiment of the present invention. The method to be executed by the tandem 1/0 test system in FIG. 3a starts at step 301, which inputs the clock signal from the clock probe 47 to the memory element and passes the first pin 32, pin 32 is a clock input pin. As shown in Fig. 7, it is a "reading, instruction test" of a single memory element according to the embodiment of the tandem 1 / () test system 42 of the present invention. In the timing sequence, the clock signal 94 is used for synchronization.

^ 554twf.ptd

567501 V. Description of the invention (13) In step 303, the serial address pin 34 is entered by the address probe 49 to γ °, the second connection diagram of the address pin, and the serial address It is synchronized to the clock piece 19. The reference to the seventh address again includes 20 clock cycles related to 2. In this example, the tandem AU ... A0), each cycle lasts 50n ... Address bit ⑷9. The bottom of the period will be called tandem input period 96. These 20 (logical values change from 0 to 1) are input address bits. When the pulse signal 94 becomes the high-level input signal, the clock The period is divided into the number 94, which is the high-power rise time, which is related to the time when the clock signal 94 becomes high. The hold time is the period of 7G after the clock signal 94 becomes high, including the rise time and the hold time. Therefore The serial address of each address is synchronously input to the clock cycle. It can be confirmed that w is familiar to the person skilled in the art, 'it may come when the clock signal 94 becomes a low potential (logic value changes from 1 to 0). The input signal is within the range of this implementation *. It is synchronized with the rising clock signal. Other signals or data of 2 pulses are as shown. General input. Action and timing with the time signal, which is equivalent to the tandem bit system. This embodiment includes 20 address bits, which allows 2 to 20 addresses. 2 The address bits of each address will be related to the single-address pin. ::: Γ '= Yuan address requires 20 pins. According to this month, during the test, the same 20 bits Meta address or any address :: pin is reduced to 1. 纟 In this embodiment, the single-clock cycle is used for each address bit. ', ^ Page 18 567501 V. Description of the invention (14 ) The instruction is based on the serial I / 〇 test dragon preparation ^ 9 ^. ^ Qn ,. The system 42 turns into the memory element 19 in step 305. As in the previous month, j, Bucket buckle. 9 -V Τ / Π ^ 4- X This order can be input to the record by the I / O probe 5 1 of the serial I / O test system 4 2; from, n, ^ τ / π ^ + ancient, n has the third pin 36 (which is the I / 0 pin) of the thinking body 19. In this method, Shijia plus 7 R7 ^, μ, t ^ OQ ^ I this Two possible instructions include read instruction 87, hardened finger 89 and erase instruction 91. This method skips to step 30 7. When How can I get this Ding Bei? On July 7th, when Tian orders the personalization instruction 89, this method jumps to step 309; when the erasure instruction 91 0 # is executed, + + i makes this force possible. This method jumps to step 315. This method skips to step 315. Because the private, shell material input and data output signals all share the third pin 3 6, various operation systems are better based on _卩 彳 &# m 时间 刀 布 0 Refer to Figure 7 again. The clock period t2 and t23 are used to decide which command η should be regarded as v 〇λ 疋. Each instruction is the same as a clock and is related to a particular clock cycle position. For example, if the clock period t 2 1 is related to reading a finger 8 R 7 g to read on 7 7 87, then if at t21, the second pin 36 receives the "1" value, the Shanghai person to be defended ^ ^ ~, ^ ^ ^ ^ & The daily order of the track line is read instruction 87, and this method continues to step 3 07. It is called instruction cycle 98 here. "After the three clock cycles of the instruction are issued, after the read instruction 8 7 is issued, the system uses two clock cycles with one 7 ^ ^ R ^ ^ ^ ^ 糸, which is referred to as the redundant cycle. The pipeline A // Λ is used for synchronization. No extra period is used Γ ^ 42δΛ, Γ ^ System 4 2 will communicate with the memory element as before 丨 9 ,. When 12 = 1 is read command 87, the memory Body components ... :: Two Γ1Α column input cycles at 96 when inputted to the addresses A19, A18,. ^ 0 of the second pin 34. Take care to set Λ ^ L 丄 4々々 水 门 丄 — 贝 抖. This typically involves synchronizing to the clock signal 94 in a serial fashion while previously being programmed (programmed) into memory

567501 V. Description of the invention (15) The material of the body element 19 'is passed through the first test system 42. This output process is displayed ^ 36 and output to the serial I / 〇 output in synchronization with the clock signal 94. Here, it occupies Fig. 7, where the data is the element value (DO, D, D15), so that the 16 clock pulses / data output bit element 19 outputs this value. This clock month &. The month is used to follow the Ji Yi body 102. A pulse period can be called a data output period. As can be seen in Figures 6 and 7, the money saved in this example (step 303) to the memory content output (two are over =, from the address input period, including 20 serial input cycles 96, flutter = clock extra cycles 100 and 16 data output cycles ^ cycle 98, two continue to refer to Figure 6 'When the stylized instruction 选择 is selected, the initial step 309 ^ into ^ memory ^ Item 19> 'Through the third pin 36, input data in the steps. These cycles, as shown in Figure 8 into the cycle 104. After inputting the tandem initial data, the process follows = ΪIT Step 311). This process is accompanied by the use of the string j = style pulse ★. In each program pulse, 'in this example, ^ or 70 clock cycles, the memory element 19 enters the data wheel mode 〇6. In this data polling mode 10, it is being programmed; it has been switched to 时 输入 when the serial input = bit (1 t〇D) of the memory element 19. This signal shows when the memory position has switched from its initial value to 0) to its final value (㈧ or 丨). When this switch occurs, the polling bit is page 20 ^ 554twf.ptd 567501 V. Description of the invention (16) " 'The meta signal is synchronized to the clock through the third pin 36 and output to the serial I / 0 Test system 42. In this example, a program pulse is required to switch the memory value from 1 to 0, or from 0 to 1. The 16 clock cycles are consumed by the polling bit signal. The yuan consumes one clock cycle. The memory location is programmed and verified using serial initial data—positive. In this example, the program process requires a total of 54 clock cycles; including 20 serial input cycles 96, three instruction cycles 98, 16 serial inputs = cycle 104 and 16 of the polling bit signal Each data output cycle is because of 10 program pulses, 35 microseconds, which is also used for the actual programming of the memory components. Therefore, the process of the above embodiment actually takes 755 clock cycles. In voxel step 315 ’, once the erase command 91 is received, it is related to the memory position erase related to the address received by the second pin 34. One of the methods of erasing the memory position of the memory element 19, is similar to the program instruction in essence. Among them, the difference is that during the input period of the shell material 104, a blank step can be input. The body has been erased '#It is output through the third pin 36 in the same signal ^ 6 formula, which is similar to the program mode Poll bit

Middle, after Sun Su 307, 313 and 317. In step 319, the quasi-information is compared with the data stored in the serial I / O test system 42. When the read instruction 87 is executed in step 307, the initial I / O in the I / O test system 42 is written. Material = 'compared to being stored in a string)' to confirm that the reading process is positive; Section II's 々 state ratio is 81 隹 and the first write and current read and write

567501 V. The memory address of the description (17) is defect-free. One line is in steps 309 to 311. Required ;. The ^ type instruction 89 series of material is compared to the tandem type! / 〇 test; the formula in the system = the initial input of the ^ material to confirm the written Zhijiuzhuan '\, the serial initial reference and the execution of the erasure instruction in 317, the input address / data is not defective. When writing data in step 315 and especially shell data with erasure state ~, it must be a tandem material to determine whether the heart of the memory address has been written by the second system compared to the standard data, including the data shown in Figure 3. As shown here, this serial I /. ; Test method Fang Zhifa 7 feet 2

Pass the fourth pin U and send it to the memory element. Second = Pass the fifth pin 28 and send it to the memory: U pass the sixth pin 30 and send it to the memory element 19. Step by step to the moon ^ Speak through In the M embodiment, the above-mentioned tandem 1/0 test system can test a plurality of memory elements when it is completed. Fig. 9 *-Tandem voxel: System 4 2nd if touched by the plurality of probes 44--a delta memory element 1 0 9 and a third memory element 1 丨Work to _ η solid / memory body 70 pieces 1 13 ° Each memory S piece has--32, first pad 34, a third pad 36, and an additional fourth pad 26, a fifth Pad 28 and a sixth pad 30, and can be constructed similar to the above-mentioned memory elements 19 and 19 ". The memory elements are tested side by side, so it will not take long to test the eight smart body elements It takes ^ days to test a memory element. Because each memory element includes three (or, for example, 2 or 6) pads, a test system including 48 probes can test in parallel to 9554twf at a time. .ptd Page 22 567501

Probe to test fewer than eight memory elements simultaneously. More or fewer memory elements can be utilized. A figure 10 shows a test system connected to the first memory element 1 07, the second memory a :: X 丨 ί: ° self 丨 thinking 70 pieces of 111 to nth memory elements 113 42, which is different from FIG. 9 in that the memory π part appears in a package form. Therefore, the contact points are pins, not pads. The structure and operation of the memory element are similar to those of the above-mentioned memory elements 19 and 19 'with reference to Figs. 2 to 8.

The tandem method of testing a plurality of memory elements in parallel is shown in FIG. 11. The method of testing a plurality of memory elements starts at step 29, where the serial I / O test system 42 detects the number of memory elements connected to it. In this embodiment, the tandem 1/0 test system 42 is connected to n §memory elements. In a certain embodiment, n = 8. When n memory elements are detected, the serial I / O test system 42 then proceeds to step 300, where it queries each connected memory element and waits until all clocks are sent when a clock signal is sent. Sync with each other. In a variant embodiment, step 3 0 0 can synchronize the sequence of the signals by connecting the memory elements, such as clocks, addresses, instructions, and / or polling signals. The I / 0 test system 4 2 is synchronized to the connected memory components. The test system then simultaneously performs the flow of the first component 丨 5, the flow of the second component 11 7, the flow of the third component 〖9, and the flow of the fourth component 1 21. The individual test procedures for each § memory component are the same. The timing diagram of FIG. 12 depicts the read instructions of the test method of the present invention to test a plurality of memory elements simultaneously. First memory element 丨 〇7, second

9554twf.ptd Page 23 567501

113, 70 parallel parts Π: the third memory element 11 1 to the nth memory element memory excess cycle ion access, tandem input cycle 96, instruction cycle 98, 13th fixed display-two, polling The bit signals 106 preferably appear simultaneously. Similarly, the sequenced instructions of the multiple $ _month 忒 methods are applied to the timing chart of m 'pieces at the same time. During the programming and erasing operation, the memory element has received the polling bit signal. -Once all m; according to the preferred embodiment, the necessary polling bit signals are forwarded ^ Bayi Chao goes to step 31.9. Time gate: 15 technicians' test time of reading procedure of traditional test element _τ is one clock cycle, and two books γ each time the pulse k is 50ns at this time, The test time is equal to SlUi for a single element. When the present invention (using 48 pins) is used to test 8 in parallel ^ ^ J2T1: ^ Γ; Γ6P2, f # ^ DUT " ^ 1/8 戍 26 2.5ns. For a traditional juxtaposed 1/0 test machine using the same number of probes (compared with type 2 ~ solid eye element ^ probes, such as 42), it will take 24 00ns because of the eight memories 7G pieces must be tested at a time and can only be called 0. For example, if the traditional test machine has ^ number of pins, it can indeed test all eight under the condition that the test time of each DUT is 300. Memory elements. However, @, if the test system of the present invention also has 8 times the number of pins, or 384 and the test time is 32.8ns, you can measure one element at a time.

9554twf.ptd Page 24 567501 V. Description of the invention (20) pieces. The test time is 30ns on a conventional test machine with the same number of pins. Valley βϋΤ Even, for those skilled in the art, the test time of using traditional test procedures is 50 to 115 (for the stylized process) of each component. 3 5us (for the actual use of 10 stylized pulses) In terms of programming, the test time for male and female is 35.5US. When the V 弋 ′ test time of the present invention is about 755 clock cycles for each DUT, in the case of the formula, the test time is equal to 37.75us. When using 1 till f ΓΛ4 3 70} ^ ^ ^ ", J ^ 8 ^ ^ ^ ^, J 忒 time is still 37.75US, making the test time of each DUT or 4.72u. For using the same number of probes (such as 48) or similar ,: 'Because 8 memory elements must be tested at one time ^ 1 unified test machine has 8 times the number of pins, and its value is as if J ^ ^ 35. 5us ^ ^ τ ^ ,, f; ^ UT;…, and, if the “!! test system of the present invention is also a piece of ^, a pin, the available test time is. _5; 64 元 # 'Compared with the same number of pins; and Lu, the test time of each DUT is 35 5u tandem = machine quality can reduce the test time. ^ The person skilled in the art of the present invention can know that The effective test of the method of the present invention uses the serial signal 丨 / 〇 / to signal the memory element. Although the present invention has been used to define the invention: i = not used to limit the invention. Anyone familiar with this, and its combination It ’s also worth noting that the present invention does not depart from the present invention ^ 554twf.ptd Page 25 567501 5. Within the spirit and scope of the invention description (21), it can be modified and retouched. For example, a tandem I / 0 test system More than one physical location to test the memory components, for example, the serial I / 0 test system can have four locations, each location Including 48 probes to facilitate testing of 32 memory elements at the same time. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

9554twf.ptd Page 26 567501 The diagram briefly illustrates a block diagram of a conventional technology connected to a memory element of a parallel 丨 / 0 test system. The second diagram is a block diagram of a connection to Semiconductor wafer: tandem I / 〇 test system for memory IC; Figures 3a and 3b are tandem I / O connections to sealed, self-body components according to two embodiments of the present invention 〇 Block diagram of the test system; Figure 4 shows the functional elements of the DRAM under test connected to the tandem 1/0 test system of the present invention; Figure 5 shows the serial 丨 / 〇 test system of the present invention Figure 6 of the functional element is a flow chart for testing a single memory element according to an embodiment of the present invention;-▲ Figure 7 is a single ° It body element implemented by the tandem 丨 / 〇 test system according to the present invention The sequence of the "read" instruction test;-Figure 8 is a list implemented by the tandem 丨 / 〇 test system according to the present invention. The timing sequence of the "programmed" instruction test of the memory element; Figure 9 above is a serial I / O test system connected to a plurality of memory element ICs on a semiconductor wafer according to an embodiment of the present invention; FIG. 10 is a tandem I / 0 test system connected to a plurality of package components and 1 C body according to an embodiment of the present invention; FIG. 11 is a test of a plurality of memories according to an embodiment of the present invention Figure 12 shows the sequence of the " read " instruction test of the memory device implemented by the tandem 丨 / 〇 test system according to the present invention; and

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Claims (1)

567501 VI. Scope of Patent Application Line 2: Financial Law 'It is performed by the test system: Fewer: d pieces, the memory element has a -th pin and an extra t foot. The test method includes the following steps : Input a clock to the memory / component through the first pin; input a serial address to the memory element through the additional pin, where the serial address is synchronized to the clock And input ;, when a command is input to the memory element and a pin read command, a serial write data is output from the extra pin at the clock, wherein the content write data is related The data is written in series in the memory element. 2. The test method as described in item 1 of the scope of patent application, wherein: the additional pin is a second pin; and the method further includes comparing the serially written data with an original step. σ, Bamboo Heart 3. The test method described in item 1 of the scope of patent application, further including steps: When the instruction is a stylized instruction, an initial data is input in series through the additional pin, where the The initial data is synchronized to the clock; the initial data is programmed into the memory element; and the programmed initial data is output from the memory element through the additional pin, where the programmed initial data is Data is output in synchronization with this clock. 4. The test method described in item 3 of the scope of application A, further including the step of comparing the stylized initial data with a wide range of data. 567501 6. Scope of patent application 5 · The test method described in item 1 of the scope of patent application, further includes the following steps: When the instruction is an erase instruction, the step of erasing the data stored in the memory element; And outputting a serial write data from the memory element through the additional pin, wherein the serial write data is related to being stored in the memory element and should be erased by the erase command Write data serially. 6. The test method as described in item '5 of the scope of patent application, wherein: the additional pin includes a second pin and a third pin; the serial address is input through the second pin The serial writing data is output from the third pin; and the test method further includes a step of analyzing the serial writing data. 7. The testing method described in item 6 of the scope of patent application, wherein the memory element further includes a fourth pin, a fifth pin, and a sixth pin, and the method further includes the following steps: A step of inputting a chip enable signal to the memory element at the fourth pin; a step of inputting an output enable signal to the memory element through the fifth pin; and an input of one through the sixth pin A step of writing an enable signal to the memory element. 8. A test method comprising the following steps: a step of providing a memory element and a timing signal; a step of serially inputting a bit address to the memory element, wherein the bit 9554twf.ptd Page 30 567501 6. The scope of patent application is synchronized with the timing signal and turns in; the step of inputting a command to the memory element analyzes the step of the command; once the command is analyzed as a read command , Using the address to access a memory location of the memory element; and once the instruction is analyzed as a read instruction, synchronize with the timing letter and output from the § memory location Information steps. 9 The testing method as described in the scope of the patent application 苐 8, wherein the step of outputting data from the memory position includes a step of outputting data from the memory position serially in synchronization with the timing signal. 10. The test method described in item 9 of the scope of patent application, wherein the step of providing a memory element and a timing signal is followed by the step of inputting the timing " is 5 tiger to the brother memory element. 11. The test method as described in item 10 of the scope of patent application, wherein the step of inputting the timing signal includes the step of inputting a clock " is 5 tiger to the A memory body element from the test system. 12. The testing method as described in item 11 of the scope of patent application, wherein the step of serially outputting data from the memory location includes: writing the previous serial from the memory location to the memory location Steps for serial data output. 13. If the test method described in item 12 of the scope of the patent application includes the method of comparing the serial output data with / original data. 14. The test method as described in item 12 of the scope of patent application, wherein: the step of providing a memory element is provided. The provision includes a first round Page 31 567501 6. The steps of applying for a memory element in the scope of patent application, a second input and a third input / output; the clock signal is input to the memory element through the first input; the address Input to the memory element through the second input; and the data output from the memory element through the third input / output. 15. The test method described in item 14 of the scope of patent application, wherein the step of providing a memory element includes: providing a memory element including an OPT ROM, an MTP ROM, an EPROM, and a flash memory. The steps. 16. The testing method according to item 14 of the scope of patent application, wherein the step of inputting a command to the memory element includes the step of inputting a command to the memory element through the third input / output. 17. The test method as described in item 14 of the scope of patent application, wherein once the instruction is analyzed to a stylized instruction, the step of analyzing the instruction is followed by the following steps: Synchronized in series with the clock signal Input to the memory element; program the initial data into the memory element, the memory location is related to the address; use the address to access the memory location; and synchronize with the clock signal Data is output from the memory location. 1 8. The test method described in item 17 of the scope of patent application, further comprising the step of comparing the output data with an original data. 1 9. The test method described in item 14 of the scope of patent application, wherein once 9554twf.ptd Page 32 567501 6. When the scope of patent application analyzes that the instruction is an erase instruction, the step of analyzing the instruction is followed by the following steps: Erase the data stored in the memory element, the memory The location is related to the address; using the address to access the memory location; and outputting data from the memory location in synchronization with the clock signal. 20. The test method described in item 19 of the scope of patent application, further comprising the step of analyzing output data from the memory location. 2 1. The test method described in item 14 of the scope of patent application, wherein the memory element further includes a fourth input, a fifth input, and a sixth input, and the method further includes the following steps: through the fourth A step of inputting a chip enable signal to the memory element through the input; a step of inputting an output enable signal to the memory element through the fifth input; and a write enable signal through the sixth input Steps to the memory element. 2 2. A tandem input / output test method, which is executed in a test system to test a memory element, the method includes the following steps: inputting a timing signal from the test system to the memory element; tandem Inputting an address to the memory element, the address being input to the memory element in synchronization with the timing signal from the test system; using the address to access a memory location; and 9554twf.ptd Page 33 567501 2 3: Such as :: 2 T ”and 5 times from the memory position, the second half of the turn, centered: 资料 the series described in item 22 of the patent scope ^ information. / 24 、 如^ Includes input-instructions to this memory element; wheel in and out test squares, straight through the steps described in item 23 of the scope of patent application. Method ,, and Chinese-style wheel in and out test side instructions ^ access When the input is executed, the command is a read. When the command is a read command, the output includes serially written data. The rotation in the step ♦ When the command is a read When fetching the instruction, the method writes the data with an original data. Compare the series 25. As in the method of patent application No. 23, where: 歹 歹 type input and output test party when the instruction is a stylized instruction Steps to pull the two positions and column t: At 7 o'clock, the access step is a step of serially inputting the element following the sequence of "sequence signal"; and a memory element; and a step of outputting data and an original data . ’It includes multiple I / O pins for convenience (b) programming the initial data to the method further includes comparing side-by-side communication of a parallel memory element between the parallel memory element and an external element in a standard operating mode of the memory element In one test mode, one of the pins of the parallel memory element is a clock-in clock signal and the other pin of the parallel memory element is synchronized with the clock signal and an external memory is used. 567501 VI. Scope of patent application Test the test piece to perform tandem I / 〇 fall. 2 7 · According to the parallel memory element described in item 26 of the scope of patent application, in the test mode 5, the other pin is synchronized to the $ Hla ^ τ pulse signal and input in series. Address signal. 2 8 · According to the parallel memory element described in item 27 of the scope of patent application, in the test mode, the other pin is a serial output signal synchronized to the clock signal, the data signal It is related to the assets stored in the memory unit of the parallel memory element indicated by the serial input address signal. ° ' 29. The parallel memory device according to item 28 of the scope of patent application, wherein the I / O pins include the one pin and the other pin. 30. The parallel memory device as described in the 28th item of the patent application scope, wherein the other pin includes:, a pin, which is in tandem input in synchronization with the clock signal in the test mode The address data; and, a pin, in the test mode, synchronizes the data signal with the clock signal in series. 31. The parallel memory device described in item 3 () of the scope of patent application, wherein the I / O pins include the certain pin and the other pin.