TW565907B - Manufacturing method of dielectric layers - Google Patents

Manufacturing method of dielectric layers Download PDF

Info

Publication number
TW565907B
TW565907B TW91125106A TW91125106A TW565907B TW 565907 B TW565907 B TW 565907B TW 91125106 A TW91125106 A TW 91125106A TW 91125106 A TW91125106 A TW 91125106A TW 565907 B TW565907 B TW 565907B
Authority
TW
Taiwan
Prior art keywords
layer
furnace tube
silicon
dielectric layer
manufacturing
Prior art date
Application number
TW91125106A
Other languages
Chinese (zh)
Inventor
Yung-Hsien Wu
Cheng-Che Li
Original Assignee
Promos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Promos Technologies Inc filed Critical Promos Technologies Inc
Priority to TW91125106A priority Critical patent/TW565907B/en
Application granted granted Critical
Publication of TW565907B publication Critical patent/TW565907B/en

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A manufacturing method of dielectric layers includes putting a substrate into a furnace and forming a silicon oxide layer on the substrate; performing an anneal process for transforming silicon oxide layer into silicon oxy-nitride layer; forming a silicon nitride layer on the silicon oxy-nitride layer; and forming a silicon oxide on the silicon nitride layer. Then silicon oxy-nitride layer/silicon nitride/silicon oxide stacked dielectric layers are formed on the substrate. The silicon oxy-nitride layer/silicon nitride/silicon oxide stacked dielectric layers are formed in the same furnace, so the process steps are reduced.

Description

565907565907

曰 修正 ^ 本發明是有關於一種應用在半導體元件上的一種介電 s的製造方法,且特別是有關於一種電容器介電層的製造 万法。 當整個半導體元件的積集度往越來越高時,動態隨機 存取記憶體(Dynamic Random Access Memory, DRAM)之纪 ,胞的面積也跟著越來越小。因此如何在有限的面積下提 記憶胞中電容器的儲存電荷量,也就成為一個重要 的课題。 容。。二般而言,增加電容器儲存電荷能力的方法有增加電 積、減少電容器介電層之厚度、以及 吊數之介電材料等。然而,增加雷 包 的穑隹谇η + ‘· 、丁 %令态的面積會使得dram J積本度(I n t e g r a t 1 ο η )下降;減,丨 六 八 則基於介電層均句度及穩定度的考旦广‘二入曰之厚度 成仍無法適當的應用。因此,辦力父溥的,,電層的形 方法,目前是往使用高介電常存電荷能力的 目前常用之電荷儲存電容的介;厗二:的方向發展。 矽所形成之堆疊層,例如氧化碎/ ―電層為由乳化矽和氮化 (Si/0/Ν)、氮化矽/氧化矽(N〇) 1化矽(0N)堆疊介電層 化矽/氧化矽/氮化矽(NON)堆聶八宜介電層(Sl/N/0)、氮 對於氧化矽/氮化矽(0N) $ 1,層(Si/N/0/N)。 堆疊介電層(Si/N/〇) 層之氧化層係在常壓下成長,無定7丨電層而言,由於其底 因此氧化矽/氮化矽(〇 N )堆疊介、、、去缩減其有效介電厚度, 的最大儲存電荷量。於是,氧化\層會嚴重的影響電容器 層(Si/0/Ν)已被氮化石夕/氧化 夕/氮化石夕(0N)堆疊介電 結構取代。 〇)Modification ^ The present invention relates to a method for manufacturing a dielectric s applied to a semiconductor device, and more particularly to a method for manufacturing a capacitor dielectric layer. When the integration degree of the entire semiconductor device is getting higher and higher, in the era of Dynamic Random Access Memory (DRAM), the area of the cell is also becoming smaller and smaller. Therefore, how to increase the stored charge of the capacitor in the memory cell under a limited area has become an important issue. Content. . Generally speaking, methods to increase the capacity of a capacitor to store charge include increasing the capacitance, reducing the thickness of the dielectric layer of the capacitor, and the number of dielectric materials. However, increasing the area of the 穑 隹 谇 η + '· and Ding% order of the thunder packet will make the dram J product degree (I ntegrat 1 ο η) decrease; decrease, 丨 68 is based on the average level of the dielectric layer and The stability of Kao Danguang's thickness is still unable to be properly applied. Therefore, the method of forming the electrical layer is currently the direction of the current commonly used charge storage capacitors with a high dielectric constant charge capacity; II: The direction of development. Stacked layers made of silicon, for example, oxidized particles /-the electrical layer is made of emulsified silicon and nitride (Si / 0 / N), silicon nitride / silicon oxide (N〇), siliconized silicon (0N) stacked dielectric layered Silicon / silicon oxide / silicon nitride (NON) stack Nie Bayi dielectric layer (Sl / N / 0), nitrogen for silicon oxide / silicon nitride (0N) $ 1, layer (Si / N / 0 / N) . The oxide layer of the stacked dielectric layer (Si / N / 〇) layer is grown under normal pressure. As for the dielectric layer, the silicon oxide / silicon nitride (〇N) stacked dielectric layer is To reduce its effective dielectric thickness, the maximum amount of stored charge. As a result, the oxide layer will seriously affect the capacitor layer (Si / 0 / N) has been replaced by the nitride dielectric / oxide / nitride (0N) stacked dielectric structure. 〇)

9727twfl.ptc 5659079727twfl.ptc 565907

對於氮化石夕/氡化矽(N ) 由於矽/氮化矽之取而浐访/11且” % ^〇1/Ν/〇)而言, 化石夕之界面缺陷Λ面ΛΓ,:石夕之界面差,亦即石夕/氮 此也會產生較hit f j:,界面缺陷密度高,因 有鑑於此,本發明之—目的 方法,可以於單一爐管中f作種,丨電層的製造 /氮化矽/氧化矽玱π 11製作具有间介電係數之氮氡化矽 /為〜化便夕,化…介電層(si/Sion/n/o),因此製程^ 夠 儲 本2明之另一目的為提出一種介 增加介電膜層的有效介電常· m :方法,能 存的電荷數增加,而提高電容器之:早位面積所能 :鑑於:’本發明提供一種: 而 基底置入-爐管中,然後在同一個姨二’::法’將-驟:於基底上形成—層氧化矽層,^中=序進行下列步 氧化矽層變成一層氮氧化矽層。接^谩’進仃回火製程使 成-層ι化矽層。之》,於氮化矽居:=氧化矽層上形 於基底上形成氮氧化碎/氮化珍/ ^ 21 一氧化碎層。 本發明於形成氮氧化矽/氮化疊介電層。 "SiON/N/O)之製程中係以臨礼化矽堆疊介電層 n Sltu)之方式形成For the nitride nitride / silicon nitride (N) due to the selection of silicon / silicon nitride / 11 and "% ^ 〇1 / N / 〇), the interface defect Λ plane ΛΓ of the fossil evening: Shi Xi The interface is poor, that is, Shi Xi / Ni will produce more than hit fj :, the interface defect density is high, so in view of this, the method of the present invention can be used to seed f in a single furnace tube. Manufacture / Silicon Nitride / Silicon Oxide π 11 Fabrication of Silicon Nitride Silicon with Dielectric Constant / It is a chemical layer (si / Sion / n / o), so the manufacturing process is sufficient Another purpose of Ming is to propose an effective dielectric constant that increases the dielectric film layer. M: method, which can increase the number of charges that can be stored, and increase the capacity of the capacitor: early area capacity: in view of: 'The present invention provides: The substrate is placed in the furnace tube, and then the same step: ': method' will be used to form-a layer of silicon oxide layer on the substrate, and the following steps are performed in order to form a silicon oxide layer into a silicon oxynitride layer. . Then ^ 谩 into the tempering process to form a silicon layer. In the silicon nitride layer: = silicon oxide layer is formed on the substrate to form oxynitride / nitridation. . / ^ 21 oxide broken layer of the present invention for forming silicon oxynitride / nitride stack of dielectric layers ". SiON / N / O) of the fabrication process based at Pro propriety of silicon stacked dielectric layers n Sltu) of the formed

565907 案號 91125106 年 月 曰 修正 五、發明說明(3) 之,即不同之時間下對同一個反應爐管通入不同之氣體來 進行不同之反應,完全不需如習知一般需要隨反應的不同 而更換反應爐管,因此可以簡化製程。 而且,先在低壓下形成一層薄的氧化矽層,然後再以 氧化亞氮為反應氣體,進行氧化製程後回火製程以形成氮 氧化矽層。利用上述方式所形成之氮氧化矽層與矽之界面 品質較直接於矽上形成氮氧化矽較之界面品質要好,因此 以本發明之方法形成之介電層具有較好之品質。 此外,以氧化亞氮為反應氣體,進行氧化製程後回火 製程時,藉由以S i - N鍵取代S i - 0鍵,不但可以增強氧化矽 層之品質,還可以減少電子陷入速率以及氧化矽缺陷點。 因而,可以增加氮氧化石夕層之可靠度。 另外,以氧化亞氮為反應氣體,進行氮化矽層之再氧 化製程,除了可以減少氮化矽層中的未完成鍵結的鍵結數 量,並且可以填補氮化石夕層中所可能產生針孔(P i n h ο 1 e s ) (亦即,可減少氮化矽層之缺陷),因此可以防止電容可能 會產生漏電之現象並提高崩潰電壓,使電容器可適用於高 電壓之操作。 而且,以本發明之介電層的製造方法所製造出之氮氧 化矽/氮化矽/氧4匕矽堆疊介電層可以作為堆疊式(S t a c k ) 電容器之介電層、溝渠式(Trench)電容器之介電層、以及 快閃記憶體之控制閘極與浮置閘極之間的多晶矽層間介電 層(Inter-Poly Dielectric Layer)等 ° 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂,下文特舉較佳實施例,並配合所附圖式,作詳細565907 Case No. 91125106 Amendment V. Description of the Invention (3) That is, different gases are introduced into the same reactor tube at different times to carry out different reactions. There is no need to follow the reaction as usual. The reaction furnace tube is changed differently, so the process can be simplified. Furthermore, a thin silicon oxide layer is formed under a low pressure, and then nitrous oxide is used as a reaction gas, and then an oxidation process is performed and then a tempering process is performed to form a silicon nitride oxide layer. The quality of the interface between the silicon oxynitride layer and silicon formed by the above method is better than that of forming the silicon oxynitride directly on silicon, so the dielectric layer formed by the method of the present invention has better quality. In addition, when nitrous oxide is used as a reaction gas and the tempering process is performed after the oxidation process, by replacing the Si-0 bond with Si-N bonds, not only the quality of the silicon oxide layer can be enhanced, but also the rate of electron trapping and Silicon oxide defects. Therefore, the reliability of the oxynitride layer can be increased. In addition, using nitrous oxide as a reaction gas to perform the re-oxidation process of the silicon nitride layer, in addition to reducing the number of unfinished bonds in the silicon nitride layer, and filling the pins that may be generated in the nitride layer Pins (P inh ο 1 es) (that is, the defects of the silicon nitride layer can be reduced), so that the capacitor may prevent leakage and increase the breakdown voltage, making the capacitor suitable for high voltage operation. Moreover, the silicon oxynitride / silicon nitride / oxygen silicon stacked dielectric layer manufactured by the manufacturing method of the dielectric layer of the present invention can be used as the dielectric layer and trench type of stacked capacitors. ) The dielectric layer of the capacitor, and the poly-crystalline silicon inter-layer dielectric layer (Inter-Poly Dielectric Layer) between the control gate and the floating gate of the flash memory. In order to make the above and other objects, features, And advantages can be more obvious and easy to understand, the following exemplifies preferred embodiments, and cooperates with the accompanying drawings to make details

9727twfl.pt c 第7頁 565907 _案號 91125106_年月日_ 五、發明說明(4) 說明如下: 圖式之標記說明: 10 0 基 底 10 2 下 電 極 層 10 4 氧 化 矽 層 10 6 氮 氧 化 矽層 10 8 氮 化 矽 層 11 0 氧 化 矽 層 11 2 上 電 極 層 實施例 本發明係為一種介電層的製造方法,在此係以製作一 電容器為實例做說明。 第1 A圖至第1 D圖是依照本發明較佳實施例的一種電容 器的製造方法流程圖。 請參照第1 A圖,提供一基底1 0 0,例如是矽基底,且 基底1 0 0上已完成部份半導體元件之製造,例如是已完成 金氧半電晶體(未圖示)之製造。接著,在基底100上形成 一層電容器之下電極層1 0 2。下電極層1 0 2之材質例如是多 晶矽,其形成的方法例如是化學氣相沉積法,或是以部份 矽基底單晶矽作為下電極。在下電極層1 0 2形成之後,下 電極層102於含氧的環境中,其表面會與周圍的氧產生氧 化反應,此氧化反應在室溫下即會進行,因而形成一層薄 薄的二氧化矽,稱為原生氧化層。因此,在進行下一製程 之前,通常會進行一清洗製程以移除原生氧化層。此清洗 製程例如是以氫氟酸作為清洗液。9727twfl.pt c Page 7 565907 _Case No. 91125106_Year_Month_5. Description of the invention (4) The description is as follows: 10 0 Substrate 10 2 Lower electrode layer 10 4 Silicon oxide layer 10 6 Nitrogen oxide Silicon layer 10 8 Silicon nitride layer 11 0 Silicon oxide layer 11 2 Example of the upper electrode layer The present invention is a method for manufacturing a dielectric layer, and a capacitor is used as an example for illustration. 1A to 1D are flowcharts of a method for manufacturing a capacitor according to a preferred embodiment of the present invention. Please refer to FIG. 1A to provide a substrate 100, such as a silicon substrate, and the manufacture of some semiconductor components on the substrate 100 has been completed, for example, the manufacture of a metal-oxide semiconductor (not shown) has been completed. . Next, an electrode layer 102 under the capacitor is formed on the substrate 100. The material of the lower electrode layer 102 is, for example, polycrystalline silicon, and a method for forming the lower electrode layer 102 is, for example, a chemical vapor deposition method, or a part of silicon-based single crystal silicon is used as the lower electrode. After the lower electrode layer 102 is formed, the surface of the lower electrode layer 102 will react with the surrounding oxygen in an oxygen-containing environment. This oxidation reaction will occur at room temperature, thus forming a thin layer of dioxide. Silicon is called the native oxide layer. Therefore, before the next process, a cleaning process is usually performed to remove the native oxide layer. This cleaning process uses, for example, hydrofluoric acid as a cleaning solution.

9727twfl.ptc 第8頁 565907 _案號91125106_年月日__ 五、發明說明(5) 然後,將基底1 0 0置入低壓化學氣相沈積爐管(L 0 W Pressure Chemical Vapor Deposition Furnace),於下 電極層102上形成一層氧化石夕層104。此氧化石夕層104之形 成方法例如是以氧氣為製程氣體,通入低壓化學氣相沈積 爐管中以進行反應,反應壓力例如是0 . 5托耳(T 〇 r r )、反 應溫度例如是9 0 0 °C左右,使氧氣與多晶矽(矽)反應而形 成厚度例如是1 5埃之氧化矽層1 0 4。 接著,請參照第1 B圖,進行氧化製程後回火製程。在 同一個低壓化學氣相沈積爐管中,以氧化亞氮(N20 )為製程 氣體以進行反應,反應壓力例如是0 . 5托耳(T ◦ r r )、反應 溫度例如是9 0 0 °C左右,使氧化亞氮與氧化矽層1 0 4反應而 形成氮氧化矽層1 0 6。在以氧化亞氮氣體進行氧化製程後 回火製程時,藉由以S i - N鍵取代S i - 0鍵而在矽/二氧化矽 之界面附近形成富氮層(Nitrogen-Rich Layer),不但可 以增強氧化矽層之品質,還可以減少電子陷入速率以及氧 化矽缺陷點。因而,可以增加氮氧化矽層1 0 6之可靠度。 接著,請參照第1 C圖,於氮氧化矽層1 0 6上形成一層 氮化矽層1 0 8。此氮化矽層1 0 8之形成方法例如是以二氣矽 烷(SiH2Cl2)與氨氣(NH3)為製程氣體,通入低壓化學氣相沈 積爐管中以進行反應,反應壓力例如是〇 . 2 5托耳(T 〇 r r )、 反應溫度例如是7 0 0 °C左右,使二氯矽烷(Si H2C12)與氨氣 (N H.0反應而於氮氧化矽層1 0 6上形成厚度例如是3 5埃之氮 化石夕層1 0 8。 請參照第1 D圖,在未更換低壓化學氣相沈積爐管之情 況下,進行氮化矽層1 0 8之再氧化製程。以氧化亞氮(N20 )9727twfl.ptc Page 8 565907 _Case No. 91125106_Year_Month__ V. Description of the invention (5) Then, put the substrate 100 into the low pressure chemical vapor deposition furnace tube (L 0 W Pressure Chemical Vapor Deposition Furnace) A stone oxide layer 104 is formed on the lower electrode layer 102. The method for forming the oxidized stone layer 104, for example, uses oxygen as a process gas, and passes it into a low-pressure chemical vapor deposition furnace tube to perform a reaction. The reaction pressure is, for example, 0.5 Torr (Torr), and the reaction temperature is, for example, At about 900 ° C, oxygen is reacted with polycrystalline silicon (silicon) to form a silicon oxide layer 104 having a thickness of, for example, 15 angstroms. Next, referring to FIG. 1B, the tempering process is performed after the oxidation process. In the same low-pressure chemical vapor deposition furnace tube, nitrous oxide (N20) is used as the process gas for the reaction. The reaction pressure is, for example, 0.5 Torr (T ◦ rr), and the reaction temperature is, for example, 9 0 ° C. Right and left, the nitrous oxide is reacted with the silicon oxide layer 104 to form a silicon oxynitride layer 106. Nitrogen-Rich Layer is formed near the silicon / silicon dioxide interface by replacing the Si-0 bond with the Si-N bond during the tempering process after the oxidation process with a nitrous oxide gas. Not only can enhance the quality of the silicon oxide layer, but also reduce the rate of electron sinking and silicon oxide defect points. Therefore, the reliability of the silicon oxynitride layer 106 can be increased. Next, referring to FIG. 1C, a silicon nitride layer 108 is formed on the silicon oxynitride layer 106. The formation method of the silicon nitride layer 108 is, for example, two gas silane (SiH2Cl2) and ammonia gas (NH3) as a process gas, which is passed into a low-pressure chemical vapor deposition furnace tube for reaction, and the reaction pressure is, for example, 0. 25 Torr (Torr), the reaction temperature is, for example, about 700 ° C, dichlorosilane (Si H2C12) and ammonia (N H.0) are reacted to form a thickness on the silicon oxynitride layer 106 For example, it is a nitride layer with a thickness of 35 angstroms 108. Please refer to Figure 1D, and perform the reoxidation process of the silicon nitride layer 108 without changing the low-pressure chemical vapor deposition furnace tube. Nitrous (N20)

9727twfl.ptc 第9頁 565907 _案號 91125106_年月日__ 五、發明說明(6) 為製程氣體以進行反應,反應壓力例如是0 . 5托耳 (T 〇 r r )、反應溫度例如是9 0 0 °C左右,使氧化亞氮與氮化 石夕層108反應而形成一層氧化石夕層110。在I化石夕層108之 再氧化製程中,除了可以減少氮化矽層1 0 8中的未完成鍵 結的鍵結數量,並且可以填補氮化矽層1 0 8中所可能產生 針孔(P i n h ο 1 e s )(減少氮化石夕層之缺陷),因此可以防止電 容可能會產生漏電之現象並提高崩潰電壓,使電容器可適 用於高電壓之操作。 之後,再於氧化矽層110上形成一層電容器之上電極 層1 1 2。上電極層1 1 2之材質例如是多晶石夕,其形成的方法 例如為化學氣相沉積法。 由上述本發明較佳實施例可知,本發明於形成氮氧化 矽/氮化矽/氧化矽堆疊介電層(S i / S i Ο N / N / 0 )之製程中係 以臨場(I n S i t U )之方式形成之,即不同之時間下對同一 個反應爐管通入不同之氣體來進行不同之反應,完全不需 如習知一般需要隨著反應的不同而更換反應爐管,因此可 以簡化製程。 而且,先在低壓下形成一層薄的氧化石夕層,然後再以 氧化亞氮為反應氣體,進行氧化製程後回火製程形成氮氧 化矽層。利用上述方式所形成之氮氧化矽層與矽之界面品 質較直接於矽上形成氮氧化矽較之界面品質要好,因此以 本發明之方法形成之介電層具有較好之品質。 此外,以氧化亞氮為反應氣體,進行氧化製程後回火 製程時,藉由以S i - N鍵取代S i - 0鍵,不但可以增強氧化矽 層之品質,還可以減少電子陷入速率以及氧化矽缺陷點。9727twfl.ptc Page 9 565907 _ Case No. 91125106 _ year month day__ 5. Description of the invention (6) is a process gas for the reaction, the reaction pressure is, for example, 0.5 Torr (T 〇rr), the reaction temperature is, for example, At about 900 ° C., the nitrous oxide is reacted with the nitrided oxide layer 108 to form a layer of oxided oxide layer 110. In the re-oxidation process of the I fossil layer 108, in addition to reducing the number of unfinished bonds in the silicon nitride layer 108, and can fill pinholes that may occur in the silicon nitride layer 108 ( P inh ο 1 es) (reducing the defects of the nitride nitride layer), so it can prevent the leakage of the capacitor and increase the breakdown voltage, making the capacitor suitable for high voltage operation. After that, a capacitor electrode layer 1 1 2 is formed on the silicon oxide layer 110. The material of the upper electrode layer 1 12 is, for example, polycrystalline stone, and a method for forming the same is, for example, a chemical vapor deposition method. It can be known from the above-mentioned preferred embodiments of the present invention that the present invention is based on the field (I n) in the process of forming a silicon oxynitride / silicon nitride / silicon oxide stacked dielectric layer (S i / S i Ο N / N / 0). S it U) method, that is, different gases are passed into the same reaction furnace tube at different times to carry out different reactions. There is no need to replace the reaction furnace tube with the different reactions as is common practice. Therefore, the process can be simplified. In addition, a thin layer of oxidized stone is formed under low pressure, and then a nitrous oxide is used as a reaction gas, and then an oxidation process is performed to form a silicon nitride oxide layer. The quality of the interface between the silicon oxynitride layer and silicon formed by the above method is better than that of directly forming silicon oxynitride on silicon. Therefore, the dielectric layer formed by the method of the present invention has better quality. In addition, when nitrous oxide is used as a reaction gas and the tempering process is performed after the oxidation process, by replacing the Si-0 bond with Si-N bonds, not only the quality of the silicon oxide layer can be enhanced, but also the rate of electron trapping and Silicon oxide defects.

9727twfl.ptc 第10頁 565907 _案號 91125106_年月日_^_ 五、發明說明(7) 因而,可以增加氮氧化石夕層之可靠度。 另外,以氧化亞氮為反應氣體,進行氮化矽層之再氧 化製程,除了可以減少氮化矽層中的未完成鍵結的鍵結數 量,並且可以填補氮化矽層中所可能產生針孔(P i n h ο 1 e s ) (減少氮化矽層之缺陷),因此可以防止電容可能會產生漏 電之現象並提高崩潰電壓,使電容器可適用於高電壓之操 作。 在本發明之實施例中係以形成電容器介電層為實例做 說明,當然以本發明之介電層的製造方法所製造出之氮氧 化矽/氮化矽/氧化矽堆疊介電層還可以作為堆疊式電容器 之介電層、溝渠式電容器之介電層、以及快閃記憶體之控 制閘極與浮置閘極之間的多晶石夕層間介電層(I n t e r - Ρ ο 1 y Dielectric Layer)等 。 雖然本發明以較佳實施例揭露如上,然其並非用以限 定本發明,任何熟習此技藝者,在不脫離本發明之精神和 範圍内,當可作各種之更動與潤飾,因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。9727twfl.ptc Page 10 565907 _Case No. 91125106_ Year Month Day _ ^ V. Description of the invention (7) Therefore, the reliability of the oxynitride layer can be increased. In addition, using nitrous oxide as the reaction gas to perform the re-oxidation process of the silicon nitride layer, in addition to reducing the number of unfinished bonds in the silicon nitride layer, and filling the pins that may be generated in the silicon nitride layer Pins (P inh ο 1 es) (reducing defects in the silicon nitride layer), so it can prevent the capacitor from leaking and increase the breakdown voltage, making the capacitor suitable for high voltage operation. In the embodiment of the present invention, the formation of a capacitor dielectric layer is taken as an example for description. Of course, the silicon oxynitride / silicon nitride / silicon oxide stacked dielectric layer manufactured by the manufacturing method of the dielectric layer of the present invention can also be used. As the dielectric layer of stacked capacitors, the dielectric layer of trench capacitors, and the polycrystalline silicon interlayer dielectric layer between the control gate and floating gate of flash memory (I nter-Ρ ο 1 y Dielectric Layer). Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

9727twfl.ptc 第11頁 5659079727twfl.ptc Page 11 565907

9727twil.pic 第12頁9727twil.pic Page 12

Claims (1)

565907 _案號 91125106_年月日__ 六、申請專利範圍 1 . 一種介電層的製造方法,該方法包括: 提供一基底; 將該基底置於一爐管中; 在該爐管内’於該基底上形成一氧化石夕層; 在該爐管内,進行回火製程包括將一氧化亞氮通入該 爐管中,使該氧化亞氮與該氧化碎層反應形成一氮氧化石夕 層; 在該爐管内,於該氮氧化矽層上形成一氮化矽層;以 及 在該爐管内,於該氮化$夕層上形成一氧化石夕層。 2 ·如申請專利範圍第1項所述之介電層的製造方法, 其中在該爐管内,於該基底上形成該氧化矽層之步驟包括 將一氧氣通入該爐管中,使該氧氣與該基底之碎反應形成 該氧化矽層。 3. 如申請專利範圍第1項所述之介電層的製造方法, 其中在該爐管内,於該氮氧化矽層上形成該氮化矽層之步 驟包括將一二氣矽烷與一氨氣通入該爐管中,使該二氯矽 烷與該氨氣反應形成該氮化矽層。 4. 如申請專利範圍第1項所述之介電層的製造方法, 其中在該爐管内,於該氮化矽層上形成該氧化矽層步驟包 括將一氧化亞氮通入該爐管中,使該氧化亞氤與該氮化矽 層反應形成該氡化石夕層。 5. —種電容器介電層的製造方法’適用於一基底’該 基底已形成一下電極層之製造,該方法包括:565907 _ Case No. 91125106_year month__ VI. Patent Application Scope 1. A method for manufacturing a dielectric layer, the method includes: providing a substrate; placing the substrate in a furnace tube; inside the furnace tube; A oxide layer is formed on the substrate; in the furnace tube, the tempering process includes passing nitrous oxide into the furnace tube, so that the nitrous oxide reacts with the oxidized fragment layer to form a nitrous oxide layer Forming a silicon nitride layer on the silicon oxynitride layer in the furnace tube; and forming a stone oxide layer on the nitrided layer in the furnace tube; 2. The manufacturing method of the dielectric layer according to item 1 of the scope of the patent application, wherein the step of forming the silicon oxide layer on the substrate in the furnace tube includes passing an oxygen gas into the furnace tube to make the oxygen gas The chip reaction with the substrate forms the silicon oxide layer. 3. The method for manufacturing a dielectric layer according to item 1 of the scope of the patent application, wherein the step of forming the silicon nitride layer on the silicon oxynitride layer in the furnace tube includes combining a two-gas silane and an ammonia gas. Pass into the furnace tube, and react the dichlorosilane and the ammonia gas to form the silicon nitride layer. 4. The method for manufacturing a dielectric layer according to item 1 of the scope of patent application, wherein the step of forming the silicon oxide layer on the silicon nitride layer in the furnace tube includes passing nitrous oxide into the furnace tube. , Reacting the hafnium oxide with the silicon nitride layer to form the hafnium fossil layer. 5. A method for manufacturing a capacitor dielectric layer is applicable to a substrate. The substrate has been formed with an electrode layer, and the method includes: 9727twfl.ptc 第13頁 565907 _案號 91125106_年月日__ 六、申請專利範圍 將已形成該下電極層之該基底置於一爐管中; 在該爐管内,於該下電極層上形成一氧化矽層; 在該爐管内,進行回火製程包括將一氧化亞氮通入該 爐管中,使該氧化亞氮與該氧化矽層反應形成一氮氧化矽 層; 在該爐管内,於該氮氧化矽層上形成一氮化矽層;以 及 在該爐管内,於該氮化矽層上形成一氧化矽層。 6 .如申請專利範圍第5項所述之電容器介電層的製造 方法,其中在該下電極層之材質包括多晶矽。 7.如申請專利範圍第6項所述之電容器介電層的製造 方法,其中在該爐管内,於該基底上形成該氧化矽層之步 驟包括將一氧氣通入該爐管中,使該氧氣與該下電極層之 矽反應形成該氧化矽層。 8 .如申請專利範圍第5項所述之電容器介電層的製造 方法,其中在該爐管内,於該氮氧化矽層上形成該氮化矽 層之步驟包括將一二氯矽烷與一氨氣通入該爐管中,使該 二氯矽烷與該氨氣反應形成該氮化矽層。 9 .如申請專利範圍第5項所述之電容器介電層的製造 方法,其中在該爐管内,於該氮化矽層上形成該氧化矽層 步驟包括將一氧化亞氮通入該爐管中,使該氧化亞氤與該 氮化矽層反應形成該氧化矽層。 1 0 .如申請專利範圍第5項所述之電容器介電層的製造 方法,其中該爐管包括低壓化學氣相沈積爐管。9727twfl.ptc Page 13 565907 _Case No. 91125106_Year_Month__ Sixth, the scope of the patent application is to place the substrate that has formed the lower electrode layer in a furnace tube; in the furnace tube, on the lower electrode layer Forming a silicon oxide layer; performing a tempering process in the furnace tube includes passing nitrous oxide into the furnace tube, and reacting the nitrous oxide with the silicon oxide layer to form a silicon nitride oxide layer; in the furnace tube Forming a silicon nitride layer on the silicon oxynitride layer; and forming a silicon oxide layer on the silicon nitride layer in the furnace tube. 6. The method for manufacturing a capacitor dielectric layer according to item 5 of the scope of patent application, wherein the material of the lower electrode layer includes polycrystalline silicon. 7. The method for manufacturing a capacitor dielectric layer according to item 6 of the scope of the patent application, wherein the step of forming the silicon oxide layer on the substrate in the furnace tube includes passing an oxygen gas into the furnace tube to make the Oxygen reacts with the silicon of the lower electrode layer to form the silicon oxide layer. 8. The method for manufacturing a capacitor dielectric layer as described in item 5 of the scope of the patent application, wherein the step of forming the silicon nitride layer on the silicon oxynitride layer in the furnace tube includes dichlorosilane and ammonia. Gas is passed into the furnace tube, and the dichlorosilane and the ammonia gas are reacted to form the silicon nitride layer. 9. The method for manufacturing a capacitor dielectric layer according to item 5 of the scope of patent application, wherein the step of forming the silicon oxide layer on the silicon nitride layer in the furnace tube includes passing nitrous oxide into the furnace tube In the process, the ytterbium oxide is reacted with the silicon nitride layer to form the silicon oxide layer. 10. The method for manufacturing a capacitor dielectric layer according to item 5 of the patent application scope, wherein the furnace tube comprises a low-pressure chemical vapor deposition furnace tube. 97271 wt'l . pt c 第14頁 565907 _案號 91125106_年月日__ 六、申請專利範圍 1 1 . 一種介電層的製造方法,該方法包括: 提供一基底; 將該基底置於一爐管内; 於該爐管中通入一第一氣體,以於該基底上形成一第 一介電層; 於該爐管中通入一第二氣體並進行回火製程,以使該 第一介電層變成一第二介電層; 於該爐管中通入一第三氣體,以於該第二介電層上形 成一第三介電層;以及 於該爐管中通入一第四氣體,以於該第三介電層上形 成一第四介電層。 1 2 ·如申請專利範圍第1 1項所述之介電層的製造方 法,其中該第一氣體包括氧氣。 1 3 ·如申請專利範圍第1 1項所述之介電層的製造方 法,其中該第二氣體包括氧化亞氮。 1 4 .如申請專利範圍第1 1項所述之介電層的製造方 法,其中該第三氣體包括二氯矽烷與氨氣。 1 5 ·如申請專利範圍第1 1項所述之介電層的製造方 法,其中該第四氣體包括將氧化亞氮。 1 6 .如申請專利範圍第1 1項所述之介電層的製造方 法,其中該第一介電層包括氧化矽層。 1 7 .如申請專利範圍第1 1項所述之介電層的製造方 法,其中該第二介電層包括氮氧化矽層。 1 8 .如申請專利範圍第1 1項所述之介電層的製造方97271 wt'l. Pt c page 14 565907 _ case number 91125106_ year month__ VI. Patent application scope 1 1. A method of manufacturing a dielectric layer, the method includes: providing a substrate; placing the substrate on A furnace tube; a first gas is passed into the furnace tube to form a first dielectric layer on the substrate; a second gas is passed into the furnace tube and a tempering process is performed so that the first A dielectric layer becomes a second dielectric layer; a third gas is passed into the furnace tube to form a third dielectric layer on the second dielectric layer; and a A fourth gas to form a fourth dielectric layer on the third dielectric layer. 1 2. The method for manufacturing a dielectric layer according to item 11 of the patent application, wherein the first gas includes oxygen. 1 3. The method for manufacturing a dielectric layer according to item 11 of the patent application, wherein the second gas includes nitrous oxide. 14. The method for manufacturing a dielectric layer according to item 11 of the scope of patent application, wherein the third gas includes dichlorosilane and ammonia gas. 1 5. The method for manufacturing a dielectric layer according to item 11 of the patent application, wherein the fourth gas includes nitrous oxide. 16. The method for manufacturing a dielectric layer according to item 11 of the scope of patent application, wherein the first dielectric layer includes a silicon oxide layer. 17. The method for manufacturing a dielectric layer according to item 11 of the scope of patent application, wherein the second dielectric layer includes a silicon oxynitride layer. 1 8. The manufacturer of the dielectric layer as described in item 11 of the scope of patent application 9727twfl.ptc 第15頁 5659079727twfl.ptc Page 15 565907 9727twfl.pt c 第16頁9727twfl.pt c p. 16
TW91125106A 2002-10-25 2002-10-25 Manufacturing method of dielectric layers TW565907B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW91125106A TW565907B (en) 2002-10-25 2002-10-25 Manufacturing method of dielectric layers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW91125106A TW565907B (en) 2002-10-25 2002-10-25 Manufacturing method of dielectric layers

Publications (1)

Publication Number Publication Date
TW565907B true TW565907B (en) 2003-12-11

Family

ID=32502672

Family Applications (1)

Application Number Title Priority Date Filing Date
TW91125106A TW565907B (en) 2002-10-25 2002-10-25 Manufacturing method of dielectric layers

Country Status (1)

Country Link
TW (1) TW565907B (en)

Similar Documents

Publication Publication Date Title
US7479425B2 (en) Method for forming high-K charge storage device
JP5032056B2 (en) Method for manufacturing nonvolatile semiconductor memory device
US8211811B2 (en) Semiconductor device and method for manufacturing the same
CN101271841B (en) Method of manufacturing semiconductor device
US7122415B2 (en) Atomic layer deposition of interpoly oxides in a non-volatile memory device
CN100452440C (en) Nonvolatile semiconductor memory device and method of manufacturing the same
US8426909B2 (en) Nonvolatile semiconductor memory device
JP5032145B2 (en) Semiconductor device
US8609487B2 (en) Method of manufacturing semiconductor device
US7405482B2 (en) High-k dielectric film, method of forming the same and related semiconductor device
JP5443873B2 (en) Semiconductor device and manufacturing method thereof
US7595240B2 (en) Flash memory device with stacked dielectric structure including zirconium oxide and method for fabricating the same
US7508649B2 (en) Multi-layered dielectric film of microelectronic device and method of manufacturing the same
JP2007043147A (en) Method of forming silicon-rich nanocrystal structure using atomic layer deposition process and method of manufacturing nonvolatile semiconductor device using the same
US20090309187A1 (en) Semiconductor Device and Method of Fabricating the Same
JP2008270700A (en) Non-volatile memory element and manufacturing method
JP2005005715A (en) Sonos memory device and its manufacturing method
JP2007073926A (en) Dielectric film and its forming method, and semiconductor memory device equipped with dielectric film and its manufacturing method
US10741383B2 (en) Semiconductor device and method of manufacturing the same
US20080157181A1 (en) Non-volatile memory device and fabrication method thereof
JP2010062387A (en) Nonvolatile semiconductor storage device
CN111725224A (en) Semiconductor memory device and method of manufacturing the same
TW565907B (en) Manufacturing method of dielectric layers
US8604536B2 (en) Semiconductor device and method of manufacturing the same
CN1249791C (en) Manufacturing method of dielectric layer

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent