TW564562B - Three dimensional integrated circuits using sub-micron thin-film diodes - Google Patents

Abstract

This invention provides practical methods to fabricate sub-micron 3D integrated circuits using multiple layers of diodes manufactured on polycrystal1ine or amorphous semiconductor thin films. The long existing problems for using poly diodes for high density IC are solved by design and manufacture methods. The circuit design methods of the present invention improve the tolerance in non-ideal properties of diodes. The resulting IC products can function correctly even when many of their diodes are defective. We also developed manufacture procedures fully compatible with current art IC technologies. No additional masking steps or high temperature procedures are used. The 3D IC devices of the present invention are ready to be manufactured by current art IC technologies. Integrated circuits with unprecedented densities are therefore realized by stacking thin film diodes upon common active devices.

Description

564562 V. Description of the invention (1) ———— [Background of the invention] (1) Field of the invention If the method of the present invention is about how to improve the density of high-performance integrated circuits, especially the method of using-human micron thin film diodes Active components are stacked vertically to increase integrated circuit density. (2) Description of the conventional art The element is metal oxide. The 3D circuit described in the present invention means that there is more than one active element on the same substrate area. Under the current prior art, it is impossible to have more than or equal to the active area in the same base area. usually! c Most active semiconductor (MOS) transistors and bipolar transistors are used. Components that play a key role in the performance of the overall component are often made on a semiconducting substrate to obtain quality control; the same can be produced on it: quality: millions of transistors. Since it is impossible at the same time ^) t ® Til Ϊ i transistor to share a substrate, it is impossible to use ^ ^: thin 2: 3D circuit. Some people have made efforts ‘by growing more’ and saying “early sun /,” I made 3D circuits. However, it has proved to be quite difficult to produce performance-consistent MOS transistors on such films. To our knowledge, no research effort has been successful. The main active element used in IC design for integrated circuits is the transistor. Diodes are rarely used because it is difficult to make a large number of diodes with the same performance. Many inventions have proposed the use of silicon diodes to make read-only memory (ROM). For example, in U.S. Patent No. 4,399,450, Lohstroh uses silicon monopoles to make ROM. In U.S. Patent No. 4, 6 6 1, 9 27, Graebel uses Schottky diodes (Schottky diodes ^ 564562 V. Description of the invention (2) to make programmable logic array (PLA) and ROM. In the United States In Patent No. 5, 5 5 0, 0 75, Hsu et al. Introduced a technology for making ROM using small silicon-based diodes. Diodes are described in US Patent No. 4,845,679 ~ Field-effect transistor logic circuit (diode-FET logic circuit), and Ogura et al. In the United States Patent No. 4, 65 9, 947 gave another PLA design. The above inventions are made on a single crystal substrate diode A single crystal diode is not necessarily smaller than a M0S transistor. The traditional M0S transistor circuit will be more superior in terms of performance, production and cost. There is nothing to make a integrated circuit using a single crystal diode. Advantages. At the same time, because this type of diode uses a single crystal substrate, there is nothing to make 3D circuits. Another method is to use polycrystalline silicon or two =. As a thin film diode. In the United States No. 5, 2 72, 37〇 Junior High School ~ Said that a thin silicon film is used for ROM thin film elements. Su T 'FrenCh describes Shi Xi Diode. The type of thin film diode occupies a small area' but ', it is controlled in contact with the production process. Amorphous silicon and polycrystalline silicon materials have many defects: = quality! Components that are difficult to manufacture will deviate far Ideally, components made on multi-defective material crystals are compared to reverse-biased electricity generators. These components and monocrystalline silicon have been studied in large scales.1 Now polycrystalline silicon and beta-cell area components are being studied. From the average effect, these thin-film diodes exhibit good integrated circuit of large area density secondary parts with two defects, making large: consistent. It is very difficult for high sub-micron thin-film diodes. The defect density of the same nature body is almost impossible to predict if it is less than the mother sub-micron diode. Sung 箄 ren ^ The performance plug of the solo diode was in contact with the opening, and it can be said that because the daggers are made more clearly Through. In those sub-micron contact holes

Page 6 V. Description of the invention (3) The particle size of Xi Xing Shi Xi must be within the range of μm for quality control of alfalfa β elements. For such a special technical process to make these diodes, the above inventions all require the core two heat:;: know the materials required to use the diode. Since these ports are known, there are far > there are high integrated circuits manufactured using the current existing technology. [Objective of the Invention] The primary purpose of the present invention is to provide a feasible method for manufacturing sub-micron 3D integrated circuits. Another object is to provide an improved and reproducible thin film diode. Another object is to provide a method for improving the inconsistency of the unintended characteristics of the thin film diode. Another main goal is to achieve this through a manufacturing process compatible with existing process technology. All of those goals are achieved by the design and manufacturing methods of the present invention. For the sake of simplicity, in the following description, "polycrystalline or amorphous" thin films are referred to as "polycrystalline." · Polycrystalline diodes are used as active elements in high-density integrated circuits, and there are two main difficult. The first difficulty is that it is very difficult to make the same sub-micron thin film diode. The second difficulty is to make these diodes without damaging other integrated circuit components. Thin-film diodes are fabricated on defective materials. When the performance characteristics of these small components are determined by local defects, it is difficult to produce a large number of sub-micron thin-film diodes with the same performance. Therefore, the manufacturing technology of the present invention is developed and improved, so that the active area of the element is far from the high-density defect area, and the thin film diode is matched.

564562 V. Description of Invention (4)

The internal defects are not sharp. At the same time, we also describe design methods to improve the tolerance of non-ideal characteristics of the diode. Reduce the number of diodes at each node. Use a three-phase driver to reduce the effect of reverse leakage current. Improvements in design and manufacturing methods have enabled the use of polycrystalline thin film diodes to fabricate integrated circuits. However, in actual implementation, another obstacle will be encountered. As part of the manufacturing process, polycrystalline thin films require high temperature annealing. This high temperature process can affect important properties of other integrated circuit units, such as the punch-through voltage of sub-micron transistors, or the electro-migration characteristics of metal wires. The introduction of high-temperature heat treatment in integrated circuit manufacturing technology requires detailed standardization and considerable labor. Therefore, the present invention discloses a manufacturing process that is completely compatible with the existing manufacturing technology, without using an additional high-temperature heat treatment process, and without using an additional cover. The present invention shows that the existing integrated circuit manufacturing technology can be used to manufacture 3D integrated circuit components. Ultra-high-density integrated circuits can be realized by stacking thin-film diodes and traditional MOS transistors together. The density of logic circuit components has increased by almost an order of magnitude.

When we explain the novel features of the present invention in an additional statement, the present invention, both in terms of organization and content, together with its other purposes and features, will be well understood in the detailed description of the accompanying drawings And agree. [Comparison of drawing numbers] 1 0 1 P 2 C mask 1 0 2 Source region of transistor. 1 0 3 Drain region of transistor 1 0 5 Isolation region oxide 1 15 Insulation layer 117 P3C mask

Page 8 564562 V. Description of the invention (7) Mask step 2 (MS2): Construct a p-well region with a p-well mask. The doping of the P-well is obtained by ion implantation. °° s Zone Growth Screen Step 3 (MS3): Construct active active area oxide with active area screen. Fig. 1a shows the soil 1 of the oxide 105 in the isolation region. The structure is masked. Step 4 (MS4): A thin film isolation layer is formed on the active region described in MS3. A first polycrystalline film (P 丨) is deposited. Through tampering, the polycrystalline thin film connection and transistor gate region are defined. For current DRAM technology, P1 generally performs n-type high doping. In order to reduce the & impedance of the p-line, a silicide layer is often grown on P1. A series of 'manufacturing processes, such as the deposition of a space isolation layer, are used to construct the gate structure of the MOS transistor. A. Mask step 5 (MS5): Use the n + mask to construct the _ diffusion region. The n-type doping is achieved by ion implantation. The construction of the source regions 102 and> of the n-channel Mos transistor and the region 103 and the n-type diffusion · region are completed in this step. Mask step 6 (MS6): Use ρ + mask construction? Type diffusion zone. Ion implantation is used to achieve p-type doping. The construction of the source and drain regions of the p-channel Mos transistor and the p-type diffusion region are completed in this step. An intermediate insulating layer 115 is deposited to form an isolation layer, as shown in the cross-sectional view in FIG. All of the above manufacturing processes are known processes. So far. The element structure is the same as the conventional element structure. This is how we only use the u figure to show the component structure after the above 6-step mask process. It is not necessary to describe it in the detailed description later. Mask step 7 (MS7): Make the P2C mask 101 a second polycrystalline film

564562 V. Description of the invention (π) 5 types of M 1 contacts: diffusion contact (CC) forms a connection between M 1 and the substrate source region 102, and polycrystalline contact (Cp4—Cpl) between M1 and the polycrystalline layer (P4— P1) to form a connection, as shown in Figure lm. These five types of Ml contacts (CC, Cp4-Cpl) are formed simultaneously using the same traditional process in the same mask step. All these contacts are ohmic contacts. Mask step 14 (MS14): M1 region is constructed using M1 mask, followed by etching. After the etching is completed, another intermediate insulating layer 198 is deposited to form an isolation.

Mask step 15 (MS 15): Use the channel mask to define the contact area for the second metal layer (m2), use M1 as the blocking layer, and select the plasma to etch the contact opening. After the mask is removed, a second metal layer (M2) is deposited. The only M2 contact currently allowed in integrated circuits forms a connection between M2 and M1. This contact is called π channel π. Mask 16 (MS16): The M2 area is formed by the M2 mask and the etching process. After the etching is complete, a layer of waterproof layer 199 is deposited to provide protection. The above process of the present invention has the following advantages: (1) The monopoles Cd23 and Cd34 are placed on the upper part of the active region of the MOS transistor. Multilayer diodes (Cdl2, Cd23, Cd34) can be stacked one after the other. This 3D structure allows us to obtain ultra-high-density element densities (2) The manufacturing process is consistent across all manufacturing processes of the present invention. Our type of 3D integrated circuit. (3) It is used to define the traditional contact process and the use of traditional integrated circuit technology. A new mask step can be made using traditional manufacturing methods. It can be used to define the film.

Page 15 564562 V. Description of the invention (12) Diode region. Compared with the traditional integrated circuit manufacturing process, the number of mask steps has not changed. (4) The polycrystalline thin film layer used in the conventional IC technology can be used to make a thin film diode. Since we do not use an additional polycrystalline layer, no change will occur during high temperature thermal processing. Here we have only shown some specific embodiments of the invention, and those skilled in the art know that many changes and modifications are possible. It should be understood that the above examples are merely examples and are not the entire contents of the present invention. For example, the doping characteristics and doping type of each layer can be changed. The complexity of the manufacturing process can be greatly reduced by reducing the number of polycrystalline layers used. If the number of diode layers is small, the thin film diode of the present invention can coexist with DRAM. These or those modifications and alterations should be construed to cover alterations and modifications within the original spirit and scope of the invention. In order to show the flexibility of the present invention, we will introduce another manufacturing process based on the modified 4P2M technology. These two examples differ in that M 1 is deposited after P 4 in the previous example, and M 1 is deposited before P 4 in the modified method. This sequence change can significantly increase component density. The first ten mask steps (MSI-MS10) are the same in both examples, and we will not repeat them here. The only difference is that the top of P3 is not heavily doped in this modified method. After completing the first 10 mask steps, the following process includes the following steps: Mask step 1 1 '(MSI Γ): Starting from the geometry shown in Figure 1i, P4 will be replaced with the deposit M1. The contact mask 201 is used to define the contact area of the first metal layer (M 1), and then a selective isoplasmic etching is performed to open the contact opening.

564562 V. Description of invention (15) Be fast. Therefore, products made with this have better performance. At the same time, it also has the advantages of regular examples. The main disadvantage is that M1 needs to undergo a high temperature heat treatment process for P4 annealing. Without careful calibration, this heat treatment process can affect the electromigration (EM) characteristics of Ml. Figures 3 to 5 describe in more detail the manufacturing process for making separate thin-film dipole vessels. To make a thin film diode between two polycrystalline thin films, a contact region 303 should be opened on the bottom of the polycrystalline thin film 302 at the bottom, as shown in Figure 3a. The contact area is defined by the photoresistor 30 9. After removing the photoresist, a top polycrystalline film layer 301 having opposite doping is deposited thereon as shown in FIG. 3b. The contact region 303 is filled with such a surface polycrystalline material. Another mask 308 is used to engrave the surface polycrystalline film region 301. During the heat treatment, the doping of the two polycrystalline thin film layers (301, 302) diffused into the contact region 303. If the doping concentration of the bottom layer 302 is higher than that of the top layer 301, a PN-polar body (pNt) will be formed on the top layer 30 as shown in Fig. 3c. Since the depletion region of the dipole vessel reduces the conductive region, the vertical impedance of the top polycrystalline layer 301 increases. Several examples of PNt diodes (D34, D23, D12) are shown in the first butterfly. When the bottom polycrystalline film layer 302 is covered with a layer of silicide, this type of diode is certain. Desirable 1 If the doping concentration of the top layer 30 is higher than the bottom layer 302, it will be formed at the bottom layer 302 A PN diode (pNb) Similarly, the vertical resistance of the bottom polycrystalline layer increases due to the reduction of the conductive area in the dipole-ship depletion region. If the depth of the contact area is greater than the diffusion length, or the same as the impurity concentration, a PN diode (i Mm) may be formed in the middle of the contact area, as shown in circle 3e. The defect density of the polycrystalline material in the contact area is high. Therefore, defective PNm diodes may

Page 19 564562 V. Description of the invention (16), more sex. In other words, its resistance to the two conductive layers (3 〇, 3 〇 2) ~ not much. Examples of a pn m diode (D 1 4) are shown in Figure lk. Figure 4e shows the thin film diode fabrication process when the bottom layer is a polycrystalline thin film layer and the top layer is a metal layer. First, a contact opening is formed by the contact cover curtain 40, as shown in the figure. After removing the photoresist, a tunnel insulation layer 40 5 is grown at the bottom of the contact f 4 03. Then a layer of gold is deposited and a metal cover Act 40 The area where the layer is engraved, as shown in Figure 4c = Γ ° forms an insulator-semiconductor (MTS) diode, as shown in Figure 4d. If 4k y »a ^ we do not grow a tunneling insulating layer As shown in Fig. K, a Schottky diode ΛΑ C ^ is shown. Compared to a Schottky diode, the MTS diode has good stability, but its forward bias current is small. Brother 5a Figure 5 ^ Fr * # v Ding M "I Figure 5e shows the bottom layer is a metal layer and the top layer is a polycrystalline layer. First, a contact opening o R n q is opened by the contact screen 509, as shown in Fig. 5a. After removing the photoresist 509, a tunnel insulating layer 505 is grown on the contact film layer 501. A layer of polycrystalline silicon is then deposited. The area of this layer is engraved with polycrystalline silicon curtain 5 08 neodymium, as shown in Fig. 5c, and 5d, as shown in Fig. 5d. A metal insulator-semiconductor (MTS) diode is used, if not. The tunnel insulation layer shown in the figure is grown on metal. It is not common in the conventional process to penetrate the insulation layer. If we do not grow to form a Schottky diode (MS) with Ling, as shown in Figure 5e. Meiji has since been fabricated on multi-defective materials. As a result, these films are far from ideal. Figure 6 shows the actual current-voltage (IV) characteristic curve of a non-centered diode. Figure 6

Page 20 564562 V. The dotted line 601 in the description of the invention (17) shows a typical IV relationship curve of a diode made on a semiconductor substrate; the solid line represents the IV relationship curve of a thin film diode. In Figure 6, these IV relationship curves can be divided into three different regions with different performances; rectification region 6 11, reverse breakdown region 6 1 2, and non-ideal forward bias region 6 1 3. In the rectification region 6 1 1, the behavior of the diode is close to the ideal situation; the forward bias current increases exponentially with the voltage, while the reverse bias current is small. In the reverse breakdown region 6 1 2, the reverse bias current starts to increase rapidly with the voltage. In the non-ideal forward bias region 6 1 3, the serial impedance begins to control the I V characteristic, and the forward bias current no longer increases exponentially with the bias voltage. The thin-film diode 6 0 2 tends to have a small rectification region, as shown in FIG. 6. In other words, the thin film diode tends to have a large reverse bias leakage current 'and a relatively small forward bias current. An example of the I-V relationship curve of a defective diode is also shown in Figure 6, which is represented by a double dashed line. Defective diodes do not have significant rectification regions. In any case, a defective diode can be analogized by a diode with a small breakdown voltage and a parallel leakage resistance. Thin film diodes are highly likely to have defects. Current popular integrated circuit design methodologies assume good consistency among circuit components. If any of the basic circuit components is incomplete, the product design based on this design methodology will have poor returns. In order to use those non-ideal thin film diodes to design integrated circuits, we must develop new circuit design methods to improve the fault tolerance of non-ideal diodes. The circuit design examples in the following sections show the problems and solutions in the 3D integrated circuit of the present invention. Figure 7a shows a schematic diagram of a read-only memory (ROM) sub-array

564562 V. Description of Invention (18). The read-only memory (ROM) sub-array includes N groups of word lines (WL1, WL2, E, WLn, E, WLN) and M group of bit lines (BL1, BL2, E, BLm, E, BLM), among which N, M, n, and m are all integers. Thin film diodes (70, 702) are placed at the intersections of the word lines and bit lines. Each intersection with a diode (701, 7 0 2) represents a binary state, and an intersection without a diode 7 0 5 represents another binary state. Each word line is driven by a decoding unit 7 11 of a decoder 7 1 5. The bit line is connected to the output circuit 71 4 and the pre-control circuit 71 2. The pre-control circuit 71 2 is controlled by a pre-control signal. (PCG). When the ROM array is idle, the PCG is activated and the transistor in the pre-control circuit 712 is turned on, so that the electric grinding of the bit line becomes the zero voltage (Vss). The details of the output circuit 7114 are shown in Figure 7b. Each bit line (BLm, BLm-1, BLm-2, BLm-3) is connected to the source of each bit line selection transistor (MNm 4-Μ Nm 1); the gate of each selection transistor Controlled by each bit line selection signal (XA4-X.A1), as shown in Figure 7b. These bit line selection signals (X A 4 _ X A1) are mutually exclusive, so that only one of them is activated at any time. The drains of all selected transistors are connected together to the gate of the output transistor (Mno). The source of the data transistor (MN0) is connected to the zero line (Vss) and the drain is connected to the next bit line (βK). Figure 7c shows the time relationship between the critical signals of the ROM sub-array. Before time T1, the bit line is preset at Vss. The next bit line (B1 in this example) is preset to a high potential (Vcc) through their own pre-control circuit (not shown). For the sake of simplicity, we only show the waveforms of one active word line (WL2) and two bit lines (BL3, BL1), as shown in Figure lc

Page 22 564562 V. Description of the invention (19). The first step to read data from the ROM is to disable the pre-control signal (PCG) at time T1, as shown in Figure 7c. At time T2, the PCG has just failed, and one of the word lines (WL2 in this example) is immediately activated. All diodes connected to this activated word line (W L 2) are forward biased. The voltage on the activated word line (WL2) is propagated to the bit lines (BL2, BL3, BL4, BLM-3, BLM-2, 丨 BLM-1) connected to the diode |. The voltages of the bits! | Of the element line (611, 61 ^) without diodes connected to the activated word line (So2) remain at 733. The bit line selection transistor (M N 4-MN 1) on the output circuit 714 selects a part of the signals in the bit line (bl 1-bl M), and simultaneously propagates the selection signal to the next bit line (B1, Bk). ). To end the read operation, the activated word line (WL2) is invalid at time T4 ′ PCG is activated at time T5. After PCG is activated, all other signals are idle. .

The decoder 715 in Fig. 7a includes a large number of decoding units 71. Each decoding unit 7 11 controls one word line. The decoders 7 and 5 can be designed in various ways. Figure 7d shows a typical decoding unit design method. This kind of Yuan Bao / a surface (741) and a reverser. MND asks Γ ^; queue: the ground Λ line (YA) is connected. The output of NA_ (C #) is connected to the input of reverse benefit 742. The output of the inverter 7 乜 is connected to a straight character line (WLn). The decoding unit port H in Figure 7 is driven only when all inputs are at a high potential. NAND gate = the element line is at Vss. The decoder 715 will decode each word 'meta', which will make the word the word line address (YA), so that it will not ^ 71! Have a unique start at the same time. In circuit design t, the word line on solution two mr: is 564562 V. Invention description (20) There are many kinds of decoders. These decoders have a common feature in that their outputs are strongly driven. The use of the conventional decoder in the 3D integrated circuit of the present invention causes many problems, which will be described in the following sections. During the reading process, ideally, the voltage on these activated bit lines (BL3 in this example) should reach the supply voltage Vcc. However, due to non-ideal effects, the bit line voltage often only reaches a lower Voltage (Vbl), as shown in Figure 7c. In the steady state, the bit line voltage (Vbl) is determined by the current balance condition between the diode 701 that should be turned on under forward bias and the diode that will not be turned on by the leakage current on the same bit line. . When the leakage current of other diodes increases, the bit line voltage (Vb 1) decreases. This is a major problem for polycrystalline diodes because they tend to have a poor reverse bias characteristic as shown in FIG. If we use Figure 7d to represent the decoder to control the word lines, then all invalid word lines are driven to V ss; the bias voltage of those diodes in reverse bias is Vb 1 and the leakage current is controlled by those The reverse bias characteristic of the polycrystalline diode is determined. When a thin film diode with a large amount of data on a bit line, the leakage current through those diodes will be so large that the forward biased diode 701 cannot provide a detectable bit line voltage ( Vbl). Elsewhere, similar problems can occur when a large number of diodes are connected to the same wire. The situation becomes even worse when one of the diodes on the bit line (BL3) has a defect, as shown in an example in Figure 7a. When the corresponding word line (WLn) is strongly driven, the leakage current of the defective diode 70 9 may be large enough that Vb 1 will never send a detectable one.

Page 24 564562 V. Description of the potential of the invention (21). One solution to the above problem is to limit the number of diodes on each wire. For this reason, the size of the ROM sub-array of the present invention is always much smaller than that of the conventionally designed ROM. Since each sub-array must have its own peripheral circuits, such as the decoder 7 1 5, the pre-control circuit 7 丨 2, and the output circuit 7 1 4, the reduction in the size of each sub-array will greatly increase the total number of ROM components. area. But for the 3D ROM of the present invention, the situation is different, because we can "hide" the peripheral circuits in the diode array. It is therefore possible to have a small-sized sub-array without significantly increasing the component area. The 3D ROM of the present invention may have multiple layers of bit lines, word lines, and thin film diodes. For simplicity, we only show one layer in this example. 'The problems with multilayer organization can be solved in the same way. ^ Said. < Another method can improve the fault tolerance of non-ideal diodes without reducing the number of diodes on each wire. Figure 7e shows a modified decoding unit designed for this purpose by the present invention. The decoding unit also has a NAND gate 74. Its connection method is shown in Figure 7d. nandw (dec # output is connected to a P-channel transistor (MPw). The p-channel transistor is connected to the inverse signal (PCG #) of the pre-control signal (PCG). The pole of the Mpw is connected to the word line (Win % On the drain of the n-channel transistor (MNw). · The gate is connected to the pre-control signal PCG, and its source is connected to Vss. When the ROM sub-array is idle, pcG is at a high potential and pcG # is at a low level Potential, the word το line WLn is strongly driven to Vss. When the r0m sub-array is on, PCG is at a low potential and pcG # is at a high potential. Only when all the inputs of the NAND gate (741) are at a high potential, the word Yuan line WLn is only activated

Page 25 564562 V. Description of Invention (22) When the PCG is in an inactive state and the inputs of the NAND gate are not all at a high potential, why? Mpw and Mη are tenderly closed, and the word line WLn is in a high-resistance state. The decoding unit shown in Fig. 7e is connected to the word line, and the activated word line can be driven to V c c while the other word lines are left floating. Thus, since all reverse biased diodes are connected to the floating word line, the reverse bias leakage current is small. Leakage current is not determined by non-ideal diode characteristics. The bit line voltage Vbl is always at (vCc-Vd). When we use a thin film diode with poor reverse characteristics, Vd is also in the range of 0 · 4 V ~ 0 · 7 V. By dangling the invalid character line, we can k and one pole body's fault tolerance. However, if one of the bad diodes is in a low resistance state, the problem is different. This problem is illustrated by the example in Figure 7a. When WL2 is pulled to a high potential by the decoder 7 1 5, BL3 is also pulled to a high potential. If the diode connected to BL3 and WLn is a bad diode 709, because the decoder unit is in a floating state, WLn is pulled to a high potential state. When WLn is pulled to a high potential, BL1 is also pulled to a high potential because it is connected to WLn through the diode 702. Assume that BL1 is at Vss potential when WL2 starts. Therefore, the signal of BL1 has an error. Fortunately, the problem caused by the bad diode 709 in the above example can be distinguished from its behavior in the timetable in Figure 7c. The last waveform in the γ pass shows the behavior of B L1 in this state. The false positioning element line (B L1) is at V s s at all times. The potential of BL1 rises due to the influence of the bad diode (7.09), but because BL1 is driven by multiple lines, its rise rate is much smaller than the normal bit line (BL3). Eventually BL1 can reach 电位 a high potential enough to cause erroneous reading, but we can

Page 26 564562 V. Description of the invention (23) The word line (WL2) that was activated before the bit is raised sufficiently to avoid this error, as shown in Figure 7c. As long as the peak potential of the error signal is low enough that the output signals (Bl, Bk) are not affected, we can ignore this problem. In other words, we can improve the fault tolerance of non-ideal diodes by getting the correct results before the wrong results have enough time to cause problems.

Another way to solve this problem is to use a weak signal driver to drive the invalid word lines without leaving them completely floating. The weak signal driver can keep the reverse bias current at a low level, so we can still get a good fault tolerance of a non-ideal diode. Generally, a weak signal driver makes it difficult for a bad diode 7 0 9 to propagate an erroneous signal; therefore, the fault tolerance of the obtained diode is improved. Figure 7f shows a decoder unit with better fault tolerance than the two error mechanisms described in the previous section. The decoder unit includes a depletion mode transistor (M D w). The gate of M D w is connected to an address signal through a set of mutually exclusive gate selection signals (YAg). The drain of MDw is connected to another address signal generated by another set of mutually exclusive drain select signals (YAd). The source of MDw is connected to one of the word lines (WLn). The input connection of each decoder unit of the decoder 7 1 5 is unique, so that no two or more word lines are activated at any one time. The turn-on voltage (Vt) of the transistor (MDw) is near Vss. When YAg is high and Y A d is high, the word line is driven to V c c and the word line is activated. When YAg is high and YAd is low, the word line is driven to Vss. When YAg is low and YAd is high, the word line is driven to a small positive potential of about 0.6V. When YAg is low and YAd is low, due to the gate

Page 27 564562 V. Description of the invention (24) A ^ ---- A · The potential is near vt, and the word line is barely driven to Vss. Table i lists the logic states of the diodes. For the examples in Table 丨, we assume that there are four drain mutually exclusive selection signals (YAd) * 8 gate mutually exclusive selection signals (Μ㈧). The last column in Table 1 lists the word lines for each state The table shows that most of the word lines are driven by weak signals, and W has better fault tolerance for bad energy.-A small number of invalid word lines are forcibly driven by SS to a small number. The influence of polar fault tolerance is very small. The decoder unit in Figure 7f provides the best fault tolerance of the non-ideal characteristics of thin film diodes. At the same time, it uses only one transistor for each word line, which takes up a small area Table 1. Logical Table of Decoder Unit in Figure 7f

Yag potential Yad potential Character line potential Drive power The number of lines in this state Vcc Vcc Vcc large '---- 1 Vcc Vss Vss large ---- 3 Vss Vcc ~ 0.6 V small ------------ -7 Vss Vss Vss small 21 2 ~ 1 Figure 8 shows the top view of the ROM element of the present invention. The element includes 4 sets of ROM arrays. Each group included a large number of Ro liver arrays 805. Here, the f array 80 5 is shown in Fig. 7a, and they use the decoder unit shown in Fig. 7f. The selection signal () (eight 4 _) ^ 1) of the output circuit 714, the gate selection signal (YAg4-YAgl) of the decoder 715, and the pre-control number (PCG) of the sub-array are all provided by the vertical decoder 803. Those sub-array decoders ^ and pole selection signals (YAd4-YAdl) are provided by the horizontal decoder (802). that

Page 28 564562 V. Description of the invention (25) The output signals (B3-B0) in the same column of some sub-arrays are connected together and sent to the sensor amplifier at the ROM element boundary. According to the foregoing, the ROM element of the present invention can obtain the following advantages. (1) Using multilayer thin-film diodes, we can obtain ultra-high-density memory density. (2) By hiding the peripheral circuits under the thin-film diode, we can use small sub-arrays without increasing the total area; meanwhile, the component area and power consumption can be greatly reduced. (3) The new design of the decoder circuit effectively improves the error of non-ideal diodes. (4) No p-channel transistor is used in the ROM array; there is no need to connect the Vcc power lines together, and no well is used in the ROM array. Here we have only demonstrated some specific embodiments of the invention, and the industry 2 knows that many changes and modifications are possible. It should be understood that the above two examples are only used as examples and are not the entire contents of the present invention. For example, while the line holds the same function, the polarity of the diode can be changed, and the starting potential of the word line can be changed. The specific circuit in this example can be replaced by a peripheral circuit of the modified type. These or those modifications and corrections are interpreted to encompass changes and modifications in the original spirit and field of the invention. The data signal is characterized by its potential amplitude. For example, a number is represented by a potential value greater than VCC / 2, while its opposite value is wrong, and a potential of cc / 2 is represented. In order to increase the capacity of non-ideal diodes, we use the current drive power of the signal driver to represent the digital

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5. The value of invention description (26). The full-scale current of the driver drives the digital value of the power meter, and the opposite value is represented by the low power of the driver. The leakage current of the / non-starting diode no longer depends on its reverse bias characteristics. Conversely, the leakage current depends on the current drive of the transistor driver. Μ In other applications, as another application example, Figures 9a to η β Master-7 Stewart's 3D Programmable Logic Array (PLA). 9 & Figure β ^ Schematic diagram of the function and geometry of PLA . Fact =. ^ ° Diode array. For the sake of simplicity, in Section I, there are two: diode arrays. In order to limit j == to each wire connected, the PLA of the present invention is often divided into several sub-blocks. In the figure "^ sub @@ sub-blocks (901, 911), the actual product can have more sub-blocks. 3 Sub-block 901 includes two diode arrays. The first diode array '9〇 The function of 2: is to perform AND operation on all of its inputs. Therefore, it is called AND gate array (AND). The AND array of PLA sub-block includes] pairs of inputs, 11 #, 12, 12 #, E, dagger, E, IJ, IJ #), and ^ output letters, (Al, Α2, E, Ak, Ε, AK), where j, j, κ are integers

number. The thin film diode 900 is selectively placed between the input line of the AND array and the output line of the AND array to control the logic function. In the example of Fig. 9a, the eighth 丨 is connected to I 1, I 2 #, I j # through a polar body. If any of the connected medicines (I 1, I 2 #, I j #) is at a low potential, A 丨 is at a low potential. In other words, A1: [Γ1 AND 12 # AND Ij #]. Ak is connected to 12, IJ # through the diode, so Ak = [; [2 AND IJ #], and so on. Second diode array

Page 30 564562 V. Description of the invention (27) Column 90 3 is called PLA 'OR array (OR) because its function is to perform logical OR operation. The OR array of PLA subblock 901 includes κ input signals (Abl, Ab2, E, Abk, E, IbK) and I output signals (〇1, 〇2, E, 〇i, E, 〇I) 'Where i, I, k' K is an integer ... The thin film diode 109 is selectively placed between the input line and the output line of the OR array to control its logic function. In the example in Figure 9a, 01 passes through the diode and Abl, Ab2,

Abk is connected. If any of the connected signals (Abl, Ab2, Abk) is high, 01 is high. In other words, 〇1 = [Abl OR Ab2 OR Abk]. 01 is connected to Ab2, Abk, AbK through the diode, so 01 = [Ab2 OR Abk OR AK], and so on. , PL ^] external input signals (I N 1, Ί N 2, E, I N j, E, I N J), where j and j are integers. These input signals are connected to the P L A input circuit (905, 9 1 5) of the P L A sub-block. Figure 9b shows the details of the P L A input circuit 905. The input signal (I n j) of p L A is connected to an inverter 9 2 1 to generate a reverse signal! n j #, the signal is connected to the gate of the n-channel transistor (MN1). The source of μ N1 is connected to the anode of another n-channel transistor (MN3). The drain of MN 1 is connected to the input signal (I j) of the PLA AND array, and this input signal is also connected to the dip of the p-channel transistor (MP 1). The source of MP1 is connected to the power line Vcc. The gate of MP1 is connected to the pre-control signal PG #, and this control signal is also connected to the gate of mn3. The source of MN3 is connected to Vss. I n j # is inverted by the inverter 92 2 before being connected to the n-channel electric crystal (MN2). The drain of MN 2 is connected to the input signal of the PLA A AND array (I j #), and the input signal is also connected to the anode of the p-channel transistor (MP2). The source of MP2 is connected to Vcc, and the gate of MP2 is connected to the pre-control signal PG #. The gate of MN4 is also connected to PG #

Page 31 564562 V. Description of the invention (28). The source of MN4 is connected to Vss. When pla is idle, PG # is at a low potential, and the input circuit 905 pulls I j 'and I j # degrees up to the power supply potential Vc c. When PG # is pulled to a high potential, PLA is activated and I j and I j # are also activated; if lnj is high, I j # is driven to zero potential V ss and I j is in a high impedance state ; When I j η is low, I j is driven to zero potential vss, and I j # is in a high impedance state. As with the ROM application examples discussed earlier, setting the invalid signal in a high-impedance state can improve the fault tolerance of non-ideal diode characteristics. Returning to Fig. 9a, the paired signals are connected to the vertical input lines (II, II #, 12, 12 #, E, Ij, Ij #, E, IJ, IJ #) of the AND array 902. The input lines of these AND arrays cross the horizontal output lines (A1, A2, E, Ak, E, AK) of the AND array. In the idle state, the multi-level lines (A 1, A 2, E, Ak, E, A K) of these AND arrays are preset to Vcc by the p-channel transistor 9 0 4 controlled by the preset signal P G #. PG # is also connected to the delay circuit 908 to generate a preset signal (PG, PG1 #) of the OR array. FIG. 9c shows the structure of the delay circuit 9 0 ′ 9 1 8. A programmable delay circuit g 2 5 provides a suitable delay time. The output of the delay circuit is connected to an inverter 9 2 6 to generate a PG signal. The PG signal is also connected to another inverter 9 2 J to generate a signal. PG 1 #. These OR array preset signals (pc, pc 1 #) control the data converter (90 7,917) between the AND array and the OR array. The structure of the data converter (907, 91 7) is shown in Figure 9d. The AND array output signal (Ak) is inverted by the inverter g23 before being connected to the gate of the p-channel transistor (MP5). The source of MP5 is connected to P G 1 # and its drain is connected to the OR input line (A b k). The #Abk is also connected to the drain of the n-channel transistor (MN 5). The gate of MN5 is connected to P G 'and its source is connected to the neutral line v s s. When the 0 card rank is activated

Page 32 564562 V. Description of the Invention (29)

When PG is low, PG1 # is high. When Ak is high, Abk is driven to V c c. On the contrary, when Ak is low, it is in high impedance. As in the ROM application example discussed earlier, setting the invalid signal to a high-impedance state can improve the fault tolerance of non-ideal diodes. The structure of the second PLA sub-block in Figure 9a is the same as the first sub-block. The peripheral circuits of this sub-block include an input circuit 915, a delay circuit 918, and a data converter 9 1 7, which are consistent with those described in FIGS. 9b and 9d. The external input signal (INI-INJ) is connected to the input circuits (915, 905) of different sub-blocks through a high-level metal connection (not shown). Subblock 911 also has its own

The own AND array 9 1 2 and the OR array 9 1 3; diodes on those planes are connected together to provide additional logic operations. The 0R array 9 1 3 output and the first sub-block output (01 — 0 I) are connected to the output circuit 9 1 6. The structure of the output circuit 9 1 6 is shown in Fig. 9e. The 0th train output (0i) of the first sub-block 901 is connected to the gate of the n-channel transistor (Mni). The corresponding OR array output (factory 0) of the second sub-block is also connected to the gate of another 値 n-channel transistor (Mni,). The sources of both transistors (Mni, Mni,) are connected to Vss. The drains of these two transistors are connected together to a wired-NOR signal (Ri #). These whM —nor signals (Ri #) are connected to the output circuits 916 of many other sub-blocks through a south-layer metal connection (not shown) in the top view output circuit 9f as shown in FIG. 9f. Comment 11 ^ (110 Gallon (1 ^ #) is connected to the input of 1) channel transistor (Off 9), 、 向, 、, 226. The output of this inverter is PLA's final = t ί MP9's gate is twisted with PG #, and its source is connected with vw. : At the month setting, PG # is low and Ri is also low. When PG # is high, R1 will output all the arrays of different sub-blocks (0, 0, E).

564562 V. Description of the invention (30) OR result. Therefore, the combination of all sub-blocks is called a complete PLA array. Figure 9g shows the time waveform of the PLA critical signal. Before Tst, PLA is in an idle state; PG # and PG 1 # are both at low potential; all AND array input signals (Ij, Ij #, Ij ', Ij #', Bu 1, E, J) and output signals ( Ak, k = 1, E, K) are 咼 potentials; all input signals of the OR array (Abk, Abk ', k = 1, E, K) and output signals of PLA (Ri, i = 2, E, I) ) Is a low potential. At time Tst, pull PG # to a high potential and start the AND array. The output signal of the AND array (Ak, k = 1, E, K) is pulled low according to the diode connection and the input signal value of PLA. At time Tr in Fig. 9g, PG1 # is pulled to a high potential, and the PLA A OR array is started, and the value of the output of the AND array (Abk, eight 61 ^) is propagated in a column of 0_, producing 1 ^ tender out ({^ ). 1) 1 ^ output (Ri) is valid at Td. To terminate the pLA operation, pG # is pulled low at Trst 'and all signals return to the idle state at Te. Once again, the PLA is turned off immediately after the output of the PLA is valid. Similar to the previous ROM example, it is beneficial to improve the fault tolerance of non-ideal diode characteristics. Here we have only demonstrated some specific embodiments of the present invention. The industry t t f can have many changes and modifications. It should be understood that the above ^ 0f is used as an example and is not the entire content of the present invention. For example, the start voltage of the array and the OR array, as long as the function remains unchanged, the same situation T u is replaced by NOR and nand array. The AN job is being finalized. 'We can change the logic order, do it first and then execute the edge circuit instead. The specific circuit in the example can be made up of other types of identical sub-blocks with different polarities. Different sub-blocks

564562 V. Description of the invention (31) ~ ^ ~ -1 The peripheral circuits are not necessarily the same. We can use simple buffers as repeaters to connect different sub-blocks. These or those modifications and alterations should be construed to cover the alterations and modifications within the original spirit and field of the present invention. In the example in Fig. 9a, pla is divided into small PLA sub-blocks to improve the fault tolerance of non-ideal diode characteristics. There are also other methods of segmenting a diode array. Figure 9h shows a method for partitioning PLA AND arrays. The AND array 9 0 2 is divided into a large number of sub-arrays (9 3 1, 9 3 2). For simplicity, only two subarrays are given in 9_. Each sub-array has j pairs of inputs (I 1 — I),

Acl, -AcK,). The output of each sub-block is connected to the interface circuit 9 3 3. The output signal (Ack) from the left sub-block 931 is inverted by the inverter before it is connected to the ^ channel transistor (MN8). The output signal (Ack,) from the right sub-block 9 32 is inverted by the inverter before it is connected to another n-channel transistor (MN8,). The sources of both transistors (Mn N, M N 8 ') are connected to vs s. The drains of the two transistors (MN8, MN8 ') are connected to the total output (Ak) of the AND array. The total output signal (AK) is connected to the interface circuit g33 of the total sub-array; when one of the sub-array input signals connected to the diode is low, ^ is low. Therefore, the combination of all sub-arrays forms a complete pLA AND array. OR arrays can be split in a similar way. The above PLA and ROM application examples only give a one-layer diode array. In practice, there are often many layers of diodes. Figure 丨 0 shows a symbol diagram of a small part of the 3D circuit of the present invention. The circuit consists of two layers of thin film diodes (953,954) placed on top of a MOS transistor (962,963). Indicated by dotted line

564562, invention description (32) = Diode layer 953 is connected between the second polycrystalline layer and the third polycrystalline layer. . A monopolar layer 952 connects the third polycrystalline layer 9 54 and the fourth polycrystalline layer to each other ::, the non-polarity of the P-channel transistor 963 is connected to a polycrystalline layer through a polycrystalline layer. connection. The gates of the MOS transistor are connected together through a first gate layer 956. The metal line 9 5 7 forms a metal connection between the p-channel transistor 963 and the n-channel transistor 9 6 2 drain. Figure 丨 〇 = Simplified example demonstrates the element density and components achieved by the present invention. In summary, we can easily draw the following advantages of the present invention. Mach PLA has as

(1) By dividing p L A into small sub-blocks or sub-arrays, the fault-tolerance of the characteristics of the diode is considered. (1) Through the digital lean material representation method of the present invention, the fault tolerance of non-polar characteristics is improved. Heart ~ Performance (3) The power consumption characteristics are improved by dividing the PLA into small sub-blocks to obtain super-a-by using an active transistor to overlap the multilayer thin film diodes, the element density is reduced. Although ...: The present invention has been specifically described with reference to its preferred embodiments.

It is clear that those skilled in the art should understand that various changes can be made without departing from the spirit and scope of the present invention. And details

Page 564562 Schematic illustrations Figures 1a to 1m are cross-sectional views of the process of manufacturing the thin film diode of the present invention using a manufacturing process that is' compatible with traditional dynamic random memory (DRAM) technology. . Figures 2a to 2f are cross-sectional views of another manufacturing process for manufacturing the thin film diode of the present invention using a modified DRAM technology. Figures 3a to 3e are cross-sectional views of a manufacturing process for manufacturing a thin film diode between two polycrystalline layers. Figures 4a to 4e are cross-sectional views of the thin-film diode manufacturing process when the bottom layer is a polycrystalline layer and the top layer is a metal layer. Figures 5a to 5e are cross-sectional views of the thin film diode manufacturing process in the case where the bottom layer is a metal layer and the top layer is a polycrystalline layer. FIG. 6 is a schematic diagram of a diode current-voltage relationship (I V) curve under non-ideal conditions. Figures 7a to 7f are schematic diagrams of a circuit design method of a read-only memory (ROM) according to the present invention. FIG. 8 is a schematic top view geometrical structure of a ROM element according to the present invention. Figures 9a to 9h are not intended for the programmable logic array (PLA) circuit design method of the present invention. FIG. 10 is a schematic diagram of a 3D circuit structure of the present invention.

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Claims (1)

564562 Case No. 91109424 Amendment VI. Patent Application Scope (IV)-one opening in the insulating layer for the first and second electrodes of the polycrystalline silicon diode; and (c) one including one on the substrate An active semiconductor element of a metal oxide semiconductor (MOS) transistor on the substrate, the element vertically overlapping with a polycrystalline silicon diode stacked in a common overlapping region within the upper main surface. 6 · The 3 D semiconductor device according to item 5 of the patent application scope, wherein: The insulating layer of the polycrystalline diode further includes a tunnel insulating layer grown between the first and second electrodes of the polycrystalline diode and the second diode, wherein the thickness of the tunnel is 1 × 10. —L 3x10 ^ m. 7 · An active integrated circuit (1C) element formed on a semiconductor substrate having an upper major surface, comprising: at least two thin film submicron diodes on the substrate, wherein the thin film submicron diode They are stacked vertically in a common overlapping area of the upper main surface. 8 · The active integrated circuit (IC) component as described in item 7 of the scope of patent application, wherein: The thin film sub-micron diodes overlap each other, and the upper thin film sub-micron diodes and the lower thin film sub-micron diodes are partially overlapped and stacked in a common partial overlap region of the upper main surface. 9. An active integrated circuit (1C) element formed on a semiconductor substrate having an upper main surface, comprising: a thin-film submicron diode and a metal oxide semiconductor (MOS) transistor deposited on the substrate, Where the thin film sub-micron diode P.40 564562 _Case No. 91109424_Year Month Date _ «: _ VI. Scope of Patent Application The metal oxide semiconductor (MOS) is stacked vertically in the common overlapping area of the upper main surface. 10 · The active integrated circuit (IC) device according to item 9 of the scope of patent application, wherein: the thin film sub-micron diode is partially overlapped on the metal oxide semiconductor (MOS), wherein the thin film sub-micron Diodes are partially stacked on the metal oxide semiconductor (MOS) in a common overlap region of the upper main surface. 11. An active integrated circuit (1C) device fabricated on a semiconductor substrate including a diode, comprising: a first polycrystalline semiconductor forming a first electrode; a metal layer forming a second electrode; and A tunnel insulation layer is grown between the first and second electrodes. 1 2 · The active integrated circuit (I C) device according to item 11 of the scope of patent application, wherein the thickness of the tunnel insulation layer is 1 X 1 0 3 X 1 0 -9 m. 1 3 · A method for improving the fault tolerance of the non-ideal characteristics of the polycrystalline diode of the 3D semiconductor device according to item 1 of the scope of patent application, including: (a) providing a signal driving circuit for driving a digital input signal to the polydiode; (b) defining a strong current driving state for the signal driving circuit provided in step (a); (c) for this step ( a) the provided signal driving circuit defines another weak current driving state; Page 41 564562 Case No. 91109424 Amendment VI. The scope of patent application (d) defines a digital input signal value for the polydiode, using this value as the high current driving state provided in step (b); and (e) Define another digital input signal value for the polycrystalline diode, and use this value as the weak current driving state provided in step (c), wherein the reverse bias leakage current of the polycrystalline diode is determined by the The weak current drive performance of the signal drive circuit is determined. 14. The method according to item 13 of the scope of patent application, wherein the step (a) of providing the driving circuit further comprises: (al) forming a p-channel metal oxide semiconductor (MOS) transistor (MP1), wherein The source of MP1 is connected to the power line Vcc, the gate of MP1 is connected to the control signal PC #, and the drain of MP1 is connected to the output (Ij) of the driving circuit; (a2) forming an n-channel MOS transistor (MN1) Where the gate of MN1 is connected to the input signal (Dn j), the drain of MN 1 is connected to the output signal I j; and (a3) forms an n-channel MOS transistor (MN3), where the source of MN3 is connected to The gate of ground V ss, MN 3 is connected to the source of MN 1, where when PG # is high and Dnj is high, it is defined as the strong current driving state of the signal driving circuit, and when PC # is high Potential, when Dn j is low, it is defined as a weak current driving state. 15 · The method as described in item 13 of the scope of patent application, characterized in that the step (a) of providing the driving circuit further comprises: (a) forming a p-channel M0S transistor (MP5), wherein the source of MP5 Connected to the input signal (PG1 #), the gate of MP5 is connected to another input Page 42 564562 _Case No. 91109424_ Year Month Amendment_ VI. Patent application range input signal (Dnk #), the drain of ^ 1? 5 is connected to the output (Abk) of the driving circuit; (b) forming an η Channel MOS transistor (MN5), where the gate of MN5 is connected to the input signal (PG), the drain of MN5 is connected to the output signal Abk, and the source of MN 5 is connected to the ground Vss, where, when PG1 # High potential, when PG is low, Dnk # is defined as a strong current driving state of the signal drive circuit, and when PC # is high, PG is low, and Dnk # is high, it is defined as weak Current driving state. 1 6 · A method for improving the performance of a 3D semiconductor device including a large amount of polycrystalline silicon diodes, comprising: dividing a wire connected to the plurality of polycrystalline silicon diodes into discrete wires, wherein the wires are divided into discrete wires Before the wires, each of the wires connected to the plurality of diodes is connected to the same diode. 1 7 · A method for improving the performance of a 3D semiconductor device containing a large amount of polycrystalline silicon diodes, comprising: optimizing the 3D semiconductor device so that a correct output signal is generated in the large polycrystalline silicon diode The response speed is much faster than the error signal, and the correct signal output is obtained before the error signal has enough time to affect the output of the 3D semiconductor element. 18 · A method of making a polycrystalline diode, comprising the following steps: (a) depositing a conductive layer on a semiconductor substrate, the surface of the substrate has been deposited to generate a conductive layer and an insulating layer in the previous manufacturing process; (b) applying a masking step to define a region for the conductive layer in step (a) Page 43 564562 Case No. 91109424 Amendment 6. Scope of patent application, (c) Applying a mask opening to the semiconductor (d), the step (I) exposes (Π) the exposed mask (e) Used in this semiconducting structure package (I), its electrode (Π) step other, its deposition An insulating layer is deposited on the bulk substrate. The step of etching on the insulating layer on the semiconductor substrate includes: the surface of the conductive layer deposited in step (a), and one or a large number of other conductive surfaces deposited in step (a). A mask step is used to open the surface of the exposed electrical layer, the purpose of which is to reduce the required steps; and to deposit another conductive layer on the body substrate. The conductive layer deposited in step (e) as two of them in the body, and the connection between the conductive layer deposited in step (e) and the conductive layer made before step (a) in the surface exposed in step (d). Crystalline diodes and connections are formed in the same process to reduce the number of process steps required. Page 44