TW564555B - Method and apparatus for using parasitic effects in processing high speed signals - Google Patents

Abstract

Techniques for designing an electronic circuit system with multiple field effect transistors (FETs) made by a variety of nonstandard industrial processes are disclosed. With the techniques, the circuit parameters of the various components of the individual functional building blocks of the circuit system are systematically adjusted to minimize many deteriorating effects resulting from system-level interactions among these functional building blocks. In one embodiment, the techniques are applied to a silicon on insulator (SOI) CMOS IC that is a divide-by-16 divider where the functional building blocks are four divide-by-2 dividers. The resulting drastic improvement of output signal ripple from each divider stage is presented. In another embodiment, the techniques are applied to another SOI CMOS IC that is a bang bang phase detector where the functional building blocks are three master slave D-type flip flops. The resulting drastic improvement of output signal ripple is also presented.

Description

564555 V. Description of the invention () Fields of the invention: The present invention summarizes the field of data communication. More specifically, the present invention relates to a generic design method for a new group of field-effect transistor (FET) integrated circuit (IC) fabricated by non-standard industrial processes. Therefore, the direct applications of this method include various types of functions and system functions, such as the master-slave D-Flip (MS-DFF), frequency divider, bang phase detector (BBpD), frequency detection (FD ), Phase and frequency lead measurement (pFD), voltage-controlled oscillator (VCO), and phase-locked loop (PLL) in the optical switcher used for data communication 〇1 Bright background: Today, due to the high frequency The good signal quality makes it free from electromagnetic interference, so the optical fiber has been used for sound and data communication. The inherent optical data rate of the single-mode laser beam through the modulation of the optical fiber can easily exceed 1000 Gbit / s However, due to the lack of a true optical communication system, the bandwidth of an optical communication system that can actually be reached has been limited by signal conversion in the optical and electronic range and related electronic hardware. Although it is manufactured using standard and has a general rate performance CMOs (Complementary Metal Oxide Semiconductors) have moved to the electronic hardware used in optical communication systems-because such electronic hardware has low manufacturing costs, low operating power consumption, low supply voltage requirements and excellent With advantages such as road density, FETs manufactured by non-standard industrial processes will still be used in a variety of suitable fields or unforeseen applications. For example, non-standard c μ qs processes are manufactured and have sapphire ICs with insulating substrates like this—referred to as the first (please read the precautions on the back before filling out this page)-Order _ Printed by Line 1 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives Crystal (⑽s SQI) —Although the very advantage of handling very low parasitic capacitance is very high, its potential for operating materials is far greater than the potential potential of bipolar ICs manufactured by standard industrial processes. Although such non-standard FET integrated circuits It can be used in ultra-high-speed applications with its basic rate efficiency in actual circuits, but still must develop a harmonious and balanced design method. Purpose and summary of the invention: The present invention is directed to a field-effect transistor manufactured by non-standard industrial processes ( FET) new group of integrated circuits (IC) and corresponding generic design methods. One of the objects of the present invention is to provide a non-standard industrial process Generic design method for the new group of integrated circuits manufactured; it can reduce the ripple of the individual logical signal levels reached immediately after the switching operation. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Make it, and its achievement is clear, and the content is published. The examples attached to the picture above can be concluded as soon as the description of the implementation of the implementation is shown to show the real reason to borrow; 7V 、-J: Lu ..... :: Order :: 7: Line · (Please read the notes on the back before filling in this page) The instruction sheet can show the diagram and the range tt · Shenli special Attached to the description is a reference to the use of reference-switching die-type electric power equipment to show an example of the implementation of the first: the present data according to the Genfa 4 This series is illustrated 1 more page 6 arp Μ This paper size applies to China National Standard (CNS) A4 specification (210x297 Gongchu), invention description 丨 Typical circuit architecture of the second-division divider printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs; Block diagram of the logic function of the controller; Figure 2B shows The logic function block diagram of the typical 16th and 2c frequency division of the two-way divider shown in Figure 丨; C H2D diagrams respectively show the standardized CMOS t-crystal junction cup standardization CMOS transistor structure, these structures provide the first The implementation of the 16-division divider shown in Figure 2E B; Figure:? The 2F diagram is a capacitor model showing the standardized cm0s transistor structure and the normalized CMOS transistor structure. These results are as follows: Provide the implementation of the 16-division divider shown in Figure 2B; The round-robin signal between the implementation and the present invention is compared with the first building block of the frequency divider used in the sixteenth divider in FIG. 2B. The 3B block diagram is a typical example. The comparison between the output signal and the present invention is based on the second construction block of the frequency divider used in the eighteenth divider of the second and second τ 2B diagrams; FIG. 3C is a typical implementation and The comparison of the rotation signal between the present invention is the third building block for the frequency divider used in the sixteenth divider of FIG. 2B. The 3D ^ is a comparison between the typical implementation and the present invention. The comparison of the signal is based on the fourth building block of the frequency divider used by the 分 2B 胄 sixteenth divider as an example. Figure 4 shows D, which has the function of current mode switching. Dichotomous Dichotomous Dichotomizer (Μί 1-: ···, ··· 11 ·: €: —. — ^, ΜΦ (please first Read the notes on the reverse side and rewrite this page} Page 7 The paper size is applicable to the national standard (CNS) A4 specification (2 297 Kung) 564555 A7 B7 5. Typical circuit architecture of the invention description () DFF); Figure 5A is a logic function block diagram of MS_DFF shown in Figure 4; Figure 5B is a logic function block diagram of a typical bang phase detector (BBpD) 'The BBPD is based on ms-DFF shown in Figure 4 as Its logical building blocks; Figures 6A and 6B are comparisons between the typical implementation of BBPD in Figure 5B and the signal ripple of the present invention; Figures 7A and 7B respectively illustrate standardized CMOS Crystal structure and another non-standardized CMOS transistor structure, these structures are provided for the implementation of the sixteen divider shown in Figure 2B and the BBPD shown in Figure 5B. Please read the "Notes on the back" item first Fill in% on this page again. Order the printed drawings of the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives for comparison of drawing numbers: 1 Frequency divider 1 卜 12 Clock signal 13, 14 Output data signal 20 Frequency divider 21 Input clock 30 Frequency divider 31 N-type substrate 32 P-well 34 N + -type source and drain 35 P-type source And drain 37 silicon dioxide 38 gate 39 metal 40 frequency divider 41 substrate 44 N + source sum and 45 pole P-type source and dead 47 silicon dioxide 48 gate 49 metal 50 frequency divider 51 CMOS Capacitor Model Page 8 This paper is scaled to Chinese National Standard (CNS) A4 (210X297 mm) 564555 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () 52 SOI CMOS capacitor model 60 Frequency signal 62, 64, 66, 68 Signal ripple 70 D-type flip-flop 71, 72 Input clock signal 73, 74 Input data signal 75, 76 Output data signal 80 Bang phase detector 81, 82, 83 D-type flip-flop 85 vco input signal 86 data input signal 88 output signal PHASE 91 signal ripple 100 NMOS field effect transistor 101 source 102 sink 103 gate 110 interface FET 111 source 112 non-pole 113 gate . 114 P-type gate region 115-channel invention detailed description: In the following detailed description of the present invention, the details proposed are to fully understand the present invention. However, those skilled in the relevant art will understand that the present invention may be practiced without these details. In other cases, well-known methods, procedures, components and circuits have not been described in detail to avoid confusing the technical features of the present invention. The detailed description will refer to logic boxes and other symbols, which can directly or indirectly simulate the operation of a signal processing device coupled to the network. These descriptions and symbols indicate the methods used by people with extensive experience or familiar with this technology, which can convey the main points of their work to other experts in the most effective way. Page 9 This paper applies Chinese national standards. (CNS) A4 specification (210X297), ... — I ..... — 'OK —. Line · (Please read the precautions on the back before filling out this page) 564555 V. Consumption by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Cooperative cooperatively prints the description of the invention (those skilled in the art. Here, "—the embodiment" or "the embodiment", which refers to the technical features, structure or special features described in an embodiment, is incorporated into at least one implementation of the invention For example, the words "in one embodiment" appearing in different places in the Taiqi bh 杳 & do not necessarily refer to the same embodiment, nor do they necessarily refer to other different embodiments that are incompatible with each other. In addition, the representative The order of the blocks in the process flow diagram of one or more embodiments of the present invention does not imply any particular order, nor does it imply the limitations of the present invention. The first ffl system is only implemented in accordance with one of the present invention. , Significant Shows the circuit of a two-division divider with current mode switching function. In the example circuit, the supply voltage AVDD is 1.8 volts, but other voltages, such as 2 · 5 volts, can also be used. AGND is marked as "anal ground gr〇und) ”, vcs is the bias voltage applied to the gates of the transistors Mcl and Mc2, so as to establish the amount of source current corresponding to the gates. When passing through the divider, CLK 1 1 and 1 2 The frequency of the differential signal will be divided into half, which is the differential signal between Q 1 3 and 14. 4. Different transistors (such as NMOS transistors) in operation are marked as Mcl, Mc2, Ml, M2 ... And M16. The four boost resistors are labeled R3, R4, R13 and R14. I can understand that this circuit structure can be achieved using standardized CMOS integrated circuits and various non-standard CMOS integrated circuit processes. In addition, if the frequency divider 1 can be quantitatively designed to provide high-quality speech output with a high CLK frequency—for example, 2 · 5 G Η z for OC-4 8 communication, the divider 1 is a low-cost optical network Switcher is used as a basic building block. For convenience, related Series of functional blocks shown in Figure 2 eight. Page 10 of this paper scale applicable to Chinese National Standard (CNS) A4 size (210X297 mm)

564555 A7 V. Description of the invention () 2B is a typical sixteen divider divider 60. The logical function block diagram uses the two divider divider shown in Fig. 1 as its logical building block. Specifically, the repeated logical building blocks are labeled as frequency divider 20, frequency divider 30, frequency divider 40, and frequency divider 50. Those skilled in the art can easily know that the input clock (INPUT CLCK) 21 will be divided into two and become a differential signal q at the frequency divider 20 = liao = douti. Similarly, the INPUT CLOCK 21 will be divided by four (4) at the output of the divider 30 to become a differential signal 卩 —liao == 〇〇] ^ 2. The frequency of the input clock (1 > ^ 11 D CLOCK) 21 will be divided by eight (8) at the output of the frequency divider 4 to become a differential signal Q-red = DOUT3. Finally, the frequency of INPUT CLOCK 21 will be divided by sixteen (16) at the output of the divider 50 to become differential §fl Q-Q_ = D Ο U T 4. Figures 2C and 2D are cross-sections showing typical sizes of the standardized CMOS transistor structure and the non-standardized CMOS transistor structure, respectively. These structures will provide the implementation of the 16-point divider shown in Figure 2B. . The standard CMOS structured substrate in FIG. 2 is composed of an n-type substrate 31 and a p_well 32. The N-type substrate 31 is biased VBB. Inside the N-type substrate 31, a p-type source and a drain 35 are formed. An N + -type source and a drain 34 are formed within the p_well 32. In the upper part of the p-well 32, a number of dioxide particles 37 are formed, which are selectively deposited with a number of metals 39. In addition, a selected amount of silicon dioxide 37 is embedded in a corresponding number of polycrystalline silicon gates 38 to form its gates prepared from NMOS and PMOS transistors. The completed standardized CMOS circuit is driven by the gate calendar, and the current is supplied by the voltage VSS and GND. Page 11 This paper size applies Chinese National Standard (CNS) A4 specification (210x297 mm); τ V… ,: whip ..... ::-order ---- τ… 'line · (Please read the back first Please fill out this page again} Printed by A7, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs

564555 V. Description of the invention () The non-standardized CMOS transistor structure shown in Figure 2D as the 16-divider of Figure 2B is called the silicon-on-insulator (SOI) structure. The sapphire substrate 41 has a thickness of 27 mm to 27000 μm. Therefore, the biased sapphire substrate 41 is biased ν Β Β. Similar to the standardized CMOS transistor structure, various CMOS circuit elements are composed of several n + sources and drains 44, several P-type sources and drains 45, several silicon dioxides 47 selectively deposited in polycrystalline silicon gates 48, and deposited metals. 49 formation. Similarly, the completed non-standardized CMOS circuit is driven by the gate voltage Gate, and current is supplied by the voltages VSS and GND. Figures 2E and 2F show the capacitance models of the standardized CMOS transistor structure and the non-standardized CMOS transistor structure, respectively. These structures are provided by the implementation of the sixteen-divider divider shown in Figure 2B. use. The standardized CMOS capacitor model 51 in Figure 2E contains the (parasitic) capacitor components of each externally available node. For example, for the node Gate, the corresponding capacitance component is:

Cgs, Cgd, and Cgb. In another example, for the node VBB-substrate contact one, the corresponding capacitance component is:

Cgb, Csb, Cdb, and more.

Qualitatively, the SOI CMOS capacitor model 52 shown in FIG. 2F shows that it is equivalent to the standardized CMOS capacitor model 51. However, quantitatively, there is a significant difference in capacitance values observed between the 'standardized CMOS structure and the SOI CMOS structure due to the material and thickness. For example, the following table lists the standardized CMOS structure and SOI CMOS.--The first version, the Zhang scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297). ,,: Ί V: · 土.....- Order——T…, Line · (Please read the notes on the back before filling out this page) Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 564555 A7 B7 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the invention () One of the two structures of the transistor, the rate of inactivity is increased for a long time, and the approximate value of each different capacitance component is tolerated: Standardized C Μs transistor structure capacitance

Cd = 1.4 fF & m2 (ΗΜ5 Faraday / micron 2)

Cg = 7.8 fF & m2 (10-15 Faraday / micron 2)

Cs = 5_0 fF & m2 (1 (M5 Faraday / micron 2)

Cb = 2.0 fF / pm2 (10-15 Faraday / micron 2) SOI CMOS transistor structure capacitance Cd = 0.6 ΐ ¥ / μιη2 Cg = 2.4FF / pm2 Cs = 1.6 ΐ ¥ / μτη2

Cb = 0.2 fF / pm2 It should be noted that, in the standardized CMOS structure in FIG. 2C, each n + source and drain 3 4 in the P-well 3 2 is only separated from the conductive N-type substrate 3 1 A thickness of less than 1 · 2 microns. In addition, each of the p-type source electrodes and / or electrodes 35 and 5 is in direct contact with the conductive N-type substrate 31, but passes through a correspondingly formed negative bias diode structure. Therefore, the capacitance value Cb in the standardized C μ Ο S structure is high. However, in the SOI CMOS structure in FIG. 2D, the 'N + source and drain 44 and the p-type source and drain 45 are in direct contact with a very thick insulating sapphire substrate 41 (27000 microns). Therefore, the capacitance value cb in the SOI CMOS structure is much smaller than the capacitance value Cb in the standardized CMOS transistor structure. In addition, the other capacitors Cd, Cg, and Cs are much smaller than their values in the standardized CMOS structure. Therefore, in the same circuit circuit, in general, when the signal waveform is high, the first Paper size applies to China National Standard (CNS) A4 specification (210X297 mm) ---, ........ I-order ---: ----- line · (Please read the note on the back first? Matters reproduced on this page) 564555

V. Description of the invention () The relevant quantitative signal waveforms from the SOI CMOS structure will be very different from those produced by the & standardization CMOS structure. Therefore, the above circuit 1 will be quantitatively adjusted to the SOI CM0s structure to achieve a new circuit design that can produce high-quality output signals. It is especially suitable for high clock frequencies used in optical communications. Will explain in more detail. It is well known in this technical field that for the IC design of a given wafer process, the conductivity of a MOS transistor is mainly determined by the following parameters: W / L, where W = channel width and L = channel length. For simplicity 'the following parameters are defined: Electronic Equivalent Channel Geometry (EECG) = W / L. Given the above definitions, Table A shows a comparison of the tabular design between the typical implementation and the present invention. This comparison is the first construction of the two-divider divider 20 used by the sixteen-divider divider 60 in FIG. Cube. For example, in a typical implementation, the EECG of both transistors Mcl and Mc2 are 60 'and the EECG of transistors 1VH, M2, M11, and M12 are all 120. Similarly, in the present invention, the EECG of both the transistors Mel * Mc2 is 60 'and the EECG of the transistors Ml, M2, Ml 1 and Ml 2 are 180. C Please read the notes on the back before filling out this page) Line-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Page 14 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 564555 A7 B7 V. Description of the invention () Table 1A Typical implementation of EECG design of frequency divider 20 The EECG ratio of EECG of the present invention EECG EECG ratio Mcl 60 1 Mcl 60 1.00 Mc2 60 1 Mc2 60 1.00 Ml 120 2 Ml 180 3.0 0 M2 120 2 M2 180 3.00 Mil 120 2 Mil 180 3.00 M12 120 2 M12 180 3.00 M3 120 2 M3 200 3.33 M4 120 2 M4 200 3.33 M5 120 2 M5 240 4.00 M6 120 2 M6 240 4.00 Ml 3 120 2 M13 200 3.33 M14 120 2 M14 200 3.33 M15 120 2 M15 240 4.00 M16 120 2 M16 240 4.00 (Please read the precautions on the back before writing this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

According to the advantages of the present invention, various parasitic effects can be appropriately and inherently formed by having a transistor that conforms to different EEC G, where EEC G is obviously different from the traditional design. For the convenience of explanation, a separate line called "EECG _page 15_ This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 564555 A7 _B7 _ V. Description of the invention () ratio" is further defined as each The simplest possible EECG ratio that may exist in the entire transistor set for a design situation. In this way, the EECG ratios of the various designs constitute separate columns. For example, according to the present invention, it can be obtained from Table 1A that the EECG ratio of M3: M5: M 1 3 = 3 · 3 3: 4 · 00: 3 · 3 3 and so on. In this way, the obvious potato characteristics of quantitative design can be more easily presented, and the results are shown in Tables 1 B, 1 C, and 1 D, respectively, which show the comparison of tabular designs between typical implementations and the present invention, These comparisons are for the second, third, and fourth building blocks of the sixteen-divider divider 60, respectively. (Please read the precautions on the back before copying this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, page 6 gl This paper size applies to China National Standard (CNS) A4 (210X297 mm) 564555 A7 B7 V. Invention Description () Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Table 1B. EECG design of frequency divider 30. Typical implementation of the EECG ratio of EECG of the present invention. 2 Ml 120 2.40 M2 100 2 M2 120 2.40 Mil 100 2 Mil 120 2.40 M12 100 2 M12 120 2.40 M3 100 2 M3 120 2.40 M4 100 2 M4 120 2.40 M5 100 2 M5 480 9.60 M6 100 2 M6 480 9.60 M13 100 2 M13 120 2.40 M14 100 2 M14 120 2.40 M15 100 2 M15 480 9.60 M16 100 2 M16 480 9.60 Page 17 This paper size is applicable to China National Standard (CNS) A4 (210X297 mm): 7 ------- « ........ Order · *, ·: 1 line · (Please read the precautions on the back before filling out this page) 564555 A7 B7 V. Description of the invention () Table 1C Typical design of EECG of divider 40 Implementation • The EECG ratio of the EECG of the present invention ECG ratio: Mcl 40 1 Mcl 40 1.00 Mc2 40 1 Mc2 40 1.00 Ml 80 2 Ml 100 2.50 M2 80 2 M2 100 2.50 Mil 80 2 Mil 100 2.50 M12 80 2 M12 100 2.50 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs M3 80 2 M3 100 2.50 M4 80 2 M4 100 2.50 M5 80 2 M5 900 22.50 M 6 80 2 M6 900 22.50 M13 80 2 M13 100 2.50 M14 80 2 M14 100 2.50 M15 80 2 M15 900 22.50 M16 80 2 M16 900 22.50 7: ·:-Let · .—— :: Order · ——, —— Line · (Please read the precautions on the back before filling out this page) Page 18 This paper size applies to China National Standard (CNS) A4 (210X297) (Centi) 564555 A7 B7 V. Description of the invention () Table 1D Typical design of EECG of frequency divider 50 Implementation of EECG ratio of EECG of the present invention EECG EECG ratio of half Mcl 30 1 Mcl 30 1.00 Mc2 30 1 Mc2 30 1.00 Ml 60 2 Ml 80 2.67 M2 60 2 M2 80 2.67 Mil 60 2 Mil 80 2.67 M12 60 2 M12 80 2.67 M3 60 2 M3 80 2.67 M4 60 2 M4 80 2.6 7 M5 60 2 M5 1400 46.67 M6 60 2 M6 1400 46.67 M13 60 2 M13 80 2.67 M14 60 2 M14 80 2.67 M15 60 2 M15 1400 46.67 M16 60 2 M16 1400 46.67 (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Please refer to Tables 2 to 5 now, which further show typical implementations and the present invention The difference between the EECG and EECG ratios in the quantitative design of the building blocks of the selected transistor. For example, according to a typical implementation of the transistor _ page 19_ This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 564555 A7 B7 V. Description of the invention () The EECG and EECG ratio of the body M1 can be as follows Table-2 shows: Table-2 EECG of transistor M1-typical implementation of frequency divider 20 frequency divider 30 frequency divider 40 frequency divider 5 0 EECG 120 100 80 60 EECG ratio 2 2 2 2 However, according to this The EECG corresponding to the transistor M1 of the invention (please read the notes on the back before filling in this page) The EECG ratio is shown in the following table-3: Table-3 EECG of the transistor M1 — frequency divider 20 of the present invention Divider 30 Divider 40 Divider 50 EECG 180 120 100 80 EECG ratio 3 2.4 2.5 2.67

In another example, the ratio of EECG and EECG of the transistor M 1 3 according to a typical implementation can be shown in the following Table-4: Table-4 EECG of the transistor M 13 -A typical implementation of the frequency divider 20 Frequency divider 30 Frequency divider 40 Frequency divider 5 0 EECG 120 100 80 60 EECG ratio 2 2 2 2 However, the EECG corresponding to the transistor M13 according to the present invention and the consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs, the printed EECG ratio is as follows Table-5 shows: Table-5 EECG of transistor Ml 3-frequency divider 20 of the present invention 3 frequency divider 3 0 frequency divider 40 frequency divider 5 0 EECG 200 120 100 80 EECG ratio 3.33 2.4 2.5 2.67 page 20 This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 564555 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

The female watch · 2 shows that although the crystal G1 of the coffee G has a falling heart: the device 20 to the frequency divider 5. The time is in the frequency divider ~ frequency 52: 拄 but the individual design value of the individual ratio 2β Similarly, 'invariant' it is the electric crystal Zhao Ml divider 20 to the frequency divider 50 hours and 4 It shows that although the frequency potential is divided, the individual EECGtb = ^ 3 UECG also tends to decrease, which is the second of the transistor: the A thunder in the typical implementation when the frequency divider 2 ° to the frequency divider 50 Said I alone design value 2. In fact, the comparison is also shown in the system of% $ $ EECG 纟 EECG ratio. It is clear from the observation result that the frequency divider is 60. Therefore, all the construction areas shown in the typical implementation are the same as the fixer + extravagance. The ratio of those who are familiar with this technology is 4 and a. 10 is essentially the second of all transistors: frequency converter M to frequency divider 50. (Ca) The frequency has been decreased when the frequency is successively divided. The reason is that the current pulse must correspond to Lower operating power, reduced circuit operating rates will only require reduced power. Machine at this time has a lower EECG value to refer to the building blocks of the present invention shown in Table 3, although the transistor M1 < EECG decreases similarly from ρ 20 to divider 50 However, when the frequency divider 20 to the frequency divider 50 are used, all the building blocks of the frequency divider 60 do not have the same separate design values for the individual EECG ratios. Simultaneous recognition of the master r ^ ground 'table_5 shows that · Although the EECG of the electric solar hemisphere Ml 3 has a downward trend from the frequency divider 20 to the frequency divider 50, the frequency divider] divider 5 0 In the case of the individual EECG ratio of the transistor M 1 3, all the building blocks of the frequency divider 60 do not have the same individually set δ ten value. In fact, 'EECG and EECG of other transistors in the present invention page 21 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 1 Note Ε η line 564555 A7 B7 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the cooperative V. Invention description () The systematic comparison of ratios also showed the same observations. Therefore, with the present invention, the quantitative design of the individual building blocks of the divider 60 will be different from each other. For those skilled in the art, the present invention discloses a unique design technical feature, which is obviously different from the typical typical implementation. This is based on the fact that the present invention requires that all individual building blocks of the divider 60 be different. The method is designed to obtain higher quality output signals, but the techniques taught by typical implementations cannot achieve this effect. It can be further found from the above table that each of the frequency dividers 20, 30, 40, and 50 has a set of ratios and one set of ratios used for one divider (such as 20) is different from the other set of ratios used for Another set of ratios for another divider (such as 60). As used herein, a group of ratios refers to the Common Factor (CF) and is defined as a ratio array or ratio vector (if all ratios are arranged in a row and column). Accordingly, as a feature of the present invention, the CF of one frequency divider (such as 20) is different from the CF of another frequency divider (such as 60). Table 1 E series shows the results of all design comparisons regarding the ratio of typical implementations to the EECG of the present invention ', which is compared against the sixteen-divider divider 60 shown in Figure 2B. Obviously, although the qualitative design of all the individual building blocks of a typical implementation of the divider 60 is very similar, the quantitative design of each building block of the divider 60 of the present invention will be different because each building block Blocks need to be adjusted individually in order to obtain high-quality output signals under the adverse effects of output loads and interactions between adjacent building blocks. The second paper size is applicable to the Chinese National Standard (CNS) A4 specification (210x297 mm) ΊΙΪ ---- II ----- I --- ^ ----- J (Please read the precautions on the back first Refill this page} 564555 A7 B7 V. Description of the invention () Table 1E Overview of the EECG design of the frequency divider 60 The Ministry of Economic Affairs Intellectual Property Bureau employee consumer cooperative printed a typical implementation of this invention BEDGtk # EBOG neck DIV1 DIV2 DIV3 DIV4 DIV1 DIV2 DIV3 DIV4 Mcl 1 1 1 1 Mcl 1.00 1.00 1.00 1.00 Mc2 1 1 1 Mc2 1.00 1.00 1.00 1.00 Ml 2 2 2 2 Ml 3.00 2.40 2.50 2.67 M2 2 2 2 2 M2 3.00 2.40 2.40 2.50 2.67 Ml 1 2 2 2 2 Mil 3.00 2.40 2.50 2.67 M12 2 2 2 2 M12 3.00 2.40 2.50 2.67 M3 2 2 2 2 M3 3.33 2.40 2.50 2.67 M4 2 2 2 M4 3.33 2.40 2.50 2.67 M5 2 2 2 2 M5 4.00 9.60 22.50 46.67 M6 2 2 2 2 M6 4.00 9.60 22.50 46.67 M13 2 2 2 2 M13 3.33 2.40 2.5 0 2.67 M14 2 2 2 2 2 M14 3.33 2.40 2.50 2.67 M15 2 2 2 2 M15 4.00 9.60 22.50 46.67 M16 2 2 2 2 M16 4.00 9.60 22.50 46.67 (Please read the notes on the back before filling this page) _Page 23 This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 564555 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (Typically, these effects will occur at high CLK frequencies More obvious, such as the high CLK frequency used for high-speed optical communication. Thus, Figure 3A compares the output signal DOUT! Between the typical implementation and the present invention. This comparison is for the second half of the sixteenth divider 6G. The first-building block of the frequency divider 20, and the sixteenth frequency divider 60 is driven by the input clock (INpuT CL0 (^) 2i) with a frequency f (CLK) = 2.5G GHz. It should be noted that 'in this typical implementation, the output signal fails in its frequency divider function due to all frequency errors, but the signal ripple 62 of the present invention is clearly visible. This result shows great progress. Similarly, the 帛 3B, 帛 3C, and 3D pictures are respectively compared with the round-off signal ripples DOUT2, dout3, and DOUT4 between the typical implementation and the present invention. The building blocks of the frequency divider 30, the frequency divider 40 and the frequency divider 50 used by the frequency divider 60, and the sixteenth divider 60 is composed of an input clock (ΙΝρυτ CLOCK) with a frequency f (CLK) = 2.50 GHZ 21 to drive. A significant improvement between the complete failure of a typical implementation and the clearly visible signal ripples 64, 66 and 68 of the present invention can be observed again. Another application example of the present invention is shown in FIGS. 4 to 6. Figures 4 and 5A are block diagrams showing a typical circuit of a D-type flip-flop (MS-DFF) 70 with a current mode switching function and related logic functions according to an embodiment of the present invention. In this circuit, the supply voltage AVDD is 1.8 volts, but other voltages such as 2.5 volts can also be used. The input clock signal is CLK 71 and CLKL72. The input data signal is D 73. Page 24 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) VI-: ·: " ::: · -.— —.… Order :: * ——4 · (Please read the notes on the back before filling this page) 564555

V. Description of the invention () and 11 74. The output data signals are Q 75 and Q_ 76. Different NMOS transistors in operation are labeled Ncl, Nc2, Nl, N2 ... and N16. The four boost resistors are labeled S3, S4, su, and si4. It can be known that such a circuit structure can be made clear by using a standardized CM integrated circuit and various non-standardized CMOS integrated circuit manufacturing processes. In addition, if it can be quantitatively designed to provide high-quality signal output with a high CLK frequency, such as 2.5GHz used in OC-48 communication, the MS-DFF 70 can also be used as a low-cost optical switch for optical networks. Basic building blocks. FIG. 5B is a logic function block diagram of a typical BBPD 80. The BBPD uses MS-DFF 70 as shown in FIG. 4 as its logic building block. The eight-body 'repeating logical building blocks are labeled 81, MS-DFF 82, and MS-DFF 83. The input signals include vc〇 85 and DATA-IN 86. The output signal includes PHASe 88. Those who are familiar with this technology can easily know that the logic state of PHASE 88 will change with the leading or trailing phase relationship between the two input signals vc〇 85 and DATA-IN 86. For the sake of simplicity, the following differential signals are also defined: △ PHASE = PHASE-PHASE. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed as before, although it uses the same MS-DFF 70 circuit architecture with current mode switching function. The different quantitative settings of BBPD 80 will still produce very different output signal quality, especially the high VCO frequency used in optical communication. Tables 2A, 2B, 2C, and 2D present this result in a manner similar to the first example of the divider 60. Page 25 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 564555 A7 B7 V. Description of the invention () Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2AA MS-DFF 81 Typical EECG design The EECG ratio of the EECG used in the present invention Ncl 60 1 Ncl 60 1.00 Nc2 60 1 Nc2 60 1.00 N1 120 2 N1 200 3.33 N2 120 2 N2 200 3.33 Nil 120 2 Nil 200 3.33 N12 120 2 N12 200 3.33 N3 120 2 N3 200 3.33 N4 120 2 N4 200 3.33 N5 120 2 N5 320 5.33 N6 120 2 N6 320 5.33 N13 120 2 N13 200 3.33 N14 120 2 N14 200 3.33 N15 120 2 N15 320 5.33 N16 120 2 N16 320 5.33 r ---- 1 ^ --- • 丨 I ........ ^ --- ^ ----- (Please read the precautions on the back before filling out this page) Page 26 This paper size applies Chinese national standards ( CNS) A4 specification (210 X 297 mm) 4564555 A7 B7 V. Description of the invention () Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economy 2B MS-DFF 82 EECG design typical implementation • EECG EECG EECG EECG ratio ratio Ncl 60 1 Ncl 60 1.00 Nc2 60 1 Nc2 60 1. 0 0 N1 120 2 N1 200 3.33 N2 120 2 N2 200 3.33 Nil 120 2 Nil 200 3.33 N12 120 2 N12 200 3.33 N3 120 2 N3 320 5.33 N4 120 2 N4 320 5.33 N5 120 2 N5 200 3.33 N6 120 2 N6 200 3.33 N13 120 2 N13 320 5.33 N14 120 2 N14 320 5.33 N1 5 120 2 N15 200 3.33 N1 6 120 2 N16 200 3.33 / 丨 ---- I ^ --- I ........--- t 1- I »I t ^ (Please read the notes on the back before filling in this page) Page 27 This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) 564555 A7 B7 V. Description of the invention () Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2C: The EECG design of MS-DFF 83 is a typical implementation of the EECG of the present invention. The EECG EECG ratio ratio Ncl 60 1 Ncl 60 1.00 Nc2 60 1 Nc2 60 l .〇〇N1 120 2 N1 100 1.67 N2 120 2 N2 100 1.67 Nil 120 2 Nil 100 1.67 N12 120 2 N12 100 1.67 N3 120 2 N3 100 1.67 N4 120 2 N4 100 1.67 N5 120 2 N5 1100 18.33 N6 120 2 N6 1100 18.33 N13 120 2 N13 100 1.67 N14 120 2 N14 100 1.67 N15 120 2 N15 1100 18.33 N16 120 2 N16 1100 18.33 「T --- JTII! I I ------- (Please read the precautions on the back before filling out this page) Page 28 This paper size applies Chinese National Standard (CNS) A4 (210X297 mm) 564555 A7 B7 V. Invention Description () Table 2D BBCG 80 EECG design overview typical implementation EBOG ratio EBOG ratio EBOG ratio MS-DEF1 MSOHF2 MSCEF1 EEGG ratio EBOG ratio EBOG ratio MS4DEF1 MSDFF2 MSDFF1

Ncl 1 1 1 Ncl 1.00 1.00 1.00 (Please read the notes on the back before copying this page)

Nc2

Nc2 1.00 1.00 1.00 N1 2 2 2 N1 3.33 3.33 1.67 N2 2 2 N2 3.33 3.33 1.67

Nil 2 2 2 Nil 3.33 3.33 1.67 N12 2 2 2 N12 3.33 3.33 1.67 N3 N4 2 2 2 N3 3.33 5.33 1.67 2 2 2 N4 3.33 5.33 1.67 Page 29 This paper applies to China National Standard (CNS) A4 specification (210X297 mm) 564555 A7 B7 V. Description of invention () N5 2 N6 2 2 N13 2 2 N14 2 2 N15 2 N16 2 2 N5 5.33 3.33 18.33 N6 5.33 3.33 18.33 N13 3.33 5.33 1.67 N14 3.33 5.33 1.67 N15 5.33 3.33 18.33 N16 5.33 3.33 18.33 (Please read the precautions on the back before filling out this page) _ installed. This is printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, although BBPD 80 The quantitative design of all the individual building blocks is similar to the typical implementation, but the quantitative calculations of the building blocks of BBPD 80 and B 80 are based on the materials of the present invention, so that ^ In the case of adverse effects of output load and interaction between the construction blocks, a high-quality rotation signal can be obtained. Again, these effects are more pronounced at high VCO frequencies, such as the high VCO frequencies used in high-speed optical communications described herein. FIG. 6 is a comparison of a typical implementation of the output signal APHASE between BBPD 80 and the BBPD 80 of the present invention. The frequency of vc〇 85 of BBPD 80 is f (CLK) = 2.50 GHz. It should be noted that, in a typical implementation, the output signal is ultra-high frequency in terms of its phase detector function. Page 30 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm)! Order_ % 564555 A7 B7 Consumption cooperation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, Du printed 5. The invention description () was invalidated, but the output of the invention is still fully functional with its clearly visible signal ripple 9 i. This result shows great progress. Figures 7A and 7B illustrate the standardized CMOS transistor structure and another non-standardized CMOS transistor structure, respectively. These structures provide the sixteen-divider divider shown in Figure 2B and the structure shown in Figure 5B. Shows BBPD implementation. The NMOS field-effect transistor 100 in FIG. 7A includes a source electrode 101, a gate electrode 102, and a gate electrode 103, and the gate electrode 103 and the channel connecting the source electrode 101 and the drain electrode 102 are dielectrically insulated from each other. The interface of Figure 7B, fET 110, has been described in Schilling and Belove (see McGraw-Hill Books, 1979, Electronic, by Donald Schilling and Charles Belove.

Circuits Discrete and Integrated, pp. 134-137). The junction FET 110 includes a source electrode 111, a gate electrode, and a gate electrode jig, where the gate electrode 113 is insulated from each other by two diodes formed between two P-type gate regions 114 and an N-type channel 115, and the channel 丨丨 5 series connects the source ui and the drain 1 1 2. At this point, those skilled in the art will understand that the electronic circuit, as shown in the structure of the transistor structure, the systematic adjustment design method of each building block, can also be applied to the interface FET or any other non-standard FET structure. Another important point about the present invention is that although the preferred embodiments are based on the systematic adjustment of NMOS transistors in individual building blocks as an example, in fact, many or all related passive circuit elements can be correspondingly adjusted. For example, in Figure 1, the resistors R3, r4, R13, and Rl4 can individually apply to each building block of the divider 60 in Figure 2B ------- 3rd Top Book, I Zhang scale is applicable to China National Standard (CNS) A4 specification (210X297 mm) V Ί T: I: Meal ----- ,: Order: ·· ——.- Line · (Please read the precautions on the back before filling (This page) 564555 Α7 Β7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Adjustments; however, for the sake of explanation, such adjustments are not illustrated. For another example, in Figure 4, resistors S3, S4, S13, and S14 can be individually adjusted for each building block of BBPD 80 in Figure 5B; however, for the same reason, such adjustments Also not illustrated. As in the two examples described above, by systematically adjusting the circuit parameters of some or all components of individual building blocks of an electronic circuit system, the quality of the corresponding output signal can be greatly improved. This effect is especially important for applications with high clock frequencies; for example, in optical communications, these effects are more pronounced in the output load and interactions between functionally connected building blocks. The invention has been described with reference to preferred embodiments. However, for those skilled in the art, the preferred embodiments can be easily adjusted and modified to make it suitable for other applications without departing from the spirit and scope of the present invention. Some related applications include: · Optical communications at data rates of 2.5 Gbit / sec (OC48) and 10 Gbit / sec (OC192), Gigabit Ethernet, 10 Gigabit Ethernet, Bluetooth ( (Blue Tooth) technology (2.4 GHz) and wireless local area network (laN) (5.2 G) z), but not limited to the above. At such a high data rate, the hardware infrastructure for multimedia information ultra-high-speed lines can also be implemented. Therefore, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the present invention actually covers various changes and similar configurations based on the same operating principle. Therefore, the scope of patent application should be interpreted in the broadest sense to cover all such changes and similar configurations. The 3rd paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) V Ί: ·: Τ:: —— :: Order --------- line · (Please read the first (Please fill in this page again)

Claims (1)

564555 A8 B8 C8 D8 Sixth, the scope of patent application 1-An electronic circuit system for signal processing, which includes at least: a plurality of individually adjusted building blocks, each building block has a similar circuit topology, the circuit topology further includes:, passive components A set of interconnections with several EFT (Field Effect Transistors) manufactured by non-standard industrial ... processes, in which each FET is provided with an adjustable value of the electronic equivalent channel geometry (EECG), which is defined as an individual The ratio of the channel width to channel length of a FET; and a vector called a common factor (CF), which is defined as the ratio of the vectors between the EECG sets of the FETs, and where the The adjustment method is such that the CFs of the individual building blocks that are individually adjusted will not share the same direction, so as to obtain a set of required output signals with improved characteristics. 2. The electronic circuit system described in item 丨 of the scope of patent application, wherein the improved characteristics of the above-mentioned required output signal include reducing the adverse effects caused by the interaction of two or more building blocks at the system level. 3. The electronic circuit system as described in item 丨 of the scope of patent application, wherein the improved characteristics of the above-mentioned required output signal include reducing the degree of output signal ripple. 0 4 · The electronic circuit system as described in item 1 of Shen Qing's patent scope Among them, the improved characteristics of the required output signal include reducing the jitter of the output signal. Page 33 This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm)! 1 1 {Please read the precautions on the back before filling this page) Order · ------.-- -1 line 564555 A8B8C8D8 printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Scope of patent application 5. The electronic and electrical I system as described in item i of the scope of patent application, where the improved characteristics of the above-mentioned output signals include: The degree of the oscillating sign. -4 Required output information 6 · If the scope of patent application is 帛! The electronic m ^ ^ Ψ -xr ^ system described in the above item, wherein the improved characteristics of the above-mentioned output signal including the 増 range are also included. Dynamics of output signals 7. The electronic signal system described in item 丨 of the scope of patent application, wherein the improved characteristics of the above-mentioned required output signals further include 増 ▲ 'characteristics. The linearity of the output signal 8 · If the scope of patent application is the highest! In the electronic circuit system described in the item, the improved characteristic of the required output signal further includes increased accuracy.衢 Wave out: ——1! 羲 (Please read the “Notes on the back side before filling this page”) Order -------. 1 · ---. Line. Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Print 9. The electronic circuit system as described in the scope of the patent application (1), wherein the improved characteristics of the above-mentioned required output signal further include increasing the accuracy of the output signal ^. Ascending month 1 If the scope of patent application is the first! The electronic circuit system described in the above item is particularly selected from the group-the group includes: positive, frequency divider, register and counter, timer, memory, anti special page 34 of this paper Standards are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) 564555 A8 B8 C8 D8 6. Application for patents Application integrated circuit (ASIC), Zeng i L) Alienation and logic unit (ALU), embedded Controller, microprocessor, Zhaobankou digital and analog filters, phase frequency detector frequency port generator, multiplier and signal modulator, multiplexer and demultiplexer, phase locked loop, data converter And multistage amplifier. 11. A method of sighing electronic circuit system for signal processing, which includes at least:,, providing a plurality of individual building blocks for adjustment, wherein each building block has a similar circuit topology, and the circuit topology further includes Passive component disks are interconnected sets of several EFTs manufactured by non-standard industrial processes; find the adjustable value of the electronic equivalent channel geometry (EECG) for each FET, which is defined as the channel width and channel degree of individual chirps Ratios; specify a vector called a common factor (CF), which is the vector ratio between the EECG sets of sense FETs; and "adjust each building block individually adjusted, and the adjustment method can be adjusted individually The CF of each construction and block will not share the same amount, so as to obtain a set of required output signals with improved characteristics. The whole length is printed to the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. [丨 The method described in the item 丨 The method of the electric circuit system, wherein the improved characteristics of the above-mentioned required output signal include reducing the interaction of two or more building blocks on the system surface The non-production caused by the use should be 0 square layers. Page 35 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) A8B8C8D8 564555 6. Application for patent scope 1 3. If the scope of patent application for item 11 The method of designing an electronic circuit system described above, wherein the improved characteristics of the above-mentioned required output signal include reducing the degree of output signal ripple. 1 4 · Designing an electronic circuit system as described in item 11 of the scope of patent application in May Method, wherein the improved characteristic of the above-mentioned required output signal further includes reducing the degree of output signal jitter. *. 15 · The method for designing an electronic circuit system as described in item n of the scope of patent application, wherein the above-mentioned required output signal is improved The characteristics also include reducing the degree of unwanted output signal oscillation. 1 6 · The method of designing an electronic circuit system as described in item 11 of the scope of patent application, wherein the improved characteristics of the above-mentioned required output signals further include the dynamics of increasing the output signal Scope. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 17 · Design of electronic circuit system as described in item n of the scope of patent application. Method, wherein the improved characteristic of the above-mentioned required output signal further includes an increase in the linear characteristic of the round signal. 1 8 · The method for designing the electronic signal system as described in item i 1 of the scope of patent application, wherein the above-mentioned required output signal The improved characteristics also include you. The accuracy of the signal waveform is still increased. The 36th paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) A8B8C8D8 564555 6. Application for patent scope 19. Such as The method for designing an electronic circuit system as described in the patent application, wherein the improved characteristics of the above-mentioned required output signal further include increasing the precision of the phase angle of the output signal. 1 The method for designing an electronic circuit system as described in item 胄 U of the patent application scope, wherein the above electronic circuit system is specially selected from a group consisting of a flip-flop, a frequency divider, a register and a counter, Timers, cryptographic special application integrated circuits (ASIC), arithmetic and logic units (ALU), embedded controllers, microprocessors, digital and analog filters, phase frequency detectors, frequency synthesizers, multiplication And signal modulators, multiplexers and demultiplexers, phase-locked loops, data converters and multi-stage amplifiers. 21. An integrated circuit for processing high-speed signals, the integrated circuit includes at least a first differential circuit to receive an input signal having a frequency, a first differential circuit, and The first differential circuit is connected, each of the first and the second differential circuits includes several transistors, and each of the transistors is associated with an electronic equivalent channel geometry (EEcg) value, and the EECG decides to surround the The parasitic capacitance of each transistor; wherein a ratio of each transistor is determined as the EECG value of each transistor divided by any eecg value selected from one of the transistors; and page 37 This paper size applies to the national standard of the country (CNS) A4 (210 X 297 public love) < Please read the precautions on the back before filling in this page) Intellectual Property Bureau Printed Clothing for Consumer Cooperatives § 564555 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 564555 Sixth, the scope of application for patents 63 The scope of application for patents No. 22 The scope of the integrated circuit of the “Finite-m”, in which the first and the second differential circuits are connected, the .e-yang system is a CMOS circuit Crystal or% effect transistor. 27. If the n-th integrated circuit in the scope of the patent application is applied, the transistors in the two circuits are manufactured with a standard CMOS structure substrate or an insulating layer overlying a dream (SOI) structure substrate. From the integrated circuit as described in item 27 of the scope of patent application, wherein the lower parasitic capacitance in the fairy structure substrate is adjusted by the above-mentioned: differential circuit and the second differential circuit. The parasitic capacitance compensation formed by the EECG of the crystal. 29 · —An integrated circuit system for high-speed signal processing, the integrated circuit includes at least: a first building block that receives an input signal having a frequency and generates an output signal; a second building block , Which is coupled to the first building block and receives the output signal of the first building block, wherein each of the two building blocks includes: several transistors, each of which has an electronic equivalent channel geometry (EECG) value to determine the parasitic capacitance that surrounds each transistor; one of the above-mentioned ratios of each of the transistors is determined to be the Chinese National Standard (CNS) A4 specification (210 pages per page). X 297 mm) 564555 VI. Patent application scope-The EECG value of a transistor is divided by any EECG value selected from one of the transistors; and when the ratio of each transistor of the first building block is adjusted with reference to the frequency, such that The parasitic capacitance is formed inherently and appropriately to establish a parasitic effect to minimize possible epigenetic phenomena in one of the outputs from the first building block. 30. The integrated circuit system as described in item 29 of the Shenjing patent scope, wherein the ratio of each transistor of the second building block is adjusted so that an output from one of the second building blocks The signal with the smallest epigenetic phenomenon is introduced into the second building block. 3 1 · The integrated circuit system described in item 29 of the scope of patent application, wherein any one of the first and second building blocks includes a first differential circuit coupled to a second differential circuit, each -The differential circuit includes several transistors. 32. The integrated circuit system described in item 31 of the scope of patent application, wherein the ratio of each of the at least several transistors in the first building block is different and each corresponding in the second building block The ratio of the transistor is 0 33. The integrated circuit system described in item 29 of the scope of the patent application, wherein the transistor systems in both the first and second differential circuits are based on a standard ---- ; ---.-- Ί .-- Ί 1 ----- Order 4 ----- „(Please read the notes on the back before filling in this page) Line ------- Brother 40 One sheet of paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) 564555 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs B8 C8 D8 VI. Application scope of patents ^ CIVI0 S structural base; or "-Shaoyue Lane Plate A is made of silicon (SOI) structural substrate on the insulation layer. 34. The integrated circuit system as described in item 33 of the patent application scope, wherein the lower parasitic capacitance in the SOI and 纟 0 substrates is adjusted by the first differential circuit and the first differential circuit respectively as described above. The parasitic capacitance formed by each transistor ^ EECG in the two differential circuits is compensated. 3 5 · A method for processing high-speed signals, the method includes at least the following steps: · Deciding one of the frequencies of an input signal, the signal is received in a first differential circuit; providing a coupling to the first differential circuit A second differential circuit, each of the first and first differential circuits including a plurality of transistors, each of which has an electronic equivalent channel geometry (EeCG) value to determine the surrounding of each The parasitic capacitance of the crystal; determining a ratio of each of the transistors described above, where the ratio is determined as the EECG value of each transistor divided by any EECG value selected from each transistor; and adjusting each The ratio of a transistor is adjusted with reference to the frequency so that the parasitic capacitance is formed inherently and appropriately. 36. The method as described in item 35 of the scope of patent application, wherein the transistors in the first and second differential circuits inherently establish various parasitic effects with the parasitic capacitance. ). ___Page 41__ This paper size applies to the Chinese National Standard (CNS) A4 (210 X 297 mm) ΓΓΙΙΙ ^ ΙΙΙΙ ^ Ι! Ί IIIIIIIII -Ί I — — — — ΓΙ — I — — — — — — Ll · !. (please read the precautions on the back before filling in this page) A8B8C8D8 564555 6. Application for patent scope 37. The method described in item% of the scope of patent application, in which the parasitic effects mentioned above are referred to The frequency is adjusted to optimize one or both of the ratios of the first group and the second group. 3 8. The method according to item 37 of the scope of patent application, wherein the parasitic effect described above is optimized to minimize possible epigenetic phenomena in the output from one of the first or second differential circuits. 39. The method according to item 36 of the scope of patent application, wherein the parasitic effect described above is optimized by adjusting the ratio of each transistor in the first and second differential circuits, so that the Possible epigenetics in one of the outputs from the first or second differential circuit are minimized. 40. The method according to item 36 of the scope of patent application, wherein the transistor systems in both the first and second differential circuits are CMOS transistors or field-effect transistors. 41. The method according to item 36 of the scope of patent application, wherein the transistor systems in the first and second differential circuit circuits have a standard CMOS structure substrate or a silicon-on-insulator (SOI) structure Substrate manufacturing. 42. The method according to item 41 of the scope of patent application, wherein the lower parasitic capacitance in the SOI structure substrate is adjusted by each of the first differential circuit and the second differential circuit as described above. EECG of crystals_ page 42 This paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm) (please «read the precautions on the back before filling this page) Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Developed by 丨 丨 丨 tl! 丨 丨 丨 丨 丨 · 564555 A8B8C8D8 印 Printed by the Intellectual Property Bureau Employees Consumer Cooperatives of the Ministry of Economic Affairs 6. The parasitic capacitance compensation formed by the scope of patent application. Page 43 (please read the notes on the back before filling in this page) Order-! 7-!-Line-------- jjllrnf ΙΓ .----- This paper size applies to China Standard (CNS) A4 specification (210 X 297 mm)