TW564544B - Semiconductor structure with a coil below the first wiring layer or between two wiring layers - Google Patents

Abstract

A semiconductor structure comprises a device layer of a semiconductor material, a dielectric layer (12) disposed above the device layer (2), a wiring layer (14) disposed on the dielectric layer (12) and a coil (60) disposed in the dielectric layer (12) and connected to contacts (66, 68) in the wiring layer (14).

Description

(1) (1) 564544 Di and Dad's explanation (Brief description of the invention: Brief description of the technical field, prior art, content, embodiments and drawings of the invention) The present invention relates to a semiconductor structure with a coil, especially It is about a semiconductor structure in which a coil is arranged under a wiring layer or between two wiring layers. In many applications (such as when connecting to a transmission-receiving device according to the GSM or UMTS standards), a semiconductor structure having a coil with a high Q value or a coil with a high coefficient of quality must be used. In the prior art, two different coil configurations were used in or on the semiconductor structure, which will be described earlier. The production of semiconductor structures is usually divided into two parts. In the front-end production line (FEOL), semiconductor devices (such as CMOS devices) are generated in the semiconductor material device layer on the substrate. In the back-end production line, the channel conductors of the first wiring layer and the wiring conductors of several wiring layers are passed. These semiconductor devices are connected. These wiring layers are arranged in the surface of the device layer facing away from the substrate ', wherein a dielectric layer is inserted between the two wiring layers to isolate each other. Each wiring layer includes an insulating layer made of an electrically insulating material, in which one or more wiring wires made of a conductive material are arranged. _ The contacts between the wiring wires in each wiring layer are formed by the contact channel, the channel conductor, and the channel through the dielectric layer between the two wiring layers. The contacts between the first wiring layer and the dielectric layer are also formed by channel conductors, channels, and contact holes, respectively. The dielectric layer and the insulating layer can be made of the same electrical insulating material and can be produced at the same time. There is only a geometrical difference between the dielectric layer and the insulating layer, and it is used to define a more precise coil configuration in a semiconductor device. In the following way, high-quality coils can be produced (more specifically (2) (2) 564544, which has a high Q value) ..... A wire structure that overlaps in a plurality of wiring layers, and It connects consistently. The biggest shortcoming of this kind of coil θ and connecting them through the channel conductors in parallel will have a space bar in the wiring layer. "Because of the connection / control in the multiple wiring layers, they will affect the respective And restrictions If the Q value of the coil is limited, the guide ^ is implemented as the farthest from the device layer: low $, the coil may be able to ^ «Oft ^ ® ^ ^, the metal wire in the terminal layer. To produce the same W value, the resistance value of the coil comes from $ ® ^ ^ φ, <, as small as possible. For a particular material, metronidyl, requiring a low resistance value is equivalent to the i-plane.哕 Lvyuan μ 2 s ^ Requires the largest metal wire cut "Another practical condition of the coil is the same as that of every other conductor structure, and it must occupy the minimum space. Although typical wiring The thickness and thickness of the layer and the wiring and a lead disposed therein are 300 nm-700 nm, respectively, and the thickness of a typical dielectric layer between two adjacent layers of the α 1 layer is 300 n: 700: m ', and the south of the coil typically made of metal wire in the last wiring layer is 2_ to 3_ (or even higher), but to produce a line section with minimum line width and minimum line spacing The higher the height, the better. The upper limit of the height of the metal wire depends on the product of the ratio between the maximum aspect ratio and the height and width that can be obtained when constructing (metal · surname engraving). The edges should be as parallel as possible. Compared to the first condensed coil created by connecting a plurality of coiled wires in parallel to the wiring layer, the last described coil is made up of extremely high metal wires in the last wiring layer. The advantage lies in its productivity, and its structure Advantages (the comparison does not limit (or even does not limit at all) the shape and configuration of the other connecting wires in the second layer) "However, in this comparison, (3) (3) 564544 also has several disadvantages Several of them are described as follows:, / w produces metal layers for a long time, and the thickness of the layer is 4 times larger than that of the general wiring layer, which reduces the I production by 75%; Design rules and layout parameters,

For example, the pitch of the thick metal wires forming the coil must be 4 8 " mgan A · / um, which will greatly limit the usability of the last wiring layer itself (that is, as a wiring wire); the last wiring layer is used Lithography must meet different conditions from the coil geometry 'connecting pads and wiring leads, but so far it can only be compromised; 2 to 3 deep coil edges and the metal forming the coils Wire edge, which must improve the insulation treatment of IMID, thereby incurring additional processing costs; in the subsequent processing of the semiconductor structure during package assembly, when the wafer is fixed by negative pressure and suction, the coil is narrow and high A mechanical stress is generated in the metal layer of the metal layer, which causes a twist to damage its insulation treatment, causing the coil to be damaged in the future due to a situation similar to moisture intrusion. An object of the present invention is to provide an improved semiconductor structure having a coil and a method for manufacturing the same. The semiconductor structure according to the scope of patent application 1 and the method according to the scope of patent application 8 can achieve this purpose. A semiconductor structure according to the present invention includes a device layer composed of a semiconductor material, a dielectric layer disposed on the device layer, a wiring layer disposed on the dielectric layer, and a configuration-on the dielectric layer. Coil in and connected to contacts in this wiring layer. A method for generating a semiconductor structure according to the present invention includes: providing a device layer in the semiconductor structure; (4) 564544 applying a dielectric layer to construct a recess in the coil in the dielectric layer; introducing a conductive material into the recess; Create a wiring layer; and

The coil is brought into contact with a contact in the wiring layer. A preferred development method is defined in the scope of the attached application patent. The principle of the present invention is based on the fact that the first wiring layer θ Γ can be used to take the space in the dielectric layer between the wiring layers, and the coil is arranged on the semiconductor structure. It is desirable to arrange the coil on the metal layer and the wiring layer of the semiconductor junction, and it is desirable to be able to be placed on the ILD (Interlayer Dielectric) and the copper BE 0 L standard process (back-end production line) between the two wiring layers. The channel is etched in the electrical layer, or in the top or bottom layer of the first additional etch step or below the first wiring layer. Therefore, these coils can be used in the oxide layer and the medium.

Structures are converted to ILDs, such as spiral trenches. Then the copper can be used to fill the ditch after money engraving, and at the same time, these channels can be filled.

According to the semiconductor structure of the present invention, the conductor structure produced by the method of the present invention and the manufacturing method itself have several advantages: • Metal layers with high stacking thickness and layer thickness are not required. • It can avoid a significant reduction in manufacturing yield due to the extremely thick metal layer used to form the coil in the last wiring layer. -There is no need to customize the design rules and layout parameters of the last wiring layer specifically for the coil, so the usability of the last wiring layer itself will not be limited. -The coil arrangement of the present invention enables the semiconductor structure to resist mechanical stress in its further processing. 564544

(5)-No IMID insulation treatment is used. Instead, the standard without IMID is used: quasi-insulation treatment, which can save processing costs. -Compared with the above-mentioned coils made of parallel circuits of the same coil device in several wiring layers, the coil of the present invention has a larger space gain and a lower space condition limit, because In other words, it occupies a smaller number of wiring layers. -The manufacturing method of the coil of the present invention can be easily integrated into the manufacturing process. The manufacturing of the coil can be performed partly simultaneously with the further element φ that produces the semiconductor structure, so only a few additional method steps need to be added. Preferred specific embodiments of the present invention will be discussed in more detail below with reference to the accompanying drawings. The system shown in the figure: three cross-sectional views of the first specific embodiment shown in FIG. 1; three schematic diagrams of the second specific embodiment shown in FIG. 2; and the system shown in FIG. 3 according to the present invention. A schematic diagram of a manufacturing method of a specific embodiment. FIG. 1 shows three cross-sectional views of the first embodiment of the present invention. Fig. 1a is a vertical cross-sectional view of the semiconductor structure of the present invention taken along the line A-A 'in the sub-images 1b and 1c. The sub-graphs lb and lc are horizontal cross-sectional views, that is, the cross-sections of the layer structure parallel to the semiconductor structure along the lines B-B 'and C-C' of FIG. 1a, respectively. Shown in the sub-picture la are a device layer, a first wiring layer 10, a dielectric layer 12, a second wiring layer 14, and another dielectric layer 16. One or more semiconductor devices (not shown) are arranged in the device layer 2. The other dielectric layer 16 is disposed on the device layer 2 and the surface 18 of the device layer 2 respectively. First wiring layer

564544 1 0 is disposed on the other dielectric layer 16 and its surface opposite to the device layer 2 = surface 2 0 respectively. The dielectric layer 12 is disposed on the first wiring layer 10 and the surface 22 facing away from the other dielectric layer 16, respectively. The second wiring layer 14 is disposed on the dielectric layer 12 and the surface 24 facing away from the first wiring layer 10, respectively. The surface 26 of the second wiring layer 14 facing away from the dielectric layer 12 is also the surface of the semiconductor structure, that is, the surface 26 of the second wiring layer 14 has a connection pad and a solder pad in a region separated from the region shown in the figure. , And an insulation or protective layer is coated in a place separated from the connection pads and the solder pads (not shown in the figure). The first wiring layer 10, the dielectric layer 12, the second wiring layer 14, and the other dielectric layer 16 all include an electrically insulating material, such as an oxide. The wiring wires 3 0, 3 2, 3 4 and 36 are arranged in the first wiring layer 10 and the second wiring layer 14. The channel conductor and the channels 40, 42, 44 are respectively arranged in the dielectric layer 12 and the other dielectric layer 16 and are respectively conductively connected to the two wiring wires 30 arranged in the two different wiring layers 10 and 14. , 32, 34, 36, and will also touch the device layer. · The coil 60 of the spiral coil wire 62 parallel to the surfaces 18, 20, 22, 24, and 26 is arranged in the two wiring layers 10, 14 and the dielectric layers 12 and 16. It can be seen in Fig. 1a that the cut surface of the coil wire 62 is narrow and high, and has low swelling properties in a direction parallel to the layers, and high swelling properties in a direction perpendicular to the layers. The coil 60 and the coil lead-wire 62 respectively extend from the surface 26 of the second wiring layer 14 to another dielectric layer 16 in the vertical direction, and even extend almost to the surface 18 of the device layer 2. Therefore, in the case of FIG. 1, the coil depth is equivalent to the thickness of two dielectric layers having two wiring layers. Contacts 66, 68 -10- 564544

(7) is more configured in ^ 〆, eight galls from the knife, and implement. The coil wire 62 and the contacts 66 and 68 both include a conductive material (filling copper in this embodiment) which fills the spiral trench 70 starting from the surface 26 of the second wiring layer 14, which respectively defines the coil 60 and the coil wire 62 and the shapes of the contacts 6 6 and 6 8. In the transverse direction, the coil 60 will be completely surrounded by a topological ring 80, which, like the coil wire 62 ', extends from the surface 26 of the second wiring layer 14 almost to the surface 18 of the device layer 2. The topological ring 80 is produced for processing, and its purpose is to stabilize the lithography and #etching of the trench 70 which defines the shape of the coil wire 62. For all coil wires 62, the function of the topological ring 80 is to provide a local environment with a completely equal structural thickness, and in the transverse direction, no coil 60 will fall on the semiconductor structure that has been constructed and not yet. In the border zone between construction areas. Instead, it is the topology ring 80 that lies in the lateral boundary region between the constructed region (coil 60) and the unstructured region (around the coil 60). Therefore, the photoresist in the photolithographic etching will not be completely 1 in the position of the topography ring 80, and in the subsequent etching step, it will not reach the expected depth of the coil 60 channel 70. , But will < the same money to depth and different trench depth. Therefore, the shape of the topology ring actually produced during the fabrication of the structure will be larger than the shape shown in the figure, but the two coils 6. The effect of the function is not great. The extension ring must be in the shape of a closed ring, and it can also be open at several positions; When the topology ring does not necessarily achieve the perfect shape of the ditch 70 and the coil 60, when it does not show the shape, it must be reduced. In Figure 11C, the line can be seen. Zichen 62's spiral shape. Advance -11 · 564544

(8) In one step, the contacts 66 and 68 can also be seen, which can be regarded as the laterally extending area of the side of the coil wire 62 in the second wiring layer 14. FIG. 2 shows three cross-sectional views of another embodiment of the present invention. The cut views in these sub-pictures are the same in position and direction as the sub-pictures shown in FIG. 1, except that a tangent line C-C 'is placed along the surface 22 of the first wiring layer 10. Correspondingly, the sub-FIG. 2c does not show the channel conductors 42, 44 in the dielectric layer 12, but shows the wiring wires 30, 32 in the first wiring layer 10. Furthermore, the second surface 20 and the surface 24 of the other dielectric layer 16 are not shown in FIG. 2. This corresponds to a modified example of the semiconductor structure of the present invention, in which another electrical insulating material of the dielectric layer 16 and the electrical insulating material of the first wiring layer 10 are separately formed and applied in a single step. Therefore, at this time, The first wiring layer 10 is defined only by the vertical expansion and arrangement of the wiring wires 30 and 32. The same situation applies to the dielectric layer 12 and the second wiring layer 14 respectively, and to define the second wiring layer 14. The difference between the embodiment shown in FIG. 2 and the embodiment shown in FIG. 1 is that the height and vertical expansion of the coil 60 are low, and the arrangement of the contacts in the coil 60 is different. The trench 70 and the coil wire 62 will extend from the surface 26 of the second wiring layer 14 to the surface 22 of the first wiring layer 10, respectively. Therefore, their height is equal to the sum of the first wiring layer 10 and the second wiring layer 14. In this specific embodiment, the coil 60 is not connected to the contacts in the second wiring layer 14, but is connected to the contacts 92, 94 in the first wiring layer 10. Its effect on the manufacturing method is as follows. The contact 94 connected to the inner side of the coil 60 will be further connected to the channel conductor 96 in another dielectric layer 16, whereby the coil can be connected to the semiconductor device in the lower layer of the device layer 2 (not shown in the figure -12-

564544 display). Unlike the specific embodiment shown in Fig. 2, the coil 60 in Fig. 1 can also be contacted through the contacts in the second wiring layer 14. In this case, the first wiring layer 10 under the coil 60 is not required. This is equivalent to arranging the coil 60 in the other dielectric layer 16, and thus it will be between the device layer 2 and the first wiring layer 10. In FEOL, the method of manufacturing the semiconductor structure of the present invention and the method of manufacturing the semiconductor structure of the present invention is the same as the manufacturing method of the prior art and the method of manufacturing the semiconductor structure of the prior art by φ. In BEOL, the dielectric layers 12, 16 and the wiring layers 10, 14 are generated using the wires 30, 32, 34, 36 and the coil 60. In order to manufacture the specific embodiment shown in FIG. 2, the trench 70 of the coil 60 can be generated by using the same lithography mask in the same lithography etching step, the same etching step, and the same metallization step, thereby facilitating Channel conductors 42, 44 and wire structures 34, 36 may be generated in the dielectric layer 12, respectively. In a better system, trenches 70 and coil wires 62 are produced using different lithographic etching and etching steps, so that the process parameters conform to the geometry of the coil 60. To be clear, a better system is that the implementation of the trench 70 is not controlled by the endpoints like the channels of the channel conductors 42 and 44 but is permanent. Therefore, the coil depth after the coil 60 has been defined And the vertical dimension will not change due to the thickness of the ILD, so the ILD thickness variation caused by the manufacturing process can be compensated, and the cross-section of the coil wire 62 will not be negatively affected. The additional effect of another exposure mask and another etching step can produce adaptive geometry and optimal exposure and etching processes and parameters. These parameters are used for lithographic etching and etching of wiring leads and channel conductors. 13- 564544

(ίο) The parameters are quite different. With separate lithographic etching and etching steps, the quality can be further improved, especially the Q value of the coil. However, instead of using a permanent and controlled etching step, an etch stop layer in the form of a hidden pad in the ILD may be used or the existing metal lines in the underlying wiring layer may be passed through. FIG. 3 is a schematic diagram of a specific embodiment of a method for manufacturing a semiconductor structure according to the present invention. Sub-graphs 3a to 3e represent cross-sectional views of the dielectric layer 12 and the second wiring layer 1 ^ of the semiconductor structure at five different stages in the manufacturing method. However, it may be another dielectric layer 16 and a first wiring layer 10 directly connected to the device layer 2. The insulating layer shown in Fig. 3a is the dielectric layer 12 and the second wiring layer 14 before the subsequent construction. As mentioned above, both have the same electrical insulation material and (preferably) are produced at the same time. After subsequent construction, there will be differences and differences between the dielectric layer 12 and the second wiring layer 14. First, the first photoresist mask can be used to etch the notches 9 8 of the wiring wires 3 4 and 3 6 in FIG. 3 b to the surface 26. After that, the recesses 100 of the channel conductors 40 and 42 are etched by using the second photomask to achieve the state shown in Fig. 3c. The order of the etching process is not interchangeable. Preferably, the two etching steps are performed with different process parameters suitable for different geometries (especially different widths and depths of the notches 98 and 100). Finally, by using another photomask and other process parameters, the trench 70 of the coil wire 62 and the recess 102 of the topological ring 80 can be etched to achieve the state shown in Fig. 3d. Then, the notches 98 and 100 and the trench 70 are simultaneously filled with a conductive material (for example, copper) to simultaneously generate the wiring wires 34, 36, the channel conductors -14- (11) (11) 564544 42, 44 and the coil wires 62. So state. The final second wiring layer 14 shown in FIG. 3e can be achieved. This layer is configured to define the second winding line 34, 36 (30, 32). Therefore, 9 1 4 is in the notch. 9 Swellability. Located in this article! -The vertical expansion in y 8 throughout the ice, a wiring layer 14 and 括 a, called dielectric layer 12. Relative to the layer between the first wiring layer 10, the first-conductor layer 30, 32, and the wiring layer 10 is defined as the connection layer 10 and the device " electrical layer 16 is Defined as a layer between the first clothes 2. As a better guide of the coil 60, the steel is above the last wiring layer, and often used as a prior art. Alternatively, the performance can be improved when compared to that, and it is suitable for being deposited in a narrow and electrically-active material, especially a metal. In this way, Ff can be used in a trench (such as trench 70). I sang with you as an oxide to make eight two # ΑΑ Φ; 丨 electric layer 1 2, 16 and wiring layer 1 ο, 1 4 of the better electrical insulation materials, .. u can also use other electrical Insulating materials, such as lice silicon, are different in Λ = t, ', " to 16. Different from Figures 1 and 2, it is easy to see that the layers of the dielectric layers 12, 16 and the wiring layers 10, 14 are not necessarily parallel, 4 af 卞 仃, and the degree of parallel difference may be The side meetings are different, and all are determined by the manufacturer's watch. Further, one or more layers (especially an additional dielectric layer and a third wiring layer) may be arranged in the surface 26 of the second wiring layer 14, so that the coil 60 is not directly arranged on the semiconductor structure. Below the surface, but separated from it. Different from the schematic diagrams of FIGS. 1 and 2, one or several additional dielectric layers or wiring layers may be arranged between the device layer 2 and another dielectric layer 16. In this case, the 'channel conductor 96' enables the coil 60 to be electrically connected to one of the additional • 15- 564544 invention descriptions on the wiring layer in the wiring layer on the continuation sheet (12). The number of windings of the coil 60 may be more or less than the schematic diagrams in FIGS. 1 and 2. Further, the coil 60 may be arranged only in the dielectric layer 12 or may extend to the wiring layers 10, 14 next to the dielectric layer 12 as in the drawings. On this, the coil 60 may extend into or exceed the other dielectric layer 16 or may be disposed only in the other dielectric layer 16. The difference from the schematic diagram of FIG. 2 is that if the coil does not fully extend to the surface 22 of the first wiring layer 10 but is spaced apart from it, the wiring in the first wiring layer 10 can be freely designed.

I wire, thereby further reducing the effective space condition limit of the coil 60. The contacts 6 6, 6, 8, 9, 2 and 9 4 can be different in shape and size from the diagrams in Figures 1 and 2 and need not be integrated with the coil wires. Description of the drawing representative symbols 2 Device layer 10 First wiring layer 12 Dielectric layer 14 Second wiring layer 16 Another dielectric layer 18 Surface of device layer 2 20 Surface of another dielectric layer 1 6 First wiring layer 1 0 surface 24 surface of the dielectric layer 12 26 surface of the second wiring layer 14 30 wiring conductor 32 wiring conductor -16- 564544 (13) 34 wiring guide 36 wiring guide 40 channel guide 42 channel guide 44 channel guide 60 coil 62 Coil guide 66 contact 68 contact 70 ditch 80 top ring 92 contact 94 contact 96 channel guide 98 wiring guide 100 channel guide 102 top ring body notch body 40, 42 notch 80 notch line body body line invention description continued page

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Claims (1)

564544 Patent application scope 1. A semiconductor structure comprising: a device layer (2) of a semiconductor material; a dielectric layer (12) disposed on the device layer (2); a configuration on the dielectric A wiring layer (14) above the layer (12); and a coil (60), the wire section of which can extend to the dielectric layer (12) and the wiring layer (14) or another wiring layer (10), And connections (66, 68; 92, 94) in the wiring layer (14). _ 2. For the semiconductor structure according to item 1 of the patent application scope, wherein the other wiring layer (10) is disposed between the device layer (2) and the dielectric layer (12). 3. For example, the semiconductor structure of the first patent application scope, wherein the wiring layer (14) is the only wiring layer or a wiring layer among a plurality of wiring layers, which is closest to the device layer (2). 4. For example, the semiconductor structure of the scope of patent application, wherein the wiring layer (14) includes an insulating layer, in which a wiring wire (34, 36) is arranged. 5. If the semiconductor structure according to item 4 of the patent application, the dielectric layer (1 and the insulating layer have the same dielectric material. 6. If the semiconductor structure according to item 4, the coil (60) And the wiring wires (30, 32, 34, 36) have the same conductive material. 7. If the semiconductor structure of the first scope of the patent application, the wire section of the coil (60) will further extend # to the other wiring Among the layers (10). 8. If the semiconductor structure of the first patent application scope has a further dielectric layer (16), the coil (60) will be further arranged in the other 564544 In the dielectric layer (16). 9. The semiconductor structure of claim 6 in which the conductive material includes copper. 10 · —A method for producing a semiconductor structure, comprising: providing a device layer in the semiconductor structure; applying a dielectric layer (12); generating a wiring layer (14); using a recess of the coil (60) ( 70) Constructing the dielectric layer (12) and the wiring layer, wherein the wire section of the coil defined by the notch will extend into the dielectric layer (12) and the wiring layer (14) or another Wiring layer (10); introducing a conductive material into the notch (70); and letting the coil (60) and a contact (66, 68) in the wiring layer (10) or in another wiring layer (14) 92, 94). 11. The method of claim 10, wherein when the conductive material is introduced into the recess (70), contact can be made by contacting the contacts (92, 94) in the wiring layer (10). 12. The method as claimed in item 10 of the patent application scope, wherein generating the wiring layer (ΐ4) · includes: applying an insulating layer; using another recess of the wiring wire (34, 36) to construct the insulating layer, and ... A conductive material is introduced into the other recess. 13. The method of claim 12 in which the dielectric layer (12) and the insulating layer have the same material, and the conductor material is introduced simultaneously 564544 the recess (70) and the conductive material is introduced into the other recess. 14. The method of claim 12 in which the notch (70) and the other notch are connected. 15. The method of claim 12 in which the depth of the notch (70) is greater than the depth of the other notch. 16. The method of claim 10, wherein the conductive material includes copper. 17. The method of claim 10, wherein when the dielectric layer (12) is constructed, the annular portion (80) of the recess (70) surrounding the coil (60) is formed completely or partially. Another notch (102).