561692 A7 __— _B7 ___ 五、發明說明（/ ) 發明背景 發明之領域 本發明大致上係關於電子電路。本發明尤其係關於用 於減少與用於閂鎖器爲基礎之電路的時脈訊號相關之雜訊 的方法。 相關先前技藝之描述 於所有以微處理器爲基礎之包含電腦之系統中，該時 脈電路係爲一個重要的元件。該時脈電路係產生一個同步 及控制該系統之每一個操作之時序的穩定的時序脈波流之 時脈訊號。第1圖係圖示一個理想的先前技藝之時脈訊號 的圖形1 0。一個完整的時脈週期1 2係包含一個上升或 者前緣1 4及一個下降或者後緣1 6。該些前緣1 4及後 緣1 6係界定該訊號之低準位及高準位之間之轉變。 第2圖係顯示一個先前技藝之本地時脈訊號分配系統 之方塊圖。該時脈訊號3 0 a係輸入至一個作爲緩衝該時 脈訊號之時脈前置器3 2。由該時脈前置器3 2，該時脈 訊號3 Ob係被輸入至一個邊緣觸發閂鎖器3 4，該邊緣 觸發閂鎖器3 4係用以觸發該閂鎖器。一個閂鎖器係一個 常使用於積體電路之一個記憶元件。其係根據一個時脈訊 號而起始化其功能。閂鎖器係取得輸入資料且於整個時脈 爲高之狀態下分配輸出資料。大部分的資料傾向於等待該 閂鎖器直到該時脈爲高時，因而大部分之閂鎖器係於該時 . 脈之上升緣處切換。閂鎖器亦係被實施成於時脈低之情況 下工作’且因而傾向於在該時脈之下降緣處切換。該兩種 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ---------訂---------^^1. A7 561692 B7 五、發明說明（i ) 形式之閂鎖器係常被使用，以利用該時脈之兩種相位以用 於計算。 第3圖係顯示一個示於第2圖之該先前技藝的本地時 脈訊號分配系統之數位邏輯示意圖。該時脈訊號3 0 a係 被輸入至該時脈前置器3 2。該時脈前置器3 2係包含一 個反及閘3 6及一個反相器3 8 a。一旦於該時脈前置器3 2中，該時脈訊號3 0 a係爲至該反及閘3 6之輸入之一 。另一個反及閘輸入端4 2輸入係爲一個高準位之訊號， 使得該閘3 6係僅反相該時脈訊號3 0 a之値。假如有需 要的話，該反及閘輸入端4 2係被切換成低準位，以關閉 該時脈前置器3 2。其次，該訊號3 0 a係傳輸通過反相 該訊號回其原始値之反相器3 8a。然後，該時脈訊號3 0 b係由該時脈前置器3 2傳輸至該閂鎖器3 4。一旦於該 閂鎖器3 4中，該訊號3 Ob係被分割成爲兩個路徑。該 第一路徑係傳送通過一個反相器3 8b，且該第二路徑係傳 送通過兩個連續的反相器3 8 c及3 8 d。每一個路徑係饋 入至個別的控制電晶體4 0a及4 Ob，該個別的控制電晶 體4 〇a及4 Ob係控制該閂鎖器3 4之該DATA_IN4 4 及 DATA_0UT4 6 路徑。 於該系統電源柵極上之時脈引起之電源供應雜訊（下 稱“時脈雜訊”）問題通常係由用於時脈訊號分配之大量 電流所引起。此電流係由被該時脈訊號所控制之該切換電 晶體而來。由於這些電晶體切換狀態，該電流雜訊係由於 該切換電晶體之電流需求或者“電流汲取”而附著於該電 4 紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------'----------訂---------^9— (請先閱讀背面之注意事項再填寫本頁) 561692 A7 ____B7____ 五、發明說明（' ) 源柵極上。這些高的電流需求係由於電壓下降及固有的系 統電感（Ldi/dt)而導致該系統電壓供應上之雜訊。一個時 脈訊號分配電路係於一個短的時間內使用一個相當大量的 電流，因爲該尖峰波於每一個時脈週期內產生兩次：一次 係於該前緣之電流汲取之下而另一次係於該訊號之後緣之 電流汲取之下。此係使該雜訊於一非常高頻之下（該時脈 頻率之兩倍）。假如該電源係太低，此雜訊能夠導致迷失 之時序，或者假如該電源係太高，則此雜訊能夠導致元件 失效。該雜訊甚至能夠“離開該晶片”而影響該系統之其 他元件。 第4圖係顯示於一個以閂鎖器爲基礎之電路之時脈週 期期間之電流拉引圖形。該電路能夠使用上升緣閂鎖器及 下降緣閂鎖器。該値“Γ 3 5係表示一個電流拉引之全部 値。該値“3/41” 3 7係表示一個電流拉引之全部値之 百分之7 5，而値“1/21” 3 9係表示一個電流拉引之 全部値之百分之5 0。該圖形之該第一電流汲取4 1係代 表由一個時脈週期（於時脈週期等於0時）之該前緣所造 成之電流汲取。該圖形之該第二電流汲取4 3係代表由一 個時脈週期（於時脈週期等於t/2時）之該後緣所造成之 電流汲取。如圖所示，該第一電流汲取4 1係爲電流拉引 之全部値“Γ 。而該第二電流汲取4 3係等於該第一電流 汲取4 1之値。此外，當該値係高於“1/2 Γ 3 9時， 該第一電流汲取4 1及該第二電流汲取4 3係具有一個期 間（“d”）4 5。 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------------- — 訂--------- (請先閱讀背面之注意事項再填寫本頁) A7 561692 ___B7____ 五、發明說明（f ) 減少雜訊之一個共同的技術係爲增加額外的電力至該 柵極。該電力係於感測出由於雜訊造成之電壓降時被加入 。然而，如此之技術係僅能回應於在一比時脈雜計低很多 之頻率下的雜訊，且僅能對於一特定臨限雜訊作出回應。 因此，需要一個對於在與該時脈雜訊本身同步化之頻率下 之時脈雜訊產生一回應之技術。 發明槪要 於某些觀點，本發明係關於用於減少閂鎖器爲基礎之 電路的時脈訊號之雜訊之方法及裝置，該方法係包含下列 步驟：於接收一個第一訊號時儲存一個電荷；及於接收一 個第二訊號時，將該電荷傾卸至一個系統電源柵極，其中 ，該儲存該電荷及傾卸該電荷係以至少一個閂鎖器之操作 而同步化。 根據另一個觀點，本發明係關於用於減少閂鎖器爲基 礎之電路的時脈訊號之雜訊之方法及裝置，該方法係包含 下列步驟：於接收一個第一訊號時儲存一個電荷之步驟； 於接收一個第二訊號時將該電荷傾卸至一個系統電源柵極 之步驟；及以至少一個閂鎖器之操作而同步化該儲存該電 荷及該傾卸該電荷之步驟。 由下列敘述及後附申請專利範圍，本發明之其他觀點 及優點將變得明白。 圖式簡單說明 第1圖係顯示一個理想的時脈訊號之圖形； 第2圖係顯示一個先前技藝之用於一閂鎖器之時脈電 6 木紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ------- —訂--------- 561692 A7 _B7_ 五、發明說明（t ) 路之一個方塊圖； 第3圖係顯示一個先前技藝之用於一閂鎖器之時脈電 路之一個數位邏輯示意圖； 第4圖係顯示於一個閂鎖器爲基礎之電路之一個時脈 循環週期期間電流汲取之圖； 第5圖係顯示本發明之一個實施例之一個方塊圖； 第6圖係顯示本發明之一個實施例之一個數位邏輯示 意圖； 第7a圖係顯示於一充電期間示於第6圖之該數位邏 輯示意圖之一部分的一個等效電路； 第7b圖係顯示於一放電期間示於第6圖之該數位邏 輯示意圖之一部分的一個等效電路； 第8圖係顯示本發明之一個替代實施例之一個數位邏 輯示意圖； 第9圖係顯示本發明之一個替代實施例之一個數位邏 輯示意圖； 第10圖係顯示本發明之一個替代實施例之一個數位 邏輯不意圖； 第1 1圖係顯示於示於第6至1 0圖之本發明之實施 例之一個時脈循環週期期間電流汲取之圖。 〔元件符號說明〕 10 時脈訊號的圖形 12 時脈週期 14 上升或者前緣 7 (請先閲讀背面之注意事項再填寫本頁)561692 A7 __— _B7 ___ V. Description of the Invention (/) Background of the Invention Field of the Invention The present invention relates generally to electronic circuits. The invention relates in particular to a method for reducing noise associated with clock signals used in latch-based circuits. Description of Related Prior Art The clock circuit is an important element in all microprocessor-based systems including computers. The clock circuit generates a clock signal that synchronizes and controls a stable timing pulse wave flow of each operation of the system. Figure 1 is a graph 10 of an ideal prior art clock signal. A complete clock cycle 12 consists of a rising or leading edge 14 and a falling or trailing edge 16. The leading edges 14 and trailing edges 16 define the transition between the low level and the high level of the signal. Figure 2 is a block diagram showing a local clock signal distribution system of the prior art. The clock signal 3 0 a is input to a clock pre-processor 3 2 as a buffer for the clock signal. From the clock pre-processor 32, the clock signal 3 Ob is input to an edge-triggered latch 34, and the edge-triggered latch 34 is used to trigger the latch. A latch is a memory element commonly used in integrated circuits. It initiates its function based on a clock signal. The latches take input data and distribute output data while the clock is high. Most data tend to wait for the latch until the clock is high, so most latches switch at the rising edge of the clock. The latch is also implemented to work with a low clock 'and therefore tends to switch at the falling edge of that clock. The two 3 paper sizes are applicable to Chinese National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the precautions on the back before filling this page) --------- Order ---- ----- ^^ 1. A7 561692 B7 V. Description of the invention (i) The latch is often used to use the two phases of the clock for calculation. Figure 3 is a digital logic diagram of the local clock signal distribution system of the prior art shown in Figure 2. The clock signal 3 0 a is input to the clock pre-processor 32. The clock preamplifier 3 2 series includes a reverse AND gate 36 and an inverter 3 8 a. Once in the clock pre-processor 32, the clock signal 30a is one of the inputs to the inverse gate 36. The other anti-gate input terminal 4 2 input is a high-level signal, so that the gate 36 can only invert the clock signal 30 a. If necessary, the inverse gate input terminal 4 2 is switched to a low level to turn off the clock pre-processor 3 2. Secondly, the signal 30a is transmitted through an inverter 38a which inverts the signal back to its original frame. Then, the clock signal 30b is transmitted from the clock pre-processor 32 to the latch 34. Once in the latch 34, the signal 3 Ob is divided into two paths. The first path is passed through one inverter 3 8b, and the second path is passed through two consecutive inverters 3 8 c and 3 8 d. Each path is fed to an individual control transistor 4 0a and 4 Ob, and the individual control transistors 4 0a and 4 Ob control the DATA_IN4 4 and DATA_0UT4 6 paths of the latch 34. The problem of power supply noise (hereinafter referred to as “clock noise”) caused by the clock on the power grid of the system is usually caused by a large amount of current used for clock signal distribution. This current comes from the switching transistor controlled by the clock signal. Due to the switching state of these transistors, the current noise is attached to the transistor due to the current demand or "current draw" of the switching transistor. 4 The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)- ---------'---------- Order --------- ^ 9— (Please read the notes on the back before filling this page) 561692 A7 ____B7____ Five , Invention description (') on the source gate. These high current requirements are due to voltage drops and inherent system inductance (Ldi / dt), which cause noise on the system's voltage supply. A clock signal distribution circuit uses a considerable amount of current in a short period of time, because the spike wave is generated twice in each clock cycle: once under the current draw of the leading edge and another time The current is drawn below the trailing edge of the signal. This keeps the noise below a very high frequency (twice the clock frequency). If the power supply is too low, this noise can cause lost timing, or if the power supply is too high, this noise can cause component failure. The noise can even "leave the chip" and affect other components of the system. Figure 4 shows a current draw pattern during a clock cycle of a latch-based circuit. This circuit can use rising edge latches and falling edge latches. The "Γ 3 5" represents the total current drawn by a current. The "3/41" 3 7 represents 75% of the total current drawn by the current, and the "1/21" 3 9 Represents 50% of the total current drawn by a current. The first current draw in the figure 4 1 represents the current caused by the leading edge of a clock cycle (when the clock cycle is equal to 0). Sinking. The second current sinking of the figure 4 3 represents the current sinking caused by the trailing edge of a clock cycle (when the clock cycle is equal to t / 2). As shown in the figure, the first current sinking 4 1 is the total 値 "Γ of the current pull. The second current draw 4 3 is equal to the first current draw 4 1. In addition, when the series is higher than "1/2 Γ 3 9", the first current draw 4 1 and the second current draw 4 3 have a period ("d") 4 5. 5 This paper scale applies to China National Standard (CNS) A4 Specification (210 X 297 mm) ----------------- — Order --------- (Please read the notes on the back first (Fill in this page again) A7 561692 ___B7____ 5. Description of the Invention (f) A common technique for reducing noise is to add extra power to the grid. This power is detected when a voltage drop due to noise is sensed. Added. However, such a technology can only respond to noise at a frequency much lower than the clock noise meter, and can only respond to a specific threshold noise. Therefore, a need for Pulse noise itself is a technique for generating a response to clock noise at a frequency that is synchronized. Invention. In some aspects, the present invention relates to reducing noise in clock signals for latch-based circuits. A method and device, the method comprising the steps of: storing a charge when receiving a first signal; and receiving a charge when receiving a first signal; At the second signal, the charge is dumped to a system power grid, wherein the storage of the charge and the dumping of the charge are synchronized by the operation of at least one latch. According to another aspect, the present invention is Regarding a method and a device for reducing noise of a clock signal of a latch-based circuit, the method includes the steps of: storing a charge when receiving a first signal; and receiving a second signal The step of dumping the charge to a system power grid; and synchronizing the step of storing the charge and the dumping of the charge by the operation of at least one latch. From the following description and the appended patent application scope, this Other aspects and advantages of the invention will become clear. Brief description of the drawing. Figure 1 shows a graph of an ideal clock signal; Figure 2 shows a prior art clock circuit for a latch 6 Paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) ------- --Order --------- 561692 A7 _B7_ V. Hair A block diagram illustrating the (t) path; Figure 3 shows a digital logic diagram of a prior art clock circuit for a latch; Figure 4 shows a latch-based circuit Diagram of current draw during a clock cycle; Figure 5 is a block diagram showing an embodiment of the present invention; Figure 6 is a digital logic diagram showing an embodiment of the present invention; Figure 7a is shown at An equivalent circuit shown in a part of the digital logic diagram in FIG. 6 during a charging period; FIG. 7b shows an equivalent circuit shown in a part of the digital logic schematic diagram in FIG. 6 during a discharge period; Figure 9 shows a digital logic diagram of an alternative embodiment of the invention; Figure 9 shows a digital logic diagram of an alternative embodiment of the invention; Figure 10 shows a digital logic diagram of an alternative embodiment of the invention Not intended; Figure 11 is a diagram showing current draw during a clock cycle of the embodiment of the invention shown in Figures 6 to 10. [Explanation of component symbols] Graphic of 10 clock signal 12 Clock cycle 14 Rise or leading edge 7 (Please read the precautions on the back before filling this page)
-· ϋ ·ϋ I ϋ n n^-(eJ· n n n ϋ n ϋ ϋ I 衣紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 3 0a 3 0b 3 2 3 4 4 8 5 0 5 1 5 0a 5 0b 5 0c 5 〇d 5 〇e 5 2 5 3a 5 3b 5 4 5 5 5 6 5 7a 5 7b 5 7c 5 8 5 9 561692 A7 B7 五、發明說明（4 ) 下降或者後緣 時脈訊號 時脈訊號 時脈前置器 邊緣觸發閂鎖器 時脈雜訊減少電路 電荷 反及閘 第一反相器 第二反相器 第三反相器 反相器 反相器 充電訊號 第四反相器 第五反相器 傾卸訊號 反或閘 充電控制電晶體 第四反相器 第五反相器 第六反相器 傾卸控制電晶體 反或閘 ----------1 --------訂--------- (請先閱讀背面之注意事項再填寫本頁) 木紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 561692 A7 B7 五、發明說明（1 ) 6 0 連接電晶體 6 2a 充電電容器 6 2b 充電電容器 6 3 時脈雜訊減少電路 6 9 雜訊減少電路 7 1 時脈雜訊減少電路 7 3 反及閘 較佳實施例詳細說明 本發明之範例性實施例將參照後附圖式而予以敘述° 圖式中類似之元件係以相同的參考符號予以顯示。 第5圖係根據本發明之一個實施例之具有一個加入的 時脈雜訊減少電路之本地時脈訊號分配系統之方塊圖（類 似於示於第2圖之系統）。該時脈訊號30a係輸入至一 個作爲緩衝該時脈訊號之時脈前置器3 2。由該時脈前置 器3 2，該時脈訊號3 〇b係被輸入至一個邊緣觸發問鎖 器3 4，該邊緣觸發閂鎖器3 4係用以觸發該閂鎖器。於 本發明之實施例中，該時脈訊號3 〇a係於該時脈訊號3 0 a被輸入至該時脈前置器3 2之前係被分割。該時脈訊 號3 〇a之平行的分割訊號係被輸入至一個時脈雜訊減少 電路4 8。於感測該時脈訊號3 0 a之上升緣時，該時脈 雜訊減少電路4 8將傾卸電荷5 0至該系統之電源柵極上 。該被傾卸之電荷5 0將減少與該時脈週期相關之該電流 雜訊尖峰。 第6圖係顯示根據本發明之一個實施例之一個時脈雜 9 (請先閲讀背面之注意事項再填寫本頁) ---1丨 —丨訂·--------· 本、纸張尺度適用中國國家標準（CNS)A4規格（210 X 297 3 " 561692 A7 ____B7___ 五、發明說明（e ) 訊減少電路4 8之一個邏輯示意圖。特別是，第6圖係顯 示於該時脈訊號之該上升緣上被觸發之一個時脈雜訊減少 電路之一個實施例。一旦於該雜訊減少電路4 8之內，該 時脈訊號3 〇a係被分割成爲兩個分離的分支。該第一分 支係直接輸入至一個反及聞5 1。另一個分支係輸入至一 個第一反相器5 0 a，該第一反相器5 0 a係僅反相該訊號 値。接著，該訊號係被輸入至一個第二反相器5 0 b，該第 二反相器5 Ob係反相該訊號而回到其原始値。最後，該 訊號係被輸入至一個第三反相器5 0 c，該第三反相器5 0 c係再次反相該訊號。然後，該第三反相器5 0 c之輸出係 輸入至該反及閘5 1之該第二輸入端。 該反及閘5 1之該輸出係輸入至一個第四反相器5 3a 。該第四反相器5 3 a係反相該訊號値。該訊號5 2 (下 文稱爲“充電訊號”）係被分割成爲兩個分支。該充電訊 號5 2之一個分支係被輸入至一個第五反相器5 3b，該第 五反相器5 3 b係再次反相該訊號。然後，該第五反相器 5 3b之該輸出（下文稱爲“傾卸訊號”）係沿著該充電 訊號5 2而被輸入至三個電路控制電晶體：一個充電控制 電晶體5 6 ; —個傾卸控制電晶體5 8 ;及一個連接電晶 體6 0。重要的是應注意··該充電訊號5 2及該傾卸訊號 5 4將具有相反的値，因爲該電充電訊號係通過該第五反 相器5 3b。 該充電控制電晶體5 6係透過一個充電電容器6 2a 而連接該系統電源（Vdd)及該系統接地（Vss)。該充電 10 私紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） ----------'—--------訂--------- (請先閱讀背面之注意事項再填寫本頁) A7 561692 ^-21- 五、發明說明（？） 電容器6 2 a係位於該充電控制電晶體5 6及該Vss之間 。該充電控制電晶體5 6係以該充電訊號5 2控制（亦即 導通或關閉）。該充電控制電晶體5 6係爲一個“P型” 電晶體’其思味當該充電訊號5 2係爲低準位時，該些電 晶體係爲“導通”（允許電流通過）。反之，當該充電訊 號5 2係爲高時，該充電控制電晶體5 6係爲“關閉”。 該傾卸控制電晶體5 8亦透過一個充電電容器6 2 b 而連接該系統電源（Vdd)及該系統接地（Vss)。該充電 電容器6 2 b係位於該傾卸控制電晶體5 8及該Vdd之間 。該傾卸控制電晶體5 8係以該傾卸訊號5 4控制（亦即 導通或關閉）。該傾卸控制電晶體5 8係爲一個“N型” 電晶體，其意味當該傾卸訊號5 4係爲高準位時該些電晶 體係爲“導通”（允許電流通過）。反之，當該傾卸訊號 5 4係爲低準位時，該傾卸控制電晶體5 8係爲“關閉” (不允許電流通過）。 最後，該連接電晶體6 0係連接該電路之兩側。特別 是，該連接電晶體6 0係連接於該控制電晶體5 6，5 8 及該充電電容器6 2a，6 2b之側邊之間。該連接電晶體 6 0係爲一個“P型”電晶體，其意味當該傾卸訊號5 4 係爲低準位時，該電晶體係爲“導通”（允許電流通過） 。反之’當該傾卸訊號5 4係爲高準位時，該連接電晶體 6 0係爲“關閉”（不允許電流通過）。 於正常操作之下，該控制電路係具有兩個操作狀態： 一個充電狀態及一個傾卸狀態。 11 衣紙張尺度適用中國國家標準（CNTS)A4規格（210 X 297公釐) 一 " ------.-------------訂-------- (請先閱讀背面之注意事項再填寫本頁) 561692 A7 B7 -- 五、發明說明（P ) 於每一個狀態下，該電路係被一個“主動低（active low) ”訊號所致動。此意味當該個別的控制訊號（充電訊 號5 2或者傾卸訊號5 4 )係爲低準位而非高準位時，該 個別的控制訊號（充電訊號5 2或者傾卸訊號5 4 )係起 始化其個別的狀態。明確言之，於該充電狀態下，該充電 訊號5 2將爲低準位且該傾卸訊號5 4將爲高準位。因此 ，當該連接電晶體6 0係爲“關閉”時，該充電控制電晶 體56及該傾卸控制電晶體58皆爲“導通”。此係允許 該充電電容器6 2 a及6 2 b兩者係被充電以準備該傾卸狀 態。於該傾卸狀態期間，該充電訊號5 2將爲高準位，而 該傾卸訊號5 4將爲低準位。因此，當該連接電晶體6 〇 係爲“導通”時，該充電控制電晶體5 6及該傾卸控制電 晶體5 8皆爲“關閉”。此係允許該充電電容器6 2 a及 6 2b兩者係皆傾卸其電荷於該電源柵極之下，且因而減 少該尖峰電流汲取。 於比較第6圖及第3圖之下，重要的是應注意··該時 脈前置器3 2及閂鎖器3 4係以該時脈雜訊減少電路4 8 同步化。該時脈則置窃3 2及問鎖器3 4係具有沿著該反 及閘3 6之三個個別的反相器層3 8a，38b，38c, 3 8d，而該時脈雜訊減少電路4 8係具有一個總計Θ個反相 器5CU—c，53a—c及一個反及閘5丄。第6圖之元件 係被比例化’使得該充電控制電晶體5 6，該傾卸控制電 晶體5 8及該連接電晶體6 0係如同第3圖之該個別的控 制電晶體4 0 a及4 0 b，於同一時間被切換。此係導致當 12 木紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚) '~ ——·——-Lf--------tr---------p (請先閱讀背面之注意事項再填寫本頁) 561692 A7 五、發明說明（Π ) 第3圖中之DATA—IN首先被DATA—0UT4 6所驅動時 ，該電荷傾卸係產生。 第7 a及7 b圖係分別顯示於一個充電狀態及一個放電 狀態期間示於第6圖之該數位邏輯示意圖之一部分之該等 效電路。於每一個圖中，該“關閉”電晶體係已經被刪除 ，而該“導通”電晶體係已經被一個標準電路連結所取代 。明確言之，第7a圖係顯示於該充電狀態期間之一個等 效電路。其顯示並聯於Vdd及Vss之間之兩個電容器6 2 a及6 2b。第7b圖係顯示於該效電狀態期間之一個等效 電路。其顯示串聯於Vdd及Vss之間之兩個電容器6 2 a 及 6 2 b。 當該電容器6 2a及6 2b於充電狀態期間係並聯時， 該電容器6 2a及6 2b之每一個係儲存一個電荷値“Q，， ，其中，Q=(電容値“C，，）*Vdd。因此，由該電路所儲 存之總電荷係爲2 Q。當該電容器6 2 a及6 2 b於該傾卸 期間係串聯時，該電容器6 2a及6 2b之每一個係具等於 Vdd/ 2之電壓。因此，該電容器6 2 a及6 2 b之每一個 對於一個電路之總計爲q之儲存電荷將僅儲存q/2。該 超過之電荷將被傾卸至該電源柵極。 示於第6圖之該電路4 8係於該時脈訊號3 Oa之該 上升緣處觸發該傾卸狀態。然而，該電路能夠輕易地被配 置成爲於該時脈訊號3 〇a之該下降緣處觸發該傾卸狀態 。第8圖係顯示根據一個下降緣觸發電路之一個實施例之 一個時脈雜訊減少電路6 3之一個邏輯示意圖。該雜訊減 ------·——— 會--------tr---------$r (請先閱讀背面之注意事項再填寫本頁) 家標準（CNS)A4 g(21〇 χ 297：^--- 561692 A7 ____B7______ 五、發明說明（A ) 少電路6 3係類似於示於第6圖之該上升緣觸發電路4 8 ’其係在於其係具有於該電路6 3內之分割成爲兩個分離 的分支之時脈訊號3 〇a之相同結構。然而，該兩個分支 係皆輸入至一個反或閘5 5。該第一分支係以該時脈訊號 3 0 a直接輸入至該閘5 5。該第二分支係於透過該時脈 訊號3 〇a而經由三個序列之反相器5 〇a，5 0，5 〇c而 輸入至該閘5 5。 該反或閘5 5之輸出係透過一個第四反相器5 7a及 一個第五反相器5 7b。該訊號5 2 (此後稱爲“充電訊號 ”）然後係被分割成爲兩個分支。該充電訊號52之一個 分支係被輸入至一個再次反相該訊號之第六反相器5 7 c。 然後，該第六反相器5 7c之該輸出訊號（下文稱爲“傾 卸訊號”）及該充電訊號52係被輸入至三個電路控制電 晶體：一個充電控制電晶體5 6 ; —個傾卸控制電晶體5 8 ;及一個連接電晶體6 0。該充電控制電晶體5 6，該 傾卸控制電晶體5 8及該連接電晶體6 0之每一個係對於 Vdd，Vss及電容器6 2 a，6 2b以一類似於第6圖之該 上升緣電路4 8之結構配置。重要的是應注意··該充電訊 號5 2及該傾卸訊號5 4係具有相反之値，這是因爲該充 電訊號係通過該第六反相器5 7 c。 該電路6 3將以類似於示於及敘述於第6，7a及7b 之該電路4 8而實施。然而，示於第6圖及第8圖之該些 電路之間之主要差異係在於該傾卸訊號5 4及該充電訊號 5 2。如上文所述，用於示於第6圖之該電路之該傾卸訊 14 (請先閱讀背面之注意事項再填寫本頁) n ϋ ϋ n ϋ 1^^· d ϋ> I l ί l · 幸、紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 561692 A7 ______B7 _____ 五、發明說明（π ) 號係於該時脈訊號3 Oa之上升緣期間係變成“低準位” ，且因而於該上升緣起始該傾卸狀態。相對之下’用於示 於第8圖之該電路之該傾卸訊號係於該時脈訊號3 CU之 下降緣期間係變成“低準位”，且因而於該下降緣起始該 傾卸狀態。如上文所敘，於每一個電路中，該個別的充電 訊號5 2係其個別的傾卸訊號5 4之反相。如此一來’該 充電狀態係被起始化，以於該時脈訊號之一個緣傾卸，且 於其後之一短期間再次充電。該狀態將於該其他時脈轉換 期間不作任何動作。該些電路之兩種形式之效能之其他方 面係基本上相同。 第9圖係顯示根據一個上升緣觸發電路之替代實施例 之一個時脈雜訊減少電路6 9之邏輯示意圖。該雜訊減少 電路6 9具有與示於第6圖之該上升緣觸發電路4 8相同 之效能。該雜訊減少電路6 9類似於示於第6圖之該上升 緣觸發電路4 8係在於其係具有於該電路6 9內之分割成 爲兩個分離的分支之時脈訊號3 0 a之相同結構。然而， 該兩個分支係皆輸入至一個反或閘5 9。該第一分支係於 傳輸該時脈訊號3 Oa通過四個序列之反相器5 〇a，5 〇b， 5 0 c及5 0 d之後被輸入至該閘5 9。該第二分支係於被 輸入至該閘5 9之前傳輸該時脈訊號3 〇a通過一個第五 反相器5 〇e。 該反或閘5 9之輸出係被分割成爲兩個分支。該輸出 5 2 (下文稱爲充電訊號）之一個分支係被輸入至一個再 次反相該訊號之第六反相器6 1。然後，該第六反相器6 15 (請先閱讀背面之注意事項再填寫本頁)-· Ϋ · ϋ I ϋ nn ^-(eJ · nnn ϋ n ϋ ϋ I The size of the paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) 3 0a 3 0b 3 2 3 4 4 8 5 0 5 1 5 0a 5 0b 5 0c 5 〇d 5 〇e 5 2 5 3a 5 3b 5 4 5 5 5 6 5 7a 5 7b 5 7c 5 8 5 9 561692 A7 B7 V. Description of the invention (4) Falling or trailing edge Clock signal Clock signal Clock front edge Edge trigger latch Clock noise reduction circuit charge reversal first inverter second inverter third inverter inverter inverter charging signal Four inverters fifth inverter dump signal reverse OR gate charge control transistor fourth inverter fifth inverter sixth inverter dump inverter control transistor reverse OR gate -------- --1 -------- Order --------- (Please read the notes on the back before filling in this page) Wood paper size is applicable to China National Standard (CNS) A4 (210 X 297) (Mm) 561692 A7 B7 V. Description of the invention (1) 6 0 Connected transistor 6 2a Charge capacitor 6 2b Charge capacitor 6 3 Clock noise reduction circuit 6 9 Noise reduction circuit 7 1 Clock noise reduction circuit 7 3 Reverse gate is better Exemplary embodiments of the present invention will be described in detail with reference to the following drawings. Similar elements in the drawings are shown with the same reference signs. Fig. 5 shows an embodiment according to the present invention. The block diagram of the local clock signal distribution system of the added clock noise reduction circuit (similar to the system shown in Figure 2). The clock signal 30a is input to a clock front to buffer the clock signal Device 3. 2. The clock pre-processor 32, the clock signal 3 0b is input to an edge-triggered interlock 34, the edge-triggered latch 34 is used to trigger the latch. In the embodiment of the present invention, the clock signal 30a is divided before the clock signal 30a is input to the clock pre-processor 32. The clock signal 30a is parallel The divided signal is input to a clock noise reduction circuit 48. When the rising edge of the clock signal 30a is sensed, the clock noise reduction circuit 48 will dump the charge 50 to the system On the power grid. The dumped charge 50 will reduce the Current noise spike. Figure 6 shows a clock noise 9 according to an embodiment of the present invention (please read the precautions on the back before filling this page) --- 1 丨 — 丨 Order · ----- --- · The dimensions of this paper are in accordance with China National Standard (CNS) A4 (210 X 297 3 " 561692 A7 ____B7___) 5. Explanation of the invention (e) A logical diagram of the reduction circuit 48. In particular, Fig. 6 shows an embodiment of a clock noise reduction circuit triggered on the rising edge of the clock signal. Once within the noise reduction circuit 48, the clock signal 30a is split into two separate branches. The first branch is directly input to a counter-infection 51. The other branch is input to a first inverter 50a. The first inverter 50a only inverts the signal 値. The signal is then input to a second inverter 50b, and the second inverter 5Ob inverts the signal and returns to its original frame. Finally, the signal is input to a third inverter 50 c, which inverts the signal again. Then, the output of the third inverter 50 c is input to the second input terminal of the inverse AND gate 51. The output of the inverting gate 51 is input to a fourth inverter 5 3a. The fourth inverter 5 3 a inverts the signal 値. The signal 5 2 (hereinafter referred to as "charging signal") is divided into two branches. A branch of the charging signal 52 is input to a fifth inverter 5 3b, and the fifth inverter 5 3 b inverts the signal again. Then, the output of the fifth inverter 5 3b (hereinafter referred to as a "dump signal") is input to three circuit control transistors along the charging signal 5 2: a charge control transistor 5 6; A dump control transistor 5 8; and a connection transistor 60. It is important to note that the charging signal 5 2 and the dumping signal 5 4 will have opposite chirps because the electric charging signal passes through the fifth inverter 5 3b. The charging control transistor 5 6 is connected to the system power source (Vdd) and the system ground (Vss) through a charging capacitor 6 2a. The standard of the charging 10 private paper is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm) ----------'---------- Order ------ --- (Please read the precautions on the back before filling this page) A7 561692 ^ -21- 5. Description of the Invention (?) The capacitor 6 2 a is located between the charge control transistor 56 and the Vss. The charging control transistor 5 6 is controlled by the charging signal 5 2 (that is, on or off). The charge control transistor 56 is a "P-type" transistor, which means that when the charge signal 5 2 is at a low level, the transistor systems are "on" (allowing current to pass). Conversely, when the charging signal 52 is high, the charging control transistor 56 is "off". The dump control transistor 58 is also connected to the system power source (Vdd) and the system ground (Vss) through a charging capacitor 6 2 b. The charging capacitor 6 2 b is located between the dump control transistor 58 and the Vdd. The dump control transistor 5 8 is controlled by the dump signal 5 4 (that is, on or off). The dump control transistor 58 is an “N-type” transistor, which means that when the dump signal 5 4 is at a high level, the transistor systems are “on” (allowing current to pass). Conversely, when the dump signal 5 4 is at a low level, the dump control transistor 58 is “off” (current is not allowed to pass). Finally, the connection transistor 60 is connected to both sides of the circuit. In particular, the connection transistor 60 is connected between the control transistor 5 6, 5 8 and the sides of the charging capacitor 62 2a, 6 2b. The connection transistor 60 is a "P-type" transistor, which means that when the dump signal 5 4 is at a low level, the transistor system is "on" (allowing current to pass). Conversely, when the dump signal 5 4 is at a high level, the connection transistor 60 is “off” (current is not allowed to pass). Under normal operation, the control circuit has two operating states: a charging state and a dumping state. 11 Applicable paper size for China National Standard (CNTS) A4 (210 X 297 mm)-" ------.------------- Order ------ -(Please read the notes on the back before filling out this page) 561692 A7 B7-V. Description of the invention (P) In each state, the circuit is activated by an “active low” signal . This means that when the individual control signal (charging signal 5 2 or dump signal 5 4) is a low level rather than a high level, the individual control signal (charging signal 5 2 or dump signal 5 4) is Initialize its individual states. Specifically, in the charging state, the charging signal 5 2 will be a low level and the dump signal 5 4 will be a high level. Therefore, when the connection transistor 60 is "off", the charge control transistor 56 and the dump control transistor 58 are both "on". This allows both the charging capacitors 6 2 a and 6 2 b to be charged in preparation for the dump state. During the dumping state, the charging signal 5 2 will be at a high level, and the dumping signal 5 4 will be at a low level. Therefore, when the connection transistor 60 is "on", the charge control transistor 56 and the dump control transistor 58 are both "off". This allows both the charging capacitors 6 2 a and 6 2b to dump their charge under the power supply gate, and thus reduces the peak current draw. When comparing Fig. 6 and Fig. 3, it is important to note that the clock pre-processor 32 and the latch 34 are synchronized with the clock noise reduction circuit 4 8. The clock tampering 3 2 and the interlock 3 4 have three individual inverter layers 3 8a, 38b, 38c, 3 8d along the reverse gate 36, and the clock noise is reduced. The circuit 48 has a total of Θ inverters 5CU-c, 53a-c and a reverse gate 5 闸. The element system of FIG. 6 is scaled so that the charge control transistor 56, the dump control transistor 58 and the connection transistor 60 are the same as the individual control transistor 4 0a of FIG. 3 and 4 0 b, switched at the same time. This is the reason why when the size of 12 wood paper is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 Gongchu) '~ —— · ——- Lf -------- tr -------- -p (Please read the notes on the back before filling this page) 561692 A7 V. Description of the invention (Π) When DATA_IN in Figure 3 is first driven by DATA_OUT46, the charge dump is generated. Figures 7a and 7b show the equivalent circuits shown in part of the digital logic diagram in Figure 6 during a charge state and a discharge state, respectively. In each figure, the "off" transistor system has been deleted, and the "on" transistor system has been replaced by a standard circuit connection. Specifically, Fig. 7a shows an equivalent circuit during the state of charge. It shows two capacitors 6 2 a and 6 2b connected in parallel between Vdd and Vss. Figure 7b shows an equivalent circuit during this power state. It shows two capacitors 6 2 a and 6 2 b connected in series between Vdd and Vss. When the capacitors 6 2a and 6 2b are connected in parallel during the charging state, each of the capacitors 6 2a and 6 2b stores a charge 値 "Q ,,", where Q = (capacitance 値 "C ,," * Vdd . Therefore, the total charge stored by this circuit is 2 Q. When the capacitors 6 2a and 6 2b are connected in series during the dumping period, each of the capacitors 6 2a and 6 2b has a voltage equal to Vdd / 2. Therefore, the stored charge of each of the capacitors 6 2 a and 6 2 b for a circuit totaling q will only store q / 2. The excess charge is dumped to the power grid. The circuit 48 shown in Fig. 6 triggers the dumping state at the rising edge of the clock signal 3 Oa. However, the circuit can be easily configured to trigger the dump state at the falling edge of the clock signal 30a. Fig. 8 is a logic diagram showing a clock noise reduction circuit 63 according to an embodiment of a falling edge trigger circuit. The noise reduction ------ · --—— will -------- tr --------- $ r (Please read the precautions on the back before filling this page) Home Standard (CNS) A4 g (21〇χ 297: ^ --- 561692 A7 ____B7______ 5. Explanation of the invention (A) The small circuit 6 3 is similar to the rising edge trigger circuit 4 8 'shown in FIG. 6 The system has the same structure as the clock signal 3 0a divided into two separate branches in the circuit 63. However, the two branch systems are both input to a reverse OR gate 5 5. The first branch system is based on The clock signal 30 a is directly input to the gate 55. The second branch is input through the clock signal 3 0a through three sequence inverters 5 0a, 50, 5 0c. To the gate 5 5. The output of the OR gate 5 5 passes through a fourth inverter 5 7a and a fifth inverter 5 7b. The signal 5 2 (hereinafter referred to as a "charging signal") is then It is divided into two branches. One branch of the charging signal 52 is input to a sixth inverter 5 7 c which inverts the signal again. Then, the output signal of the sixth inverter 5 7 c (hereinafter referred to as "Dumping No. ") and the charging signal 52 are input to three circuit control transistors: one charge control transistor 5 6; one dump control transistor 5 8; and one connection transistor 60. The charge control transistor 5, 6, each of the dump control transistor 5 8 and the connection transistor 60 is for Vdd, Vss and capacitor 6 2 a, 6 2 b with a structure similar to the rising edge circuit 4 8 of FIG. 6 Configuration. It is important to note that the charging signal 5 2 and the dumping signal 5 4 have the opposite, because the charging signal passes through the sixth inverter 5 7 c. The circuit 6 3 will Implemented similar to the circuit 48 shown and described in Figures 6, 7a and 7b. However, the main difference between the circuits shown in Figures 6 and 8 is the dump signal 5 4 And the charging signal 5 2. As mentioned above, the dumping message 14 for the circuit shown in Figure 6 (please read the precautions on the back before filling this page) n ϋ ϋ n ϋ 1 ^^ · d gt > I l ί l · Fortunately, the paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) 561692 A7 ______B7 _____ 5 Description of the Invention (π) No. becomes "low level" during the rising edge of the clock signal 3 Oa, and thus the dumping state is initiated at the rising edge. The dump signal of the circuit becomes a "low level" during the falling edge of the clock signal 3 CU, and thus the dump state is initiated at the falling edge. As described above, in each circuit, the individual charging signal 5 2 is the inverse of its individual dump signal 54. In this way, the state of charge is initialized so that one edge of the clock signal is dumped and recharged in a short period of time thereafter. This state will do nothing during this other clock transition. Other aspects of the performance of the two forms of these circuits are essentially the same. Figure 9 is a logic diagram showing a clock noise reduction circuit 69 according to an alternative embodiment of a rising edge trigger circuit. The noise reduction circuit 69 has the same performance as the rising edge trigger circuit 48 shown in FIG. The noise reduction circuit 6 9 is similar to the rising edge trigger circuit 4 8 shown in FIG. 6 in that it has the same clock signal 3 0 a as the division in the circuit 6 9 into two separate branches. structure. However, both branches are input to a reverse OR gate 59. The first branch is input to the gate 59 after transmitting the clock signal 3 Oa through four sequence inverters 50a, 50b, 50c and 50d. The second branch transmits the clock signal 3 oa through a fifth inverter 50 e before being input to the gate 59. The output of the OR gate 59 is divided into two branches. A branch of the output 5 2 (hereinafter referred to as a charging signal) is input to a sixth inverter 61 which inverts the signal again. Then, the sixth inverter 6 15 (Please read the precautions on the back before filling this page)
--------訂--------I 衣紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^" A7 561692 ______________ 五、發明說明（W) 1之該輸出訊號（下文稱爲“傾卸訊號”）及該充電訊號 5 2係被輸入至三個電路控制電晶體：一個充電控制電晶 體5 6 ; —個傾卸控制電晶體5 8 ;及一個連接電晶體6 0 °該充電控制電晶體5 6，該傾卸控制電晶體5 8及該 連接電晶體6 0之每一個係對於Vdd，Vss及電容器6 2 a ，6 2b以一類似於第6圖之該上升緣電路4 8之結構配 置。重要的是應注意：該充電訊號5 2及該傾卸訊號5 4 係具有相反之値，這是因爲該充電訊號係通過該第六反相 器6 1。 第10圖係顯示根據一個下降緣觸發電路之替代實施 例之一個時脈雜訊減少電路7 1之邏輯示意圖。該雜訊減 少電路7 1具有與示於第8圖之該下降緣觸發電路6 3相 同之效能。該雜訊減少電路7 1類似於示於第8圖之該下 降緣觸發電路6 3係在於其係具有於該電路7 1內之分割 成爲兩個分離的分支之時脈訊號3 CU之相同結構。然而 ，該兩個分支係皆輸入至一個反及閘7 3。該第一分支係 於傳輸該時脈訊號3 Oa通過四個序列之反相器5 CU，5 0 b，5 〇c及5 〇d之後被輸入至該閘7 3。該第二分支係於 被輸入至該閘7 3之前傳輸該時脈訊號3 〇a通過一個第 五反相器5 〇e。 該反及閘7 3之輸出係被輸入至一個第六反相器5 3 a 。該反相器5 3 a係反相該訊號値。然後，該訊號5 2 ( 下文稱爲充電訊號）係被分割成爲兩個分支。該充電訊號 5 2之一個分支係被輸入至一個再次反相該訊號之第七反 16 木紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚1 —— —，——「會--------tr---------· (請先閱讀背面之注意事項再填寫本頁) A7 561692 ______B7___ 五、發明說明（) 相器5 3 b。然後，該第七反相器5 3 b之該輸出訊號（下 文稱爲“傾卸訊號”）及該充電訊號5 2係被輸入至三個 電路控制電晶體··一個充電控制電晶體5 6 ; —個傾卸控 制電晶體5 8，·及一個連接電晶體6 0。該充電控制電晶 體5 6，該傾卸控制電晶體5 8及該連接電晶體6 0之每 一個係對於Vdd，Vss及電容器6 2 a，6 2 b以一類似於 第6圖之該上升緣電路4 8之結構配置。重要的是應注意 :該充電訊號5 2及該傾卸訊號5 4係具有相反之値’這 是因爲該充電訊號係通過該第五反相器5 3b。 第11圖係顯示如示於第6至8圖之該上升緣及下降 緣雜訊減少電路之一個時脈週期期間之電流拉引圖。於該 兩個電路中，於該時脈訊號切換期間之減少該電流拉引之 結果係類似的。明確言之，第1 1圖之該圖係以相同於示 於第4圖之先前技藝之圖形之比例而設定。該値“1” 3 5 係表示一個電流拉引之全部値。該値“ 3/4 Γ 3 7係表 示一個電流拉引之全部値之百分之7 5，而値“1/21” 3 9係表不一個電流拉引之全部値之百分之5 0 °該圖形 之該第一電流汲取7 0係代表由一個時脈週期（於時脈週 期等於0時）之該前緣所造成之電流汲取。該圖形之該第 二電流汲取7 2係代表由一個時脈週期（於時脈週期等於1 /2時）之該後緣所造成之電流汲取。如圖所示’該第一 電流汲取7 0及該第二電流汲取7 2係皆爲大約電流拉引 之全部値之5 0% (1/21) °此係代表藉由減少該尖峰 電流接引之一個於雜訊減少上之實質改進。該第一電流汲 17 木紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） (請先閲讀背面之注意事項再填寫本頁) 1 in 1« im n n 一 e n —i an an n em§ l 1 A7 561692 五、發明說明（A ) 取7 0及該第二電流汲取7 2之每一個係具有一個大約爲 示於第4圖之該先前技藝電流接引4 1，4 3之對應期間 (“d”）之兩倍期間（“2d”）。 所有上述之電路係產生一個控制該電容器之切換之一 個脈波（透過於其他輸入端之反及閘或者反或閘及反相器 )。當該些閂鎖器係切換且該額外的充電能夠被使用時， 該脈波係導致該些電容器變成串聯。於該些閂鎖器已經被 切換之後，該脈波係離開，導致該些電容器回到平行，且 實質上將電荷拉回至該些電容器內。該總結果係一個較長 的電流尖峰且具有一個較小的振幅’且因而具有較少之雜 訊。 雖然本發明已經對於有限的實施例予以敘述’熟悉本 項技藝人士於此揭示之下係可以瞭解’於不偏離本發明之 範疇之下可以推導出其他實施例。因此’本發明之範圍應 僅受限於後附之申請專利範圍。 木紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------Λ----------訂--------- (請先閱讀背面之注意事項再填寫本頁)-------- Order -------- I Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) ^ " A7 561692 ______________ 5. Description of the invention (W) 1 of the output signal (hereinafter referred to as the "dump signal") and the charging signal 5 2 are input to three circuit control transistors: a charge control transistor 5 6; a dump control transistor 5 8; And a connection transistor 60 °, the charge control transistor 56, the dump control transistor 58, and each of the connection transistor 60 are similar to Vdd, Vss, and capacitors 6 2a, 6 2b The configuration of the rising edge circuit 48 in FIG. 6. It is important to note that the charging signal 5 2 and the dumping signal 5 4 are opposite, because the charging signal passes through the sixth inverter 61. Fig. 10 is a logic diagram showing a clock noise reduction circuit 71 according to an alternative embodiment of a falling edge trigger circuit. The noise reduction circuit 71 has the same performance as the falling edge trigger circuit 63 shown in FIG. The noise reduction circuit 7 1 is similar to the falling edge trigger circuit 6 3 shown in FIG. 8 in that it has the same structure as the clock signal 3 CU divided into two separate branches in the circuit 7 1 . However, both branches are input to a reverse AND gate 73. The first branch is input to the gate 73 after transmitting the clock signal 3 Oa through the inverters 5 CU, 50 b, 50 c, and 50 d of four sequences. The second branch transmits the clock signal 3 oa through a fifth inverter 50 e before being input to the gate 73. The output of the inverting gate 7 3 is input to a sixth inverter 5 3 a. The inverter 5 3 a inverts the signal 値. Then, the signal 5 2 (hereinafter referred to as a charging signal) is divided into two branches. A branch of the charging signal 5 2 is input to a seventh inversion 16 of the signal again. The wood paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 Gong Chu 1 —— —, —— ” -------- tr --------- · (Please read the notes on the back before filling out this page) A7 561692 ______B7___ V. Description of the invention () Phase device 5 3 b. Then, the The output signal of the seventh inverter 5 3 b (hereinafter referred to as the “dump signal”) and the charging signal 5 2 are input to three circuit control transistors. One charging control transistor 5 6; one The dump control transistor 58 and a connection transistor 60. The charge control transistor 56 and the dump control transistor 58 and the connection transistor 60 are each for Vdd, Vss, and a capacitor. 6 2 a, 6 2 b are configured with a structure similar to the rising edge circuit 4 8 in FIG. 6. It is important to note that the charging signal 5 2 and the dump signal 5 4 have opposite 値This is because the charging signal passes through the fifth inverter 5 3b. Figure 11 shows the rising edge and falling edge noise as shown in Figures 6 to 8. Reducing the current draw during a clock cycle of the circuit. In both circuits, the result of reducing the current draw during the clock signal switching is similar. Specifically, Figure 11 The drawing is set at the same scale as the figure of the previous art shown in Fig. 4. The "1" 3 5 represents the total current drawn by a current. The "" 3/4 Γ 3 7 represents a current 75% of the total current drawn, and “1/21” 3 9 represents 50% of the total current drawn by a current ° The first current draw of the graph is 70% The current drawn by the leading edge of a clock cycle (when the clock cycle is equal to 0). The second current draw of the graph 7 2 represents a clock cycle (when the clock cycle is equal to 1/2) Current) caused by the trailing edge. As shown in the figure, 'the first current draw 70 and the second current draw 7 2 are both about 50% (1/21) of the total current drawn ) ° This represents a substantial improvement in noise reduction by reducing one of the spike currents. The first current draw 17 The size of wood paper is applicable to China National Standard (CNS) A4 (210 X 297 cm) (Please read the precautions on the back before filling out this page) 1 in 1 «im nn 一 en —i an an n em§ l 1 A7 561692 V. Description of the invention (A) Each of taking 7 0 and the second current drawing 7 2 has a corresponding period approximately corresponding to the prior art current connection 4 1, 4 3 shown in FIG. 4 ("d ") (" 2d "). All of the above circuits generate a pulse (via the inverse AND gate or the inverse OR gate and inverter at the other input terminals) that controls the switching of the capacitor. When the latches are switched and the additional charging can be used, the pulse wave system causes the capacitors to become series. After the latches have been switched, the pulse train leaves, causing the capacitors to return to parallel and substantially pulling charge back into the capacitors. The overall result is a longer current spike with a smaller amplitude ' and therefore less noise. Although the present invention has been described with respect to a limited number of embodiments, those skilled in the art will understand that other embodiments can be derived without departing from the scope of the invention. Therefore, the scope of the present invention should be limited only by the scope of the attached patent application. Wood paper scale is applicable to China National Standard (CNS) A4 (210 X 297 mm) ---------- Λ ---------- Order --------- (Please read the notes on the back before filling this page)