TW560000B - Method to fabricate contact via on the NiSix layer - Google Patents

Abstract

The present invention discloses a method to fabricate contact via on the NiSix layer, whose feature is to utilize physical etching to resolve the problem of etchant reacting with highly active NiSix layer in the process of prior art. The first method is: do not remove the etch stop layer completely in one time, but remain a very thin etch stop layer, and remove the remaining etch stop layer in the way of physical etching, so that the etching gas will not react with the NiSix layer. The second method is: use a novel etch buffer layer between the etch stop layer and the NiSix layer, and use physical etching to remove the etch buffer layer. In the same way, the etchant gas will not react with the NiSix layer.

Description

560000 V. Description of the invention (1) Field of the invention: The present invention relates to a method for making a contact hole, and in particular to a method for making a contact hole over a nickel silicide layer. Relevant technical description: In semiconductor technology, metal-oxide-semiconductor (MOS) transistors are composed of a gate, a source, and a drain ((^ & 丨 11) It is composed of three electrodes, among which M0S is the main body forming the gate structure. The early% 0S was composed of a metal layer, silicon dioxide (Si02), and a silicon-based substrate. Layer material. However, since most metals have poor adhesion to silicon dioxide, polys i 1 icon, which has better adhesion to silicon dioxide, has been proposed to replace metals. However, the use of polycrystalline stone has a problem that the resistance value is too high. Even if the polycrystalline stone is doped, its resistance value is still too high to be suitable for the metal layer to be replaced. Therefore, those familiar with this art A solution is proposed, that is, another layer of metal silicide (metal si 1 pesticide) with a thickness equivalent to that of the polycrystalline silicon layer is added to the surface of the polycrystalline silicon, and the metal silicide and polycrystalline having better conductivity are used. Together, they form a conductive layer. Then, contact holes are formed to form interconnects over the entire gate layer. The conventional method of making contact holes over the silicide gate layer is briefly described below. First, please refer to Figure 1A, Provide a Shi Xi base 100, including ...

560000

Second, an oxide layer (gate oxide) 102 is formed on the surface of the substrate 100; a gate conductive layer composed of a polycrystalline stone layer 104 and a metal silicide layer 106 is formed on the gate oxide layer 10 On the surface, the metal lithoxide can be Shixiuhua, titanium silicide, or cobalt silicide; a pair of silicon nitride spacers 108 formed on the sidewall of the entire gate conductive structure; a pair of ion implants The regions s, D 'are formed on the surface of the substrate 100 on both sides of the gate conductive structure with the silicon nitride spacer 08, and are used as a source / drain region.

Next, an etch stop layer is formed conformably on the entire surface of the substrate. At this moment, the material of the stop layer 11 is preferably silicon nitride or silicon oxynitride, and its thickness is about 250 to 300 A. Next, referring to FIG. 1B, an inner dielectric layer 112 is formed on the entire surface of the substrate. Deposit one or more insulating materials' on the entire substrate surface as inter layer dielectrics (ILD) 112, such as borophosphosilicate glass (BPSG), tetraethoxysilane oxide layer (TE0S), spin-on coating Glass (S0G) and so on. For example, under the environment of SiH4, pij3, using atmospheric pressure chemical vapor deposition (apcvd) to form butterfly silica glass, or tetraethoxysilane (TEOS;

tetraethyl-ortho-silicate) is a reactive gas, and a low pressure chemical vapor deposition (L P C V D) method is used to form an oxide layer. Preferably, the inner dielectric layer 112 may be planarized by chemical mechanical polishing (CMP) to obtain a flat upper surface. Next, referring to FIG. 1C, for example, using a spin coating method (s p i ^ coat ing) and an appropriate lithography development program, a pattern having a predetermined pattern is formed.

560000 V. Description of the invention (3) The patterned photoresist 114 covers the surface of the inner dielectric layer 112 and exposes only the area above the nickel silicide layer 106 where the contact hole is intended to be formed. Next, please refer to FIG. 1D, using the patterned photoresist 114 as a mask, and then etch the inner dielectric layer 11 2 ′ to form a contact hole I in the inner dielectric layer 112 above the Shixihua recording gate 106. Inside, until the surface of the etching stop layer 11 is exposed, the two inner dielectric layers 212 can be etched using a mixed gas containing (: 4ιγ8 / (: 2Η2Ι? 2 / Αγ) or a mixture containing Cs Fg / 〇 2 / A r The gas is electrically engraved. Finally, please refer to FIG. 1E. After removing the patterned photoresist 214, the etching stop layer 1 in the contact hole I is partially removed, and the contact outside the metal silicide is completed. However, common metal silicides include the early tungsten silicide (ws 丨) and titanium silicide (TiSD), and processes below 0.18 use cobalt silicide (coSi) as the cobalt silicide. The use of NiSix has become a popular research course. However, when nickel silicide is used as the gate layer material, the removal of the etching stop layer is very easy because of the high activity of nickel. Etchants such as: 02, F, or C0 react to form oxygen In view of this, in order to solve the above problems, the main purpose of the present invention is to provide a method for making a contact hole over a nickel silicide layer to avoid the reaction between the nickel silicide and the etchant. Summary of the invention: Ϊ ^ · Π8Β 〇503-8384TWF (N): TSMC2002-0297; Felicia.ptd page 8 560000 5. Description of the invention (4) The purpose of the present invention is to provide the first method for making contact holes above the nickel silicide layer. Method to avoid the reaction between the etchant and the nickel silicide and reduce the conductivity of the nickel silicide layer. In order to achieve the above-mentioned object, the present invention proposes the first method for making a contact hole over the j-silicon layer. The main purpose of this method The waiting point is that the etching stop layer is not completely removed at one time, and an extremely thin etch stop layer is left. The remaining etching stop layer is removed by physical etching, and the etching gas will not react with the nickel silicide layer. The steps mainly include: First, a substrate is provided with a nickel silicide layer on the surface. Next, an etching stop layer is formed on the surface of the nickel silicide layer. Next, an inner dielectric layer is formed on the entire surface of the substrate. Then, the inner dielectric layer is patterned to form a contact hole over the nickel silicide layer to expose the surface of the etching stop layer. Then, a part of the contact is removed. The etch stop layer in the hole leaves only one residual etch stop layer with a thickness of 50 to 150 A. Finally, the residual etch stop layer is removed by physical etching until the surface of the shattered gate is exposed. According to the present invention In the step of removing the residual etching stop layer, the physical #etching method may be performed by bombarding the residual etching stop layer with an inert gas plasma such as argon. This step may further include using a fluorine-containing gas plasma having a content of, for example, 10% for chemical etching. As mentioned above, the material of the etching stop layer may be silicon nitride or silicon nitride, and the material of the inner dielectric layer may be stone oxide. As mentioned above, the method for patterning the above-mentioned inner dielectric layer may include:

560000 V. Description of the invention (5) First, a patterned photoresist is formed, covering the inner layer to expose the above-mentioned patterned photoresist that is intended to form a contact hole over the nickel silicide layer as a mask, and the above-mentioned interlayer contact hole is etched on the silicide The inner dielectric layer above the nickel gate is etched until the surface of the termination layer is etched. Finally, as described above, the step of removing the step of removing the patterned photoresist from the step of damaging the money-engraved termination layer in the contact hole described above is to achieve the above purpose. method. This method newly quotes the moment between the stop layer and the nickel silicide layer, and then uses the first moment to remove the etching buffer layer, and the etching gas will not react with the silicon. The steps of this method mainly include: First, a substrate is provided, the surface of which has an etched layer and an etch buffer layer and an etch stop layer are sequentially formed on the surface. Next, an inner dielectric layer is formed on the entire substrate and the inner dielectric layer is patterned to form a contact hole at the square 'to expose the surface of the above-mentioned stop layer, and then the stop layer is etched. Finally, the etching buffer layer is removed by a physical etching method until the nickel silicide gate is exposed as in the first method of the present invention. The above physical etching, such as an inert gas plasma of argon, bombards the etching. This step may further include: The content is, for example, 0.1 to 10 ×% for chemical money engraving. Dielectric layer area. The electrical layer, the layer, and the photochemical step can be applied before or on the surface of the nickel layer in the method of engraving and slowing, and then only to form a resist until exposed. After removal. Used as a contact hole and punched in a physical corrosion layer to generate a nickel layer. Next, the surface of the nickel silicide layer is as described above. Next, the β-etching method on the nickel silicide layer except for the inside of the contact hole and the inside surface of the contact hole can be performed using a buffer layer. Fluorinated gas plasma

560000 V. Description of the invention (6) ^ In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following exemplifies the preferred embodiments and the accompanying drawings to make a detailed description as follows: Examples ·· First Embodiment Please refer to the cross-sectional schematic diagrams of the process in FIG. 2A to FIG. 2H to describe a preferred embodiment according to the present invention in detail. In this embodiment, nickel silicide is applied to the gate layer as an example to illustrate the present invention. However, nickel silicide can also be applied to the source / drain. The application of the nickel silicide of the present invention is not limited. In the interpolar layer. First, referring to FIG. 2A, a silicon substrate 200 is provided, which includes a gate oxide layer 202 formed on the surface of the substrate 200; a polycrystalline silicon layer 204 and a nickel silicide layer 206 One of the gate conductive structures is formed on the surface of the gate oxide layer 002; a pair of silicon nitride spacers 208 is formed on the side wall of the entire gate conductive structure;-the ion implantation area S, D, formed on the surface of the substrate 200 on both sides of the gate conductive structure with the silicon nitride spacer 208, is used as a source / drain region. Those skilled in this art can form a nickel silicide layer 206 by reacting a polycrystalline silicon layer and a nickel metal layer with a rapid thermal process (RTP), which is a conventional metal silicide process. Since these processes are not related to the features of the present invention, they are not described in detail here.

560000 V. Description of the invention (7) Next, referring to FIG. 2B, an etch stop layer 2 1 0 is formed conformably on the entire substrate surface. The material of this etch stop layer 2 1 0 is preferably silicon nitride or silicon oxynitride. Low pressure chemical vapor deposition (LPCVD) can be used. Two gas silanes (SiCl2H2) and ammonia (NH3) are used as reaction gases. 250 ~ 400 ° 0: Deposited at the operating temperature, its thickness is about 250 ~ 300A. Next, referring to FIG. 2C, an inner dielectric layer 212 is formed on the entire surface of the substrate. Deposit one or more insulating materials' on the entire substrate surface as inter layer dielectrics (ILD) 212, such as borophosphosilicate glass (BPSG), tetraethoxysilane oxide layer (TE0S), spin coating Glass (SOG), etc. For example, Boronite glass can be formed by using atmospheric pressure chemical vapor deposition (apcvd) under the environment of SiH4, PH3, B2H6, or tetraethyl-ortho-silicate can be used. ) Is a reaction gas, and a low-pressure chemical vapor phase < CVD (LPCVD) method is used to form an oxide fragment. Preferably, the inner dielectric layer 212 may be planarized by chemical mechanical polishing (CMP) to obtain a flat upper surface. Next, please refer to FIG. 2D, for example, using a spin coating method. (Sp in coating) and appropriate lithographic development procedures to form a patterned photoresist 214 having a predetermined pattern, covering the surface of the inner dielectric layer 212 ', exposing only the area where the contact hole is intended to be formed above the nickel silicide layer 206. ^ Then “see FIG. 2E” with the patterned photoresist 214 as a mask, and then the inner dielectric layer 212 is formed to form a contact hole u in the inner dielectric layer 212 above the nickel silicide gate 206 ' Until exposed

560000

11 \ 2 ^ 〇 # /, j ^ f ^ ^ C4F8 / C2H2F2 / Ar ^ > f, grafting a mixed gas of 5 8 / 〇z / Ar for plasma etching. Except for a part of the contact Γ / τ, see the diagram 'Remove the patterned photoresist 214, and then go to thickness: in the rest of the termination layer 210, leaving only about 1/3 ~ 1/2 of the originalized t-trench stop layer ⑽ For example: 5 ° ~ 150 in. Removal of the pattern layer 21 (This step can be performed at the step of removing the etching termination (H Sf) in the contact hole, and after or after, there is no need to limit it. Sulfuric acid 2 4 0 hydrogen peroxide (H 2 0 2 ) Of the mixed solution to remove the photoresist 214 at a temperature of 90 to 130 t. The etching of the partial etching stop layer 21 is performed by etching with a high selectivity ratio of nitride and oxide, which can be used as an etchant to control in a time mode. Finally, please refer to Figure 2G, using physical etching method 500, such as inert gas plasma bombardment, to remove the remaining etching stop layer 10a in the contact hole 丨 until the nickel oxide gate 2 is formed. Up to 0 surface, this is one of the main features of the present invention. In addition, a small amount of chemical properties can be added during the physical etching process of 50 (). For example, the content is about 0 · i ~ 丨 〇% Fluoride gas plasma (NF3, HF) for etching. In this way, the contact hole opening π above the petrified nickel layer 20 6 can be completely opened, as shown in FIG. 2H, but the physical etching is 5 0 0 No reaction will occur to the nickel silicide layer 206. Among them, The inert gas is, for example, argon (Ar), and its flow rate is about 100 to 1 00000 sccm. The plasma etching temperature can be between 0 and 300 ° C, the plasma etching pressure can be between 0.1 and 10 mTorr, and the power of the power source is about 10%. 〇 ~ 800W, the bias power is about 100 ~ 800W.

560000 V. Description of the invention (9) Second embodiment Please refer to the cross-sectional schematic diagrams of the processes in FIGS. 3A to 3 (a) to describe another preferred embodiment according to the present invention in detail. Similarly, in this embodiment, nickel silicide is applied to the gate layer as an example to illustrate the present invention. However, nickel silicide can also be applied to the source / drain. The nickel silicide of the present invention is applied It is not limited to the gate layer. First, referring to FIG. 2A, a silicon substrate 300 is provided, which includes: a gate oxide layer 302 formed on the surface of the substrate 300 and composed of a polycrystalline silicon layer 304 and a nickel silicide layer 306 A gate conductive structure is formed on the surface of the gate oxide layer 302; a pair of silicon nitride spacers 308 is formed on the entire side wall of the gate conductive structure;-the ion implantation regions S and D are formed on The surface of the substrate 300 on both sides of the gate conductive structure with the silicon nitride spacer 308 is used as a source / drain region. Those skilled in the art can react with each other to form a petrified nickel layer 306 by a rapid thermal process (rapt thermal prc) (CH; RTP) through a polycrystalline silicon layer and a nickel metal layer, which is a known metal petrified compound. Salicides. Since these processes are not related to the features of the present invention, they are not described in detail here. Next, referring to FIG. 3B, an etch buffer layer 310 and a etch stop layer 312 are sequentially formed on the entire substrate surface in compliance. The etching buffer layer 3 1 0 is one of the features of the present invention, and its material is preferably silicon oxide, and tetraethy 1-orth0-Siiicate can be used as a reaction gas, and a low-pressure chemical gas is used. Phase Deposition (LPCVD) or Electropolymerization

560000 V. Description of the invention (10) Vapor deposition (PECVD) to form a silicon oxide layer, the thickness of which is about 50 ~ 150 A ° Oxidized stone, and the buffer layer can also use high temperature, for example: 300 ~ 5〇 〇c, a mixed gas with SiH4 gas or a mixed gas of NH3, N2 * SH4 is reacted to form. In addition, the material of the etch stop layer 3 1 2 is preferably nitride or silicon oxide. Low pressure chemical vapor deposition (LPCVD) can be used, and two gas silane (SiCl2H2) and ammonia gas (〇3) are used as reaction gases. It is deposited at an operating temperature of 250 ~ 40 ° C and has a thickness of about 250 ~ 300A. Then, 'see FIG. 3C, an inner dielectric layer 314 is formed on the entire substrate surface. On the entire substrate surface Deposit one or more insulating materials' as inter layer dielectrics (ILD) 314, such as borophosphosilicate glass (BPSG), tetraethoxysilane oxide layer (TEOS), spin-on glass (s 〇G), etc. For example, in the environment of SiIj4, pjj3, ^, atmospheric pressure chemical vapor deposition (APCVD) method can be used to form borophosphite glass, or tetraethoxysilane (TE0S; tetraethyl -ortho-silicate) is a reactive gas, and a low-pressure chemical vapor deposition (LPCVD) method is used to form a silicon oxide layer. Preferably, the inner dielectric layer 314 can be planarized by chemical mechanical polishing (CMP). Processing to get a flat upper table Surface 0 Next, referring to FIG. 3D, for example, a patterned photoresist 316 having a predetermined pattern is formed by using a spin coating method and an appropriate lithography development program to cover the surface of the inner dielectric layer 314. A region where a contact hole is intended to be formed above the nickel silicide layer 306 is exposed.

0503-8384TWF (N): TSMC2002-0297; Felicia.ptd 560000 V. Description of the invention (11) Next, referring to FIG. 3E, the patterned photoresist 316 is used as a mask, and the inner dielectric layer 314 is etched to form a Touch flTTTi μ to wind the contact 111 in the inner dielectric layer 314 above the nickel silicide gate 30e, until the #etch stop layer 312 is used to etch the second inner dielectric layer 314. Etching using C4F8 / C2H2F2 / Plasma etching is performed on a mixed gas of Ar or a mixed gas containing QFjO ^ Ar. Next, referring to FIG. 3F, after removing the patterned photoresist 316, the etching stop layer 312 in the contact hole ill is removed. The step of removing the patterned photoresist 316 may be performed before or after the step of removing the etch stop layer 3 丨 2 in a part of the contact hole, without limitation. The photoresist 214 can be removed by using a mixed solution of sulfuric acid (H2S04) and hydrogen peroxide (H2O2) at a temperature of 90 to 130 ° C. The etching of the stop layer 210 is removed, and etching with a high selectivity ratio of the nitride to the oxide can be used. Clh / OVAr can be used as an etchant until the oxide etch buffer layer is exposed. Finally, referring to FIG. 3G, the physical etching method 600, such as bombardment with an inert gas plasma, is used to remove the etching buffer layer 3 in the contact hole 11 I until the nickel oxide gate 3 06 is exposed. On the surface, this is one of the main features of the present invention. The far-reaching gas is, for example, argon (A r). In addition, a small amount of chemical etching can be performed during the physical cooking process of 600, for example, using a fluorine-containing gas plasma (Nρ3, HF) with a content of about 0 ·! ~ 10% for etching. In this way, the contact hole opening 111 above the nickel silicide layer 306 can be completely opened, as shown in FIG. 3H, but the physical etching of 600 will not cause any reaction to the nickel silicide layer 306. The inert gas is, for example, argon (Ar), and its flow rate is about 1000 to 1000 sccm. The plasma etching temperature can be between 0 and 300 ° C, and the plasma etching pressure can be between 0.1 and 10 mT. rr, power supply is about

0503-8384TW (N); TSMC2002-0297; Felicia.ptd

560000 V. Description of the invention (12) 100 ~ 800W, the bias power is about 100 ~ 800W. Although the present invention is disclosed in the preferred embodiments above, the scope of the present invention is within the spirit and scope of any person skilled in the art, and can be modified and protected within the scope of the patent. Without departing from the decoration of the present invention, the subject of the present invention shall prevail.

0503-8384TWF (N) * · TSMC2002-0297 · Felicia.ptd page 17 560000 Figures briefly explain Figures 1 A to 1 E are the cross-sections of the conventional process for forming contact holes above the metal silicide gate layer schematic diagram. 2A to 2D are schematic cross-sectional views of a process according to a preferred embodiment of the present invention. Figures 3A to 3D are schematic cross-sectional views showing a process according to another preferred embodiment of the present invention. Explanation of symbols: 100, 200, 300 ~ semiconductor substrate; S ~ source; D ~ drain; 102, 202, 302 ~ gate oxide layer; 104, 204, 304 ~ polycrystalline silicon; 106, 206, 306 ~ metal stone Compounds; I 0 8, 2 0 8, 3 0 8 ~ spacers; II 0, 2 1 0, 3 1 2 ~ remaining stop layer; 3 1 0 ~ remaining buffer layer; 11 0 a, 21 0 b, 3 1 2 a ~ patterned etch stop layer; 210a ~ residual etch stop layer; 112, 212, 314 ~ inner dielectric layer; 112a, 212a, 314a ~ patterned inner dielectric layer; 114, 214, 316 ~ patterned Photoresist; I, 11, 111 ~ contact hole; 3 10a ~ patterned etching buffer layer; 5 0, 6 0 0 ~ physical money engraving procedure.

0503-8384TWF (N) i TSMC2002-0297: Felicia.ptd

Claims (1)

560000 A method for making a contact hole over a nickel silicide layer, comprising: providing a substrate having a nickel silicide layer on a surface thereof; and sequentially forming a buffer layer and an etching stop layer on the surface of the silicide layer in sequence; Forming an inner dielectric layer on the entire substrate surface; patterning the inner dielectric layer to form a contact hole over the nickel silicide layer to expose the surface of the etch stop layer; removing the etch stop layer in the contact hole; and The physical etching method removes the etching buffer layer in the contact hole until the surface of the nickel silicide gate is exposed. 2. The method for making a contact hole over a nickel silicide layer as described in item 1 of the scope of the patent application, wherein the material of the etching buffer layer includes silicon oxide. 3. The method for making a contact hole over a nickel silicide layer as described in item 1 of the scope of the patent application, wherein the thickness of the etching buffer layer is 50 to 150A. 4. The method for making a contact hole over a nickel silicide layer as described in item 2 of the scope of the patent application, wherein the above-mentioned etching buffer layer is formed by a chemical vapor deposition method. 5. The method for making a contact hole above the nickel silicide layer as described in item 2 of the scope of the patent application, wherein the above-mentioned insect-etching buffer layer is formed by injecting a 10 gas at high temperature to react with the above-mentioned nickel silicide. 6. The method for making a contact hole over a nickel silicide layer as described in item 1 of the scope of the patent application, wherein the material of the #etch stop layer includes silicon nitride or silicon oxynitride. 7. Make contact holes in nickel silicide as described in item 1 of the scope of patent application 560,000 patent application method over the layer, wherein the material of the above-mentioned inner dielectric layer includes silicon oxide. 8. The method for making contact holes in nickel silicide as described in item 1 of Shen Qing's patent scope, wherein the physical etching method is to bombard the remaining buffer layer with an inert gas plasma. • The method of making contact holes above the nickel layer of Shixihua as described in item 8 of the patent claim, wherein the above inert gas plasma includes argon. 1 · The method for making a contact hole over a nickel silicide layer as described in item 1 of the scope of the patent application, wherein the step of removing the etching buffer layer in the contact hole further includes: using a small amount of fluorine-containing plasma for chemical properties Etching. 1 11. The method for making a contact hole over a nickel silicide layer as described in item 10 of the scope of the patent application, wherein the above-mentioned plasma content is 1 to 10%. 1 2 · The method for making a contact hole over a nickel silicide layer as described in item 1 of the scope of the patent application, wherein the method of patterning the above-mentioned inner dielectric layer includes: forming a patterned photoresist covering the above-mentioned inner dielectric layer On the surface, only the area where the contact hole is intended to be formed above the nickel silicide layer is exposed; using the patterned photoresist as a mask, the inner dielectric layer is etched to form a contact hole on the inner dielectric layer above the nickel silicide gate. Inside until the surface of the etch stop layer is exposed; and removing the patterned photoresist. 1 3 · The method for making a contact hole over a nickel silicide layer as described in item 12 of the scope of the patent application, wherein the step of removing the patterned photoresist is performed before the step of removing the etch stop layer in the contact hole. 1 4 · The method for making a contact hole over a silicided nickel layer as described in item 12 of the scope of the patent application, wherein the step of removing the patterned photoresist is performed 0503-8384TWF (N); TSMC2002-0297; Felicia.ptd page 20 560000 After the step of removing the etch stop layer in the contact hole. \ 5. A method for making a contact hole over a nickel silicide layer, including: providing a substrate with a nickel silicide layer on the surface; forming an etch stop layer on the surface of the nickel silicide layer; forming an inner dielectric layer on The entire substrate surface; patterning the inner dielectric layer to form a contact hole above the silicidation layer to 'expose the surface of the rice-cut stop layer; removing part of the etching stop layer in the contact hole, leaving only 1/2 A remaining etching stop layer with a thickness of ~ 1/3; and removing the remaining etching stop layer by a physical method until the surface of the nickel silicide gate is exposed. 16. The method for making a contact hole over a silicide layer as described in item 15 of the scope of the patent application, wherein the material of the above-mentioned etching stop layer includes silicon nitride or oxynitride. 1 7 · The method of making contact holes on the silicidation layer as described in item 15 of the scope of patent application ', wherein the material of the above-mentioned inner dielectric layer includes an oxidation sentence. 18 · As described in item 5 of the scope of patent application A method for making a contact hole over a silicide layer, wherein the physical etch method is to bombard the residual etching stop layer with an inert gas plasma. 19 · The method for making a contact hole over a nickel silicide layer as described in item 8 of the patent application scope, wherein the inert gas plasma includes argon. 2 0. The method for making a contact hole above a silicided nickel layer as described in item 5 of the scope of the patent application, wherein the step of removing the above-mentioned residual money stop layer is more 560000 6. Scope of patent application Including ... Chemical etching using a small amount of fluorine-containing gas plasma. 2 1 · The method for making a contact hole over a nickel silicide layer as described in item 20 of the scope of the patent application, wherein the above-mentioned plasma content is 0 · 10. / 〇. 2 2 · The method for making a contact hole above a silicide layer as described in item 15 of the scope of patent application, wherein the method of patterning the above-mentioned inner dielectric layer includes: forming a patterned photoresist to cover the above-mentioned inner layer dielectric The surface of the layer only exposes the area where the contact hole is planned to be formed above the nickel silicide layer. Using the patterned photoresist as a mask, the inner dielectric layer is etched to form a contact hole in the inner layer dielectric above the nickel silicide gate. Inside the electrical layer until the surface of the coin stop layer is exposed; and removing the patterned photoresist. 2 3 · The method for making a contact hole above a silicified ballast layer as described in item 15 of the scope of the patent application, wherein the step of removing the patterned photoresist is a step of removing an etch stop layer in a part of the contact hole. prior to. 24. The method for making a contact hole over a nickel silicide layer as described in item 15 of the scope of the patent application, wherein the step of removing the patterned photoresist is performed after the step of removing an etch stop layer in part of the contact hole. . 25 · —A method for making a contact hole over a nickel silicide layer, comprising: providing a substrate having a nickel silicide layer on a surface thereof; forming an etch stop layer on the surface of the nickel silicide layer; forming an inner dielectric layer on the entire substrate Surface; patterning the inner dielectric layer to form a contact hole over the nickel silicide layer to expose the surface of the etch stop layer; page 22 560000 50 ~ 1st copies of the etch stop layer in the contact hole, leaving only one remaining etch stop layer with a thickness of 0 A; and ^ ί ， 性 # 刻 法 Remove the above residual # etch stop layer until exposed Up to the nickel gate surface. 26. The method for making contact holes in silicidation II = dead side as described in item 25 of the scope of the patent application, wherein the material of the above-mentioned etching stop layer includes nitride nitride or silicon oxynitride. 27. The method for making a contact hole over a silicide layer as described in item 25 of the Shenjing patent scope, wherein the material of the inner dielectric layer includes an oxide dream. 28. The method of making a contact hole over a silicide layer as described in item 25 of the scope of the patent application, wherein the physical etching method is to bombard the residual etching stop layer with an inert gas plasma. 29. The method for making a contact hole over a nickel silicide layer as described in item 28 of the scope of the patent application, wherein the inert gas plasma includes argon. 30. The method for making a contact hole over a nickel silicide layer as described in item 25 of the scope of the patent application, wherein the step of removing the residual etching stop layer further includes: chemically etching a plasma containing a small amount of fluorine-containing gas. 3 1 · The method for making contact holes above the stone nickel layer as described in item 30 of the scope of the patent application, wherein the above-mentioned electromagnet content is from 0.1 to 10%. 3 2 · The method for making a contact hole above a nickel oxide layer as described in item 25 of the scope of patent application, wherein the method of patterning the above-mentioned inner dielectric layer includes: forming a patterned photoresist to cover the above-mentioned inner layer Dielectric layer surface, only 0503-8384TWF (N); TSMC2002-0297; Felicia.ptd page 23 560000 Expose the area where the contact hole is scheduled to form the contact hole in the figure above; form a contact hole in the upper hole T as a cover, and etch the inner dielectric layer to expose the remaining stopper. In the inner dielectric layer above the gate, it is 4 to the surface of the stop layer; and the patterned photoresist is removed. Record μ + make the contact hole in silicidation as described in item 25 of the patent application scope. ^ ^ 'The step of removing the patterned photoresist is performed;', part of the etching stop layer in the contact hole Before the steps. 3 4 · The method for making contact holes above the silicon recording layer as described in item 25 of the scope of the patent application, wherein the step of removing the patterned photoresist is performed by removing part of the etching stop layer in the contact holes. After the steps. 0503-8384TWF (N); TSMC2002-0297: Felicia.ptd page 24