TW559964B - Method for designing a redistribution layer of a flip chip - Google Patents
Method for designing a redistribution layer of a flip chip Download PDFInfo
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- TW559964B TW559964B TW91117416A TW91117416A TW559964B TW 559964 B TW559964 B TW 559964B TW 91117416 A TW91117416 A TW 91117416A TW 91117416 A TW91117416 A TW 91117416A TW 559964 B TW559964 B TW 559964B
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
Description
559964 五、發明說明Q) # & ΐ發明是有關於一種1C設計中覆晶晶片（Flip Chip) 體輔ί ’且特別是有關於一種在電腦環境中操作’藉由軟 二=以解決人為錯誤，並減少驗證時間之覆晶晶片重配 罝的万法。 粂速5向度情報化社會的今日，多媒體應用的市場不斷地 Ζ迷，張著。積體電路封裝技術亦需配合電子裝置的數位 凋路化、區域連接化以及使用人性化的趨勢發展。為 处^上述的要求，必須強化電子元件的高速處理化、多功 :、積集化、小型輕量化及低價化等多方面的要求，於 =二體電路封裝技術也跟著朝向微型化、高密度化發展。、 所明積體電路封裝密度所指的是單位面積所含有腳位 (fin)數目多寡的程度。對於高密度積體電路封裝而言， ^ 電路與封裝基材間配線的長度，將有助訊號傳遞 姑4t 乂提昇，是以藉由凸塊（Bump)作為訊號傳遞之覆晶封 咸技f已漸成為高密度封裝的主流。 ,士構=繪示為引線接合封裝結構（左圖）&覆晶封裝 ·(右圖）之不意圖。以最常見的引線接合晶片（wire b=nvflr!ichip)為例，其上的焊墊（b〇nd pad)通常為周圍 ^里^(peripheral type)，經由引線電性連結至封裝 二板上的引線接合墊；而覆晶晶片（flip chip)上的銲^ ump pad)則通㊆是以陣列方式（array 排列，萨 ，塊（bump j電性連結至封裝基板上的凸塊接合墊。由^ 晶封裝技術已漸漸成為主流趨#，故越來越多❸產品將^559964 V. Description of the invention Q) # & ΐ Invention is about a flip chip chip in 1C design, and especially about a kind of operation in a computer environment. Errors and reduction of verification time for flip chip reconfiguration. In today's fast 5-dimensional information society, the market for multimedia applications is constantly becoming a fan. The integrated circuit packaging technology also needs to cooperate with the trend of digital withering, regional connection, and user-friendly development of electronic devices. In order to meet the above requirements, it is necessary to strengthen the high-speed processing of electronic components, multi-function: accumulation, miniaturization, weight reduction, and low cost. The two-body circuit packaging technology is also moving toward miniaturization, High-density development. The package density of the integrated circuit refers to the degree of the number of pins (fin) contained in a unit area. For high-density integrated circuit packaging, the length of the wiring between the circuit and the packaging substrate will help to improve the signal transmission by 4t. It is a flip-chip encapsulation technique using bumps as signal transmission. Has gradually become the mainstream of high-density packaging. The structure is shown as the intention of the wire bonding package structure (left) & flip-chip package (right). Taking the most common wire bonding chip (wire b = nvflr! Ichip) as an example, the bond pads thereon are usually peripheral types, and are electrically connected to the second packaging board via wires. The wire bonding pads on the flip chip are generally connected to the bump bonding pads on the package substrate by an array (bump j). Since ^ crystal packaging technology has gradually become the mainstream trend, so more and more products will be ^
559964559964
五、發明說明（2) 採用覆晶技術的方式進行封裝，然而為了封裝型態的改變 而一併更改既有產品的晶片設計，並不符合經濟原則，因 此在此一封裝型態改變的過渡時期發展出焊墊重配置技 術’藉由在原來引線接合晶片表面設置一重配置線路声 (Re-Distributing Layer; RDL)，將引線接合晶片銲墊之 周圍分佈型態進行重配置，使其成為覆晶晶片銲墊之陣列 分佈的型態，以配置覆晶封裝所需之凸塊。在重配置線路 層之凸塊配置的過程中’係先將原本引線接合晶片上之部 份線路層（即最頂層線路）移除，之後再形成1至2層之重 配置線路層於晶片的表面’以將輸入/輸出緩衝電路（I / 〇 buffer circuits)重新配置’完成表面具有多個凸塊之覆 引線接合晶片及覆晶晶片的電路佈局（Circui t layout)均各已有專屬之電腦軟體輔助設計，然而目前對 於原引線接晶片重配置成覆晶晶片的過渡時期之設計需求 (即覆晶晶片以RDL方式實現），並無任何專門的1C Layout輔助設計工具，第1B圖繪示為習知以「人為指派 (Manual-Assignment )」方式進行覆晶晶片重配置線路 層之凸塊配置設計流程方塊示意圖。請參照第1 β圖，習知 覆晶晶片進行重配置設計主要包括：產生重配置線路層 (1〇〇)、人為鍵入輸入/輸出緩衝電路之訊號名稱（丨〇2)、 人為指派凸塊焊墊與輸入/輸出緩衝電路之間的對應關係 (1 0 4) ’以及佈局與線路設計之間的驗證（丨〇 6)等步驟。 在產生重配置線路層（1 〇 〇 )的步驟中，重配置線路層V. Description of the invention (2) Packaging is performed by flip-chip technology. However, it is not in line with economic principles to change the chip design of existing products in order to change the packaging type. Therefore, the transition of this packaging type change Developed a pad relocation technology during the period. 'Re-Distributing Layer (RDL) was installed on the surface of the original wire bond wafer to reconfigure the distribution pattern around the wire bond wafer pads. The array distribution pattern of die bonding pads to configure bumps required for flip-chip packaging. In the process of reconfiguring the bumps of the reconfiguration circuit layer, 'the first part of the wiring layer (ie the topmost circuit) on the original wire bonding wafer is removed, and then the reconfiguration circuit layer of 1 to 2 layers is formed on the wafer. Surface 'to reconfigure input / output buffer circuits' (I / Obuffer circuits)' Complete wire-bonded wafers with multiple bumps on the surface and circuit t layout of flip-chip wafers have their own dedicated computers Software-assisted design. However, the current design requirements for the transition period when the original wire-bond chip is reconfigured to a flip-chip chip (ie, the flip-chip chip is implemented in RDL mode) do not have any special 1C Layout auxiliary design tools. A block diagram of a bump configuration design process for flip chip reconfiguration circuit layer in a "Manual-Assignment" manner. Please refer to Figure 1 β. The conventional flip chip design for reconfiguration mainly includes: generating a reconfiguration circuit layer (100), manually inputting the signal name of the input / output buffer circuit (丨 〇2), and manually assigning bumps. Correspondence between the pad and the input / output buffer circuit (104), and verification between the layout and the circuit design (丨 〇6). In the step of generating a reconfiguration line layer (100), the line layer is reconfigured
9183twf.ptd 第5頁 559964 五、發明說明（3) 表面配置有多個以陣列方式排列之凸塊焊墊，且凸塊焊墊 之間的間距（pi tch)依覆晶晶片及封裝基材設計之需求而 定。 在人為鍵入輸入/輸出緩衝電路（I/O buffer circuit)之訊號名稱（net name) (102)的步驟中，由於凸 塊銲墊的訊號名稱是由對應的輸入/輸出緩衝電路之訊號 名稱決定，因此，這個步驟係以人為的方式先於原各引腳 接合銲墊（bond pad)範圍内鍵入其個別之輸入/輸出緩衝 電路的訊號名稱9183twf.ptd Page 5 559964 V. Description of the invention (3) The surface is provided with a plurality of bump pads arranged in an array, and the pitch (pi tch) between the bump pads depends on the wafer and the packaging substrate Design requirements. In the step of manually typing the net name (102) of the I / O buffer circuit, the signal name of the bump pad is determined by the signal name of the corresponding input / output buffer circuit. Therefore, this step is to manually input the signal name of its individual input / output buffer circuit in the range of the original bond pads.
在於凸塊焊墊與輸入/輸出緩衝電路之間拉線（1〇4)的 步驟中，主要是將上述已鍵入有輸入/輸出緩衝電路（1/〇 bu f f er )訊號名稱之引腳接合銲墊藉由人為指派拉線的方 式與其對應之凸塊銲墊連接，通常在選擇對應之凸塊銲墊 時’會選擇距離其輸入/輸出緩衝電路最近的凸塊銲墊， 以f覆晶晶片具有良好的電氣特性。而在拉線之後，接著 便是進打佈局（lay〇ut)與線路設計之間的驗證（1〇6)步 驟0 ¥ =以人為方式進行覆晶晶片重配置線路層之凸塊配 置時，會有下列缺點： # 三胃找马方式鍵入輸入/輸出緩衝電路之訊號名稱 w ’谷易發生錯誤。 路 錯 夕門如始ί &派方式進行凸塊焊塾與輸入/輸出緩衝電 之間拉線時， ，而n亚無法正確判斷線與線之間是否易於交 …、法判斷線距是否最短。In the step of pulling a wire (104) between the bump pad and the input / output buffer circuit, the above-mentioned pin bonding with the input signal name of the input / output buffer circuit (1 / 〇bu ff er) is mainly bonded. The pads are connected to their corresponding bump pads by means of manually assigned pull wires. Usually, when selecting the corresponding bump pads, 'the bump pads closest to its input / output buffer circuit will be selected, and the chip will be covered with f. The wafer has good electrical characteristics. After the wire is drawn, it is followed by the verification between the layout (layout) and the circuit design (106). Step 0 ¥ = When the bump configuration of the flip chip reconfiguration circuit layer is artificially performed, There will be the following disadvantages: # Entering the signal name of the input / output buffer circuit in the way of “three stomachs looking for horses” w 'gu is prone to errors. When the road is wrong, when you pull the wire between the bump welding pad and the input / output buffer, you cannot determine whether the line is easy to intersect ... The shortest.
9183twf.ptd 559964 五、發明說明（4) ----- 3. 習知以人為鍵入輸入/輸出緩衝電路之訊號名稱將 耗費相當多的時間，此亦直接反映於成本上。 4. 凸塊銲墊重新指派（Re_assignment)不易，且會耗 費拫多時間。 因此’本發明的目的係針對晶片重配置線路層設計的 =作方法’提出於電腦環境中藉由軟體輔助以解決人為錯 誤，並減少驗證時間之覆晶晶片重配置線路層之凸塊配置 方法。 為達本發明之上述目的，提出一種覆晶晶片重配置線9183twf.ptd 559964 V. Description of the Invention (4) ----- 3. It will take a considerable amount of time to learn the input signal name of the input / output buffer circuit by human, which is also directly reflected in the cost. 4. Re-assignment of bumps is not easy and takes much time. Therefore, the “object of the present invention is a method for designing a reconfiguration circuit layer of a wafer” and proposes a bump configuration method for a flip-chip wafer reconfiguration circuit layer in a computer environment with software assistance to resolve human errors and reduce verification time. . In order to achieve the above object of the present invention, a flip-chip wafer reconfiguration line is proposed.
路層之凸塊配置方法，適於將一原是引線接合形式之晶片 上之所有訊號引線銲墊（b〇nd pad)重配置成一覆晶晶片形 式之訊说凸塊銲塾（bUmp pa(i)，其中該晶片上具有複數個 線接口形式之周圍分佈型態的輸入/輸出緩衝電路，此 設計方法係藉由電腦軟體全程輔助，主要步驟包括產生重 ^置線路層、建立凸塊銲墊的座標列表、建立輸入/輸出 緩衝電路之線路連接列表（包括其座標及訊號名稱）、建 立輪入/輸出緩衝電路符號及凸塊銲墊符號、設定環境及 1性三進行自動指派產生輸入/輸出緩衝電路符號及凸塊 ^〒塾符號之間的連結關係、於凸塊銲墊與輸入/輸出緩衝The bump configuration method of the road layer is suitable for reconfiguring all signal pads on a wafer that was originally in the form of wire bonding into a bump bump (bUmp pa ( i), where the chip has a plurality of input / output buffer circuits in the form of peripheral interfaces in the form of a wire interface. This design method is assisted by computer software. The main steps include generating a reset circuit layer and establishing bump bonding. List of coordinates of pads, list of line connections to establish input / output buffer circuits (including their coordinates and signal names), establishment of round-in / out buffer circuit symbols and bump pad symbols, setting of environment and nature The connection relationship between the symbol of the output / output buffer circuit and the bump ^ 〒 塾 symbol, the bump pad and the input / output buffer
電路之間進行佈局、以及進行佈局與線路設計之間的驗證 等步驟。 本發明中，覆晶晶片進行重配置線路層之凸塊配置時 所使用的軟體例如為APD (Advanced Package g eF) ’或是其他具有建立符號（create symbol)、產Layout between circuits and verification between layout and circuit design. In the present invention, the software used for the bump configuration of the flip-chip chip for the reconfiguration circuit layer is, for example, APD (Advanced Package g eF) ′ or other software having a create symbol,
c)183twf .ptd 第7頁 D9964 五、發明說明（5) 生鼠線（generate rat_line)、自動指派 (auto assignment)、檔案匯入/ 匯出（imp〇rt/eXp0rt)等 功能^本發明主要係藉由軟體在進行自動指派時產生鼠線 的功此來輔助凸塊銲墊與輸入/輸出緩衝電路之間佈局的 ，仃’其中，鼠線可以避免習知人為鍵入訊號名稱的錯 誤’且可進一步縮短後續佈局與線路設計之間驗證的時 間。此外，本發明可藉由軟體可以很快速地進行重新指派 的動作。 ^為讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 圖式之標示說明： 1 0 0〜1 0 6 ·習知覆晶晶片重配置線路層之凸塊配置之 步驟 重配置線路層 凸塊銲墊 凸塊銲墊符號 晶片 輸入/輸出緩衝電路符號 訊號凸塊銲墊與輸入/輸出緩衝電路之間的佈局 200〜216 :本實施例覆晶晶片重配置線路層之凸 置之步驟 300 302 402 400 404 406 較佳實施例 本實施例主要是將引線接合晶片（wire bondingc) 183twf.ptd Page 7 D9964 V. Description of the invention (5) Functions such as generate rat_line, auto assignment, file import / export (imp〇rt / eXp0rt), etc. The software assists the layout between the bump pads and the input / output buffer circuit by the software that generates the mouse wire during the automatic assignment. 仃 'Among them, the mouse wire can avoid the mistake of manually typing the signal name' and Can further reduce the time between subsequent layout and circuit design verification. In addition, the present invention can perform reassignment operations very quickly by software. ^ In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Symbols of the drawings: 1 0 0 ~ 1 0 6 · Know the steps for reconfiguring the bump configuration of the flip chip. Reconfigure the wiring layer bump pads. The bump pad symbols are the chip input / output buffer circuits. Symbol signal pad pads and input / output buffer circuits. The layout between 200 to 216: the step of repositioning the bumps of the flip-chip wafer in this embodiment 300 302 402 400 404 406 The preferred embodiment This embodiment is mainly a wire bonding wafer
9183twf.ptd 第8頁 559964 五、發明說明（6) ch i p )重配置成覆晶晶片（f 1 i p ch i p )，在重配置線路層之 凸塊配置的過程中，係先將引線接合晶片上之部份線路層 (即最頂層線路）移除，之後再形成1至2層之重配置線路 層（Re- Distribution Layer，RDL)於原先的引線接合晶 片，以完成具有多個凸塊銲墊之覆晶晶片。 本實施例在覆晶晶片進行重配置線路層之凸塊配置時 所使用的軟體例如為APD(Advanced Package Designer)軟 體，其具有建立符號（create symbol)、產生鼠線 (generate rat - line)、自動指派（auto - ass i gnment )、檔 案匯入/匯出（import/export)等功能，該APD軟體原本是 專門用於IC封裝基板設計。然而，本實施例下述雖以APD 軟體進行說明，但本實施例之覆晶晶片重配置線路層之凸 塊配置方法所搭配使用的軟體並非限定於APD軟體，其他 具有相同或近似功能之軟體亦可與本發明之方法搭配使 用。 本實施例係針對原是引線接合形式晶片上之所有訊號 引線銲墊上之輸入/輸出緩衝電路，重配置成一覆晶晶片 形式之訊號凸塊銲墊（signal bump pad)，其中該晶片上 具有複數個引線接合形式之周圍分佈型態的輸入/輸出緩 衝電路，將被重配置成覆晶晶片陣列形式銲墊之最外圍的 訊號凸塊鋅塾。 第2圖繪示為依照本發明一較佳實施例以軟體輔助方 式進行覆晶晶片重配置線路層之訊號凸塊配置的流程方塊 示意圖。本實施例覆晶晶片重配置線路層之訊號凸塊配置9183twf.ptd Page 8 559964 V. Description of the invention (6) ch ip) is reconfigured into a flip chip (f 1 ip ch ip). In the process of reconfiguring the bump configuration of the circuit layer, the wire is bonded to the wafer first. Part of the upper circuit layer (ie, the topmost circuit) is removed, and then a re-distribution layer (RDL) of 1 to 2 layers is formed on the original wire bonding wafer to complete the bonding with multiple bumps. Flip-chip wafer. The software used in the present embodiment when performing bump configuration for the reconfiguration circuit layer of the flip-chip wafer is, for example, APD (Advanced Package Designer) software, which has create symbol, generate rat-line, Automatic assignment (auto-ass gnment), file import / export (import / export) and other functions, the APD software was originally designed for IC package substrate design. However, although the APD software is used in the following description of this embodiment, the software used in the bump arrangement method of the flip chip reconfiguration circuit layer of this embodiment is not limited to the APD software, and other software having the same or similar functions It can also be used in conjunction with the method of the present invention. In this embodiment, the input / output buffer circuits on all signal lead pads on a wafer that is originally wire-bonded are reconfigured into a signal bump pad in the form of a flip-chip. The wafer has a plurality of An input / output buffer circuit of a wire bonding type with a distributed pattern around it will be reconfigured into the outermost signal bump zinc bump of a flip chip array pad. FIG. 2 is a schematic block diagram of a signal bump configuration of a flip chip reconfiguration circuit layer in a software-assisted manner according to a preferred embodiment of the present invention. Signal bump configuration of the flip chip reconfiguration circuit layer in this embodiment
9183twf.ptd9183twf.ptd
第9頁 559964 五、發明說明（7) 方法主要包括：產生重配置線路層並列出凸塊銲墊的座標 (200)、建立輸入/輸出緩衝電路之線路連接列表（202)、 建立輸入/輸出緩衝電路符號及凸塊輝塾符號（204)、匯入 線路連接列表於軟體中（ 206 )、設定環境及屬性（208 )、自 動指派（210)、於凸塊銲墊與輸入/輸出缓衝電路之間進行 佈局（21 2 )、槽案匯出（2 1 4 )，以及佈局與線路設計之間的 驗證（216)等步驟。 第3圖繪示為依照本發明一較佳實施例重配置線路層 中凸塊焊墊分佈的示意圖。請同時參照第2圖與第3圖，產 生重配置線路層並列出凸塊銲墊的座標（2 〇 〇 )的步驟中， 所產生的重配置線路層3〇〇中，其凸塊銲墊3〇2分佈如第3 圖所繪示’各凸塊銲墊3〇2的座標（coordinate)能提供APD 軟體建立凸塊銲墊的位置。 ^ 請參照第2圖，在產生重配置線路層並列出凸塊銲塾 的座標（200)之後，接著建立輸入/輸出緩衝電路與凸塊銲 墊之線路連接列表（2〇2)，提供APD軟體模擬出晶片上輸入 /輸出緩衝電路，以建立輸入/輸出緩衝電路的位置。此步 驟中’輸入/輸出緩衝電路之線路連接列表主要是依據晶 片上之輸入/輸出緩衝電路而建立。其中，輸入/輪出緩Βθ 電路之線路連接列表（net_list)係為一文字檔，用以表示 輸入^輸出緩衝電路之位置及其訊號名稱（net name)。 第4圖繪示為依照本發明一較佳實施例凸塊焊墊符號 與輸入/輸出緩衝電路符號的示意圖。請同時參照第2圖〜與 第4圖，在建立凸塊銲墊座標與輸入/輸出緩衝電路之線路Page 9 559964 V. Description of the invention (7) The method mainly includes: generating a reconfiguration circuit layer and listing the coordinates of the bump pads (200), establishing a line connection list (202) of the input / output buffer circuit, and establishing input / output Buffer circuit symbols and bump fascia symbols (204), import line connection list in software (206), setting environment and attributes (208), automatic assignment (210), in bump pads and input / output buffering Layout (21 2), slot case export (2 1 4), and verification between the layout and circuit design (216) are performed between the circuits. Fig. 3 is a schematic diagram showing the distribution of bump pads in a circuit layer according to a preferred embodiment of the present invention. Please refer to FIG. 2 and FIG. 3 at the same time, in the step of generating a reconfiguration circuit layer and listing the coordinates (200) of the bump pads, in the generated reconfiguration circuit layer 300, the bump pads thereof The 3202 distribution is shown in Figure 3. 'The coordinates of each bump pad 302 can provide the location of the bump pads by the APD software. ^ Please refer to Figure 2, after generating the reconfiguration circuit layer and listing the coordinates of the bump pads (200), then establish the line connection list (200) of the input / output buffer circuit and the bump pads, and provide the APD The software simulates the input / output buffer circuit on the chip to establish the position of the input / output buffer circuit. The line connection list of the 'input / output buffer circuit' in this step is mainly based on the input / output buffer circuit on the chip. Among them, the line connection list (net_list) of the input / round-out slow Bθ circuit is a text file used to indicate the position of the input ^ output buffer circuit and its signal name (net name). FIG. 4 is a schematic diagram of a bump pad symbol and an input / output buffer circuit symbol according to a preferred embodiment of the present invention. Please refer to Figure 2 to Figure 4 at the same time to establish the bump pad coordinates and the input / output buffer circuit.
9183twf.ptd 第10頁 5599649183twf.ptd Page 10 559964
連接列表（202)之後，接著進行建立輸入/輸出緩衝 號及凸塊銲墊符號（204)，用以代表晶片上輸入/輸出^ 電路及抑1^表面之凸塊銲塾，晶片4〇〇上之凸塊銲墊符號衡 4〇2與輸入/輸出緩衝電路符號4〇4的分佈情況如第彳圖^洛 示，通常輸入/輸出緩衝電路係分佈於晶片的周圍，而凸θ 塊銲墊則是以陣列方式分佈於晶片上。純，匯入線 接列表於APD軟體中（206)，將原是文字檔的線路連接列 轉成APD軟體接受的形式，使前述之輸人/輸出緩衝電 唬能對應於線路連接列表中的位置及訊號名稱。 眷 請參照第2圖，接著進行設定環境及屬性（2〇8)、自動 指派（210)，以及於凸塊銲墊與輸入/輸出緩衝電路之間進 行佈局（212)等步驟。在自動指派（21〇)的過程中，ApD軟 體會根據不同位置的輸入/輸出緩衝電路符號4〇4而自動選 擇與其相對應之訊號凸塊銲墊符號4〇2並定義之。此外， 在，動指派（210)的過程中，由於ApD軟體具有產生鼠線的 功能，將相對應之輸入/輸出緩衝電路符號及訊號凸塊銲 ^符號以線相連，故其在進行自動指派之後，鼠線可以用 來輔助凸塊銲墊與輸入/輸出緩衝電路之間佈局的進行。 第5圖繪示為依照本發明一較佳實施例凸塊焊墊與輸 入/輸出緩衝電路之間經過拉線佈局之後的示意圖。請同 時，，第2圖與第5圖，在自動指派（2丨〇 )之後，於凸塊銲 塾符號與輸入/輸出緩衝電路符號之間產生最短距離且相 對應的鼠線’接著進行凸塊銲墊與輸入/輸出緩衝電路之 間的佈局（21 2 )步驟。此步驟中，凸塊銲墊與輸入/輸出緩After the connection list (202), the next step is to create an input / output buffer number and a bump pad symbol (204), which are used to represent the input / output circuit on the wafer and the bump pads on the surface, and the wafer is 400. The distribution of the bump pad symbol 402 and the input / output buffer circuit symbol 404 is as shown in Fig. ^. Generally, the input / output buffer circuit is distributed around the wafer, and the convex θ block soldering The pads are distributed on the wafer in an array. Pure, import the connection list in the APD software (206), and convert the line connection list that was originally a text file into a form accepted by the APD software, so that the aforementioned input / output buffer can be corresponding to the line connection list. Location and signal name. Please refer to Figure 2 and proceed with setting the environment and attributes (208), automatic assignment (210), and layout (212) between the bumps and the I / O buffer circuits. In the process of automatic assignment (21), ApD software will automatically select and define the corresponding signal pad pad symbol 402 according to the input / output buffer circuit symbol 4 of different positions. In addition, in the process of dynamic assignment (210), since the ApD software has a function of generating rat wires, the corresponding input / output buffer circuit symbols and signal bump soldering symbols are connected by lines, so it is performing automatic assignment. Later, the mouse wire can be used to assist the layout between the bump pad and the input / output buffer circuit. FIG. 5 is a schematic diagram showing a wire layout between a bump pad and an input / output buffer circuit according to a preferred embodiment of the present invention. At the same time, in Figures 2 and 5, after the auto-assignment (2 丨 〇), the shortest distance between the solder bump symbol and the input / output buffer circuit symbol and the corresponding mouse line are generated. Layout (21 2) step between the block pad and the input / output buffer circuit. In this step, the bumps and I / O buffers
559964 五、發明說明（9) 衝電路之間的佈局4 0 6仍然係以人為拉線的方式進行拉 線’然而，因為已有可參考的鼠線產生，故可迅速的佈局 拉線’並可以選擇性地將部份關鍵的線路（trace)進行調 整’以將線路電氣特性的佈局最佳化。其中上述選擇性調 整部份關鍵線路的步驟，亦可在匯入線路連接列表（2 〇 6) 之前先進行特定關鍵線路的人為指派，使得之後匯入的線 路連接列表中略過已先被指派過的符號，故之後自動指派 時可避開已被指派的特定關鍵線路。559964 V. Description of the invention (9) The layout between the punched circuits 4 0 6 is still drawn by artificial cables. However, because a referenced rat line has been generated, the cables can be quickly laid out. You can optionally adjust some key traces to optimize the layout of the electrical characteristics of the lines. The above steps for selectively adjusting some key lines can also be artificially assigned to specific key lines before importing the line connection list (206), so that the line connection list imported later is skipped and has been assigned first. Symbol, so you can avoid specific key lines that have already been assigned during automatic assignment.
請參照第2圖，接著進行檔案匯出（2 1 4 )的動作，由於 本實施例中所使用的軟體為APD軟體，其可將佈局之後的 播案匯出，並匯入至一般晶片佈局之軟體如VIRTUS〇s中來 產生所需的圖檔。 請參照第2圖，最後進行佈局與線路設計之間的驗證 (2! 6)，由於本發明主要係藉由ApD軟體進行自動指派，自 動指派的同時會產生鼠線，輔助凸塊銲墊與輸入/輸出緩 衝電路之間佈局的進行，因此，自動指派可以避免習知人 為鍵入訊號名稱的錯誤，而鼠線可以使佈局拉線迅速，且 ，免拉錯凸塊銲墊，所以可進一步縮短後續佈局與線路設 =之間驗證的時間。此外，本發明藉由軟體可以很快速地 進行重新指派的動作，一般來說，若對於原本完全人為操 作的方式需一天工時的工作，則應用本發明所提供的方式 可在一小時内完成。 乡上所述，本發明覆晶晶片重配置線路層之凸塊配置 方法至少具有下列優點：Please refer to FIG. 2 and then perform the file export (2 1 4) operation. Since the software used in this embodiment is APD software, it can export the post-layout project and import it into the general chip layout. Software such as VIRTUS0s to generate the required image files. Please refer to Figure 2 for the final verification between the layout and the circuit design (2! 6). Since the present invention mainly uses the ApD software for automatic assignment, the automatic assignment will also generate rat lines and assist the bump pads and The layout between the input / output buffer circuits is carried out. Therefore, the automatic assignment can avoid the mistake of manually typing the signal name, and the mouse wire can make the layout pull quickly, and the bump pads without pulling the wrong can be further shortened. Verification time between subsequent layouts and line settings. In addition, the present invention can perform reassignment actions very quickly by software. Generally speaking, if one day's work is required for the originally completely manual operation, the method provided by the present invention can be completed within one hour. . As mentioned above, the bump arrangement method of the flip chip reconfiguration circuit layer of the present invention has at least the following advantages:
559964 五、發明說明（ίο) 1 ·本發明覆晶晶片重配置線路層之凸塊配置方法解決 了習知必須鍵入訊號名稱（n e t n a m e )到凸塊銲塾之人為錯 誤0 2 ·本發明覆晶晶片重配置線路層之凸塊配置方法中， 不但凸塊銲墊指派的時間大幅縮短，且能夠很快地完成凸 塊銲墊的座標配置。 3 ·本發明覆晶晶片重配置線路層之凸塊配置方法中， 凸塊~塾的重新指派（Re —assignment)十分容易、省時。559964 V. Description of the invention (1) 1. The bump configuration method of the chip reconfiguration circuit layer of the present invention solves the human error of having to type the signal name (netname) into the bump solder joint 0 2 · The flip chip of the present invention In the bump reconfiguration method of the wafer reconfiguration circuit layer, not only the time for assigning the bumps is greatly shortened, but also the coordinate configuration of the bumps can be completed quickly. 3. In the bump arrangement method of the flip chip reconfiguration circuit layer of the present invention, the reassignment of the bumps to 塾 is very easy and time-saving.
此外’凸塊銲墊的重新指派後，基材佈局（Substrate Layout)方面可以很快地配合修改。 4.本發明覆晶晶片重配置線路層之凸塊配置方法中， 鼠線可以降低人為拉線的錯誤率，進而減少與佈局與線路 設計之間（Layout Versus Schematic，LVS)的驗證時間。 5 ·本發明覆晶晶片重配置線路層之凸塊配置方法中， 可先設定好設計方法（Design Rule)，以減少設計方法驗 證（Design Rule Check，DRC)的時間。 6 ·本發明覆晶晶片重配置線路層之凸塊配置方法可以 大幅減少重配置的時間。In addition, after the re-assignment of the 'bump pads', the substrate layout can be modified quickly. 4. In the bump allocation method of the flip chip reconfiguration circuit layer of the present invention, the mouse line can reduce the error rate of the artificial pull line, thereby reducing the verification time between the layout and the circuit design (Layout Versus Schematic, LVS). 5. In the bump arrangement method of the flip chip reconfiguration circuit layer of the present invention, a design rule (Design Rule) can be set first to reduce the time for design rule check (DRC). 6. The bump arrangement method of the flip chip reconfiguration circuit layer of the present invention can greatly reduce the reconfiguration time.
雖然本發明已以一較佳實施例揭露如上，缺其並非用 t限定本發明，任何熟習此技藝者’在不脫離本發明之精 神和範圍内，當可作各種之更動與潤飾，因此本發明之保 蠖範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed as above with a preferred embodiment, it does not limit the present invention by t. Anyone skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The protection scope of the invention shall be determined by the scope of the attached patent application.
559964 圖式簡單說明 第1A圖繪示為引線接合封裝結構及覆晶接合封裝結構 之示意圖； 第1 B圖繪示為習知以人為方式進行覆晶晶片重配置線 路層之凸塊配置的流程方塊示意圖； 第2圖繪示為依照本發明一較佳實施例以軟體輔助方 式進行覆晶晶片重配置線路層之凸塊配置的流程方塊示意 圖， 第3圖繪示為依照本發明一較佳實施例重配置線路層 中凸塊焊墊分佈的示意圖； 第4圖繪示為依照本發明一較佳實施例凸塊焊墊符號 與輸入/輸出緩衝電路（I/O Buffer)符號的示意圖；以及 第5圖繪示為依照本發明一較佳實施例凸塊焊墊與輸 入/輸出緩衝電路（I/O Buff er)之間經過拉線之後的示意 圖0559964 Brief Description of the Drawings Figure 1A shows a schematic diagram of a wire bonding package structure and a flip-chip bonding package structure; Figure 1B shows a process for manually configuring the bump configuration of a flip-chip wafer reconfiguration circuit layer. Block diagram; Figure 2 shows a block diagram of a bump configuration of a flip-chip wafer reconfiguration circuit layer in a software-assisted manner according to a preferred embodiment of the present invention. Figure 3 shows a preferred block diagram according to the present invention. The schematic diagram of the bump pad distribution in the reconfiguration circuit layer according to the embodiment; FIG. 4 is a schematic diagram of the bump pad symbol and the input / output buffer circuit (I / O Buffer) symbol according to a preferred embodiment of the present invention; And FIG. 5 is a schematic diagram after a wire is drawn between a bump pad and an input / output buffer circuit (I / O buffer) according to a preferred embodiment of the present invention.
9l83twf.ptd 第14頁9l83twf.ptd Page 14
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW91117416A TW559964B (en) | 2002-08-02 | 2002-08-02 | Method for designing a redistribution layer of a flip chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW91117416A TW559964B (en) | 2002-08-02 | 2002-08-02 | Method for designing a redistribution layer of a flip chip |
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| Publication Number | Publication Date |
|---|---|
| TW559964B true TW559964B (en) | 2003-11-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW91117416A TW559964B (en) | 2002-08-02 | 2002-08-02 | Method for designing a redistribution layer of a flip chip |
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| TW (1) | TW559964B (en) |
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2002
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