TW559806B - Interface command architecture for synchronous flash memory - Google Patents

Abstract

A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device comprises an array of non-volatile memory cells, and a command register to store command data used to control flash memory operations. In operation, the command register is loaded by initiating a command register load operation using a predefined combination of a column address strobe (CAS#) signal, a row address strobe (RAS#) signal, and a write enable (WE#) signal.

Description

559806 A7 V. Description of the Invention (丨) The present invention relates generally to non-dependent memory devices, and in particular, the present invention relates to a synchronous non-dependent flash memory. The skeletal device of the present invention is typically provided as an internal storage area in a computer. The term memory system indicates the storage of data in the form of integrated circuit chips. There are several different types of memory. One type is ram (random access memory). This system is typically used as the main memory in a computer environment. RAM refers to reading and writing to memory; in other words, data can be written to and read from RAM. This is relative to ROM which only allows reading data. Most RAMs are electrical. This means that they need a stable current to maintain their contents. Once the power is turned off, whatever data is in the RAM is lost. Computers almost always contain a small amount of read-only memory (ROM), which holds instructions for turning on the computer. Unlike RAM, ROM cannot be written. EEPROM (Electrically Erasable Programmable Read-Only Memory) is a special type of non-Electrical ROM that can be erased by exposing it to a charge. Like other types of ROM, EEPROM has traditionally not been as fast as RAM—as fast. EEPROM consists of a large number of memory cells with electrically isolated gates (floating gates). The data is stored in the memory cell in the form of a charge above the floating gate. Charges are transferred to and removed from the floating gates by being programmed and erased separately. 3 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ----------- installation -------- order --------- (Please read the precautions on the back before filling out this page) 559806 B7 Jade, Invention Description (/) However, another type of non-electrical memory system is flash memory. The flash memory system is a type of EEPROM that can be erased and reprogrammed in blocks, rather than one byte at a time. Many modern PCSs have their BIOS stored on a flash memory chip, allowing them to be easily upgraded if necessary. This type of BIOS is sometimes called flash BIOS. Flash memory systems are commonly used in modems because they enable modem manufacturers to support new protocols that have become standardized. A typical flash memory system includes a memory array that contains a large number of memory cells arranged in columns and rows. Each of these memory cells contains a floating gate field effect transistor capable of holding a charge. These outstanding units are usually grouped into blocks. Each of the cells in a block can be electrically programmed on a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is judged by the presence or absence of the charge in the floating gate. Synchronous DRAM (SDRAM) is a type of DRAM that can execute at a faster clock speed than a conventional DRAM memory. SDRAM synchronizes itself with the bus of a CPU, and can execute under 100MHZ, which is about three times faster than the conventional FPM (Fast Page Mode) RAM, and is about a fast EDO (Extended Data Output) DRAM And BED0 (bunch burst data output) DRAM twice. SDRAM can be accessed quickly, but is electrically dependent. Many computer systems are designed to operate with SDRAM, but will benefit from non-dependent memory. 4 This paper size applies to China National Standard (CNS) A4 (210 X 297 public love) —I --------------- Order --------- (please first Read the notes on the back and fill in this page) 559806 A7 _ B7__________ V. Description of the Invention (Clever) For the reasons mentioned above and because of the others described below, it will become clear to those skilled in the art when reading and understanding this manual. For this reason, there is a need in this technology for a non-electronic memory device capable of operating in a manner similar to SDRAM operation. Summary of the Invention The above-mentioned problems concerning the memory device and other problems are dealt with by the present invention, and will be understood by reading and studying the following description. In one embodiment, the present invention provides a non-electrical synchronous flash memory, which is compatible with the current SDRAM package pin configuration. It will be apparent from reading the detailed description that a system designer with knowledge of SDRAM applications can easily implement the present invention to improve system operation. In one embodiment, a synchronous flash memory device includes an array of non-electrical memory cells and a command register to store command data used to control the actions of the flash memory. The command register can be loaded using a load command register operation mode. The load command register operation mode uses a row address strobe (CAS #) signal of a predefined combination, A column address strobe (RAS #) signal and a write enable (WE #) signal are initiated. In another embodiment, a synchronous flash memory device includes an array of non-dependent memory cells and a command register to store data commands used to control flash memory operations. The order register 5 ----------- install " ------- order ------- (Please read the precautions on the back before filling this page) The dimensions are applicable to China National Standard (CNS) A4 specifications (210 X 297 public love) 559806 A7 _____ V. Description of the invention (fire) is coupled to respond to a load command to receive the command data, which is equivalent to An update command for synchronous random random access memory (SDRAM). ~ A method for providing commands in a synchronous flash memory is also provided. The method includes starting with a predefined combination of a row address strobe (CAS #) signal, a column address strobe (RAS #) signal, and a write enable (WE #) signal. The command register loads an action, and in response to the command register loading action 'uses the address connection of the synchronous flash memory to load command data into the command register. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a block diagram of a synchronous flash memory according to the present invention; FIG. 1B is an interconnect diagram of integrated circuit pins according to an embodiment of the present invention; FIG. 1C is a block diagram of the present invention Figure 2 shows an integrated circuit interconnect bump grid array of an embodiment; Figure 2 depicts a mode register of an embodiment of the present invention; Figure 3 depicts a CAS delay read with one, two, and three clock cycles Take action; Figure 4 depicts a specific column activated in a bank of the memory of an embodiment of the present invention; Figure 5 depicts the timing between an active command and a read or write command ; Figure 6 depicts a read command; 6 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) --------- I --- Γ --- II ^ I I--I --- (Please read the notes on the back before filling out this page) 559806 A7 _B7 _ ^ _ V. Description of the Invention (4) Figure 7 depicts the continuous reading of one embodiment of the present invention. Timing: (Please read the notes on the back before filling this page) Figure 8 depicts an embodiment of the present invention Random read access within a page; Figure 9 depicts a read action followed by a write action; Figure 10 depicts a read that is terminated using a burst termination command according to an embodiment of the invention Burst action; Figure 11 depicts a write command; Figure 12 depicts a write followed by a read action; Figure 13 depicts a power saving action of an embodiment of the present invention; Figure 14 depicts a A clock pause during the burst reading period; FIG. 15 depicts a memory address mapping of an embodiment of a memory with two boot system areas; FIG. 16 illustrates a self according to an embodiment of the present invention Flow chart of timing write sequence; Figure Π is a flowchart of a complete write status check sequence according to an embodiment of the present invention; Figure 18 is a self-timed block erasure according to an embodiment of the present invention Sequence diagram; Figure 19 is a flowchart of a complete block erase status check sequence according to an embodiment of the present invention; Figure 20 is a flowchart of a block protection sequence according to an embodiment of the present invention Chengtu; 7 This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 559806 A7 __B7 V. Description of the invention (V) Figure 21 shows the complete block status according to one embodiment of the present invention Flow chart of the inspection sequence; (Please read the notes on the back before filling out this page) Figure 22 is a flowchart of the device protection sequence according to one embodiment of the present invention, and Figure 23 is an embodiment of the present invention Flow chart of the block removal protection sequence; Figure 24 depicts the timing of initialization and load mode register actions; Figure 25 depicts the timing of a clock pause mode action; Figure 26 depicts a burst read action Timing; Figure 27 depicts the timing of alternate library read access; Figure 28 depicts the timing of a burst read operation for a full page; Figure 29 depicts the timing of a burst read operation using a data mask signal Figure 30 depicts the timing of a write operation followed by a read to a different bank; and Figure 31 depicts the timing of a write operation followed by a read to the same bank. Main _ part of the brief description of representative symbols 100 memory device 102 flash memory unit 104, 106, 108, 110 memory bank II2 address register 1H column address multiplexer circuit National Standard (CNS) A4 specification (210 X 297 mm) 559806 A7 _B7 V. Description of the invention (to) 116 library control logic 118 column address latch and decoding circuit (Please read the precautions on the back before filling this page) 120 line address counter and latch circuit 122 line decoding circuit 124 circuit 126 data input register 128 data output register 130 command execution logic 132 state machine 133 command register 134 status register 136 identification register 140 Reset / power saving (RP #) connection 142 CS # 143 DQ0 to DQ15 connection 144 VCCP connection 145 high voltage switch / boost circuit 147 non-dependent mode register 148 electrically dependent mode register 150 memory Body package 152 RP # 154 Vccp 160 memory package This paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 559806 A7 ___B7__ 5. Description of the invention (g >) The detailed description of the invention is in this embodiment The following details In the detailed description, reference is made to the companion drawing of the part of the description, and it is shown by depicting a specific embodiment in which the present invention can be implemented. These embodiments are described in sufficient detail to enable those skilled in the art to implement the invention, and it will be understood that other embodiments may be utilized and logical, mechanical, and electrical changes may be made without departing from the invention Spirit and scope. The following detailed description is therefore not to be considered restrictively, and the scope of the present invention is only defined by the scope of patent applications. The following detailed description is divided into two main parts. The first part is an explanation of the interface functionality, which details the compatibility with an SDRAM memory. The second major part is an explanation of the functionality of the flash architecture function command. Description of Interface Functions With reference to FIG. 1A, a block diagram of an embodiment of the present invention is described. The memory device 100 includes an array of non-electronic flash memory cells 102. The array is configured with a plurality of addressable libraries. In one embodiment, the memory includes four memory banks 104, 106, 108, and Π0. Each memory bank contains addressable memory cell segments. The data stored in this memory can be accessed using the externally provided location address received by the address register II2. These addresses are decoded using the column address multiplexer circuit 1H. These addresses are also decoded using the library control logic 116 and the column address latch and decode circuit U8. In order to access 10 paper sizes, the Chinese National Standard (CNS) A4 specification is applicable (210 X 297). ------------------- Order ------- -(Please read the precautions on the back before filling this page) 559806 A7 ___-__B7__ V. Description of the invention (1) A proper line of memory, the line address counter and the latch circuit 120 are coupled to the received bits Address to line decoding circuit 122. Circuit 124 provides input / output gating, data mask logic, read data latch circuit, and write driver circuit. Data is input through the data input register 126 and output through the data output register 128. Command execution logic 130 is provided to control the basic actions of the memory device. A state machine 132 is also provided to control specific actions performed on the memory array and cells. A status register 134 and an identification register 136 may also be provided to output data. FIG. 1B depicts the interconnection pin configuration of an embodiment of the present invention. The memory package 150 has 54 interconnect pins. This pin configuration is substantially similar to the available SDRAM packages. Two interconnect systems RP # 152 and Vccp 154 unique to the present invention. Although the present invention may share the same interconnection symbols as SDRAM, the functions of the signals provided on such interconnections are described herein and should not be equivalent to the functions of SDRAM unless otherwise described herein. FIG. 1C depicts one embodiment of a memory package 160 having a bump connection instead of the pin connection of FIG. 1B. Therefore, the present invention is not limited to a specific package configuration. Before explaining the operating characteristics of the memory device, a more detailed description of the interconnect pins and their respective signals is provided. The input clock connection is used to provide a clock signal (CLK). The clock signal can be driven by a system clock, and the input signals of all synchronous flash memories are sampled above the positive edge of CLK. CLK also increments an internal burst counter and controls the output register. 11 Wood paper size applies to China National Standard (CNS) A4 (210x 297 mm) (Please read the precautions on the back before filling this page)

559806 A7 __B7 _____ 5. Description of the invention (The input clock enable (CKE) connection is used to activate (high state) and deactivate (low state) the CLK signal input. Deactivate the clock input system to provide "saving "Power" and "backup" actions (where all memory banks are idle), "effective power saving" (one of the memory banks in any bank is valid) or "clock pause" actions (in progress Burst / Access). Except after the device enters power saving mode, CKE is synchronous, and CKE becomes asynchronous until after leaving the mode. The input buffers including CLK are in the provincial The power mode is disabled during the power mode to provide low standby power. In systems where the power saving mode (except for RP # extreme power saving) is unnecessary, CKE can be maintained high. The chip selection ( The CS #) input connection provides a signal to enable (shown low) and disable (shown high) a command decoder that is set on the command execution logic. When CS # When displayed high, all command systems are obscured Furthermore, CS # provides library selection for external use on systems with multiple libraries, and CS # can be considered as part of the command code; but may not be necessary. Used for RAS #, CAS #, and The input connection of the input command of WE # (and CAS #, CS #) defines a command to be executed by the memory, as described below. The input / output mask (DQM) connection is used to provide Input mask signal for write access and an output enable signal for read access. When the DQM is sampled "high" during a "write" cycle, the input data is masked When the DQM is sampled "high" during a "read" cycle, the output buffer is placed in a high impedance (high Z) state (after a delay of two clocks ^ DQML corresponds to the data 12 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the notes on the back before filling this page) Order --------- 559806 A7 _B7___ V. Description of the invention (〖|) Connect DQ0 to DQ7, and DQMH corresponds to data connection DQ8 to DQ15. When using When referring to DQM, DQML and DQMH are considered to be in the same state (please read the notes on the back before filling this page). The address input 133 is mainly used to provide the address signal. In this memory, there are 12 lines (A0 to All). As described below, other signals can be provided on the address connection. The address input is in a "valid" command (column) (Addresses A0 to All) and a "read / write" command (row addresses A0 to A7) are sampled to select a location in another bank. As explained below, these address inputs are also used to provide an opcode during the operation of a "load command register". The address lines A0 to All are also used to enter the mode settings during the operation of a "load mode register". An input reset / power saving (RP #) connection 140 is used for reset and power saving actions. In one embodiment, when the initial device is turned on, for internal device initialization, after RP # has transitioned from "low" to "high", a 100 μδ delay is necessary before issuing an executable command of. The RP # signal removes the status register, sets the internal state machine (ISM) 132 to an array read mode, and when it is "low", puts the device into an extreme power saving mode. During power saving, all input connections including CS # 142 are "Don't Care", and all outputs are placed in a high-Z state. When the RP # signal is equal to a VHH voltage (5V), all protection modes are ignored during the "write" and "erase" periods. The RP # signal also allows a device protection bit to be set to 1 (protected), and when guided to VHH, a 13 paper sizes are allowed to apply Chinese National Standard (CNS) A4 specifications (210 X 297 cm) (Centi) 559806 A7 _ — ____ 5. Description of the Invention (V,) The 16-bit temporary registers are set to 0 (unprotected) block protection bits at positions 0 and 15. This protection bit is described in more detail below. RP # is held "high" during all other operation modes. The library address input connection, BAG and BA1 define which library is being applied with a "valid", "read", "write", or "block protection" command. The DQ0 to DQ15 connection 143 is a data bus connection for two-way data communication. Referring to FIG. 1B, a VCCQ connection is used to provide power isolated from the DQ connections to improve noise immunity. In one embodiment, VCCQ = Vcc or 1.8V ± 0.15V. This VSSQ connection is used to isolate the ground of the DQ for improved noise immunity. The VCC connection provides a power source, such as 3V. A ground connection is provided through the Vss connection. Another optional voltage system is provided over the VCCP connection 144. This VCCP connection can be externally connected to VCC and provides current during device initialization, "write" and "erase" actions. In other words, writing or erasing of the memory device can be performed with a VCCP voltage, and all other operations can be performed with a VCC voltage. The Vccp connection is coupled to a high voltage switch / boost circuit 145. The following sections provide a more detailed description of the operation of the flash memory. An embodiment of the present invention is a non-electrical, electrically erasable (flash), programmable, read-only memory, which contains 4,194,304 characters multiplied by 16 Bits 67,108,864. Other total density is also considered, and the present invention is not limited to the density of this example. Each memory bank is organized into four independently erasable areas. 14 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 public love). -------- Order --------- (Please read the notes on the back before filling out this page) 559806 a7 B7 --- I ----- V. Description of the invention ((3 ) Blocks (16 total). To ensure that the critical system is protected from accidental erasure or overwriting, the memory can contain sixteen 256K character hardware and software lockable areas Block. The architecture of the four banks of the memory supports truly simultaneous actions. Read access from one to any bank can be simultaneous with "write" or "erase" actions from any other library background Happened. The synchronous flash memory has a synchronous interface (all signals are displayed on the positive edge of the clock signal CLK). Read access to the memory can be targeted for bursts In other words, memory access starts at a selected location and continues with a programmed number of locations in a programmed sequence Read access begins with a "valid" command, followed by a "read" command. The address bits that appear simultaneously with the "valid" command are used to select the address to be accessed Banks and columns. The address bits displayed simultaneously with the "read" command are used to select the row position and bank for the beginning of the burst access. The synchronous flash memory system provides a burst Termination options are 1, 2, 4, or 8 positions, or the programmable read length of the entire page. Furthermore, the synchronous flash memory system uses an internal pipelined architecture to achieve high speed Action. The synchronous flash memory can operate in a low-power memory system, such as a three-volt system. An extreme power-saving mode and a power-saving backup mode are provided. All inputs and outputs are Compatible with Low Voltage Transistor-Transistor Logic (LVTTL). The synchronous flash memory has a capacity of 15 and the paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) Fill in the items again Page)

559806 A7 B7 V. Description of the Invention (VOC) is to provide substantial improvement in flash operation performance, which includes the ability to synchronize data at high data rates under automatic row address generation, and During a burst access, the address capability is changed randomly on each clock cycle. Generally speaking, the synchronous flash memory system is configured similar to a DRAM with multiple banks at low voltage, and includes a synchronous interface. Each library system is organized into columns and rows. Before the normal operation, the synchronous flash memory system is initialized. The following sections provide detailed information covering device initialization, register definitions, command descriptions, and device actions. The synchronous flash memory system is powered and initialized in a predefined manner. After the power supply system is applied to VCC, VCCQ, and VCCP (simultaneously), and the clock signal system is stable, the RP # 140 system is guided from a low state to a high state. For example, a delay of 1 () 0µ8 is required after RP # transitions high to complete the internal device initialization. After the delay time has elapsed, the memory system is placed in an array read mode and is ready for the mode register to be programmed or an executable command. After the initial programming of a non-dependent mode register 10 (NV mode register), its contents are automatically loaded into a dependent mode register H8 during the initialization period. in. The device will be powered on in a programmed state, and the non-electrical mode register I47 will not be reloaded before the operation command is issued. This is explained in more detail below. 16 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page). -------- Order ------- -559806 A7 __B7_____ 5. Description of the invention) The mode register 148 is used to define the action of the specific mode of the synchronous flash memory. As shown in Figure 2, this definition includes the selection of burst length, burst type, CAS delay, and operation mode. The mode register is programmed via a "load mode register" command, and the stored information is retained until it is reprogrammed. The contents of the mode register can be copied to the NV mode register 147. The setting of the NV mode register is automatically loaded into the mode register 148 during initialization. Details on the command sequence of "Erase NV Mode Register" and "Write NV Mode Register" are provided below. Those skilled in the art will realize that SDRAM requires a mode during each initialization operation. The register must be loaded externally. The present invention allows a preset mode to be stored in the NV mode register 147. The contents of the NV mode register are then copied to an electrically dependent mode register 148 for access during memory operation. Mode register bits M0 to M2 indicate a burst length, M3 indicates a burst type (sequential or staggered), M4 to M6 indicate a CAS delay, M7 and M8 indicate an operation mode, M9 The system is set to logic 1, and M10 and Mil are reserved in this embodiment. Because "write" bursts are not currently implemented, M9 is set to logic 1, and write access is a single location (non-bulk) access. When all banks are idle, the mode register must be loaded, and the controller must wait the specified time before starting the next action. 17 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------------------- Order --------- (Please read the notes on the back before filling this page) 559806 A7 __B7_ V. Description of the invention Uu) The read access to the synchronous flash memory can be burst oriented, where the burst length is programmable , As shown in Table 1. The burst length determines the maximum number of row positions that can be automatically accessed for a particular "read" command. Burst lengths of 1, 2, 4, or 8 positions are available for both sequential and staggered burst types, and a full page burst is available for the sequential type. The entire page of bursts can be used in conjunction with the "Burst Termination" command to generate an arbitrary burst length, in other words, a burst can be selectively terminated to provide a custom-length burst. When a "read" command is issued, a line of blocks equal to the burst length is effectively selected. All accesses to the burst occur in this block, which means that if a boundary is reached, the burst will wrap around in the block. When the burst length is set to 2, the block is uniquely selected by A1 to A7, when the burst length is set to 4, it is selected by A2 to A7, and when the burst length is set A value of 8 is selected by A3 to A7. The remaining (least significant) address bits are used to select the starting position in the block. When the boundary is reached, the entire page of clusters wraps around the page. Access in a particular burst can be programmed as sequential or staggered; this is called the burst type and is selected via bit M3. The order of access in a burst is determined by the burst length, burst type, and starting row address, as shown in Table 1. 18 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------------ Aw · — I ---- ^ --------- ( Please read the notes on the back before filling out this page) 559806 A7 B7 V. Description of the invention (Table 1 Access order defined by a burst in a burst The type of row address at the beginning of the burst = type = length order staggered 2 AO 0 0-1 0-1 1 1-0 1-0 4 A1 A0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3- 2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 A2 A1 A0 0 0 0 0-1-2-3-4- 5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3.2-5-4-7- 6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1 -2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4- 5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 integer Page N = A0-A7 Cn, Cn + 1, Cn + 2 does not support 256 (position 0-255) Cn + 3, Cn + 4… Cn-1, Cn · " 19 (Please read the precautions on the back first (Fill in this page) This paper size applies to Chinese National Standard (CNS) A4 Grid (210 X 297 mm) 559806 A7 ____B7___ V. Description of the Invention (丨?) The row address strobe (CAS) delay is a clock cycle calculated on the appearance of a "read" command and on the DQ. The delay between the first pieces of output data can be obtained on the connection. The delay can be set to 1, 2, or 3 clock cycles. For example, if a read command is displayed at the clock edge η, and the When the delay is m clocks, the data will be available at the clock edge n + m. The DQ connection will start to drive the data because of the clock edge of an earlier cycle (ii + m-1), and it is assumed When the relevant access times match, the data will be valid at the clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are consistent, if a "read" command is displayed at T0 and the delay is programmed into two clocks, the DQs It will start driving after T1 'and the data will be valid at T2, as shown in Figure 3. Figure 3 depicts exemplary operating frequencies where different clock delay settings can be used. The normal operating mode is selected by setting M7 and M8 to 0, and the stylized burst length can be applied to "read" bursts. The following truth table provides more detailed details of the motion commands of one embodiment of the memory of the present invention. Explanations of these orders are provided here and follow the true if table 2. 20 Wood paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -------------------- Order --------- (Please read the precautions on the back before filling this page) 559806 A7B7 V. Description of the Invention (β) True Table 1 Interface Command and DQM Action Name (Function) CS # RAS # CAS # WE # DQM ADDR DQs Command Prohibition (NOP ) Η XXXXXX No action (NOP) L Η Η Η XXX Valid (select bank and start column) LL Η Η X bank / column X read (select bank, row and start reading cluster) L Η L Η X Bank / line X write (select bank, line, and start writing) L Η LLX Bank / line available burst termination L Η Η LXX valid valid burst LL Η LXXX load command register LLL Η X Com code X Load mode register LLLLX operation code X 21 (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 559806 A7 B7 5 Description of the invention (θ) Write enable / output enable----L-Effective write disable / output high impedance-Surface--Η- Impedance truth Table 2 Flash memory command sequence action First cycle Second cycle Third cycle CAAD RP CAAD RP CAAD RP Μ DDQ # MDDQ # Μ DDQ # DDDDDDDDDRRRRRR Read and install LC 90 library XH column library X读 Read the C library XH to configure the read status of the RH effect A. LC 70 XXH has XXX 读 Read the XXXH status temporary RH effector LC 50 XXH status temporary RH device to erase the LC 20 library XH Yes Column library X Η Write X library DO H / stand / confirm RH effect H 22 H VH ----------- install -------- order -------- -(Please read the precautions on the back before filling this page) This paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 559806 A7 B7 V. Description of the invention (^) Write LC 40 library X Η Listed Library X Η Write Co Library DI Η / Lie / Write R 效 1 N νΗ-Η Protected Area LC 60 Library X Η Listed X Η Write X library 01 Η / block / confirm R Η Η LC LC LC Η Η LC LC LC 60 library X Η Have X library X Η Write X library F1 ν Η Set / confirm R Η Validate Η 解除 LC 60 Library X Η Yes X Library X Η Write X Library DO Η / Protector / R Η Validate Η Η Confirmed Η Erase NV LC 30 Library X Η Have X Library X Η Write X Library CO Η Mode temporarily R R Enable写入 Write to the NV LC Α0 library X Η Have X library X Η Write X library X Η The mode is temporarily R Η ---- Order --------- (Please read the precautions on the back before filling this page) The "Command Disable" function prevents new commands from being executed by the synchronous flash memory, regardless of whether the CLK signal is Be empowered. The sync flash memory is actually deselected, but actions that are already in progress are not affected. The "no action" (NOP) command is used to perform a NOP to selected (CS # is low) synchronization Flash memory. This is to prevent unnecessary 23 paper sizes from applying Chinese National Standard (CNS) A4 specification (210 X 297 mm) 559806 A7 ____ B7__ V. Description of the invention (1) The order is displayed from the idle or waiting period. Out, and the action is not affected. The mode register data is loaded via inputs A0 to All. The "load mode register" command can only be issued when all array libraries are idle, and a subsequent executable command cannot be issued until after a preset time delay is met. The data in the NV mode register 147 is automatically loaded into the mode register 148 upon boot-up initialization, and is the default data, except with the "load mode register" command. Changed dynamically. An "valid" command is used to enable (or enable) a column in a particular array library for a subsequent access. 値 on the BAA, BA1 inputs The selection library, and the address selection column provided above the inputs A0 to All. This column remains valid for access until the next "active" command, power saving, or reset. The The read command is used to initiate a burst read access to a valid column. The bank selection library on the BAA, BA1 inputs, and the address system provided on the inputs A0 to A7 Select the starting row position The read data appearing on these DQs is controlled by the logic level on the data mask (DQM) input that appears before the two clocks. If a particular DQM signal appears "high", The corresponding DQs will be high_Z (high impedance) after the two clocks; if the DQM signal is shown as "low", the DQs will provide valid data. Therefore, the DQM input is in a read The fetching period can be used to mask the output data. A "write" command is used to start on a valid column. 24 This paper size applies the Chinese National Standard (CNS) A4 (210 x 297 mm) Li) (Please read the notes on the back before filling this page)

559806 A7 ___B7____ 5. Description of the invention U30 Single-location write access. A "write" command must be preceded by a "write establish" command. The bank selection bank above the BAA0 and BA1 inputs, and the address provided above the inputs A0 to A7 selects a row position. ‘The input data that appears on the DQs is written to the memory array under the control of the DQM input logic level that appears at the same time as the data. If a specific DQM signal is displayed as "low", the corresponding data will be written into the memory. If the DQM signal is displayed as "high", the corresponding data input will be ignored, and A "write" will not be performed to that character / line position. A "write" command with "DQM HIGH" is considered a NOP. An "effective termination" command is not necessary for synchronous flash memory, but can be provided to "terminate" a read in a manner similar to the "SDRAM precharge" command. The "effective termination" command can be issued to terminate an ongoing "burst read" and may or may not be library-specific. A "Burst Termination" command is used to truncate a fixed-length or full-page burst. The "read" command that was recently displayed before the "burst termination" command will be truncated. "Burst termination" is not library specific. The "load command register" action is used to initiate the flash memory control command to the command execution logic (CEL) 130. The CEL receives and interprets commands to the device. These commands control the actions of the internal state machine 132 and the read path (i.e., memory array 102, ID register 136, or state register 134). Any "Read" or "Write" command can be issued to a Chinese paper standard (CNS) A4 (210 X 297 mm) at 25 paper sizes (please read the notes on the back before filling in (This page)

559806 A7 ___B7 ___ V. Description of the Invention (y ^) Before synchronizing a bank in flash memory, a column in the bank must be "on,". This is via the "valid" command (via CS # , WE #, RAS #, CAS #), this is the choice of both the library and the column to be started, see Figure 4. After opening a column (issue a "valid" command), received a Under the control of the time period (tRCD) specification, a "read" or "write" command can be issued to the column, tRCD (MIN) is divided by the clock period and rounded to the next integer To determine the earliest clock edge that a command can enter after a "valid" command, a "read" or "write". For example, under a 90MHZ clock (11.11ns period), a The 30ns tRCD specification results in 2.7 clocks, which are rounded to 3. This is shown in Figure 5, which covers any case where 2 < tRCD (MIN) / tCK 3. (The same procedure is used Use to switch other specification limits, from time units to clock cycles) Assuming that the minimum time interval between consecutive "valid" commands to the same library is defined by tRC, a subsequent "valid" command to a different column in the same library can be Issue without closing a previously valid column. A subsequent "valid" command to another bank can be issued while the first bank is being accessed, which results in a reduction in overall column access overhead. In the following, "effective," the minimum time interval between commands is defined by a time period tRRD. As shown in Fig. 6, the "read" burst is a "read" Command to start (defined by CS #, WE #, RAS #, CAS #). The first 26 paper sizes apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ^ wi --- ----- ^. I ------- (Please read the notes on the back before filling out this page) 559806 A7 ______B7 _ V. Description of the invention (〆). The "fetch" command is provided together. During the "read" burst, valid data output units from the starting row address will be available after the CAS delay after the "read" command. Each subsequent The data output unit will be valid at the next clock edge. At the completion of a burst, assuming no other commands have been initiated, the DQs will become a high-Z state. A full page Will continue until it is finished. (At the end of the page, it will wrap back to line 0 and continue Continued). Data from any "read" burst may be terminated with a subsequent "read" command, and data from a fixed-length "read" burst may immediately follow from a subsequent "read" "Read" command data. In either case, a continuous stream of data can be maintained. The first data unit from the new burst is the last unit following a completed burst, or a The last desired data unit for the longer burst. A new "read" command should be issued x cycles before the last desired data unit is a valid clock edge, where X equals the CAS delay minus 1. This series is shown in Fig. 7, for CAS delays of 1, 2 and 3; data unit n + 3 is the last of a burst of length 4 or the last of a longer burst Unit. This synchronous flash memory system utilizes a pipelined architecture and therefore does not require a 2n rule related to a prefetch architecture. A "read" command can Any clock cycle of the previous "read" command is initiated. Full-speed, random read access on a page can be performed as shown in Figure 8, or each subsequent "read" "Can be carried to different libraries. Data from any" read "cluster can use a follow-up" Ciren 27 "This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)- ---------- ^ -------- Order --------- (Please read the notes on the back before filling out this page) 559806 A7 _____ B7__ 5. Description of the invention (2 厶) "command (" write "command must be cut off after" write is established, and after ", and the data from a fixed-length read burst can be immediately followed by a subsequent" write , Order information (controlled by the limitations of the bus cycle). Assuming I / O contention can be avoided, the "write" is initiated on the clock edge immediately after the last (or last desired) data unit from the read burst. At a particular In system design, it is possible that the device driving the input data will change to low-z before the synchronous flash memory DQs becomes high-Z. In this example, at least a single-cycle delay should occur in the last Between reading the data and the "write," command. As shown in Figure 9, the DQM input is used to avoid I / O contention. The DQM signal must be asserted (high) before the "write" command at least two clocks (for the output buffer, the DQM delay is two clocks) to block the data output from the "read". Once the "write" command is displayed, the DQs will go high-Z (or remain high-Z), regardless of the state of the DQM signal. The DQM signal must be de-declared before the "write" command (for input buffers, the DQM delay is zero clocks) to ensure that the data being written is not masked. Figure 9 shows the case where the clock frequency system allows bus competition to be avoided without having to add a NOP cycle. A fixed-length or full-page "read" burst can be terminated with the "effective termination" (which may or may not be library-specific) or the "burst termination" (not library-specific) command. The "effective termination" or "burst termination" order should be before the last desired data device is a valid clock edge. 28 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ( Please read the precautions on the back before filling in this page) I n ϋ ϋ I n 1: 0J · ϋ fl— n I ϋ ϋ n A7 559806 ____ Β7 ____ V. Description of the invention) The x cycle is issued, where x equals the CAS delay minus Go to 1. This series is shown in Figure 10 for each possible CAS delay; data unit n + 3 is a burst of length 4 or the last desired data unit of a longer burst. As shown in Figure 11, the "write" of a single location starts with a write command (defined by CS #, WE #, RAS #, CAS #. The starting row and bank address are the same as The "write" command is provided together. Once a "write," command is revealed, a "read" command can be executed as defined in Tables 4 and 5. An example is shown in Figure 12 . During a "write" period, valid data input is displayed at the same time as the "write" command. Unlike SDRAM, synchronous flash does not require a "pre-charge" command to deactivate a specific The open columns in the library or open columns in all libraries. The "effective termination" command is similar to the "burst termination" command; however, the "effective termination" may or may not be a specific library Making the input A10 "High" during a "Valid Termination" command will terminate the "Bulk Read" in any library. When A10 is "Periodic" during a "Valid Termination" command Low ", ΒΑ0 and BA1 will decide which library will Perform a termination action. "Effective termination" is considered to be a NOP for a bank that is not addressed by A10, ΒΑ0, BA1 〇 The power-saving system occurs when the clock enables the CKE system with a NOP or "command "Prohibition" occurs simultaneously and appears as "Low" when no access is in progress. After the internal state machine actions (including the "write" action) are completed, the power-saving system is deactivated to enable the input and output buffers. (Excluding CKE), used for power saving in standby. 29 Wood paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) ~ " (Please read the precautions on the back before filling this page)

ϋ I n H ϋ I n One: OJ · n I n I ϋ ϋ I Φ. 559S06 A7 B7 f ---- ^-Jade, description of the invention (β) The power saving state is separated by The clock edge (in accordance with tCKS) shows an NOP or "command disabled" and CKE is "high". See an example of the power saving action in Figure 13. A clock pause mode occurs when a row access / burst system is in progress and the CKE system appears "low". In this clock pause mode, an internal clock system is deactivated to "freeze" the synchronization logic. For each clock edge on which CKE is sampled as "low", the next internal clock edge system is temporarily stopped. As long as the clock system is temporarily stopped, any command or data appearing on the input pin at the edge of the clock that is temporarily stopped is ignored, and any data appearing on the DQ pin will be ignored. It remains driven and the burst counter is not incremented (see the example in Figure 14). The clock pause mode exits by showing that CKE is "high"; the internal clock and related actions will continue above the subsequent clock edge. In one embodiment, the burst read / single write mode is a preset mode. All "write," commands generate access to a single line position (burst of length 1), while "read," commands access lines based on the stylized burst length and sequence. The following table 3 describes the memory operation using this CKE signal. 30 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)

559806 A7 B7 V. Explanation of the invention (>) Table 3-CKE CKEn.j CKEn Current status command η Action η LL Power-saving clock temporarily X Maintain "Power-saving" Stop X Maintain "Clock pause" LH Power-saving clock temporarily “command prohibited” Leave “power-saving” stop or NOP X Leave “clock-pause” Η L All library idle “command prohibited” “power-saving” enter to set read or write or NOP input is valid The "clock pause" enters Η H. See true table 4 True Straight Table 4-current 的 dog state library n-command to library n current state CS # RAS # CAS # WE # command / action arbitrary Η XXX "Command disabled" (NOP / continue previous action) L Η HH "No action" (NOP / continue previous action) Idle LLHH "Active" (select and start column) LLLH "Load command register "LLLL" Load mode register "LLHL" Valid termination "column valid LLLH" Read "(select the line and start" Read 31 This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm ) (Please read the back first Please fill in this page again before the installation)) ----- ΦΓΟ, · 11111111 · 559806 V. Description of the invention ㈠ °) A7 B7 LLLLLLL Η LLLH take "bundle" "write" (select the line and start " Write ")" effective termination "" load command register "read L Η LH" read "(select the line and start a new" read "burst) L Η LL" write "(select Line and start "write ,," LLHL "effective termination" L Η HL "burst termination" LLLH "load command register" write L Η LH "read" (select the line and start a new "Read" burst) LLLH "Load Command Register" True Table 5-Current State Library η-Command to Library m Current State CS # RAS # CAS # WE # Command / Action Arbitrary XXX " Command Prohibition "(NOP / continue previous action) L Η Η Η" No action "(NOP / continue previous action) Idle XXXX Any command, except the command allowed to library m 32 (Please read the back first (Please fill in this page again)

--- I ---- Order · ------- I This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 559806 A7 ___B7 V. Description of Invention U \) Column LLHH "Effective" (select and activate the column), effective L Η LH "read" (select the row and start the "read, have-take" burst) the effective final L Η "write" (select the row and Start "write-stop") LLHL "effective termination" LLLH "load command register" read LLHH "valid" (select and start column) LHLH "read" (select row and start new " Read "burst" LHLL "write" (select row and start "write") LLHL "effective termination" LLLH "load command register" 'write LLHH "valid" (select and start column ) LHLH "read" (select the line and start "read" burst) LLHL "effective termination" LHHL "batch termination" LLLH "load command register" (please read the notes on the back before filling (This page) ---- ί — 丨 Order --------- · Function description The synchronous flash memory system incorporates some features to make it ideally suitable for code storage and on an SDRAM bus at an appropriate place. (Mm) 559806 A7 ___ B7 _ V. Description of the Invention (Hong) (Please read the notes on the back before filling out this page). The memory array is divided into individual erase blocks. Each block can be erased without affecting the data stored in other blocks. These memory blocks are read, written, and erased by issuing commands to the command execution logic 130 (CEL). The CEL controls the operation of the internal state machine 132 (ISM), which completely controls all the "erase NV mode register", "write NV mode register", "write", "block "Erase", "block protection", "device protection", "remove protection of all blocks", and "verify". The ISM 132 Series protects each memory location from over-erase and keeps each memory location optimized for maximum data. In addition, the ISM greatly simplifies the controls necessary to program the device into the system or by an external programmer. The synchronous flash memory system is organized into 16 independently erasable memory blocks, which allows part of the memory to be erased without affecting the remaining memory data. Any block can be protected by hardware from accidental erasure or writing. A protected block requires the RP # pin to be driven to VHH (a relatively high voltage) before being modified. 256K character blocks at positions 0 and 15 can have additional hardware protection. Once a "protect block" command has been executed for these blocks, a "remove protection from all blocks" command will open all blocks' except for blocks at positions 0 and 15, unless the RP # The pins are tied to VHH. In the event of an inadvertent power outage or a system reset 'this provides additional security to critical codes during the update of the blades in the system. The sequence of boot initialization, "erase", "write" and "protection" is controlled by all of the programmatic algorithms in the memory array through the ISM | 34 U Dimensions (CNS) A4 specifications ( 210 x 297 male. 559806 A7 _ B7_ 5. The description of the invention (τ; 7!) Is simplified. The ISM system ensures protection from over-erase and optimizes the write boundary for each cell. During the "write" action, the ISM automatically increases and monitors "write" attempts, verifies the write boundary above each memory cell, and updates the ISM status register. When a "block erase When the action is performed, the ISM automatically overwrites the entire addressed block (eliminating over-erase), adds and monitors erase attempts, and sets the bit in the ISM status register. The 8 The bit ISM status register 134 allows an external processor 200 to monitor the status of the ISM during the "write", "erase" and "protect" actions. The 8-bit status register One bit (SR7) is set completely by the ISM and Erase. This bit indicates whether the ISM is busy with a "erase", "write" or "protection" job. Additional error information is set to the other three bits (SR3, SR4, and SR5): Writing and protecting block errors, erasing and removing all block protection errors, and device protection errors. Status register bits SR0, SR1, and SR2 provide details of the ongoing ISM action. Use The user can monitor whether a device-level or library-level ISM action (including which libraries are under ISM control) is in progress. These six bits (SR0-SR5) must be eliminated by the host computer system. The The status register is described in more detail below with reference to Table 2. The CEL 130 receives and interprets commands to the device. These commands control the operation of the ISM and the read path (ie, memory array, Device configuration or status register). Commands can be issued to the CEL when the ISM system is active. 35 4 ^ -t -------- tr --------- (Please (Please read the notes on the back before filling out this page) This paper size applies to China Standard (CNS) A4 (210 X 297 mm) 559806 A7 _____B7 _ V. Invented ^ A large power savings, the characteristics of the synchronous flash memory is very low current, extremely power saving mode. In order to enter this mode The RP # pin 140 (reset / power saving) is set to VSS ± 0.2V. To avoid inadvertent “reset”, RP # must be kept at VSS for as long as the device enters the reset mode. 100ns. After RP # is kept at Vss, the device will enter the extreme power saving mode. After the device enters the extreme power saving mode, a transition from "low" to "high" above RP # will generate a device initialization sequence as described herein. After entering this reset mode, but before entering extreme power saving mode, transitioning RP # from "low" to "high" requires a 1µδ delay before issuing an executable command. When the device enters the extreme power saving mode, all the buffers except the RP # buffer are disabled, and the current draw is low, for example, at a maximum of 50 μA at a VCC of 3.3V. The input to RP # must be held at Vss during periods of extreme power saving. Entering the "reset" mode is to delete the status register 134 and set the ISM 132 to the array read mode. The array architecture of the synchronous flash memory is designed to allow sectors to be erased without disturbing the rest of the array. The array is divided into 16 addressable, independently erasable "blocks". By erasing blocks instead of the entire array, the overall device durability is enhanced and the system flexibility is enhanced. Only the "erase" and "block protection" functions are block-oriented. The 16 addressable blocks are equally divided into four banks 104, 106, 108, and 110, each bank having four blocks. The four libraries are capable of reading and writing simultaneously. An ISM "write" or "erase" action to any library can be issued simultaneously with a "read" action to any other library. 36 This paper size applies to China National Standard (CNS) A4 (210 X 297) (Mm) Μ .-------- tr --------- (Please read the notes on the back before filling out this page) 559806 A7 ___B7____ 5. Description of the invention The status register 134 can be queried to determine which library system is in the ISM operation. The synchronous flash memory has a single background action ISM to control the boot initialization, "erase", "write" and "protect" actions. Only one ISM action can occur at any time; however, it contains a "read" action Other commands can be executed while the ISM action is taking place. An action command controlled by the ISM is defined as a library-level action or a device-level action. "Write" and "Erase" "Remove" is a library-level ISM action. After an ISM library action has been initiated, a "read" to any location in the library may output invalid data, and one to any other library "Read" will read the array. A "Read Status Register" command will output the contents of the status register 134. The ISM status bit will indicate when the ISM action will be completed (SR7 = 1). When the ISM action is completed, the library will automatically enter the array read mode. "Erase NY Mode Register", "Write NV Mode Register", "Block Protection" , "Install Protection ", and" 1SM removing the protective action of all blocks "for the system-level device. Once an ISM device-level action has been initiated, a "read" to any library will output the contents of the array. A "Read Status Register" command can be issued to determine the completion of the ISM action. When SR7 = 1, the ISM action will be completed and a subsequent ISM action can be initiated. As explained below, any block that requires the RP # pin to be "written" or "erased" before being driven to the VHH hardware circuit can be protected from Unintentionally "erase" or "write." Any block can be protected by hardware to be most sensitive to the firmware. 37 This paper size applies the Chinese National Standard (CNS) A4 (210 x 297 mm) ) I -------- ^ --------- (Please read the precautions on the back before filling out this page) 559806 A7 ________B7 ___ 5. The invention description (wonderful) section provides extra security During the "write" or "erase" of a block protected by hardware, the RP # pin must be held at VHH until the "write" or "erase" is completed So far, without RP # = VHH, any "write" or "erase" attempt on a protected block will be prevented and a write or erase error will be generated. Blocks at positions 0 and 15 can have additional hardware protection to prevent inadvertent "writes" or "erase" Action. In this embodiment, these blocks cannot be unlocked and protected by software through a "Remove Protect All Blocks" command, unless RP # = VHH. The protection status of any block can be achieved by using a " "Read status register" command to read its block protection bit and check it. Furthermore, in order to protect a block, a three-cycle command sequence must be issued with the block address. The synchronization fast Flash memory can be endowed with three different types of "read," characteristics. According to this mode, a "read" action will generate data from one of the memory array, the status register, or the device configuration register. A "read" to the device configuration register or the status register must be an "LCR-active" cycle, and the burst length of data output will be defined by the mode register setting. A subsequent "read" or a "read" without a previous "LCR-active" cycle will read the array. However, several differences exist and are described in the following sections. A "read" command to any bank outputs the contents of the memory array. When a "write" or "erase ISM" action is taking place, a "read" under ISM control to any location in the library may output invalid data. When leaving a "reset" action, the device will automatically 38 paper size applicable to China National Standard (CNS) A4 (210 X 297 mm) —I ------- ^ wi --- --- 丨 " Order --------- (Please read the notes on the back before filling out this page) 559806 A7 ____B7 _ 5. Description of the invention Enter the array read mode. The "read" of the status register 134 requires the same input sequence as when the array is read, except that an "LCR read status register" (70H) cycle must be performed during the "valid read" Before the fetch cycle. The burst length of the status register data output is defined by the mode register 148. The status register contents are updated and latched on the next clock edge after the CAS delay. The device will automatically enter the array read mode for subsequent "reads". Reading any device configuration register 136 requires the same input sequence as when reading the status register, except that a specific address must be issued. WE # must be "high", and DQM and CS # must be "low". In order to read the manufacturer compatibility ID, the address must be 000000H, and in order to read the device ID, the address must be 000001H. Any bit of the block protection bit is read at the third address position (XX0002H) in each erase block, and the device protection bit is read from position 000003H. DQ pins are used to input data into the array. The address pin is used to indicate an address location or to enter a command into the CEL during the "load command register" cycle. A command input sends an 8-bit command to the CEL to control the operation mode of the device. A "write" is used to enter data into the memory array. The following sections describe two types of inputs. In order to execute a command input, DQM must be "low" and CS # and WE # must be "low". Address pins or DQ pins are used to lose 39. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). -------- (Please read the notes on the back before filling this page) 559806 A7 ___B7 V. Description of the invention) Enter the order. Address pins that are not used to enter commands are "regardless of" and must be stable. The 8-bit command is input above DQ0 to DQ7 or A0 to A7, and is latched above the clock edge. A "write" to the memory array sets the desired bit to logic Os, but cannot change a specific bit from logic 0 to logic 1. Setting any bit to logic 1 requires the entire block to be erased. To perform a "write", DQM must be "low", CS # and WE # must be "low", and VCCP must be connected to VCC. Writing to a protected block also requires the RP # pin to be directed to VHH. A0 to All provide the address to be written, and the data written to the array is input on the DQ pins. The data and addresses are latched on the rising edge of the clock. A "write" must be preceded by a "write establish" command. To simplify the writing of memory blocks, the synchronous flash memory system incorporates an ISM that controls all internal algorithms for the "write" and "erase" cycles. An 8-bit command set is used to control the device. See the valid commands listed in one of Shinji Tables 1 and 2. The 8-bit ISM status register 134 (see Table 2) was queried to check for "Erase NV Mode Register", "Write NV Mode Register", "Write", "Erase "Remove", "Block protection", "Device protection", or "Remove protection of all blocks" completed or any related errors. The completion of an ISM action can be monitored by issuing a "Read Status Register" (70H) command. The contents of the state register will be output to DQ0 to DQ7, and will be updated above the next clock edge (affected by CAS delay) for a fixed burst length defined by the mode register setting . When 40 paper sizes are applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) Μ .-------- tr --------- (Please read the precautions on the back before Fill out this page) 559806 A7 B7 V. Description of the invention) SR7 = 1, the ISM action will be completed. All defined bits are set by the ISM, but only the ISM status bits are reset by the ISM. The erase / remove protection block, write / protect block, and device protection must be erased by a "erasing state register" (50H) command. This system allows the user to choose when to ask and delete the status register. For example, a host system can perform multiple "write" actions before checking the status register, rather than after each individual "write". Making the RP # signal actuate or saving the device will also erase the status register. (Please read the notes on the back before filling in this page) * β§ ϋ —Mi 1 «ϋ I n one by one 0, I · ϋ ϋ ϋ nn ϋ §Μ§ ·% · Table 2 Status register status bits # State register bit description SR7 “ISM state” 1 = Ready 0 = Busy When performing “write” or “block erase”, the ISMS bit shows the valid state of the state machine. The control logic queries this bit to determine when the erase and write status bits are valid. SR6 "Reserved"… 1 · " ------ Reserved for future use SR5 "Erase / Remove Protection Block Status" 1 = "Block Erase" or "Block Removal Protection" error 〇 = Successful "block erasure" or " .....................-- the maximum number of erasures without a successful verification After the cycle is executed by this ISM, the ES system is set to 丄 — ^^ -— 41 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 559806 B7 V. Description of the invention (u.). If a "block removal protection" action is unsuccessful, this bit is also set to 1. The ES can only be deleted by the "Erase Status Register" command or by "Reset". __ SR4 "Write / Protect Block Status" 1 = "Write" or "Block Protection" error 0 = Successful "Write" or "Block Protection" Without a successful verification, After the maximum number of write cycles is executed by the ISM, the WS system is set to 1. If a "block or device protection" action is unsuccessful, this bit is also set to 1. WS can only be set by " "Erase status register" command or delete it by "Reset". ----------- Install -------- Order -------- -(Please read the notes on the back before filling this page) SR2 SR1 'Library A1 ISM status' 'Library AO ISM status' When SR0 = 0, libraries under ISM control can be decoded from ΒΑ0, BA1: [0 , 0] Library 0; [0,1] Library 1; [1,0] Library 2; [1,1] Library 3 ___ SR3 "Device protection status" 1 = The device is protected, invalid actions are attempted if one Invalid "write", "erase", "protected block", "protective device" or "remove the protection station" 42 This paper size is applicable to the Chinese National Standard (CNS) A4 (210 x 297 mm) 559806 A7 _B7 Friday DISCLOSURE OF THE INVENTION (〇 〇 = The device is not protected or the RP # condition meets the condition of the block. "The DPS system is set to 1. After one of these commands is issued, the condition of RP #, the area The block protection bit is compared with the device protection bit to determine whether the desired action is allowed. It must be deleted by the "Erase Status Register" command or by "Reset". SR0 "Device / Library ISM Status" 1 = Device-level ISM action 0 = Library-level ISM action If the ISM action is a device-level action, the DBS system is set to 1. A valid "Read “Get” can be immediately followed by the “write” action of a device-level ISM. When the DBS system is set to 0, the ISM action is a library-level action. A “read” to a library under ISM control Invalid data may be generated. SR2 and SR3 can be decoded to determine which library is under the control of ISM. 43 Private paper size applies Chinese National Standard (CNS) A4 specification (210 x 297 mm) (Please read the note on the back first Refill This page)

-ϋ II ϋ ϋ H 1-0, I 1 | _1 II ϋ n I 559806 A7 ____B7__ 5. Description of the invention (recognition. The device ID, manufacturer compatibility ID, device protection status, and block protection status can be borrowed. Read by issuing a "Read Device Configuration" (90H) command. In order to read the desired register 'a specific address must be issued. For more details on the various device configuration registers 136 'Please see Table 3. Table 3 Device Configuration Device Configuration Address Data Situation Manufacturer Compatibility 000000H 2CH Manufacturer Compatibility Read Device ID 000001H D3H Device ID Read Block Protection Bits xx0002H xx0002H DQ0 = 1 DQ0 = 0 Block is protected Block is not protected by device protection bit xx0003H XX0003H DQ0 = 1 DQ0 = 0 Block protection change is prohibited Block protection change is enabled The command can be issued to make the device enter different action modes. Every Each mode has specific actions that can be performed while in that mode. Several modes require a sequence of commands to be written before reaching the mode. The following sections describe the nature of each mode Tables 1 and 2 are all the command sequences required to perform the desired action. The function of reading and writing at the same time allows the writing or erasing of a background action to be performed on any library. While reading any other library at the same time. For a write action, "LCR-Valid-Write" in Shinji Table 2, the command sequence must be completed on consecutive clock cycles. However, ' In order to simplify the operation of a synchronous flash controller, an unlimited number of NOPs or "command prohibition" can be applied to the Chinese National Standard (CNS) A4 specification (210 x 297 male Θ ~ ------) on a 44 ^^ scale. ----- Install -------- Order -------- (Please read the notes on the back before filling this page) 559806 A7 ___B7____ V. Description of the invention (y) During the entire order sequence Is issued. For additional protection, these command sequences must have the same bank address for up to three cycles. If the bank address is changed during the "LCR-valid-write", the command sequence is changed, or if The command sequence is not continuous (except for NOPs allowed and "command prohibited") Then the write and erase status bits (SR4 and SR5) will be set, and the action is prohibited. At the time of power-on and before sending any action command to the device, the synchronous flash memory system is Initialization. After the power is applied (simultaneously) to VCC, VCCQ, and VCCP, and the clock is stable, RP # is changed from "low" to "high". After RP # is changed to "high", one is needed Delay (a delay of 100 μ $ in one embodiment) to facilitate the initialization of the internal device. The device is in the array read mode when device initialization is complete, and an executable command can be issued to the device. In order to read the device ID, the manufacturer compatibility ID, the device protection bit, and each of the block protection bits, a "Read Device Configuration" (90H) command is issued. When in this mode, a specific address is issued to read the desired information. The manufacturer compatibility ID is read at 000000H; the device ID is read at 000001H. The manufacturer compatibility ID and device ID are output on DQ0 to DQ7. The device protection bit is read at 000003H; and each block protection bit is read at the third address position in each block (xx00002H). The device and block protection bits are output on DQ0. The input data to the array system needs three 45 ^ 'sheets above the continuous clock edge to apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) " ~' --- 1 ---- --- Aw * — — — — — — — I — ^ «— — — — — — I — (Please read the notes on the back before filling out this page) 559806 A7 ___ B7____ 5. Description of the invention (1) Continuous order (NOPs and command prohibitions are allowed between cycles). In the first cycle, a "load command register" command is given a "write establishment" (40H) above A0 to A7, and the bank address is issued above ΒΑ0, BA1. The next command is "valid", which starts the column address and confirms the library address. The third cycle is "write". During the third cycle, the starting row, bank address, and data are issued. The ISM status bit will be set on the following clock edges (affected by CAS delay). When the ISM performs the "write", the ISM status bit (SR7) will be at zero. A read to a library under ISM control may produce invalid data. When the ISM status bit (SR7) is set to logic 1, the 'write' has been completed and the library will be in the array read mode and ready for an executable command. Writing to a block protected by hardware also requires that the RP # pin be set to VHH before the third cycle (write), and RP # must be held at VHH until the ISM "write" action system So far. If the "LCR-Valid-Write" command sequence is not completed in consecutive cycles, or the bank address is changed in any of the three cycles, the write and erase status bits (SR4 and SR5) will be set. After the ISM has initiated the "write", it cannot be aborted except by a "reset" or by putting the part into power saving. During a "write" period, by a "reset" or by entering the part into the power saving system, the written data may be damaged. Performing an "erase" sequence will set all bits in a block to logic 1. To perform a "erase," the required command sequence is similar to a "write" command sequence. In order to provide additional blocks to prevent accidental erasure 46 This paper size applies the Chinese National Standard (CNS) A4 (210 X 297 (Gongai) " " " Install -------- Order --------- (Please read the precautions on the back before filling this page) 559806 A7 _B7_ V. Description of the invention (to ) (Please read the notes on the back before filling this page) Except for security, the "erase" of the beginning of a block requires three consecutive command sequences above the continuous clock edge. In the first cycle In the "load command register", "erasing establishment" (20H) is given above A0 to A7, and the library address of the erased block is issued above ΒΑ0, BA1. The next command is "valid", where A1 (λ, All, Β0, BA1 provides the address of the block to be erased. The third cycle is "write", during the third cycle, "erase "Delete confirmation" (D0H) is given above DQ0 to DQ7, and the bank address is issued again. The ISM status bit will be on the next Above the clock edge (affected by CAS delay) is set. After the "Erase Confirmation" (D0H) is issued, the ISM will start erasing the addressed block. Any block to the addressed block The "read" action of the library in which it is located may output invalid data. When the "erase" action is completed, the library will be in the array read mode and ready for an executable command. Erasing a block protected by hardware also requires the RP # pin to be set to VHH before the third cycle (write), and RP # must be held at VHH until the "erase" is completed (SR7 = 1). If the "LCR-Valid-Write" command sequence is not completed in consecutive cycles (NOPs and "Command Prohibition" are allowed to complete between cycles), or the library address is in the When one or more of the command cycles change, the write and erase status bits (SR4 and SR5) will be set and the action is disabled. The contents of this mode register 148 can be used A "Write to NV Mode Register" command is copied to the NV Mode Register 147 Before writing to the NV mode register, a "Erase NV mode register" command sequence must be completed to set all the bits in the NV mode register. 47 This paper standard applies Chinese national standard ( CNS) A4 specification (210 X 297 mm) 559806 A7 _____B7____ 5. Description of the invention ((Please read the precautions on the back before filling out this page) Yuan to logic 1. Execute an "Erase NV Mode Register" and " To write to the NV mode register, the required command sequence is similar to a "write" command sequence. Please see Table 2 for more information on the "LCR-Valid-Write" command required to complete the "Erase NV Mode Register" and "Write NV Mode Register". After the "Erase NV Mode Register" or "Write NV Mode Register," after the "write" cycle of the command sequence has been displayed, a "read" command can be issued to the array. A new The "write" action will not be allowed until the current ISM action is completed and SR7 = 1. Executing a "block protection" sequence enables the first level of software / hardware protection to a specific block. The memory system includes a 16-bit register, which has a bit corresponding to the 16 protectable blocks. The memory also has a register to provide a device to protect the entire device. Device bit free from write and erase actions. The command sequence required to perform a "block protection" is similar to a "write" command sequence. In order to provide added security against accidental block protection, The start of a "block protection" requires three consecutive command cycles. In the first cycle, a "load command register" is issued and one of the "protection establishment" (60H) commands is from A0 to A7 On and The bank address of the block to be protected is issued above BAA0, BA1. The next command is "valid", which starts a list of blocks to be protected and confirms the bank address. The third The cycle is "write". During the third cycle, the "block protection confirmation" (〇1Η) is issued above DQ0 to DQ7, and the bank address is issued again. The ISM certificate is 48 paper standards Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 559806 A7 __ —___ B7_______ V. Description of invention (V ^) The state bit will be set above the next clock edge (affected by CAS delay) The ISM will then start the "protection" action. If the "LCR-Valid-Write" is not completed on consecutive cycles (NOPs and "Command Prohibition" are allowed to complete between cycles), When the bank address is changed, the write and erase status bits (SR4 and SR5) will be set and the action is disabled. When the ISM status bit (SR7) is set to logic 1 When the "protection" has been completed, and the library will be in the array read mode And ready for an executable command. Once a block protection bit has been set to a 1 (protected), only the "remove all blocks" command can be reset to a 0 The command sequence of "remove protection of all blocks" is similar to the "block protect" command; however, in the third cycle, a "write" is issued in a "remove protection of all blocks" (D0H) command and the address is under "No matter". For additional information, please refer to the table of truth 2. Blocks at positions 0 and 15 have additional security. Once at positions 0 and 15 When the block protection bit has been set to a 1 (protected), only when RP # is directed to VHH before the third cycle of the "remove protection" action and remains at VHH until the action is completed (SR7 = 1), each bit can be reset to a 0. Furthermore, if the device protection bit system is set, RP # must be directed to VHH before the third cycle and kept at VHH until the "block protection" or "remove protection of all blocks" actions So far. In order to check the protection status of a block, a "read device configuration" (90H) command can be 49 ^ This paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) (Please read the note on the back first Please fill in this page for matters) --- 1 ---- Order --------- · 559806 A7 ____B7 _. V. The invention description (recognition order) was issued. Performing the "device protection" sequence sets the device protection bit to a 1 and prevents a block protection bit from being changed. The command sequence required to perform a "device protection" is similar to a "write" command sequence. The beginning of a "device protection" sequence requires three consecutive command cycles. In the first cycle, a "load command register" is issued, one of which is "protection establishment" (60H) between A0 and A7. , And a bank address is issued above ΒΑ0, BA1. The bank address is "no matter", but the same bank address must be used in all three cycles. The next command is "valid ". The third cycle is" write ". During the third cycle, a" device protection "(F1H) command is issued above DQ0 to DQ7, and RP # is directed to VHH. The ISM status bit Will be set above the next clock edge (subject to CAS delay). An executable command can be issued to the device. RP # must be held at VHH until the "write" is completed (SR7 = 1). A new "write" action will not be allowed until the current ISM action is completed. Once the device protection bit is set, it cannot be reset to a 0. The device protection bit Set to below 1, "block protection" or "block "Remove protection" is prevented unless RP # is under VHH during any action. The device protection bit does not affect the "write" or "erase" action. Please refer to Table 4 for the blocks and devices More information on protection action. 50 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ----------- AW- ^ ------- 1 ^ --------- (Please read the precautions on the back before filling out this page) 559806 A7 B7 V. Description of the Invention u)

Table protection function f 4 戸 True 値 Table function RP # CS # DQM DQO -DQ7 Device is not protected ^ Protection is established Η LHL 60H XX protection block Η LHL BA i H 01H protection device U VHh LHLXX F1H Remove protection All blocks H / V HH LHLXH DOH devices are protected by protection H or Vhh LHL 60H XX Protected blocks Vhh LHL BA H 01H Remove all protected blocks Vhh LHLXH DOH (Please read the precautions on the back before filling out this Page) ▼ -Installation · ----- II Order · -------- After the ISM status bit (SR7) has been set, the device / bank (SR0), device protection (SR3), The bank A0 (SR1), bank A1 (SR2), write / protect block (SR4), and erase / remove protection (SR5) status bits can be checked. If one or a combination of SR3, SR4, and SR5 status bits has been set, an error has occurred during the action. The ISM cannot reset the SR3, SR4 or SR5 bits. In order to eliminate these bits, 51 paper sizes are applicable to the Chinese National Standard (CNS) A4 (210 x 297 mm) 559806 A7 ______B7___ V. Description of the invention (<) A "erased state register" (5〇 H) The order must be given. Table 5 shows the wrong combination. Table 5 Status register error status bit error description SR5 SR4 SR3 0 0 0 No error 0 1 0 "write", "block protection" or "device protection" error 0 1 1 invalid "block protection" Or "device protection", RP # is invalid (vHH) 0 1 1 invalid "block" or "device protection", RP # is invalid 1 0 0 "erase" or "all block removal protection" "Error 1 0 1 Invalid" All blocks are removed from protection, RP # is invalid (Vhh) 1 1 0 Command sequence error This synchronous flash memory system is designed and made to meet advanced code and data storage requirements. To To ensure this level of reliability, VCCP must be maintained to Vcc during the "write" or "erase" cycle. Actions outside these limits can reduce the "write," and The number of "erase" cycles. Each block is designed to handle the durability of a minimum of 100,000 "write" / "erase" cycles. The synchronous flash memory system provides several power saving features, which can be used in the array read mode to save power. An extreme power saving mode is enabled by directing RP # to vss ± o.2V. In this mode 52 t -------- tr --------- (Please read the precautions on the back before filling this page) ^ The scale is applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) " 559806 A7 ____B7___ V. The current draw (ICC) in the description of the invention is low, for example, the maximum is 50μΑ. When CS # is "High", the device will enter the active standby mode. The current in this mode is also low, for example: the maximum ICC current of iOmA. If CS # is directed to "high" during a write, erase, or protection action, the ISM will continue the "write" action and the device will consume effective Iccp power until This operation is completed. Referring to FIG. 16, a flowchart of a self-timed write sequence according to one embodiment of the present invention is depicted. The sequence includes loading the command register (code 40H), receiving a valid command and a column address, and receiving a write command and a row address. The sequence then provides a query of the status register to determine if the write is complete. This query is to monitor status register bit 7 (SR7) to determine if it is set to 1. An optional status check can be included. When the writing is completed, the array is placed in the array read mode. Referring to FIG. 17, a flowchart of a complete write status check sequence according to one embodiment of the present invention is provided. This sequence looks for status register bit 4 (SR4) to determine if it is set to zero. If SR4 is 1, there was an error in this write operation. The sequence also looks for status register bit 3 (SR3) to determine if it is set to zero. If SR3 is 1, there was an invalid write error during the write operation. Referring to FIG. 18, a flowchart of a self-timed block erase sequence according to an embodiment of the present invention is provided. This sequence contains a load command register (code 20H) and receives a valid command and a column address. The memory then determines whether the block is protected. If it is not protected, the 53 paper sizes are in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) n H ϋ n ^ OJ0 n ϋ n I n ϋ ϋ I · 559806 A7 ______B7 V. Description of the Invention (γ) The memory system executes a write operation (D0H) to the block and monitors whether the status register is completed. An optional status check can be performed and the memory system is placed in an array read mode. If the block is protected, the erase will not be allowed unless the RP # signal is under a high voltage (VHH). Fig. 19 is a flowchart depicting a sequence of a complete block erase status check according to an embodiment of the present invention. This sequence monitors the status register to determine whether a command sequence error has occurred (SR4 or SR5 = 1). If SR3 is set to 1, an invalid erase or remove protection error has occurred. Finally, if SR5 is set to 1, a block erase or remove protection error has occurred. FIG. 20 is a flowchart of a block protection sequence according to an embodiment of the present invention. This sequence contains a load command register (code 60H) and receives a valid command and a column address. The memory then determines whether the block is protected. If it is not protected, the memory system executes a write action (01H) to the block and monitors whether the status register is complete. An optional status check can be performed and the memory system is placed in an array read mode. If the block is protected, the erase system is not allowed unless the RP # signal is under a high voltage (VHH). Referring to FIG. 21, a flowchart of a complete block status check sequence according to one embodiment of the present invention is provided. The sequence monitors the status register bits 3, 4 and 5 to determine if an error has been detected. FIG. 22 is a flowchart of a device protection sequence according to an embodiment of the present invention. This sequence contains a load command register (code 60H), and receives a 54 paper size that applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ^ —I ---- ^ ---- ----- (Please read the precautions on the back before filling this page) 559806 A7 _ B7 __—_—_ V. Description of the invention (0) A valid command and a column address. The recorder then judges whether RP # is in VHH. The memory system executes a write action (F1H) and monitors whether the status register is complete. An optional status check can be performed and the memory system is placed in an array read mode. FIG. 23 is a flowchart of a block removal protection sequence according to an embodiment of the present invention. The sequence contains a load command register (code 60H), and receives a valid command and ~ column addresses. The memory bank then determines whether the memory device is protected. If it is not protected, the memory system determines whether the boot locations (blocks 0 and 15) are protected. If no block is protected, the memory system executes a write operation (D0H) to the block and monitors whether the status register is completed. An optional status check can be performed and the memory system is placed in an array read mode. If the device is protected, the erase system is not allowed unless the RP # signal is under a high voltage (VHH). Similarly, if the boot positions are protected, the memory determines whether all blocks should be removed from protection. Figure 24 depicts the timing of the initialization and load mode register operations. The mode register is programmed by providing a load mode register command and providing an opcode over the address lines. The opcode is loaded into the mode register. As explained above, the contents of the non-independent mode register are automatically loaded into the mode register upon booting, so the loading mode register action may not be required. Figure 25 depicts the timing of one clock pause mode operation, and Figure 26 depicts the timing of another burst read operation. Figure 27 depicts the alternate 55 ^ " Zhang scale is applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) " '(Please read the precautions on the back before filling out this page) I installed ---- ---- Order --------- · 559806 A7 ----- B7 ---- V. Description of the invention (f) Timing of library read access. A valid command is needed to change the library address here. A full-page burst read action is depicted in Figure 28. Please note that the burst of the entire page does not terminate by itself, but requires a termination command. Figure 29 depicts the timing of the reading operation using a data mask signal. The DQM signal is used to mask the data output so that Dout m + 1 is not provided over the DQ connections. Referring to Figure 30, the timing of a write operation followed by a read to a different bank is depicted. In this action, a write is performed to bank a, and a subsequent read is performed to bank b. The same column system is accessed in each bank. Referring to Figure 31, the timing of a write operation followed by a read to the same bank is depicted. In this action, a write is performed to bank a, and a subsequent read is performed to bank a. A different column system is accessed for the read operation, and the memory must wait for the previous write operation to be completed. This is different from the read of FIG. 30, in which the read is not delayed by the write action. Interface command architecture

An SDRAM uses three command lines, RAS, CAS and WE, to decode its commands. These three lines allow decoding of eight different DRAM type commands, as known to those skilled in the art. They include NOP, valid, read, write, update, precharge, load mode registers, and burst termination. This flash memory system performs like SDRAM 56 (Please read the precautions on the back before filling out this page) -III — — — — ^ 11111111 This paper size applies to China National Standard (CNS) A4 (210 X 297) (Centi) 559806 A7 __B7 ___ 5. The description of the invention (^) reads, and thus uses most of the above commands. On the other hand, the flash memory has a series of actions and does not exist in SDRAM. Those actions include, for example, program creation, _ erase creation, erase confirmation, read array, read status, read smart identifier, command to erase status register, and related to the flash memory. Command of block protection mode. While allowing flash memory-related commands to be decoded, the present invention keeps the SDRAM command architecture as unaffected as possible. A command used in the SDRAM but not needed in the flash memory is an update command. This DRAM, because it is dynamic, needs to be updated periodically to maintain its data. The flash memory unit of the present invention is non-electrical-dependent, and therefore does not require this update action. The command architecture of the present invention utilizes a combination of three command pin SDRAM update commands to reflect a load command register (LCR) command for the flash memory. By establishing this combination, the memory system reads the address line and loads a command register. The memory system uses the contents of the command register 133 (Fig. 1A) to perform flash memory related actions. This is equivalent to turning on a secondary decoding mechanism to allow all fast memory actions to be performed, while only making very small changes to the SDRAM command interface. Commands for flash memory actions are also compatible with flash memory commands that are currently used. Therefore, 'the present invention adds a new command architecture to the SDRAM command architecture' while maintaining compatibility with other flash memory interfaces. See Table 2 for a list of example codes provided above the address line. Therefore 'when the command line contains data corresponding to a DRAM update command sequence' 57 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----------- ---- I --- Order --------- (Please read the notes on the back before filling out this page) 559806 A7 ______ Β7 ____ V. Description of the Invention (Introduction) This invention is provided with information in place A flash memory command register 133 is loaded on the address line. In a standard flash memory, data or I / O connections are used to decode motion commands. This system causes problems with synchronous memory. In other words, if a burst read is in progress and the I / O connection is being used to provide a command, the system must wait for the burst read to complete. Therefore, competition over this data bus is possible. Therefore, the present invention is to load a flash memory command register with data provided on the address line. A synchronous flash memory system includes an array of non-electrical memory cells. The memory device has a package configuration compatible with SDRAM. The memory device includes an array of non-electrical memory cells and a command register to store command data used to control flash memory operations. In operation, the command register is a kind of advance by using a row address strobe (CAS #) signal, a column address strobe (RAS #) signal and a write enable (WE #) signal. The defined combination is loaded to initiate a command register load action. 58 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) ▼---- I ---- Order ------ ---.

Claims (1)

559806 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Application for patent scope 1. A synchronous flash memory device, which includes:-an array of non-electrical memory cells; and a command temporary Register for storing command data used to control the operation of the flash memory, wherein the command register is coupled to be received through a memory address connection during a loading command register operation mode The order information. 2. For example, the synchronous flash memory device in the scope of patent application, wherein the load command register operation mode uses a row address strobe (CAS #) signal and a column address strobe (RAS # ) Signal and a write enable (WE #) signal in a predefined combination. 3. For the synchronous flash memory device in the second scope of the patent application, wherein the load command register operates in the mode where the CAS # signal is low, the RAS # signal is low, and the WE # signal The system is started on the occasion of high. 4. For example, a synchronous flash memory device in the scope of patent application, wherein the flash memory action includes at least one action selected from a group, the group system includes: reading a memory device configuration temporarily Register; read a state register of the memory device; delete the state register; perform an erase and establish operation; perform a write and establish operation; protect a block of the memory cell array; provide Write protection action of a memory device; remove the block that protects the array of the memory unit; 1 · install -------- order --------- (Please read the precautions on the back before (Fill in this page) This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 559806 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. A mode register for the device; and erasing data from the mode register. 5 · —A synchronous flash memory device, comprising:-an array of non-electrical memory cells arranged in addressable blocks; an external address connection for receiving externally provided address data Stomach; a state register for storing state data of a billion body device; a mode register for storing mode data used to set a mode of the synchronized flash memory device; and a mode register for storing A command register used to control the flash memory's command data, where the command register is coupled to receive the command data through a memory address connection in response to a load command ° 6. As requested Synchronous flash memory device according to item 5 of the patent, wherein the loading command is a row address strobe (CAS #) signal, a column address strobe (RAS #) signal, and a write enable (WE #) A predefined combination of signals. 7. For example, the synchronous flash memory device in the scope of the patent application, wherein the loading command is a announced row address strobe (CAS #) signal, a announced column address strobe (RAS) #) Signal and a declared write enable (WE #) signal. 8. For a synchronous flash memory device according to item 5 of the patent application, wherein the load command is equivalent to a synchronous dynamic random access memory (SDRAM) update command. 9. For the synchronous flash memory device in the scope of the patent application, the 2 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 x 297 meals) ----------- -------- Order ——— (Please read the notes on the back before filling this page) 559806? S8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. The scope of the patent application flash memory action includes at least one action selected from the group 'The group system includes: performing a read action of the state register;淸 delete the state register; execute an erasing and establishing action; execute a writing and establishing action; control the writer protection of the array of the non-electrically dependent memory cell; and control the mode register. 10. A synchronous flash memory device, comprising: an array of non-dependent memory cells; & a command register for storing data commands used to control flash memory operations The command register is coupled to respond to a load command to receive the command data, and the load command is equivalent to a synchronous dynamic random access memory (SDRAM) update command. 11. For example, a synchronous flash memory device under the scope of patent application, wherein the loading command is a announced row address strobe (CAS #) signal, a announced column address strobe (RAS) #) Signal and a declared write enable (WE #) signal. 12. A synchronous data system comprising: a memory controller; and a synchronous flash memory device coupled to the memory controller, and comprising a non-electrically-dependent memory unit Array, and one to store the data provided by the memory controller. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 public love). (Please read the precautions on the back before filling this page. ) ---- Order --------- 559806 A8 B8 C8 D8 VI. Application for patent range material command and register used to control the flash memory billion motion register 0 13. If the scope of patent application The synchronous data system of item 12, wherein the command register is coupled to receive the command data through a memory address connection coupled to the memory controller. The command data is in response to a command from the memory. Loaded by the controller's load command. 14. The synchronous data system of item 13 of the patent application, wherein the loading command is a announced row address strobe (CAS #) signal and a announced column address strobe (RAS #) signal , And a combination of an asserted write enable (WE #) signal. 15. The synchronous data system according to item 12 of the patent application, wherein the synchronous flash memory further includes: an external address connection for receiving address data provided by the memory controller; one for A state register for storing state data of the memory device; and a mode register for storing mode data used to set a mode of the synchronous flash memory device. 16. The synchronous data system of item 15 of the patent application, wherein the flash memory action includes at least one action selected from a group, and the group includes: performing a read action of the status register ; 淸 delete the status register; perform an erasing establishment action; 4 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -------- ^. 1 --- ---- (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 559806 A8 B8 C8 D8 Establish actions; control write protection of the non-electrically dependent billion-cell array; and control the mode register. _ 17.—A method for providing commands in a synchronous flash memory. The method includes: using a row address strobe (CAS #) signal, a column address strobe (RAS #) signal, And a pre-defined combination of a write enable (WE #) signal to initiate a command register loading action; and in response to the command register loading action to utilize the address of the synchronous flash memory Connect to load command data into the command register. 18. As in the method of applying for item No. Π, wherein the order register is loaded when the CAS # signal is declared, the RAS # signal is declared, and the WE # signal is not announced . 19. The method according to item Π of the patent application range, wherein the predefined combination is equivalent to a combination of RAS #, CAS #, and WE # used to perform an update operation of a synchronous dynamic random access memory (SDRAM). 20. The method according to item 17 of the scope of patent application, which further includes performing a memory action in response to the command data, the memory action is selected from a group of actions, the group system includes: executing a memory A read operation of the state register; delete the state register; perform an erase and establish operation; perform a write and establish operation; control the write protection of an array of non-electrically dependent memory cells; and 5 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------------------- Order --------- (Please (Please read the notes on the back before filling out this page) 559806 A8 B8 C8 D8 6. The scope of patent application controls a mode register. 21. A method of operating a synchronous flash memory, the method comprising: using a declared row address strobe (CAS #) signal, a declared column address strobe (RAS #) signal, And a combination of an undeclared write enable (WE #) signal to initiate a command register load action in response to the command register load action to utilize synchronous flash memory address connections Load command data into the command register; and execute a memory action in response to the command data. 22. The method according to item 21 of the patent application, wherein the memory action is selected from a group of actions, the group includes: reading a memory device configuration register; reading a memory device State register; delete the state register; perform an erase and create action; perform a write and establish action; protect a block of the memory cell array; provide a memory device write protect action; remove protection A block of an array of the memory unit; writing data to a mode register of the memory device; and erasing data from the mode register. 6 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -------- Order --------- (Please read the precautions on the back before filling this page ) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs