TW557551B - Two-bit mask ROM device and fabrication method thereof - Google Patents

Abstract

A 2-bit mask ROM device and a fabrication method thereof are described. The 2-bit mask ROM device includes a substrate; a gate structure, disposed on a part of the substrate; a 2-bit code region, configured in the substrate beside both sides of the gate structure; at least one spacer, disposed on both sides of the gate structure; a buried drain region, configured in the substrate beside both sides of the spacer, a doped region, configured in the substrate between the buried drain region and the 2-bit code region, wherein the dopant type of the doped region is different from that for the 2-bit code region and the dopant concentration in the doped region is higher than that in the 2-bit code region; an insulation layer, disposed above the buried drain region; and a word line disposed on the gate structures along a same row.

Description

557551

The present invention relates to a structure of a mask-style ceremonial priest, a birth square 氺, a 唯 shi shi a-type V-storage memory, and a method for manufacturing the same, and particularly relates to a double wound _ 曾 曾 上 Α structure and its Production method. The mask-only read-only memory of the mask-type read-only memory is a read-only jack:}: | Sun Zishan Tao 7 Sergeant ^ 1 ° The most basic type of thought 0 is mainly hunted by ion plants Into the process to adjust λΤ!,, 3 has a threshold voltage (Threshold

Voltage), to achieve the control of the memory list: Minr purpose, although the production of the read-only memory of the curtain type is corrected by the system of surnames such as ^ ^ ^ t ~ When the mouth is changed, the process does not need to be significantly Modification, and only need to change the set of photomasks used by μμ 扑 a $ 人 戈 灵 改, so Feiwei is suitable for production of Datong, its 5 opening and closing,】 Shikou Xi / Zheng Shengying even made part of the process first The semi-finished product οσ 'when δ Ding arrives at the factory early, Xunji U4r ll u, 〇 dry N and Ding I' can be programmed (CProgr ammi ng), which can effectively shorten its delivery time. At present, a two-bit mask-only read-only memory has been actively developed. A two-bit mask-only read-only memory is, as the name implies, a type of two-bit per cell that can store two bits of data in a single cell. Memory element. A description of the structure of such a memory element is as follows: As shown in FIG. 1, it is a schematic cross-sectional view of a conventional read-only memory structure of a two-bit mask type. Please refer to FIG. 1. The conventional double-bit mask type read-only memory includes a substrate 10, a gate structure 16, a double-bit coding area 20, an embedded drain 18, and an insulating layer. 2 2 and a character line 2 4. The gate structure 16 is disposed on a part of the substrate 10, and the gate structure 16 includes a gate conductive layer i 4 and a gate oxide layer 12 disposed under the gate conductive layer 丨 4. In addition, the buried drain 18 is disposed in the substrate 10 on both sides of the gate structure 16.

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In addition, the two-bit editing base 10. A gate structure 16 is arranged on the edge system 22 and the bit system 2 implanted for a logic state. In order to make the same column, due to the conventional and double-bit code leakage current (J unct effect (Second read memory is still susceptible to the surrounding read-only memory, it is easy to generate a second margin (Ope ra ti) The element code ions must be adjacent to each other. The two-dimensional screen with the positive electrode interface and the two-dimensional screen is only remembered by the cell volume. The operation is 20, which is arranged on the sides of the gate structure. There is a coded ion implanted in the coding region 20, and it is not programmed into a logic state in the two-bit coding region 20. It is above the buried drain 18 to isolate the two and The gate structure 16 is electrically connected to the gate structure 16 provided with the characters 绨. The buried-type read-only memory of the Wudang curtain-type read-only memory is connected together, so it is very easy to generate ion. Leakage), and it is easy to produce 。Bit Effect. In addition, there is a problem with the known dual bit mask, which is the interference of the memory cells in the memory element. Because the known dual bit cells are easily affected by the surroundings. Because of the bit effect of other memory cells, The memory element 〇n W ind 〇w) is small. Therefore, the object of the present invention is to provide a structure of a two-bit mask type read-only memory and a manufacturing method thereof, so as to eliminate the two-bit mask type read. The second bit effect in memory.

Another object of the present invention is to provide a structure of a two-bit mask type read-only memory and a method for manufacturing the same, so as to prevent the two-bit memory cells from being interfered by other memory cells. . The invention provides a structure of a dual-bit mask-type read-only memory, which includes a base, a gate structure, a dual-bit coding area, and at least two gaps.

child. Then, the photoresist layer is used as a mask—first meaning: 雔: a doped region is formed in iLi, the doped region 4 in ㊣ is different from the ion type of Γ =, and the doped region 4 is in place The ion concentration in the U-shaped and O-shaped areas is high. Then, the photoresistor shoulder 557551 V. Description of the invention (3) A wall, a buried drain, a doped region, and a gate electrode. The gate structure is arranged on a part of the base, ytterbium and-; It has the logic state of winter and the element is not edited. J = the two sides of the junction, and the buried type electrode is in the other two, the doped region is equal to: and the ion concentration of the doped region is more than that of the double layer. Above the buried poles =-placed on the same gate structure. Among them, the word layer: ㊁:] f is a metal silicide layer method on the surface of the polycrystalline silicon layer, and a method of removing a two-bit mask type read-only memory is to first form a substrate on a substrate. The gate electrode includes: the gate conductive layer and the "electrical layer" formed on the substrate. Next, a patterned photoresist and a dual 7L coding region are formed on the substrate, and then the photoresist layer is used as an implant cover. ΓΓ Horse: Step 2 of Implanting in Double Bit Coding Region

I character line. The structure includes configuration in the Zama area, ¥ code away 1 is the code area on both sides of the configuration wall. The concentration of the hair-type phase is high. The element wire is composed of a polycrystal. The manufacturer has a layer under this gate, and the exposed screen is coded one by one. and

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557551 V. Description of Invention (4)

At least one gap wall is formed on both sides of the gate structure. After that, the gate structure and the gap wall are used as an ion implantation mask, and a second ion implantation step is performed to form an embedded drain in the substrate on both sides of the gap wall to form several double-bits. Meta-coded memory cells. In each of the two-bit coded memory cells, the bit line with and without the code ion implantation is in a logical state "丨", and the bit line without any coded ion implantation is in a logical state "0". Finally, an insulating layer is formed on the square of the buried drain, and a / word line is formed on the gate structure of the same column. The doped region formed by the present invention will almost surround the double-bit code after undergoing subsequent hafnium fabrication. ... The structure and manufacturing method of the double-bit mask-type read-only memory of the present invention and the manufacturing method of the double-bit masked area are almost surrounded by the doped region, so that the memory cells can avoid mutual interference. Code region ^ ^ ^ ^ In the dual-bit mask read-only memory, due to the dual-bit encoding of this S, it is surrounded by the doped regions with higher concentration and L 4 3 ion-type cancer. 'Cause L: = Λ barrier reduction effect (Drain ln—d Barrier L should be 0w: nng) can eliminate the second bit effect of the two-bit mask-type read-only memory. The two-bit operation of the present invention does not cause mutual interaction between the memory cells. The mask ^ read-only memory, because the two bits should eliminate the two-bit mask H: interference, and the drain-induced barriers reduce the operating margin of the Titan memory element. The first-position effect, so in order to make the present invention easier to understand, the following special features, features, and advantages can be explained in more detail as follows: Niu Jia Jia Guan Example 'with the accompanying drawings Detailed

557551

Description of the drawing: 10, 100: substrate 1 2, 1 0 2: gate oxide layer 14, 104. Gate conductive layer 1 6, 1 0 5 • gate structure 1 8, 1 2 4: buried Drain 20: Double-bit coding area 2 2, 1 2 6Insulation layers 24, 128: Word lines

106. Pocket-type ion implantation step 108: Pocket-type doped region 11 0: Photoresist layer Π 2 · Double-bit code implantation step 11 4: Double-bit code region 116, 122: Ion implantation step 11 8 • Miscellaneous area 12: Figures 2A to 2E of the embodiment of the partition wall, which are schematic cross-sectional views showing the manufacturing process of the dual-bit mask read-only memory according to a preferred embodiment of the present invention. Referring to FIG. 2A, a gate structure 105 is first formed on a substrate 100. The gate structure 105 includes a gate conductive layer 104 and a gate oxide layer 102 formed under the gate conductive layer 104. In this embodiment, the material of the inter-electrode conductive layer 104 is, for example, polycrystalline silicon, and the gate oxide layer 102 is thick.

557551

The degree is, for example, about 45 angstroms. Next, a pocket-type ion implantation step is performed to form a pocket-type doped region 108 in the substrate 100 on both sides of the gate structure 105. In this embodiment, the ion implanted in the pocket-type doped region 108 is, for example, an arsenic ion. The ion implantation dose in the pocket-type ion implantation step 106 is, for example, 1 x 1013 / cm2, The ion implantation energy of one of the pocket-type ion implantation steps 106 is 50 KeV, and the ion-implantation angle of one of the pocket-type ion implantation steps 106 is 45 degrees, for example. After that, referring to FIG. 2B, a patterned photoresist layer 110 is formed on the substrate 1000, and a double-bit coding region 丨 4 is exposed. After that, a photoresist layer no- is used as an implant mask to perform a double-bit code implanting step 112 to implant a code ion in the double-bit το coding region 1 1 4. In this embodiment, the coded ions implanted in the code region 114 are, for example, Shi Shen ions, and the ion implantation dose of one of the coded implantation steps U 2 is, for example, 2 x 2 The ion implantation energy of one of the two-bit code implantation steps 112 is, for example, e, and the ion implantation angle of one of the two-bit code implantation steps 1 1 2 is, for example, 45 degrees. In the example of f 1 1, there is a coded ion implantation state in the double bit, £ 114 under the sides of the gate structure 105, and the position of Γ is opened, and the station is dead. Turn, you have a logic ^ ^ ^ M ^ without encoding the ion implanter in the subsequent line as having a logical separation " η " Xi Ar s,, * a ^ low difference Γ and because In the previous step, the double-position A of the pocket-type ion coffin n implantation has been ordered. Step 10 6; therefore, there is no pocket-type doping in the place where there is no code ion, and the flat code region District i08. … Refer to Figure 2C, and then use the photoresist layer 110 as an implant mask 557551 V. Description of the invention (?) A first embryonic area 118 is performed. The complex neutron / enter step 116 'to form an ion energy of the doped ionic energy / hetero region 11 8 in the substrate 100 and the separation of the digit code region 114 of the double bit coding region ^ ^, and The ion concentration of the doped region 1 1 8 is higher than that of the two-bit ion by, for example, two degrees.纟 In this embodiment, the implanted implant in the doped region 118 is made of two ions, and one of the first ion implantation steps 116 is -5xi ° i3 / cm2, which is the first ion implantation step. This I implantation is, for example, 40 KeV. Referring to FIG. 2D, the electrode structure is cleared, and after removing the photoresist layer 110, at least one spacer 120 is formed on the gate at a thickness of 120 °. Among them, the gap wall is, for example, 400 angstroms to 600 angstroms, and preferably about 500 angstroms. In addition, the material of the two points Η Γ may be a dielectric material such as a nitride stone or an oxide stone. However, the method of the second wall (the layer C is not, will not), and then the dielectric layer is formed by etching back. After that, please continue to refer to FIG. 2D, and perform a second ion implantation step 12 using the spacer wall 120 and the gate structure 105 as the implant mask to form the substrate 1 on both sides of the spacer wall 120. 〇〇 formed an embedded drain 1 24, and formed a number of double-bit coded memory cells. Among them, in each of the two-bit coded memory cells, the bit system with a coded ion implantation is a logic state ", " and the bit system without a coded ion implantation is a logic state ". In this embodiment, the ions implanted in the buried drain 124 are, for example, bf2 + ions, and the ion implantation dose in one of the second ion implantation steps 1 2 2 is, for example, 1 x 10 15 / cm 2 The ion implantation energy of one of the two ion implantation steps 1 2 2 is, for example, 10 kV. Next, please refer to FIG. 2E. An insulating layer 1 2 6 is formed above the buried drain electrode 1 2 4 to isolate two adjacent gate structures. Of which, absolutely

9236twf.ptd

557551 Five invention description (8) __ ,, 126 The material is, for example, oxidized dream. In addition, an insulating sound Y ^ S is formed on the substrate 1G Q—an insulating material f layer (not shown), Example ii: T〇5, and then -chemical mechanical polishing method or -back: ί ί remove Partially enough fate; g Wao carved knife, color, water layer, until the gate structure 105 is exposed. Then, a word line 128 is formed on the gate structure 05 = the gate structures 1 (5) of the column are electrically connected to each other with a phase material of, for example, polycrystalline silicon. In addition, a metal silicide layer is formed on the surface of the first and second lines 70 and 128 of the present invention (the resistance value of the zigzag character line 128. θ ^ is wrong to reduce the value of the word 值得注意), the mask of the present invention After several subsequent thermal processes in the read-only memory, the doped region 118 will almost surround: the bit coding region 114. In other words, the two-bit coding region 丨 ΐ4 will be reversed by the ion type and A higher concentration of the doped region 118 surrounds it. In this way, the drain-induced barrier reduction effect can eliminate the bit effect of the two-bit curtain read-only memory and reduce the memory cell Interference with each other, thereby improving the operating margin of the component. In summary, the present invention has the following advantages: 1 · The structure of the dual-bit mask-type read-only memory of the present invention and its manufacturing method can avoid the memory cell The two-bit mask-type read-only memory structure and manufacturing method of the present invention can eliminate the second-bit effect of the two-bit mask-type read-only memory. 3 Structure and read-only memory of dual-bit screen Manufacturing method, can increase the operating margin of the memory element. Although the present invention has been disclosed in terms of preferred embodiments consistent application above, they are not intended

9236twf.ptd Page 13 557551 V. Description of the invention (9) The invention is limited. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the invention. Therefore, the scope of protection of the invention It shall be subject to the definition in the appended patent application scope.

9236twf.ptd Page 14 557551 Brief description of the drawings Figure 1 is a schematic cross-sectional view of a conventional read-only memory structure of a two-bit mask; and Figures 2A to 2E are a preferred embodiment of the present invention. The schematic diagram of the manufacturing process of the dual-bit mask read-only memory. phosphorus

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Claims (1)

557551 VI. Scope of patent application1. A structure of a two-bit mask type read-only memory, including: a substrate; a gate structure arranged on part of the substrate; a double-bit coding area arranged on the gate In the substrate underneath both sides of the electrode structure; at least one spacer wall disposed on both sides of the gate structure; a buried drain electrode disposed in the substrate on both sides of the spacer wall; a doped region, Disposed in the substrate between the buried drain and the double-bit coding region, wherein the ion type of the doped region is opposite to that of the double-bit coding region, and the doped region The ion concentration is lower than the ion concentration of the two-bit coding region, an insulating layer is disposed above the buried drain, and a word line is disposed on the surface of the gate structure. 2. The structure of the double-bit mask read-only memory as described in item 1 of the scope of patent application, wherein the doped region surrounds the double-bit coding region. 3. The structure of the dual-bit mask type read-only memory as described in item 1 of the scope of the patent application, which further includes a pocket-type doped region arranged in the dual-bit code without the code ion implantation. Area. 4. The structure of the dual-bit mask type read-only memory as described in item 3 of the patent application scope, wherein the ion doped in the pocket-type doped region includes arsenic ions, and The doped dose is 1 X 1013 / cm2 〇5. The read-only record of the two-bit mask as described in item 1 of the scope of patent application 9236twf.ptd Page 16 557551 6. The structure of the scope of the patent application, JL φ Xi & an ion, and the ion implanted in the ^ 1-bit coding region includes arsenic 6 such as ^ & Kui Wu, The implanted dose in the code area is 2 X 1013 / cm2. 6 · Such as the scope of the patent application item 1 > Membrane structure, 1 zhongqin pine, two-position 70-style curtain-type projectile, and the ions implanted in the μ μ rural area include Bpv ions and The amount of implanted in === 5χΐ〇ΐ3 /-. 7 · Rushen # The scope of the first memory of the patent scope, the straight-centered, double-positioned 70-position mask-type erbium ions, the ions doped in the H-type drain include BF2 + two-bed erbium 'and This buried drain φ 1 015 / cm2. The dosage of Pseudotsuga chinensis is 1 · 5 X 8 · As the structure recalled in item 1 of the patent application scope, the door in the double-positioned veil of the door is the only item 5 己 9. The thickness of the bite is 400 Angstroms. To 600 angstroms. The two-bit mask screen described in Item 1 of the Pity Body Club only reads on the top of the silicon layer-metal silicide-polycrystalline silicon layer and includes in the polycrystalline: 10.-a two-bit mask screen The manufacturing method of the read-only memory includes forming a gate structure photoresist layer on a substrate, exposing a double bit to form a patterned coding region on the substrate; using the photoresist layer as a mask to perform a A double-bit coding region is implanted with a code, and the photoresist layer is used as a mask to form a doped region in a substrate. The ion type of the bit-coding region is opposite. Ions; a first ion implantation step, the ion concentration in the doping region and the ion concentration in the doped region are greater than the ion concentration 55755l The ion concentration in the double-bit coding region is high; removing the photoresist layer; forming at least one gap wall on the side wall of the gate structure; using the gap wall and the gate structure as a mask to perform a second ion implantation ^ Steps to form a buried in the substrate on both sides of the gap wall: a type of button, wherein the embedded type and the double-bit coding region have the / i region in the shape i, in which the embedded Forming an insulating layer above the drain; and forming a word line on the gate structure. II 11 · The readout of the double-bit mask as described in item 10 of the scope of patent application. The manufacturing method of memory, in which the double-bit coding area is surrounded by the operation area after several subsequent thermal processes. ^ 12. The method for manufacturing a dual-bit mask type read-only memory as described in item 10 of the scope of patent application, wherein after the gate structure is formed, a pocket-type ion implantation step is further performed, in which A pocket-type doped region is formed in the substrate under both sides of the gate structure. 1 3 · The manufacturing method of the double-bit mask read-only read-only memory as described in item 2 of the patent application scope, wherein the ions implanted in the pocket-type doped region include sand ions, and the pocket One ion implantation step is an ion implantation dose of 1 × 10 3 / cm 2, one pocket ion implantation step has an ion implantation energy of 50 KeV, and one pocket ion implantation step has an ion implantation step. The entry angle is 45 degrees. 1 4 · The manufacturing method of the read-only memory of the two-bit mask type described in item No. 丨 0 of the patent application scope, wherein 557551 6. The scope of the application for a patent. A coded ion includes a god ion, and the ion implantation dose of one of the two-bit coded implantation steps is 2 × 10 3 / cm 2. One of the two-bit coded implantation steps is ion implantation. The input energy system is 50 Ke V, and the ion implantation angle of one of the two-bit code implantation steps is 45 degrees. 1 5. The method for manufacturing a dual-bit mask type read-only memory as described in item 10 of the scope of patent application, wherein the implanted ions in the doped region include BF, ions, and the first ion implanted One ion implantation dose is 5 X 1013 / cm2, and one ion implantation energy is 40 KeV °. 16 · The manufacturing method of the dual-bit mask type read-only memory according to item 10 of the scope of patent application, wherein the ions implanted in the buried light pole include BF / ions, and the second The ion implantation dose of one of the ion implantation steps is 1 X 1 015 / cm2, and the ion implantation energy of one of the second ion implantation steps is 10 KeV 〇 1 7 The manufacturing method of the dual-bit mask type read-only memory described above, wherein the method of forming the insulating layer includes: forming an insulating material layer over the substrate to cover the gate structure; and A part of the insulating material layer is removed by an etching method or a chemical mechanical polishing method until the gate structure is exposed. 18 · According to the manufacturing method of the two-bit mask type read-only memory described in item 1 Q of the patent application scope, the thickness of the gap 璧 is from 400 angstroms to 600 angstroms. 1 9 · Double-bit mask-only readout as described in the scope of the patent application 9236twf.ptd Page 19 557551 6. A method for manufacturing a patent application memory, wherein the method of forming the word line includes: forming a polycrystalline silicon layer on the gate structure; and forming a polycrystalline silicon layer on the surface A metal stone oxide layer. 9236twf.ptd Page 20