TW556323B - Recess type gate and its formation method of flash memory - Google Patents
Recess type gate and its formation method of flash memory Download PDFInfo
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- TW556323B TW556323B TW090118491A TW90118491A TW556323B TW 556323 B TW556323 B TW 556323B TW 090118491 A TW090118491 A TW 090118491A TW 90118491 A TW90118491 A TW 90118491A TW 556323 B TW556323 B TW 556323B
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- 238000007667 floating Methods 0.000 claims abstract description 20
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 238000009413 insulation Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
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- 238000002955 isolation Methods 0.000 claims 2
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- 150000001875 compounds Chemical class 0.000 claims 1
- 239000003989 dielectric material Substances 0.000 claims 1
- 239000011229 interlayer Substances 0.000 claims 1
- 230000001404 mediated effect Effects 0.000 claims 1
- 150000002739 metals Chemical class 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000004575 stone Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 9
- 230000005641 tunneling Effects 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000003860 storage Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
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Abstract
Description
556323 _ _案號90118491_年月—日 修不 五、發明說明（1) " 發明領域： 本發明與一種快閃記憶體有關’特別是關於一種快閃 記憶體的凹陷式閘極結構與其製造方法。 發明背景·· 於習知技藝中’已有多種的非揮發性記憶體被揭露。 舉例來說，Mi tchel lx曾提出具自對準平面陣列電胞（sel -aligned planar array cell)的可抹除可程式化唯讀記 憶體（E P R Ο M S )。在此技術中’埋入式擴散自對準至浮置閘 極崩射MOS電晶體使用在位元線上。交錯點陣列（cr〇ss point array)技術已經揭露。此自對準源極與汲極將隨元 件而被最適化，即使是進一步的針對程式化速率。見A. τ.556323 _ _Case No. 90118491_Year-No.5, description of the invention (1) " Field of invention: The invention relates to a flash memory ', especially to a recessed gate structure of a flash memory and its Production method. BACKGROUND OF THE INVENTION A variety of non-volatile memories have been disclosed in the art. For example, Mitchel lx has proposed an erasable and programmable read-only memory (E P R OM M S) with a self-aligned planar array cell. In this technique, 'buried diffusion self-aligned to floating gate burst MOS transistors are used on bit lines. Cross point array technology has been revealed. This self-aligned source and sink will be optimized with the component, even for further programming speed. See A. τ.
Mitchellx，’’A New Self - Aligned Planar Cell forMitchellx, ’’ A New Self-Aligned Planar Cell for
Ultra High Density EPROMS1', IEDM, Tech. pp. 548-553， 1987。 快閃記憶體是部分非揮發性記憶體元件的其中之一。 此元件包含一浮置閘極以儲存電荷，與一元件（element) 可於浮置問極電性放置與移去電荷。快閃記憶體的應用之 一為電腦的B I 0S。傳統上，高密度的非揮發性記憶體可以 應用作為手長：式便利終端機（p〇rtabie handy terminals )、數位照相機（s〇丨i d state camera)與pc卡的大量存 儲之用。這是由於非揮發性記憶體表現很多的優點，例如 •供速的4取時間、低能量損耗與堅固而才用（r 〇匕u s七n e s s )° Bergemont提出另一種電胞陣列（cell array)應用於Ultra High Density EPROMS1 ', IEDM, Tech. Pp. 548-553, 1987. Flash memory is one of some non-volatile memory components. This element includes a floating gate to store charge, and an element can be used to electrically place and remove charge on the floating interrogator. One application of flash memory is the computer's B I 0S. Traditionally, high-density non-volatile memory can be used for hand storage: large-scale handy terminals, digital camera, and mass storage of PC cards. This is due to the many advantages of non-volatile memory, such as the speed of 4 fetch time, low energy loss and ruggedness (r 〇 匕 us ness ness) ° Bergemont proposed another cell array Apply to
556323 案號 90118491 年 月 曰 條正 五、發明說明（2) 手&式電腦與遠距通訊，參見Bergemont et al.，nLow Voltage NVGTM: A New High Performance 3V/5V Flash Technology for Portable Computing and Telecommunications Applications' IEEE Trans-Electron Devices， v〇l. ED-43， p.1510, 1996。 此提出 給低電壓NVG( NOR Virtual Ground)快閃記憶體的電胞結 構擁有快速的存取時間。於概要的快閃記憶體陣列，場氧 化層（FOX)形成在電胞之間，多晶矽層擴張至每個電胞的 FOX上以提供足夠的閘極耦合率。Bergemont也提及在積體 電路領域，手提式電腦與遠距通訊已成主要趨勢。在此技 藝中’存取時間乃低壓讀取操作的關鍵考量之一。NVG陣 列使用選取元件以達到快速存取時間，藉由對單一部份而 非全部的位元線預充電而減少預充電時間。 取。，快5 了須 存的此壓U為必 速須因低3 。度 快必。，為術厚 與是間前壓技層 源統時目電本電 電系段。，基介 應器一能時的的 供算中效極電間 低運極高閘放材 著動閘有置或底 朝行置具浮電與 ，在浮須電充極。 造求於層放乃閘壓 製需荷電或穿置電 的些電介電遂浮應 體這有的充，此供 憶為持極於者，的 記因要閘用藝率低 性，須置應技效減 發展體浮之此穿應 揮發憶緣體知遂因 非向記絕憶熟高以 方閃來記如到小 的快用閃。得縮 吳國專利案號6, 1 8 0, 45 9,標題為”Meth〇d for icating a flash memory with shallow trench556323 Case No. 90118491 Article 5: Description of Invention (2) Hand & Computer and Long-distance Communication, see Bergemont et al., NLow Voltage NVGTM: A New High Performance 3V / 5V Flash Technology for Portable Computing and Telecommunications Applications' IEEE Trans-Electron Devices, Vol. ED-43, p. 1510, 1996. This proposal proposes a fast access time for the cell structure of low voltage NVG (NOR Virtual Ground) flash memory. In the general flash memory array, a field oxide layer (FOX) is formed between the cells, and a polycrystalline silicon layer is expanded onto the FOX of each cell to provide a sufficient gate coupling rate. Bergemont also mentioned that in the field of integrated circuits, portable computers and telecommunications have become a major trend. In this technique, 'access time' is one of the key considerations for low-voltage read operations. NVG arrays use select components to achieve fast access times and reduce precharge time by precharging a single, but not all, bit lines. take. This pressure U must be saved almost 5 times and must be reduced 3 times. Degree soon. This is the section of the eye-electricity-electricity system when the system is thick and the front is pressed. Low-speed, extremely high-storage discharge materials are used when the base reactor is capable of being operated. The floating brake is installed at the bottom of the moving brake. In order to suppress the need for charging or penetrating electricity, some dielectric dielectric levitation bodies are required to be stacked. This memory is very important. The reason for the low utilization rate of the gate is that it must be installed. It should reduce the effect of the development of the body, and the memory of the body should be volatile. The memory of the body knows that it is not necessary to remember the memory, and the high flash is used to remember it. WU Guo Patent Case No. 6, 1 0 0, 45 9, titled "Meth〇d for icating a flash memory with shallow trench
第6頁 556323 案號 90118491 修正 五、發明說明（3) i s ο 1 a t i ο ηπ，於1 9 9 9年元月8日申請。習知技藝中製作快 閃記憶體時包含形成一淺溝渠絕緣（S Τ I )結構，此專利發 明方法同樣形成此結構。另一美國專利案號6，1 7 2，3 9 5， 標題為"Method of manufacture of self-alinged floating gate, flash memory cell and device manufactured thereby”，專利所有權屬於台灣半導體製 造公司（TSMC)。 其餘的習知技藝可參見美國專利案號6，1 7 2，3 9 6。此 形成符浮置閘極的方法不是凹陷形式。 發明目的及概述： 本發明之目的係形成一種快閃記憶體之凹陷式閘極結 構及其方法。 形突此上在電 已。由層成導 一上，電形二 含材面介層第 包底表一電一 少此的第介成 至於材述二形 構成底前第上 結形述在一層 極層前成。電 閘電過形極介 式介出層閘二 陷一突電置第 凹第並導浮述 之一中一 一前 體，渠第成於 憶材溝一當並 記底述。以，。 性的前間，上極 發中於其中層閘 揮其成於槽電制 非於形槽凹導控 1 渠緣凹述一為 溝絕成上第作 成出形與該層 形突 已。 一上 含材 包底 少此 至於 構成 結形 極層 閘電 式介 陷一 凹第 之一 體， 憶材 記底 性的 發中 揮其 utr Λ: 1 渠 溝 成Page 6 556323 Case No. 90118491 Amendment V. Description of the Invention (3) i s ο 1 a t i ο π, applied on January 8, 1999. Making flash memory in the conventional art involves forming a shallow trench insulation (STI) structure. This patented method also forms this structure. Another U.S. patent case No. 6, 1 7 2, 3 9 5, entitled " Method of manufacture of self-alinged floating gate, flash memory cell and device manufactured thereby ", the patent ownership belongs to Taiwan Semiconductor Manufacturing Corporation (TSMC). The remaining conventional techniques can be found in U.S. Patent Nos. 6,172, 396. This method for forming floating gates is not a recess. Purpose and Summary of the Invention The purpose of the present invention is to form a flash memory. The recessed gate structure and its method. The shape of the electrode is on top of it. The layer is formed on top of the first, the shape of the two material-containing surface interposer is the bottom of the table, the first is the first, and the second is the second. The top and bottom knots are formed in front of a layer of electrodes. The gates pass through the shape of the dielectric layer, and the gates are secondly recessed, firstly set to be recessed, and first to the first one. Formed in Yicaigou and recorded the bottom. So, the front part, the upper pole is in the middle gate, it is formed in the groove, the electric system is not shaped, the groove is guided, the groove is concave, and the groove is described as a groove. It's definitely the first time to make a shape and this layer has a sudden shape. As the gate electrode layer constituting the junction type electric trap one of the first dielectric body a recess, a bottom made of memory material is referred to in which play utr Λ: 1 into a drainage ditch
第7頁 556323 案號 90118491 Λ_η 曰 修正 五、發明說明（4) 出絕緣形成於前述溝渠中並突出過前述底材的表面，由此 形成凹槽於其間。一第一導電層沿前述第一介電層與前述 凹槽的表面均勻的形成，以當成一浮置閘極。一第二介電 層形成在前述第一導電層上，並於前述第二介電層上形成 一第二導電層作為控制閘極。 如上所述，傳統非揮發性記憶體的製程並無法降低用 來絕緣浮置閘極的介電層而無法具有較高的效能，此因介 電層的厚度係決定浮置閘極於充電或放電時的遂穿效率， 只要有厚度必致降低遂穿效率，進而增加供應電壓的需求 。相對地，本發明將浮置閘極形成於凹陷結構中，如此即 可避免遂穿介電層的厚度所導致的種種問題，尤其可符合 產業上增加遂穿效率以降低供應電壓的設計。 發明詳細說明： 本發明提出一製造快閃非揮發性記憶體的新方法。於 本發明的方法，快閃記憶體具有凹陷浮置閘極。本發明之 的詳細說明如下，所述之較佳實施例只做一說明非用以限 定本發明。 _ 本發明之結構的實施例，如圖四所示，包含一底材， 其内部已形成溝渠。一第一介電層形成於前述底材上，且 突出絕緣形成於前述溝渠中並突出過前述底材的表面，藉 此形成凹槽於其間。一第一導電層形成在第一介電層上與 上述凹槽中，以當成一浮置閘極。一第二介電層形成在第Page 7 556323 Case No. 90118491 Λ_η Revision V. Description of the invention (4) The insulation is formed in the aforementioned trench and protrudes over the surface of the aforementioned substrate, thereby forming a groove therebetween. A first conductive layer is uniformly formed along the surfaces of the first dielectric layer and the groove to serve as a floating gate. A second dielectric layer is formed on the first conductive layer, and a second conductive layer is formed on the second dielectric layer as a control gate. As mentioned above, the traditional non-volatile memory manufacturing process cannot reduce the dielectric layer used to insulate the floating gate and cannot have high efficiency. This is because the thickness of the dielectric layer determines whether the floating gate is charged or charged. For the tunneling efficiency during discharge, as long as there is thickness, the tunneling efficiency will be reduced, thereby increasing the demand for the supply voltage. In contrast, the present invention forms a floating gate in a recessed structure, which can avoid various problems caused by the thickness of the tunneling dielectric layer, and is particularly suitable for industrial designs that increase tunneling efficiency to reduce the supply voltage. Detailed description of the invention: The present invention proposes a new method for manufacturing flash non-volatile memory. In the method of the present invention, the flash memory has a recessed floating gate. The detailed description of the present invention is as follows. The preferred embodiment described is only for illustration and is not intended to limit the present invention. _ An embodiment of the structure of the present invention, as shown in FIG. 4, includes a substrate, and a trench has been formed inside it. A first dielectric layer is formed on the substrate, and a protruding insulation is formed in the trench and protrudes over a surface of the substrate, thereby forming a groove therebetween. A first conductive layer is formed on the first dielectric layer and in the groove to serve as a floating gate. A second dielectric layer is formed on the first
556323 -----—案號 90118491 五、發明說明（5) 一導電層上，並於前述第 為控制閘極。 —«_g__ 修正_ 二介電層上形成一第二導電層作 製造此元件的方法，詳述如下： 提供體底材。舉-較佳實施例，如圖-所示， 棱i' 一具<100〉或〈111〉晶向之單 ^ 成底材2上，之後圖案化此篡1品^夕底材2。一罩幕層4形 用一標準賴影及㈣步驟^v：：^2。亦即是’使 ?麻姑9、* π命 V知餘刻刖述之罩幕層4並深入 =ί;二二t =埃=:r-。二匕 作為、，.巴、，彖。間隙充填材料8為由 -^ ^ ^ rvn ^ 马甶CVD糸統形成之氧化物，即 瓜k及的CVD-oxlde。以—較佳實施 ， ΐο；Ρ^4Γ 6〇〇〇C τ ^ ^ ^ ^ ^ (CMP)和除表層的cVD-oxide 8至幕罩層4。556323 ------ Case No. 90118491 V. Description of the invention (5) On a conductive layer, the gate is controlled as described above. — «_ G__ Modification_ A method of manufacturing this component is formed by forming a second conductive layer on the two dielectric layers, as follows: Provide a body substrate. As a preferred embodiment, as shown in FIG. 1, the edge i ′ has a single crystal with <100> or <111> crystal orientation on the substrate 2, and then the pattern 2 is patterned on the substrate 2. A mask layer 4 shape uses a standard Lai Ying and ㈣ steps ^ v :: ^ 2. That is to say, “Mu Ma 9 、 * π 命 V Zhiyu's narrative mask layer 4 and go deeper = ί; 二 二 t = 埃 =: r-. Two daggers as ,,. The gap filling material 8 is an oxide formed by the-^ ^ rvn ^ horse CVD system, that is, CVD-oxlde. In a preferred implementation, ^ ο; P ^ 4Γ60000C τ ^ ^ ^ ^ ^ (CMP) and cVD-oxide 8 except for the surface layer to the curtain layer 4.
請參閱圖二’移除此幕罩層4藉以形成此昇起的絕緣 填充體，並形成孔洞10於其間。一由氧化矽組成的薄遂穿 介電層12形成於底材2之上。基本上，此氧化層12可在溫 度範圍約70 0至l〇〇(TC的氧氣環境下生成。另一種方法如 化學氣相沉積法，同樣亦可用來形成氡化層i 2。在此實施 例中，此極薄的遂穿氧化層12是以熱製程形成，且並不曝 露在電漿中，這樣可以避免底材受到電聚損傷。導電層14 ，其組成例如為摻質多晶矽或金屬1沉積在遂穿介電層Please refer to FIG. 2 'to remove the curtain cover layer 4 to form the raised insulating filling body, and form a hole 10 therebetween. A thin tunneling dielectric layer 12 composed of silicon oxide is formed on the substrate 2. Basically, the oxide layer 12 can be formed in an oxygen environment at a temperature range of about 70 to 100 ° C. Another method, such as a chemical vapor deposition method, can also be used to form the halide layer i 2. Here, it is implemented For example, the extremely thin tunneling oxide layer 12 is formed by a thermal process and is not exposed to the plasma, so that the substrate can be prevented from being damaged by electropolymerization. The conductive layer 14 is composed of doped polycrystalline silicon or metal 1 Deposited on the tunneling dielectric layer
第9頁 556323 _案號90118491_年月日__ 五、發明說明（6) 1 2上。本發明的另一個優點在於蝕刻導電層1 4的步驟被省 去而以蝕刻介電層取代。一般說來，多晶矽層1 4可選擇摻 質多晶矽或同步摻質多晶矽。舉一實施例，此摻質多晶矽 層1 4可以PH3為來源摻雜磷。然後，移除部分的導電層1 4 以得到一平坦的表面。藉以形成凹陷浮置閘極於絕緣填充 體間。此可使用電漿蝕刻·或 CMP法達成，如圖三所示。 接著，請參閱圖四，形成内多晶矽介電層（I PD ) 1 6於 凹陷浮置閘極的表面。此内多晶矽介電層1 6以ΟΝΟ (氧化物 /氮化物/氧化物）或NO為宜。最後，第二導電層18，其組 成以摻質多晶矽或金屬為例，形成於多晶矽介電層1 6上， 作為控制閘極。此摻質多晶矽層1 8可選擇摻質多晶矽或同 步摻質多晶矽。除此之外，金屬或合金亦可選擇作為導電 層1 8的組成。 請參閱圖五，另一類的選擇，可沿著填充體間的凹槽 表面，形成均勻的導電層2 0以作為浮置閘極。此種節構可 增加耦合速率。接著的步驟為沿此均勻導電層2 0的表面形 成0N0層。然後，形成第二導電層18。 本發明以較佳實施例說明如上，而熟悉此領域技藝者 ，在不脫離本發明之精神範圍内，當可作些許更動潤飾， 其專利保護範圍更當視後附之申請專利範圍及其等同領域 而定。Page 9 556323 _ Case No. 90118491 _ Month and Day __ V. Description of the invention (6) 1 2 above. Another advantage of the present invention is that the step of etching the conductive layer 14 is omitted and replaced with an etching dielectric layer. Generally speaking, the polycrystalline silicon layer 14 may be doped polycrystalline silicon or synchronously doped polycrystalline silicon. In one embodiment, the doped polycrystalline silicon layer 14 can be doped with phosphorus as a source of PH3. Then, a part of the conductive layer 1 4 is removed to obtain a flat surface. Thereby, a recessed floating gate is formed between the insulating filling bodies. This can be achieved using plasma etching or CMP, as shown in Figure 3. Next, referring to FIG. 4, an inner polycrystalline silicon dielectric layer (I PD) 16 is formed on the surface of the recessed floating gate. Here, the polycrystalline silicon dielectric layer 16 is preferably ONO (oxide / nitride / oxide) or NO. Finally, the second conductive layer 18 is composed of a doped polycrystalline silicon or metal as an example, and is formed on the polycrystalline silicon dielectric layer 16 as a control gate. The doped polycrystalline silicon layer 18 can be selected from doped polycrystalline silicon or synchronously doped polycrystalline silicon. Besides, a metal or an alloy may be selected as the composition of the conductive layer 18. Please refer to FIG. 5. For another type of selection, a uniform conductive layer 20 can be formed along the surface of the groove between the filling bodies to serve as a floating gate. This kind of structure can increase the coupling rate. The next step is to form a 0N0 layer along the surface of this uniform conductive layer 20. Then, a second conductive layer 18 is formed. The present invention is described above with reference to the preferred embodiments. Those skilled in the art can make some modifications without departing from the spirit of the present invention. The scope of patent protection should be regarded as the scope of the attached patent application and its equivalent. Field-specific.
第10頁 556323 _案號90118491_年月曰 修正_ 圖式簡單說明 利用後續說明以及下列圖式之配合，可更清析的了解 本發明之内容及優點，其中： 第一圖顯示依據本發明在半導體底材中形成突出絕緣 之步驟的半導體晶圓橫截面示意圖。 第二圖顯示依據本發明在半導體底材中形成遂穿氧化 層之步驟的半導體晶圓橫截面示意圖。 第三圖顯示依據本發明在半導體底材中形成浮置閘極 之步驟的半導體晶圓橫截面示意圖。 第四圖顯示依據本發明在半導體底材中形成控制閘極 之步驟的半導體晶圓橫截面示意圖。 第五圖為本發明之另一橫截面示意圖。 代表符號說明 2 底材 4幕罩層 6 溝渠 1 0孔洞 14導電層 18第二導電層 8 間隙充填材料 1 2遂穿介電層 1 6内多晶矽介電層 2 0均勻的導電層Page 10 556323 _Case No. 90118491_ Year and Month Amendment _ Brief Description of the Drawings Using the following descriptions and the following drawings, the contents and advantages of the present invention can be more clearly understood, of which: The first figure shows the invention A schematic cross-sectional view of a semiconductor wafer in a step of forming a protruding insulation in a semiconductor substrate. The second figure is a schematic cross-sectional view of a semiconductor wafer in a step of forming a tunneling oxide layer in a semiconductor substrate according to the present invention. The third figure is a schematic cross-sectional view of a semiconductor wafer in the step of forming a floating gate in a semiconductor substrate according to the present invention. The fourth figure is a schematic cross-sectional view of a semiconductor wafer in a step of forming a control gate in a semiconductor substrate according to the present invention. The fifth figure is another schematic cross-sectional view of the present invention. Description of representative symbols 2 Substrate 4 Curtain layer 6 Ditch 1 0 Hole 14 Conductive layer 18 Second conductive layer 8 Gap filling material 1 2 Pass through the dielectric layer 1 6 Polycrystalline silicon dielectric layer 2 0 Uniform conductive layer
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7314792B2 (en) | 2005-04-29 | 2008-01-01 | Hynix Semiconductor Inc. | Method for fabricating transistor of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7314792B2 (en) | 2005-04-29 | 2008-01-01 | Hynix Semiconductor Inc. | Method for fabricating transistor of semiconductor device |
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