TW556205B - Method for inspecting flash memory logic address - Google Patents

Abstract

A method for inspecting flash memory logic address is disclosed. It sets up a proportionally decreasing logic-physical address comparison table that uses a region as a unit in the DRAM firstly when the system turns on. Use the table to get the physical region corresponding to the logic address. Then sequentially search every block of the physical region till reaching the corresponding physical address. The balance point of the speed and space is obtained in order not to occupy too much space and keep high processing speed as well.

Description

556205

Field of the Invention: The present invention relates to a method for detecting a logical address of a flash memory, and more particularly to a method in which a plurality of blocks (bloc) are used as a zone, and the logic / entity is made by the unit of the zone. Address mapping table (Address Mapping Table, AMT or L00k — Up TaMe), and use this address mapping table to detect logical addresses. Background of the invention: One-click, in the working principle of the memory, when the microprocessor uses the memory as the data storage area, the calculation results and data are stored here. If the process j is to be accessed, it can also be accessed. Storage area. While storing data and reading data, the microprocessor will define the location of the memory by the required information. The U processor will send the address to the memory through the location bus, and then the data will be transmitted to the corresponding data. To the correct address. The most important part of the memory is the day of the fetch, from the instruction issued by the government processor to the address data, and the response of the body to the data sent to the microprocessor, until the microprocessor does receive the shell. The time taken by this process is the memory access time. In Flash memory, data is stored and read in units of blocks (Mock) composed of several bytes. Each block that can be accessed by data has a physical address. ), The flash memory space sequence is replaced by ff, such as the location of physical memory in static random access memory (), and each block records the logical bits marked by the file system of the drive Address (Page 4 of page 556205) 5. Description of the invention (2)

Address), as shown in the first (a) figure, and the corresponding logical address logical address; however, the carcass addresses each have a file operation system required to access data in the flash mechanism, because ( LoglCal's physical address knows where the logical address is, and the second system cannot be directly reached to the corresponding logical address. 11 There are usually two ways to get the first way is to build the system first when the system is turned on-the mapping table, which It records the logical address and the physical address series / physical address cell, and is designed as shown in the following table. There is a mapping relationship between multiple SRAMs. When the address mapping table is established °, 22 = address pair The mapping table is as the first one, and the corresponding physical position ^ The order of the logical address of the copper 1 address is irregularly arranged, so it must be%: Errongzhong, because the original one can build one as the first ( b) The map shown in the figure m is sorted once. The mapping table is stored in SRAM. This kind of forward entity ^ mapping table, and this = :? Create a part to save the existing mapping table. Address mapping table, and then quickly get the relative search brother in _ middle address. This kind of use imitates this master μ; For the physical address conversion time of the 5H logical address, the conversion time is short, and the method of logical address ^ ^ inch logical address has the advantages of recording the two bits, but it requires a lot of coffee and because of the current l The space occupied by the relationship is quite large; when the number is integrated into a single system chip, the field can be eroded, and the number of SRAMs cannot be increased at any time according to demand, which becomes a limitation on use. 556205

Another type of logical address inference plan does not need to establish any address to search for the head corresponding to the physical address of the parent and secondary, until the design without the SRA M is found, so you must search from the beginning when not occupying the address. The speed of data is quite slow. The method of the physical address is the SRAM-free mapping table ', which only needs to use a software program to edit the address from the logical address required in the memory. This method has space, but because the search time for each logical bit is slow, the memory access is slowed down ... Because the present invention addresses the lack of knowledge in the above two physical 1-address / logical address conversion methods. To achieve an effective balance point, so that this book takes into account the speed and space problems, in order to effectively improve the purpose and summary of the invention of data storage:. The main purpose of this month is to propose a method for detecting the logical address of flash memory. It uses the zone as a unit and first establishes a scaled factor logical / physical address mapping. Table, and obtain the regional address through the logical / physical address mapping table, and then search for the logical address relative to the physical address, so as to achieve speed increase with effective investment. . Another object of the present invention is to provide a method for detecting a logical address of a flash memory, which uses an adjustable random access memory so as to simultaneously improve the semiconductor magnetism without adding too much space. The processing speed of the disc device. In order to achieve the above-mentioned object, the present invention first sets a plurality of regions in the flash memory.

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The block is set to b & ss, the regional address corresponds to its corresponding logical address, and the physical address mapping table is stored at the time of power-on, and it is stored in the property relationship to establish a proportional reduction in access to data At first, a memory to be accessed will be provided; when the system body uses the logical address to be searched to obtain the physical area address of the random access memory pair, and then search the current address mapping table to get One phase is obtained until each logical block in the ':: domain' is obtained, and the bottom address is matched with a specific embodiment in the following. It is easy to understand the purpose of the present invention, and the drawings of the technique are explained in detail, which is more effective. T valley, characteristics and the figure of the work reached: 10 logical address to be checked 12 logical / physical address mapping table 14 detailed description of physical area: machine time = plural blocks as a zone 'in the system Open Γίίϊ Mapping Table—PPlng Table domain physical address mapping table, and with random access ° ===! To take the characteristics, search in the random access memory ^ r ^, meaning to know the physical area, It then looks for the logical address relative to the physical address in the area. When data can be stored and read in i = ΐ memory, each block that can be accessed by data has a physical address to represent the memory.

556205 V. Description of the Invention (5)! :::: Real 2! ==: Department of Soil and Inventory, the logical address set for each region, such as the position of the (__af_u) region and its corresponding non-linear correspondence. ) In Figure 2, according to the position of the second (a) figure, the system is initialized when it is initialized, that is, it will be scaled first. The scale is copied and established first. Mapping table, please also refer to storing it in the static random: take: after the mapping table 'that is:;: rr address: == 丄 == to occupy too much == contraction; = 7 body address mapping table and There is no need to recall the number of bodies. Therefore, the use of static random access can be reduced, and the above-mentioned area composed of N areas is 2η, and the area is composed of 2 " blocks. In the best case, the value of η is to be remembered, 2: Open: ‘If the system is an open system, such as the extraction flash is irregularly distributed’ At this time, it is necessary to start the 2 reorganization process. The magnetic regions with similar logical addresses are moved into the same magnetic region) 'For example: the regions 10 to 19 are the same-region zone 〇, the magnetic region 4 is the region Zone i, and the magnetic region 3. The region 39 is the same as the region Z. Move the magnetic field with the approximate Λ into the same area, then move the magnetic field and 13 into the area 2 嶋 〇, move the magnetic field ⑽ into the area one 1, and move the magnetic area 30 into the area zonek; This extraction is fast. Page 8 556205 V. Description of the invention (6) =; =; It has been moved to other systems for access. Because of the logic / physical bit == rule, compatibility can be maintained. * The system is closed. The U 夬 flash memory is fixed in the system). At the beginning, the method can be omitted. Then, the system will t; = f its corresponding logical address relationship according to the general address of the system SRAM. -Reduce the logical / real p machine proportionally as shown in the second (b) figure and store this physical / logical address mapping table at static energy = check logical address 10, please refer to the fourth figure Second; After the ^ copies of the A body address address / the U in the physical region of the logical zone 〇 built in the static random access memory, the second body Γ14 of the physical area, search for the physical address of the ζ_ ° address is I until the relative When the logic to be checked writes or updates data in the two flash memories, the storage space is wide, in the same area '· If there is not enough storage in the area to switch to another area, it is necessary to restore all the original data in the area together with the new data to an area to comply with the principle of uniform reading and writing. Example d: the spirit of it After the explanation is complete, the following special-specific examples are familiar with this month? The flash memory search process is implemented and implemented accordingly. Σ > According to the description of this example, sufficient knowledge is obtained. Check the present invention to detect the logical address The flow chart, as shown in the figure, includes the following steps: First, as in step 9 on page 556205 ····· 5χχ », invention description (7) '' 11 — S 1 0 It is shown that when the system is powered on, the physical address of the physical area and its corresponding logical address are mapped to the address list of the first place in the manner described by arrows ^ ^ m ^ ^, T 乂 11. Built:-Logical reduction logic; / in memory. Mapping table, and store it in a random access. When the system is as described in step S12, 2 ^ 3 ^ ^ ^ ^ Do not pass a logical address to be checked to the random storage; after the second, it is stored on the second machine. 'When the memory receives the logical address to be searched in step 4, it immediately obtains it from the real / address mapping table according to the logical address to be searched-to determine whether the logical bit S18 is not compared with the logical bit. Take the physical address of the second and second finals, at this time, the public address of the tank f ', if paid, the entire search has been done ;; Inverse :, P =:', as shown by Bruna Complete step S1 6 until you get ★ Hai Fangba. If the number is found, it will continue to advance. The relative physical position U in the shell body is in the same proportion. The second position is the same as the second position. Logical address, ~: self. body. In addition, because the corpus region of 1 # ± is found first, the processing speed is faster than that in the search of a small selection region. Because A, this hair = shell body = use a small number of ridges to use the concept of the area to remove 4 memory, so as not to add too much space before, so d: conductor disk set (flash memory The processing speed of the present invention also simultaneously: to achieve an effective balance point on the network, so as to improve the performance of the system to access data. Call the point ’to effectively

556205 V. Description of the invention (8) The above-mentioned embodiments are only for explaining the technical ideas and characteristics of the present invention. The purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. The limitation of the patent scope of the present invention, that is, all equal changes or modifications made according to the spirit disclosed by the present invention, should still be covered by the patent scope of the present invention.

556205 Schematic illustrations Schematic descriptions: The first (a) and the first (b) diagrams respectively show the relationship between the physical address and the logical address in the conventional memory and the logical / physical bit created by using the relationship Address mapping table. Figures 2 (a) and 2 (b) are the schematic diagrams of the relationship between the physical area and the logical address in the memory, and the proportional reduction logical / physical address mapping table established by the present invention. The third figure is a schematic diagram of the magnetic zone reorganization procedure in the open system of the present invention. The fourth figure is a schematic diagram of a structure for detecting a logical address according to the present invention. The fifth figure is a flowchart of detecting a logical address according to the present invention.

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Claims (1)

The wine system sends a box of L, M, and the machine access memory system according to the random: sub-fetch memory, which can be obtained:-the relative entity area bit: built with: address ❿ # address mapping table for the entity Each block in the area until the physical address of the relative address is obtained. The detection of the logical address of the flash memory as described in item 1 of the 1'-month patent scope pending investigation. /, Where the random access memory system is static random access memory, the second application of the patent scope of the detection of flash memory logic such as t to write or update data in far flash memory Prayer is limited to the same area. The address is the method of detecting the logical address of the flash memory as described in item 3 of the application. If there is not enough space in the area, all the data in the area and the new data are copied to Within another area. ′, There are 5 • The method for detecting the logical address of the flash memory described in Item 1 of the patent application scope, wherein the area is composed of 2n blocks. 6 • The method for detecting a logical address of a flash memory described in item 5 of the patent application scope, wherein the value of η is at least 6. 7 · Detection of the logical address of flash memory as described in item 1 of the patent application scope 556205 6. The method of applying for a patent, in which the scaled down address mapping table is a logical area address / physical address mapping table. Page 14