TW554512B - Low-voltage triggering pseudo bipolar ESD protection device for positive/negative signal input pads - Google Patents

Abstract

An electrostatic discharge (ESD) protection device for protecting semiconductor devices against high-voltage transients due to electrostatic discharges. It includes: (1) an N-type well formed in a P-type semiconductor layer (or P-substrate); (2) a plurality of first P+ regions formed in the P-type semiconductor layer, wherein each of the first P+ regions is connected to an input pad and is formed inside the N-type well, (3) a plurality of second P+ regions formed in the P-type semiconductor layer, wherein each of the second P+ regions is connected to the ground, at least one of the second P+ regions is outside the N-type well, and at least one of the second P+ regions is either in the N-type well or adjacent to it; and (4) an N+ region formed outside of the N-type well. The plurality of first P+ regions, the plurality of second P+ regions, the N+ region, and the N-type well form a plurality of pnp devices connected in parallel to allow a transient voltage to be discharged from the input pad to ground. The N+ region, the P-substrate, and the N-well form an npn device, which is not directly connected to either the ground or the input pad and which allow the transient voltages to be discharged in a reverse direction.

Description

554512 V. Description of the Invention (i) [Background of the Invention] 1. Technical Field of the Invention The present invention relates to an improved electrostatic discharge (ESD) protection device, which is used to provide protection from electrostatic discharge. Voltage transients. In particular, the present invention relates to an improved electrostatic discharge protection device 'suitable for integrated circuits to protect thin semiconductor devices from damage caused by high-voltage transients caused by electrostatic discharge. The electrostatic discharge protection device of the present invention provides excellent protection. It does not require high voltage triggering, and its unique design prevents it from being easily triggered by non-static discharge noise to activate the latch. Another advantage of the electrostatic discharge protection device of the present invention is that it also provides great flexibility to adjust its base width and optimize its collapse characteristics. 2. Description of related arts When a semiconductor device is in contact with an external static charge source (commonly referred to as an input pad), electrostatic discharge (ESD) often occurs. Semiconductor devices usually have only a small amount of series resistance in series between the input pad and the actual device. When the input pad conducts a large amount of static charge, a small amount of series resistance connected to the semiconductor device will cause a large amount of static charge to flow through the circuit in a very short time, resulting in a very large voltage transient. In recent years, this type of electrostatic discharge has been proven to be a major cause of failure of most semiconductor devices and integrated circuits including semiconductor devices. U.S. Patent No. 4,484,244 discloses an electrostatic discharge protection circuit system that uses one or more silicon controlled rectifiers (SCRs) as an electrostatic discharge compliance structure in integrated circuits. Basically, these devices are bipolar devices

I Page 6 554512 5. Description of the invention (2), each of which contains two silicon controlled rectifiers, one to avoid positive voltage transients and the other to avoid negative voltage transients. Because these devices require many diffusion regions, they are compatible with semiconductor devices formed by using metal-oxide-silicon technology. U.S. Patent No. 5,0 1, 2, 3 1 7 discloses another electrostatic discharge protection device, which includes a PNPN type device disposed between an input pad and a ground terminal. For positive voltage transients, a first P-type region is provided in an N-type well formed in the p-type layer, and a second N-type region is provided as a ground connection. This provides a silicon controlled rectifier that can be turned on by causing the middle PN junction to accumulate and collapse (avalanche), turning the device into a positive feedback mode with a positive voltage transient. For negative voltage transients, a p + -type region is provided in a P-type layer to bypass the PN junction, and an N + -type region is provided in an N-type layer to bypass the other PN junction. This provides a forward-biased diode for negative voltage transients. This positive / negative bipolar ESD protection device has been proven to provide excellent protection, but it is prone to accidental conduction due to non-ESD-related trigger noise such as latch-up. [Overview of the invention] The main purpose of the present invention is to develop an improved electrostatic discharge (ESD) protection device, which is suitable for integrated circuits including semiconductor devices. In detail, the main object of the present invention is to develop an improved electrostatic discharge protection device to protect semiconductor devices from being damaged by high voltage transients. The developed electrostatic discharge protection device of the present invention must have excellent protection in harsh environments and must not require a high trigger voltage. In addition, it must be able to overcome the shortcomings of the conventional art device so that it will not be

Page 7 554512 5. Invention Description (3) Non-ESD noises are accidentally triggered. One of the ^ keys is to plant a plurality of p + -type regions in a connection to the evaluated electric floating well. These p + -type regions are electrical discharge protection: Man = 2 ,: source of electrostatic discharge). -The static electricity of the tree. 2. Set up several p + -type regions connected to the ground, and an N + -type region connected to the ground. The N + type region is shaped outside the well. At least one of the grounded P + -type regions must be in an N-type well; BU ^: N = within the P-type layer). Other p + -type regions can be formed on the N-type

Type A, π and A1 i t are connected to a plurality of P + ⑴ ungrounded u-shaped wells in the input pad well, and (3) N-type grounded wells in the well form a plurality of open-circuited base bipolar = crystals in the well. This low-voltage switching structure is used to turn on the plurality of ^ pnp bipolar structures in a polar-mm-ungrounded ❿-type region to avoid electrostatic discharge protection of the present invention, such as noise, such as non-static discharge, being accidentally triggered. Turns on as a protection switch during an electrical discharge event. This electrically floating N-type well is used to maintain the cut-off state. It is not recognized that the main opening is positive or negative. "Enter wishes in normal operation

^ T, =: Revealing an improved electrostatic discharge protection including the following main components: (1) an N-type well formed in a P-type semiconductor layer; (2) an N-type well formed in the P-type semiconductor layer Each of the -p + type regions in the plural is connected to the-input pad and its page 8 554512 V. Description of the invention (4) and formed in the N-type well; ⑴: formed in the P-type semiconductor Multiple within layers

Each of the second and second p + -type regions is connected to the ground and at least one of the second and second P + -type regions goes to the lecturer to identify λτ and the first person is formed outside the N-type well · Yueyue (4) A ... type area formed outside the N-type well;, and (5) wherein the plurality of first p + type regions, domains, and -type areas are in the N-type well: What is the number?

Set to allow a transient voltage to discharge from the input pad to ground. ρ ρ As mentioned above, the y pseudo-type ceramic bipolar structures in the electrostatic discharge protection device of the present invention allow the electrostatic discharge ^ for ancient restoration: it can be triggered without being affected by non-static discharge noise. Electric shock [detailed description of preferred embodiments] The present invention discloses an improved electrostatic discharge (ESD) protection device, which is suitable for integrated circuits including semiconductor devices to protect the device from high voltages caused by electrostatic discharge. Damaged by transients. The electrostatic protection device of the present invention has excellent protection in harsh environments and does not require a high trigger voltage without being triggered carefully by noises such as latches and other non-static discharges.

^ Figure 1 is a schematic view showing a cross-sectional view of a conventional electrostatic discharge protection device f. A P-type semiconductor substrate n is provided with a low doping degree. An N-type well 12 is defined in the p-type semiconductor substrate 11 by a diffusion process to provide a low-doped N-type semiconductor region. Accordingly, a first PN junction is formed. A first p + type region 13 is diffused into the N page 9 554512

Well 12 ° The PN junction between the first zone 13 and the N-well 12 provides one or one PN junction.咼 -doped! The first type region 14 is defined as KN, inside the well 12, and is connected to an N-well resistance (not shown in the figure), = is connected to an input pad 15. The —N + -type region 14 is connected to the input 15 to provide a resistive connection between the input pad 5 and the n-type well 2 to allow a reverse conduction state in the first PN junction. FIG. 1 also depicts a highly doped second N + type region 16, which is provided in the p-type substrate 11 but outside the N-type well 12. The second N + type region 16 and? The joint between the base plates 11 provides a third joint. A highly doped second-type region 17 is provided inside the p-type substrate but outside the N-type well 12 to provide a p + -type low-resistance region. The second p + -type region 17 is connected to a pedestal resistor formed by a p-type substrate 11. Both the second N + -type region 16 and the second p + domain 17 are connected to VSS or ground. In operation, a positive voltage transient causes an electrical °° current to flow through the first P + -type region 13 so that the N-type well 12 and? The first PN junction between the type substrates 丨 丨 accumulated and collapsed. This current then flows from the p-type substrate u through the third M junction to the N: -type region 16, # to the ground. During the reverse transient, current flows from the second P + -type region 7 to the p-type substrate. In this mode, the current flows from the p-type substrate n through the second interface to the N-type well 12 and through the first N + -type region 14 to the input 塾 15. The electrostatic discharge protection device of US Patent No. 5,012,317 is a silicon controlled rectifier with a PNPN structure. It provides excellent protection and can be triggered at lower voltages than previous devices. However, its disadvantage is that it is easy to be accidentally touched by non-static discharge noise such as interlocking.

Page 10 554512

The electrostatic discharge protection dream disclosed in the present invention # ni9 ^ 17 ^ ^ ^ Electric 1 shows that there are many patentees similar to Yuan :: 5’012’317. However, there is still one, the electrostatic discharge companion of the present invention has a UN ^ ^ ^ ^ n ^ The protection device includes several first P + -type regions in the M well connected to the input pad, and one of the ungrounded n + And a plurality of grounded second P + -type regions $. k-Pi W r · u. ^ In addition, a plurality of grounded No. 5 nights are located in or adjacent to the N-type well. Because of the two't: the electrostatic discharge protection device includes a plurality of pnp devices connected in parallel, which are connected to an npn device. In summary, the present invention discloses an improved electrostatic discharge protection device, which includes the following main components: (1) an electrically floating N-type well formed in a P-type semiconductor layer; (2) ) A plurality of first p + -type regions formed in the P-type semiconductor layer, wherein each of the first P + -type regions is connected to an input pad and is formed in the N-type well; (3) formed in A plurality of second p + -type regions in the P-type semiconductor layer, wherein each of the first P + -type regions is connected to the ground, and at least one of the second p + -type regions is formed in the N-type well Outside, and at least one of the second P + type regions is formed in or adjacent to the N type well; and (4) an N + type region is formed outside the N type well; (5) where the floating The pnp device in the N-type well is used as a trigger element for electrostatic discharge, and the main electrostatic discharge is formed from the first P + -type region, the plurality of second p + -type regions, the N + -type region, and the n-type well.

554512

The electrical protection element to allow a transient voltage to be discharged from the input pad to the present invention will be explained by referring to the following note, the description of the following examples is explained by referring to the following description, and not based on this example It is explained in more detail. It is necessary to include the drawings of the preferred embodiment of the present invention and the patent application scope of the appendix as a limitation of the present invention. Example 1 FIG. 2 is a schematic diagram showing a cross-sectional view of an improved electrostatic discharge protection device according to one of the preferred embodiments of the present invention; and FIG. 3 is a corresponding electrostatic discharge protection device shown in FIG. 2 Circuit diagram. In a first preferred embodiment of the present invention, an electrostatic discharge protection device similar to U.S. Patent No. 5'012,317 includes a low-doped p-type semiconductor substrate 11. An N-type well 12 is defined in the p-type semiconductor substrate 11 by a diffusion process to provide a low-doped N-type semiconductor region. However, unlike U.S. Patent No. 5,012,317, which includes a P + type region in an N type well, the electrostatic discharge protection device of the present invention includes a plurality of first p + type regions 23 to n connected to the input pad 15. Inside the well 12. In addition, in this embodiment, there is no N + region in the N-type well 12. Another difference is that the electrostatic discharge protection device of the present invention also includes a plurality of grounded second P + -type regions 24 in the N-type well 12. FIG. 2 also shows that a highly doped second N + type region 26 and a highly doped second P + type region 27 are provided inside the p-type substrate n but outside the N-type well 12. However, it is different from the + type zone of U.S. Patent No. 5, 0, 2, 3, and 7.

554512 V. Description of the invention (8) Domain 16 The second N + type region 26 of the present invention is not grounded. In the present invention, only the second P + type region 27 is grounded. As shown in FIG. 3, the result of this structure is an electrostatic discharge protection device including a plurality of pnp devices (only two pnp devices are schematically shown in FIG. 3) connected to one ηρη device. Ground. The plurality of grounded second p + -type regions and the first p + -type region connected to the input pad (anode) form an open-circuit base / N-type pnp bipolar transistor in the N-well. These areas act as snap-back triggers for the entire pseudo-bipolar structure. Similar to those disclosed in U.S. Patent No. 5,0 1, 2, 3 1 7, the electrostatic discharge protection device of the present invention also provides excellent protection and does not require very high voltage to trigger its protective action. However, the improvement provided by the present invention includes a plurality of pnp devices and an ηρη device that is not directly grounded, allowing the present invention ^ The electrostatic discharge protection device is less likely to be triggered by trigger noise related to non-static discharge f such as a latch Accidentally turned on. Further, in the present invention, the interval (that is, the base width) between the type region 23 and the P + type region 24 is adjusted to optimize the breakdown characteristics. The second example is a schematic diagram of a horse, which is a cross-sectional view of an improved electrostatic discharge protection device according to one of the second preferred embodiments of the present invention. In this second preferred embodiment, similar to the electrical protection device in the first preferred embodiment, it includes a low-doped p-type semiconductor US board 1 1 = floating ⑴atlng) N-type well. 12 by-channel diffusion; process is; = the P-type semiconductor substrate u to provide-low doped _ semiconductor

554512 V. Description of the invention (9) The first ^^ ^ is an embodiment of a plurality of grounded ^ -type areas in a W-shaped well of two packs. The second preferred embodiment of the present invention is a static discharge discharge device. It does not include the grounded p + type region in the N-type well 12. Specifically, the grounded P + area is provided outside the Y-well, and at least one of the grounded P + areas is adjacent to the Y-well. Similar to the first preferred embodiment, there is no N + type region in the electrically floating N-type well. The eighth member is similar to the first preferred embodiment, and FIG. 4 also shows that a highly doped second 1U-type region 26 and a highly doped second ρ it two-conductor substrate 11 are in the N-type. Well 12 outside. Also similar to the conventional embodiment, the second N + type region 26 is not grounded. In the region of the present invention, a second second p + -type region 27 is grounded. This configuration allows the basis and width of the ρηρ transistor formed by the -ρ + -type 2 ^ -type well 12 and the ρ + -type region 34 to be further adjusted to optimize the collapse characteristics. Example 3 FIG. 5 is a schematic view showing a cross-sectional view of the third preferred embodiment of the flute f ▲ improved electrostatic discharge protection device of the present invention. The electrostatic discharge protection device in the preferred embodiment of the present invention is similar to that in the first specific embodiment, and includes a low-doped P-type semiconductor substrate and a floating N-type. The well 12 uses a diffusion process in the second half of the second p-type semiconductor substrate 11 to provide a low-doped n-type region. However, unlike the multiple grounded P + devices including N-type wells in the N-type well, the first preferred embodiment, the third preferred embodiment of the present invention includes only the electrostatic discharge protection device in the N-type well 12 Grounded p +

554512 Five, invention description (ίο) type area. Similar to the first preferred embodiment, there is no N + type region in the electrically floating N-type well. Similar to the first preferred embodiment, FIG. 5 also shows that a highly doped second N + type region 26 and a highly doped second p + split region 27 are provided in the P-type semiconductor substrate 11, Outside the N-well 12. Also similar to the first preferred embodiment, the second N + type region 26 is not grounded. In the present invention ', only the first P + type region 27 is grounded. The drawings and description of the present invention are described above in the preferred embodiments, and are only used to help understand the implementation of the present invention. They are not intended to limit the spirit of the present invention. Those skilled in the art will appreciate the spirit of the present invention after Without departing from the spirit of the present invention, when some modifications and equivalent changes can be made, the scope of patent protection depends on the scope of the patent application attached. Prisoner

Page 15 554512 Schematic Simple Outline " [Brief Description of Schematic Drawings] The drawings used to form this description depict specific embodiments of the present invention, and combine the following general description with the following preferred specific embodiments The detailed description is used to explain the principle of the present invention. Among them: FIG. 1 is a schematic diagram illustrating a cross-sectional view of a conventional electrostatic discharge protection device; FIG. 2 is a schematic diagram illustrating an improved electrostatic discharge according to a preferred embodiment of the present invention. Cross-sectional view of the protective device; Figure 3 is a diagram corresponding to the electrostatic discharge protection shown in Figure 2; Figure 1 is an equivalent circuit of the edge device. Figure 4 is a schematic diagram showing the 箆 _ of the present invention. -The horizontal structure of the improved electrostatic discharge protection device = Example FIG. 5 is a schematic diagram showing the horizontal wearing of the first and the improved electrostatic discharge protection device of the present invention ^ ^ Specific embodiments [Figure number is simple Description] 11 P-type semiconductor substrate 1 2N-type well 13 First p + -type region 1 4 First N + -type region 1 5 Input 塾 16 Second N + -type region 17 Second p + -type region 23 First p + -type region 24 Second ρ + Type area

554512 Brief description of the diagram 26 Second N + type region 27 Second P + type region 34P + type region ΙΙΙΗΙΙ page 17

Claims (1)

554512 6. Applying for a patent 'I-L Electrostatic discharge (ESD) protection device is used to protect semiconductor devices 半导体 from high voltage transient caused by electrostatic discharge, which includes: (a) — Electrically floating N-type wells formed in a p-type substrate; (b) a plurality of first type regions formed in the p-type substrate, wherein each of the first P + type regions is Connected to an input pad / and all the plurality of first P + -type regions are formed in the N-type well; (C) a plurality of second P + -type regions formed in the P-type substrate, wherein the second P + -type region Each of them is connected to the ground, at least one of the + -type regions is formed outside the N-type well, and at least one of the first P + -type regions is disposed in or adjacent to the N-type well. Outside of the well; and (0-formed area outside the N-type well, where the fine area is not grounded; (e) where the plurality of first p + -type areas, the plurality of second p-type areas, the N + -type area, forming a plurality of pnp devices with the N-type well to allow a transient voltage from the transmission The pad is discharged to the ground. 2 · If the electrostatic discharge (ESD) protection device of item 1 of the patent application scope, wherein each of the second p + type regions formed outside the N-type well is highly doped. An electrostatic discharge (ESD) protection device according to item 1, which includes a plurality of the second p + -type regions in the N-type well. 554512 VI. Application for patent scope 4 · Please apply for electrostatic discharge (Es 5.) in the N-type well (the 5.th type: p +. Please refer to the electrostatic discharge (USD) for the first range of patent scope), The N-type well does not contain any of the second p + -type region, but includes up to 6 > a P + -type region adjacent to the N-type well. An integrated circuit, which includes a Xiao / Ba Dak 3 electrostatic discharge (ESD) protection device, which protects a semiconductor device from high voltage transients caused by electrostatic discharge. The electrostatic discharge protection device includes:, a) -Electrical floating (fi0ati-type wells) formed in a P-type substrate; (b) a plurality of first p + -type regions formed in the P-type substrate, wherein each of the first P + -type regions Or is connected to an input pad, and all the plurality of first P + -type regions are formed in the N-type well; (c) a plurality of second? +-Type regions formed in the p-type substrate, wherein the second Each of the P + -type regions is connected to the ground, at least one of the second p-type regions is formed outside the N-type well, and at least one of the first P + -type regions is disposed in the N-type well or Adjacent to the outside of the N-type well; and U)-a material-type region formed outside the N-type well, wherein the ...- type region is not grounded; (G) where a is a plurality of first P + -type regions, the plurality of A second P + -type region, the N + -type region, and a plurality of pnp devices with the N-type well, Allows a transient voltage is discharged from the input pad to ground. Page 19 554512 6. Scope of patent application 7. For the integrated circuit of item 6 of the patent application scope, each of the second P + type regions formed outside the N-type well is highly doped. 8. The integrated circuit of item 6 of the patent application scope, wherein the electrostatic discharge protection device includes a plurality of the second P + type regions in the N-type well. 9. If the integrated circuit of item 6 of the patent application scope, wherein the electrostatic discharge protection device includes only one second P + type region in the N-type well. 10. If the integrated circuit of item 6 of the patent application scope, wherein the electrostatic discharge protection device does not include any of the second P + type region in the N-type well, but includes at least one P + type region adjacent to the N-type well . Page 20