TW550910B - Event detection with a digital processor - Google Patents

Event detection with a digital processor Download PDF

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Publication number
TW550910B
TW550910B TW091106842A TW91106842A TW550910B TW 550910 B TW550910 B TW 550910B TW 091106842 A TW091106842 A TW 091106842A TW 91106842 A TW91106842 A TW 91106842A TW 550910 B TW550910 B TW 550910B
Authority
TW
Taiwan
Prior art keywords
read
memory device
logic
logic state
bistable memory
Prior art date
Application number
TW091106842A
Other languages
English (en)
Inventor
Steven Eric Schlanger
Randy L Yach
Original Assignee
Microchip Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Tech Inc filed Critical Microchip Tech Inc
Application granted granted Critical
Publication of TW550910B publication Critical patent/TW550910B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Debugging And Monitoring (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)

Description

550910
og 88 8 ABCD 六
'經濟部智慧財-J.局員工消費合作杜印製 I;·:, 申請專利範圍 輸入用則貞測-事件·的發生，友-代表該雙穩態記憶體 裝置的一邏輯狀態之輸出，其中該邏輯狀態係為一第— 或一.第二邏輯位準，使得該邏輯狀態的該邏辑位準在每 --次偵測到該事件時即改變；及 .一數位處理器，該數位處理器具有一輸入耦合到該第— 雙穩態記憶體裝皇的該輸出，及另一個輸入轉合到該第 二雙穩態記憶體袭置的該輸出，藉此該數位處理器..定期 地讀取該邏輯狀態’並儲存其邏輯位準，其中該數位處 理器比較一後續讀取邏輯狀態的該邏輯位準與該存.. •邏輯位準，藉以決定該儲存的邏輯位準是否相同或不同. 於該後續讀取的邏輯狀態之邏輯位準，如果不同的話即 已發车.一事件，而如果相同的話，則沒有事件發生； 其中該事件_||仙合㈣傳送器.與該電腦及該接 收器與該電腦之間，使得該第—雙穩態記憶體裝置係耗 合於該接收器，而該第二雙穩態記德體裝置係、輕合於該 電腦的一序列輸出。 4. 如申請專利範圍第3項之數位系統，其中該傳送器的該 傳輸係自外狳、妙从始 .. 卜踝紫外線、射頻、微波及超音波所組成 的群組中選出。 5. 如申請專利._第3項之數位系統，其中該接收器的該 .接收係自k外線、紫外線、射頻、微波及超音波所組成. 的群組中選出。 如申明士利範圍第3項之數位系統，其中該電腦傳自一 扩控制·™微處理器、數位信號處理器、精簡指令集電 ^ 1 1^ ^3*裝-----------訂---^---------"^3------ (tf^閱讀背面之注意事说再填寫本-.丫 19 550910 ·>
8 888 ABCD 六、申請專利範圍 -R-0 w ο 腦出
C S 腦 電 集令 指雜複.
群 的.成組 所 \—/ C S 選 中 (請知閱讀背面之注意事項再填寫本ν.·Λ..). -T · -------- I 1 II . 11 )OJ II --- L- - - — - '經濟部智慧財^局員工消費合作社印製 .3 .準 標 家 國 ....'1:1»0 張Μ 20 I ¥ I.·'·、-'1 I.·-迅 .(2一一 Α4
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TW091106842A 2001-04-05 2002-04-04 Event detection with a digital processor TW550910B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/827,273 US6931075B2 (en) 2001-04-05 2001-04-05 Event detection with a digital processor

Publications (1)

Publication Number Publication Date
TW550910B true TW550910B (en) 2003-09-01

Family

ID=25248774

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091106842A TW550910B (en) 2001-04-05 2002-04-04 Event detection with a digital processor

Country Status (4)

Country Link
US (1) US6931075B2 (zh)
AU (1) AU2002307044A1 (zh)
TW (1) TW550910B (zh)
WO (1) WO2002082648A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI417745B (zh) * 2008-04-23 2013-12-01 Intel Corp 檢測處理器資源的架構弱點的方法與設備及使用該方法之計算系統

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7026842B1 (en) * 2004-10-13 2006-04-11 Broadcom Corporation Method and apparatus for reliable pulse event detection
US8239881B2 (en) * 2009-02-11 2012-08-07 Honeywell International Inc. Zero-power event detector
FR2967522B1 (fr) * 2010-11-12 2012-12-21 St Microelectronics Sa Memoire non-volatile securisee

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US3898689A (en) * 1974-08-02 1975-08-05 Bell Telephone Labor Inc Code converter
US4740890A (en) * 1983-12-22 1988-04-26 Software Concepts, Inc. Software protection system with trial period usage code and unlimited use unlocking code both recorded on program storage media
US4692635A (en) * 1986-06-26 1987-09-08 National Semiconductor Corp. Self-timed logic level transition detector
US4940904A (en) * 1988-05-23 1990-07-10 Industrial Technology Research Institute Output circuit for producing positive and negative pulses at a single output terminal
US4972161A (en) 1989-06-28 1990-11-20 Digital Equipment Corporation Clock recovery for serial data communications system
JP2787725B2 (ja) 1990-02-14 1998-08-20 第一電子工業株式会社 データ・クロックのタイミング合わせ回路
KR950007267B1 (ko) * 1990-10-16 1995-07-07 삼성전자주식회사 리모콘신호의 펄스폭 측정회로
US5463655A (en) * 1993-02-17 1995-10-31 National Semiconductor Corporation Single-ended pulse gating circuit
US5457719A (en) 1993-08-11 1995-10-10 Advanced Micro Devices Inc. All digital on-the-fly time delay calibrator
IT1272078B (it) 1993-12-16 1997-06-11 Cselt Centro Studi Lab Telecom Ricetrasmettitore per segnali numerici ad alta velocita' in tecnologiacmos
EP0773627A1 (en) * 1995-11-07 1997-05-14 STMicroelectronics S.r.l. Flip-flop circuit
US5822386A (en) 1995-11-29 1998-10-13 Lucent Technologies Inc. Phase recovery circuit for high speed and high density applications
US5770846A (en) * 1996-02-15 1998-06-23 Mos; Robert Method and apparatus for securing and authenticating encoded data and documents containing such data
US5982837A (en) * 1997-06-16 1999-11-09 Lsi Logic Corporation Automatic baud rate detector
US6075385A (en) * 1998-10-06 2000-06-13 Hewlett-Packard Company Intelligent precharger for a dynamic bus
WO2003015276A2 (en) * 2001-08-10 2003-02-20 Shakti Systems, Inc. Logic state transition sensor circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI417745B (zh) * 2008-04-23 2013-12-01 Intel Corp 檢測處理器資源的架構弱點的方法與設備及使用該方法之計算系統

Also Published As

Publication number Publication date
WO2002082648A3 (en) 2003-12-18
US6931075B2 (en) 2005-08-16
AU2002307044A1 (en) 2002-10-21
US20020150178A1 (en) 2002-10-17
WO2002082648A2 (en) 2002-10-17

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