TW550866B - Self-aligned process method of ridge shape waveguide semiconductor laser - Google Patents

Abstract

A kind of self-aligned process method of ridge shape waveguide semiconductor laser is disclosed, which uses dielectric planarization to achieve the purpose of self-aligned process. A dielectric layer with sufficient thickness is deposited onto the semiconductor wafer surface with ridge shape waveguide structure formed thereon, in which the derived ridge shape dielectric layer surface forms a flat surface after a self-stopped dielectric polishing. The top portion of the semiconductor ridge structure is then exposed by using global etch-back process to etch the dielectric flat surface.

Description

550866

[Technical Field] The present invention relates to a self-guided waveguide semiconductor laser of a kind of ridge waveguide semiconductor laser. [Prior art] Please refer to FIGS. -A and -b, which are two conventional ridge waveguide semiconductor lasers. Shot structure. The worm crystal structure of both includes a semiconductor substrate (semi-type semiconductor substrate), a first semiconductor waveguide layer 101, a first semiconductor confinement layer 102, and a semiconductor active layer region. 103, the second semi-conductor confinement layer 104, the second semiconductor waveguide layer 105, and a semiconductor ohmic contact layer 106; and the element structure of both includes a dielectric purification layer 107a (passivation) or 107b, the P-type metal electrode is eliminated, and an N-type metal electrode 109. Both types of element structures begin with the use of standard exposure development (phot〇1 ithography) 15 processes to define photoresist patterns on wafers, and through etching processes such as reactive ion etching (RIE) to form Doubletrench structure 110 as shown in the figure. A dielectric layer i07a or i07b is then deposited on the entire wafer surface and printed by the Consumer Affairs Agency of the Intellectual Property Office of the Ministry of Economic Affairs for passivation of semiconductor surfaces. A contact window is opened at the ridge top, and after the ohmic contact layer is exposed, a p-type metal electrode 20 108a or 108b is plated to contact the ohmic contact layer 106. Finally, the back surface of the wafer after lapping and polishing is plated with an N-type metal electrode 109. In order to reduce the threshold current (thresho 1 d current) of laser operation and to maintain the laser output in a single transverse mode, the ridge width W is generally selected to be about 2 microns. To open a contact window on the top of such a narrow ridge exposes Europe

550866 A7

550866 A7 B7 Printed by the Consumer Affairs Agency, Intellectual Property Office of the Ministry of Economic Affairs Remove this photoresist mask to expose the ohmic contact layer at the top of the ridge. At this time, other surfaces on the wafer are still covered by the dielectric layer. Since the exposure of the ohmic contact layer does not require mask alignment and exposure development processes, this method is referred to as "self-alignment". Although this type of method can achieve the purpose of simplifying the manufacturing process and maximizing the use of the ohmic contact layer, the retention of the photoresist mask makes the deposition of the dielectric 5 must be performed at a lower temperature (~ 100.00, the quality of the dielectric layer). Therefore, in order to make the photoresist mask easy to remove after the dielectric layer is deposited, the semiconductor ridge must have a proper TK (undemjt) cross-sectional shape, which deepens the complexity of the process. Second, Such as Us Pat No 5,208,183, US Pat No 10 5,474,954, US Pat. Να 5,658,823, and US Pat No. 6,171,876, which utilize the flattening ability of photoresist or polyimide. When the photoresist or When polyimide is spin-coated on the surface of a wafer with a ridge structure, its fluid properties make it known that the thickness of the photoresist or poliimide on the top of the ridge is much thinner than the thickness on other planes. Through a full etch-back process, such as RIE, the ridge top can be exposed first, while other surfaces are still covered by photoresist or polyimide, so the entire ridge top can be contacted with metal electrodes. The difference between using photoresist and Polyimide is that polyimide is exposed after the ridge top is exposed. Association On the wafer surface, the p-type metal and its binding pad are directly formed thereon as a planarized insulating dielectric layer. Therefore, it is more straightforward to make fine lyimide. In addition, by using polimide The planarization of the ridge waveguide semiconductor laser can also adopt a single-ridge structure, so as to avoid the metal coating problems encountered by dual-cavity structures. However, even if it has been overheat-hardened, p〇 The lyimide film still has some characteristics that allow for stretching. When the laser mirror is split, the polyimide film stretched at the edges may cause interference with the laser output surface, affecting the characteristics and uniformity of the device.

Lu Ding 15 20 scales are applicable to X 297 mm. Line A7 550866 5. Description of the invention (It can be seen that there are still many shortcomings in the above-mentioned conventional articles, which are not a good designer, and need to be improved. In view of the above Various shortcomings derived from the self-aligned manufacturing method of the ridge waveguide semiconductor laser are eager to improve and innovate. After years of painstaking and meticulous research, finally successfully developed the self-alignment of this ridge waveguide semiconductor laser. [Objective of the invention] The purpose of the present invention is to provide a self-aligned manufacturing method of a ridge waveguide semiconductor laser, which uses a self-terminated oxide polish, and thereafter For short (ST0P) technology, before implementing this stop technology, a thick oxide layer is deposited. Taking Si0x as an example, the thickness of the entire wafer surface with a ridge-like structure is greater than the height of the semiconductor ridge. The stop technology was used to polish the SiOx surface formed into a ridged landform to a flat surface. This polishing process quickly removed the poles at the beginning. (For example, narrower than 10 microns) Ridge 15 Printed by the Consumer Intellectual Property Association of the Intellectual Property Bureau of the Ministry of Economic Affairs to print 20 degrees. However, when the polished surface reaches the Si0x plane, the rate of its removal & thickness is greatly reduced. It is almost stagnant, so that the XQ surface of the entire ore can reach a fairly flat surface. By selecting the appropriate polishing conditions, the flatness can be determined by the mechanism of SiOx deposition rather than the polishing process. 疋[Technical content] The self-aligned process method of the ridge waveguide semiconductor laser that can achieve the above-mentioned object of the invention is to use dielectric planarization to achieve a self-aligned process. The thickness of the dielectric negative layer covers the surface of the semiconductor wafer on which the ridge-shaped waveguide structure has been formed. The dielectric surface with the ridge landform derived from the self-terminating dielectric is polished into a paper with a standard applicable to Chinese national standards ( CNSM4 regulations (21〇x 297 issued) 550866 Λ7

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (&f; flat surface); this is etched by a full etch-back process-the dielectric flat surface can make the top of the semiconductor ridge structure uniform. Exposed. [Brief description of the drawings] Please refer to the following detailed description of a preferred embodiment of the present invention and its 5 drawings, which will further understand the technical content of the present invention and its purpose / effects. The drawings related to this embodiment are: : Figure 1A is a cross-sectional view of a conventional double-slot structure ridge waveguide semiconductor laser; Figure-B is a cross-sectional view of a double-slot structure cargo conductor laser manufactured using a conventional self-alignment technique; 10 Figures 2A ~ N are A cross-sectional view of a first embodiment of the self-alignment process method using the ridge waveguide semiconductor laser; > / Fig. 3 A to P are the second implementation of the self-alignment process method using the ridge waveguide semiconductor laser Example component cross-section; Figure 4 is a schematic diagram of the change in the topography of surface 15 during the process of self-stopping oxide layer polishing. [Representative symbols of main parts] 100 semiconductor substrate 101 first semiconductor waveguide layer 102 first semiconductor confinement layer 103 semiconductor active layer region 104 second semiconductor confinement layer 105 second semiconductor waveguide layer 106 semiconductor ohmic contact layer 107a dielectric passivation layer 297 Mm) Please read the notes before filling in

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 550866 A7 B7 PAU1U4JU.UUU-0 / ^ 1 V. Description of the invention (j ^ 7) 107b Dielectric passivation layer 108a P-type metal electrode 108b P-type metal electrode 109 N Type metal electrode 110 double slot structure 200 filled with indium substrate 201 N-type InP waveguide layer 202 N-type aluminum indium arsenide confinement layer 203 active region containing multiple quantum wells 204 indium arsenide indium confinement layer 205 P-type InP waveguide layer 206 high Doped P-type indium gallium arsenide contact layer 206a Highly doped P-type InO.53GaO.47As contact layer top 207 SiNx layer 207a SiNx layer 208 photoresist mask 209 SiOx passivation layer 210 SiOx layer 210b SiOx 210a SiOx plane 210b SiOx 211 Photoresist 212a metal 212b metal This paper scale is applicable to Chinese National Standard (CNS) A4 specifications (210 x 297 public love) 14 1— J— IIJIIII — — — — — — — 11111111 I I (Please read the precautions on the back first (Fill in this page again) 550866 Λ7 B7

kauiu4 ^ u.uuo-y / ^ I V. Description of the invention (1) 213 metal electrode 300 substrate 301 N-type InP waveguide layer 302 N-type In0.52A10.48As confined layer 303 active region with multiple quantum wells 304 In0.52A10 .48As confinement layer 305 P-type InP waveguide layer 305a InP layer 306 Highly doped P-type InO.53GaO.47As contact layer 306a I nO.53GaO.47As layer 307 SiNx layer 307a SiNx layer 308 Photoresistor 309 SiOx passivation layer 310 SiOx layer 310a SiOx plane 310b SiOx Printed by the Consumer Cooperative of the Ministry of Economic Affairs Intellectual Property Bureau 311 Photoresist 312a Metal 312b Metal 313 Metal electrode 400 Wafer 401 Area 402 Si Ox plane -9- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 meals) 550866 A7 V. Description of the invention (<;-1U / ^ 1 403 ridges 403a Si Οχ spine column [Preferred embodiment] Self-alignment of the ridge waveguide semiconductor laser provided by the present invention Method, which can be used to make ridge waveguide semiconductor lasers. More specifically, this self-aligning process technology uses a so-called self-terminating oxide layer polishing technology (STOP). Planar surface oxide surface flattened The following description takes SiOx deposited by plasma-enhanced chemicai vapor deposition (PECVD) as an example. In this process, a sufficient thickness of SiOx layer is firstly deposited by PECVD on the etched out The surface of the wafer with a semiconductor ridge structure. In order to obtain a flat and completely SiOx layer surface after polishing, the thickness of the deposited SiOx layer must be greater than the height of the semiconductor ridge. Due to conformai deposition such as PECVD ), The original semiconductor surface with ridge landforms extends upwards to form a Si0x surface with ridge landforms. By polishing, the Si0x surface with ridged landforms can eventually become a flat surface. To avoid Causes uneven SiOx surfaces (such as inclined surfaces) or excessive polishing. The key to applying general polishing equipment here is to adjust the appropriate pressure to the polishing surface, so that the Si in the polishing is too narrow. 〇x, (for example, narrower than 10 microns), its height decreases rapidly; however, when the polishing touches a larger and flat SiOx surface (for example, wider than 300 microns), the behavior of removing the thickness of Si0x by polishing is almost Stagnation. In this way, the very different polishing behavior caused by the area difference can form a fairly flat Si0x surface. At the same time when the flat surface is formed, the polishing behavior of Si0x thickness has almost stagnated, as it is self-termination. The technology is named for the reason for self-terminating oxide layer polishing. The subsequent full etch-back Si0x process can uniformly expose the semiconductor ridges. This Si0x full cashback process is available. The paper size is applicable to the Chinese national standard 10

550866 V. Description of the Invention (Paid by RIE-a fairly flat wafer surface, the same level of green layer surrounds the exposed semiconductor _ all around. Really detailed description of the use of this self-aligned process Fabrication of a ridge waveguide semiconductor laser. Figures -A to II_ show the cross-sectional schematic diagrams of the semi-conductor laser element in each process step in the first preferred embodiment. Figure II shows the growth of the N-type The element stupid structure of the dished steel (InP) substrate 200 includes (from bottom to top): a frequency secret waveguide layer 201, a -N-type Shishenhua fine (In〇52A1048As) confinement layer 202, Contains multiple quantum wells (MQWs) active region 203, an indium aluminum arsenide (In.52Al.48AS) confinement layer 204, a 1.5-micron thick P-type InP waveguide 10 layer 205, and -0.2 micron thick doped P-type indium gallium (In〇53Ga〇.47As) contact layer 206. The device process begins by depositing a 2000-SiNx layer 207 on the crystal using PECVDK2500t A round surface, as shown in the figure. A 2 micron wide photoresist mask is defined on the 3 ^ layer by mask alignment and exposure development. The mask 208 pattern, as shown in Figure 2c, is used as a mask for the next side process. The CFN gas is used by RIE to etch the SiNx layer protected by the uncrossed photoresist, as shown in Figure 2D. After the photoresist mask 208, the π structure is shown in Figure 2E, and the original 2-micron-wide photoresist pattern has been transferred to the Si% layer 207a. After the wafer is cleaned and deoxidized, it is placed in the RiE process. Process chamber, using the defined SiN} ^ as an etching mask, and using a gas composition of 1 CH4: 5 H2, the semiconductor layer not protected by SiNx is etched to a depth of about 1.6 to 1.7 microns to form A semiconductor ridge structure, as shown in Figure 2 ?. The removed semiconductor layer includes the entire thickness of In53.GaAs 47As ohmic contact layer 206 and a portion of the thickness of the P-type InP waveguide layer 205. In order to obtain a suitable etching topography (That is, nearly vertical semiconductor ridges and mirror-like wafer surfaces), in the process of engraving semiconductor ridges, it must be interspersed with a gas mixture of 0 2 and Ar to remove the polymer generated during the etching process.

Order 15 20 This paper size_ (CNS) A4 secret line 11-ίο 15 550866 V. Description of the invention Compounds or carbon-containing products. After the semiconductor ridge structure is etched, after the wafer surface cleaning and deoxidation steps, a 3000-A SiOX purification layer 209 is fully deposited on the wafer surface at 250 ° C using PECVD, as shown in Figure 2g. Show. At this stage, the device manufacturing process has all gone through the conventional semiconductor process steps. The self-aligned process using STOP technology described in the following 5 is the essence of this invention. After the surface-growth SiOx passivation treatment, the wafer is placed in another PECVD process chamber, and a 3 micron-thick SiOx layer 210 is quickly deposited at 35 ° C at 2750 per minute, as shown in Figure 2 (b). This thick SiOx layer is comprehensive Covering the wafer surface, the semiconductor ridges underneath cause the SiOx surface to also form a ridge landform. With a general polishing equipment with a load adjustment (such as 0 to 1.5 kg), adjust the appropriate load to the polishing surface (apply the The load is related to the polishing area. The pressure applied in this embodiment is about 0.1 kg per square centimeter.) The original Si0x surface with ridged landforms can be polished to "(^ Plane 210a) The current planarization process in very large scale integrated circuit (VLSI) processes requires quite accurate polishing equipment, such as chemical mechanical polishing (CMP) equipment, but the equipment required in the application of this invention can be Generally used for polishing and polishing the back of wafers. By applying moderate pressure to the polishing surface, the extremely narrow SiOx ridges can be quickly polished and removed, but the larger & 〇χ plane is almost unaffected. Polishing effect. On all SiOx ridges After being flattened in time or sequentially, the broad SiOx plane makes the action of polishing the thickness of SiOx almost stagnant, as if self-terminating 20 '. Therefore, the SiOx plane shown in Figure 2 can be obtained. The SiOx plane up to the semiconductor ridge top of the In0.53Ga〇47As ohmic contact layer is uniformly exposed. Because the etching conditions of this embodiment, the rate of etching SiOx (about 300 again per minute) is higher than that of SiNx (about every minute). 〇〇〇〇) Slow, the exposure of the highly doped P-type In〇. 53Ga〇 47As contact layer top 206a will be about ______- 12- paper size _; _ fresh (CNS) A4 secret G χ 观 公 爱 「. i ~ ----------------- ^ I _ (Please read the notes on the back before filling this page) A7 550866 V. Description of the invention (, \ ) Huaiyi's low 1000, as shown in Figure II J. Such a structure allows the ridge top to be fully used for ohmic contact with metal electrodes, while providing greater tolerance for excessive etching. The next process is also known The semiconductor process is not directly related to the present invention. However, the use of the described stop polishing technology and the full cash back process The planar 5 structure formed is helpful for the following processes and can improve the process yield. After the 1n0.53Ga.47As ohmic contact layer of the semiconductor ridge top is uniformly exposed, the mask alignment and exposure development are used. The process defines a p-type metal region, as shown in Figure 2K. It must be noted that in order to facilitate the lift-off process of the metal (lift-〇ff pr〇cess), the photoresist 211 must have an approximately inverse-ladder shape (inverse- tapered) section. Then 1500a of titanium (Ti), 500% of platinum (pt), and 4,000% of gold (Au) are sequentially plated on the surface of the Japanese yen, as shown in Figure 2L. . Use acetone to dissolve the photoresist 211 pattern and remove the metal 2i2b attached to it to achieve the purpose of metal lift-off. The remaining metal 212a is in contact with the exposed in〇53Ga〇47As layer as a p-type The printed poles of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Metals and Electricity Economy are shown in Figure 2M. It is worth emphasizing that the planar structure formed by STOP polishing technology and comprehensive etch-back 15 process is the most ideal for the P-type metal process described above; on the contrary, the traditional non-planar double-groove structure is easy to cause metal coating The problem is also not conducive to metal lift-off. After rapid thermal annealing (rapid iermai annea Hng, rta) of the p-type metal on the wafer under 42 (TC, nitrogen environment for 20 seconds), the wafer was ground and polished from the back to about 100 microns Wafer thickness (200a), and 20 in sequence Luo gold 丨 000 gold germanium (Ge) nickel (Ni) alloy (84% Au, 12% Ge, 4% Ni) and 4000a gold on it As the N-type metal electrode 213, as shown in FIG. 2N, the N-type metal electrode was subjected to RTA for 20 seconds at 39 () ° C. The RTA of the metal electrode was intended to reduce the ohmic contact resistance twice. FIG. 3A to FIG. 3P show the half of each process step in the second preferred embodiment.

550866 A7

550866 A7 V. Description of the invention (I7 moved to SiNx layer 307a. After the wafer has been cleaned and deoxidized, the SiNx layer is used to clean the conductor ridges by wet wire decontamination. First, use the mixed uniform 1 H_ ·· 1 _2: 2G _ Solution removes highly doped p-type In (U3G late-gamma contact layer that is not protected by S: lNx, its rate is about 0.25 microns per minute, and it has high selectivity for the InP layer The nearly isotropic (is〇tr〇pic) etching caused this In〇53Ga〇47As layer to inevitably be slightly undercut, as shown in Figure 3_. I HF: 1〇H2〇 to remove the mask Behind the mask 'In.53Ga.47As layer 306a (Figure 30 is now the next mask of the p-type Inp waveguide layer engraved. The side of the InP is the use of mixed uniform 1 之 Π ·· 3 coffee solution The side agent has a rate of InP as high as 0.6 micrometers per minute, and has a high selectivity to the In.53Ga (U7AS layer. After the Inp waveguide layer, the cross-section of the element structure is as shown in the figure, and the InP layer 305a appears Some of the ladder-like cross sections are related to the ridge direction of the material body. The secret is implemented, and the rotation ridge direction is parallel to the wafer. Minor flat. This inverted ladder-shaped cross section, combined with the undercut of the semiconductor layer, forms a semiconductor ridge with a wider ridge top, while maintaining a narrow ridge bottom with an active area injected by a sense current, and is implemented here. In the example, it is about 2 micrometers wide. After the semiconductor ridge etching is completed, a 3000 SiOx passivation layer 309 is fully deposited on the wafer surface at 250t, as shown in FIG. III. At this stage, the device manufacturing process All are through the conventional semiconductor process steps. The following is the use of STOP technology and the full back-up process to achieve a self-aligned process. After surface growth SiOx passivation, the wafer is placed in another pECVD process cavity at 350 ° A layer of 3 micrometers in thickness of 3 丨 (^ layer 31 〇, as shown in Figure 2 J. This thickness 3 丨 0) is quickly deposited at 2750 C per minute (the layer completely covers the wafer surface, and the semiconductor ridges below it cause Ridge formations are also formed on the surface of SiOx. With ordinary polishing equipment, as before I _—__- 15- This paper size is based on the standard of CNS (A4, 297 mm) 5 10 15 20 550S66 A7 V. Invention Explanation (Employees' Consumption Cooperation As described in the printed example, the Si0x surface with the original ridge landform can be polished to the SiOx plane 310a as shown in Fig. ^. Then, the Si0x plane is completely etched back with CF4 gas up to In0. 53Ga〇. 47As ohmic contact layer is uniformly exposed. In order to further increase the contact area of the metal electrode in the future, the entire 1110.5.4 fine ohmic contact layer 306a, including its sides, is exposed, as shown in Figure 3 Show. Therefore, in contrast to the previous embodiment, the contact layer at the top of the ridge is higher than the surrounding Si0x31b. The subsequent process is also a conventional semiconductor process and has no direct relationship with the present invention. However, as in the previous embodiment, the planar structure created by the present invention is helpful for the subsequent processes. After the In.53Ga.47As ohmic contact layer at the top of the semiconductor ridge is uniformly exposed, a p-type metal region is defined using a photomask alignment and exposure development process, as shown in Fig. 3M. Photoresist 311's approximately inverse-shaped profile can help metal lift off the process. Then 50x titanium (Ti), 500mm platinum (Pt), and 4,000mm gold (Au) The surface of the wafer in order is shown in Fig. 3n. The photoresist pattern 15 311 is dissolved with acetone to remove the metal 312b attached to it, and the metal is lifted off. The remaining metal 312a and the exposed In. The .53GaOe47As layer is contacted as a p-type metal electrode, as shown in Fig. 30. After rapid thermal annealing (RTA) of this p-type metal electrode for 20 seconds under a 420 nitrogen atmosphere (RTA) ) After that, the wafer was ground and polished from the back to a wafer thickness (300a) of about 100 micrometers, and 1,000 g of gold germanium (Ge) nickel (Ni) alloy and 4,000 g of gold were sequentially evaporated. On the other hand, as the n-type metal electrode 313, as shown in FIG. 3P, RTA is performed on the N-type metal electrode at 390 ° C for 20 seconds. In the above two embodiments, the STOP polishing technology is used to align the tool. The SiOx surface of the ridge landform is flattened. Figure 4 shows the meaning of the process of implementing the STOP polishing process.

I 10 Alignment 20 -16- This paper size is applicable + National National Standard (CNS) A4 specifications (0x 297 public love) 550866 a? B7 PA010430 υοζΓΠΤΤΣΤ 5. Description of the invention (changes in surface topography. (Α) is for throwing Before grinding, the topography of the SiOx surface on the wafer 400 has ridges. As in the above two embodiments, the starting height of these ridges 403 is about 1.6 to 1.7 microns, which is much higher than that of ordinary polishing equipment. The achieved uniformity (about ± 5 microns). Therefore, as shown in (B), using a general polishing machine, after 5 minutes of polishing for the first few minutes, in a certain area range 401, SiOx ridges The height of 403a is not removed uniformly. However, the polishing removal rate of the SiOx plane 402 is almost stagnant due to the adjustment of the pressure applied by the polishing surface. On the contrary, due to the extremely small polishing area of the SiOx ridge, the Removal by polishing can be quite rapid, up to about 0.15 micron per minute. When the polishing process is continued, these SiOx * 10 will be able to be sequentially without affecting the SiOx bottom plane 402 It was completely removed by grinding, as shown in (C) or (D). That is, after all SiOx ridges have been removed, the rate of polishing the SiOx layer is almost stagnant, as if it were self-terminating. Therefore, the flatness of the final surface will be related to the SiOx deposition mechanism instead of It is greatly related to the polishing process; therefore, it can be clearly seen that the present invention is suitable for mass production environments with high requirements on process uniformity and yield. [Features and Effects] The ridge waveguide semiconductor provided by the present invention Laser's self-aligned manufacturing method of the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economics has the following advantages when compared with the aforementioned citations and other customary techniques: 20 (1) Simple and reliable process ·· Traditional The double-groove structure requires at least three mask alignment and exposure development processes, but using the self-aligned process proposed by the present invention requires only two. In addition, if the cross-sectional shape of the semiconductor ridge is not appropriate, such as inverted Trapezoidal (inverse-tapered) or undercut, the traditional double-slot structure has the problem of metal coating. 'Because the metal electrode must be coated from the top of the ridge to the bottom of the groove and then coated -17-x 297 ^ 17 m ruler Applicable to 550866 B7 V. Description of the invention (^) '' A0I04J0 D (5c -18/21) The employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed to the binding pad area. Improper cross-sectional shape may lead to excessive resistance or even disconnection. The resistance value will cause unnecessary parasitics and thermal effects, while the disconnection will cause the component to lose the binding pad, both of which will cause the component yield to decline. In contrast, flat components have no such problems; and because the entire spine top (even a little Ridge side) can be used in contact with the metal electrode, the component resistance value can reach the best situation to reduce the thermal effect. Furthermore, by using the STOP technology, chemical wet etching, which is more convenient for dry etching, can also be used to form semiconductor ridges. (2) Excellent process uniformity. · Implementing ST〇p polishing technology to flatten the SiOx surface with ridge landforms. The flatness of the SiOx plane depends on the deposition of SiOx 10. Mechanism, under normal circumstances, the flatness of this sediment can reach less than 1% of soil (except for wafer edges), so it can achieve excellent process uniformity. (3) Give the component the potential for high-speed operation: Because the binding pad is placed on a thick layer, the parasitic capacitance caused by it can be smaller than that of the traditional two-slot structure, which also increases its RC-limited bandwidth. 15 ⑷ Potential for flip-chip bonding: Due to the planar device structure, it gives the device p-side flip-chip bonding capability, which will help semiconductor laser heat dissipation. In addition, flip-chip bonding can also be used for quasi-monolithic integration of other optoelectronic active and passive components (qUasi-m0n0H). The detailed description above is specific to one of the feasible embodiments of the present invention. The embodiments are not intended to limit the scope of the patent of the present invention, and any equivalent implementations or changes that do not depart from the technical spirit of the present invention should be included in the scope of the patent in this case. In summary, this case is not only technically ideological Innovative, and can improve the above-mentioned multiple effects over conventional items, which should fully meet the novelty and progress

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I 550866 A7 B7 --- PA010430.DOC-19/21 V. Description of invention (f |) statutory invention patent elements, apply in accordance with law, and kindly ask your office to approve this invention patent application to encourage invention Deben. (Please read the notes on the back before filling this page) _ _ _ _ _ _ _ n 1 «I fliBi 1_§ | _1 ϋ · 1 > · ϋ e ^ tm n · i ^ i ai-i I n _ =口 / ¾ j Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -19- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

550866 Applicable patent scope A8 B8 C8 D8 卩 A01W3Q_m 10 15 Printed by the Consumer Cooperatives of the Smart Finance 1 Bureau of the Ministry of Economic Affairs 20 2. ―A kind of self-made manufacturing method for ridge waveguide semiconductor lasers, which includes at least the following steps: Steps provide a An epitaxial growth multilayer laser structure, which includes a semiconductor substrate, a conductor waveguide layer, a first semiconductor confinement layer, a semiconductor active layer, a second semiconductor confinement layer, a second semiconductor waveguide layer, and a semiconductor. Ohmic contact layer; step- · deposit a comprehensive _ dielectric layer on the semiconductor ohmic contact layer in step- one; step one-by-define the pattern due to the second-dielectric layer in step two, as a mask for the remainder, And carry out the _ process, with alkaline semiconducting age-like structure; Step 4: Fully deposit a second dielectric f layer on the third half of the ridge-like structure formed in Step 3 as passivation treatment on the surface of the conductor; Step 5 · Comprehensive Deposit a third dielectric layer on the wafer surface that has a ridge structure and dielectric passivation treatment in step 4; step 6 · flatten the surface of the third dielectric f layer in step 5 Step 7: Perform a comprehensive etch-back process to uniformly remove the thickness of the dielectric layer until the ohmic contact layer on the top of the semiconductor ridge is uniformly exposed; Step 8: The first-metal layer and the second metal layer on board, the first A metal layer is in contact with the ohmic contact layer of the semiconductor ridge top exposed in step 7 as the electrode of the component on the wafer surface; and the second metal layer is on the back of the polished wafer as the component on the wafer Round electrode on the back. According to the self-aligned process method of the ridge waveguide semiconductor laser described in item 1 of the scope of the patent application, the first dielectric layer described in step 2 may be SiOx, SiNx, or SiOxNy. Please read the note I above [Paper size is applicable to China CNS] ^ 50866 A8 B8 C8 D8 Patent application scope PA010430.DOC 21m 3 · 5 5. 10 6. 15 8. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 20 According to the self-aligned process method of the ridge waveguide semiconductor laser described in item 1 of the scope of the patent application, the etching of the semiconductor ridge structure described in step 3 may be wet etching, dry etching, or both. Of combination. The self-aligned manufacturing method of the ridge waveguide semiconductor laser as described in the first item of the patent application scope, wherein the layer described in the fourth step may be SH) X, SlNx, or SlOxNy. ^ The self-aligned process method of the ridge waveguide semiconductor laser described in item 1 of the scope of the patent application, wherein the thickness of the third dielectric layer described in step 5 is larger than the ridge height, which can be SiOx or SicoH. The ridge waveguide semiconductor laser as described in item (2) of the patent application. In the alignment process method, the flattening process described in step 6 in # can use the polishing process performed by a chuck-type flapping device. Such as the scope of patent application! The ridge-waveguide semiconductor laser described in item 1 of the self-aligning process method, wherein the step 7 is a comprehensive process of the flat dielectric surface, which can be wet-type, dry-type, or both. Of the combination. The female claims that the ridge waveguide semiconductor laser described in the item 彳 of the patent scope of the ^ self-alignment process method, the towel can be removed as a light-shielded first-step dielectric before step three after step four. Steps in the stratum. Please read the notes on the back first.