TW550748B - Method of forming dual damascene structure - Google Patents

Abstract

This invention discloses a dual damascene structure formation method. Firstly, a substrate is provided with a dielectric layer formed thereon. Then, a cap layer and a mask layer with at least one trench pattern are formed sequentially on the dielectric layer. Subsequently, a resist layer with at least via hole pattern is formed on the mask layer and the cap layer, in which the via hole pattern corresponds to the trench pattern. The via hole pattern is transferred to the cap layer and the upper portion of the dielectric layer and the resist layer is removed. Then, the trench pattern is transferred to the cap layer and the upper half of the dielectric layer and concurrently the via hole pattern is transferred to the lower half of the dielectric layer. Finally, a conductor layer is filled into the trench and via hole of the dielectric layer.

Description

550748 V. Description of the invention (1) Field of the invention The present invention relates to a semiconductor, and in particular, to a method for manufacturing an open circuit circuit and a specialization thereof. A method to open / double the mosaic structure to prevent phototoxin-related technology Description: Quickly and more time is devoted to the development of high-tech operations and rapid development to increase strength: Buildup :: zhi; Chengjizhi's size has been reduced Will make Lidao's clear-shaped conductor assembly problem becomes more: the resistance value of m rises, and the capacitance is effective. In order to reduce the capacitance effect of the current resistance in the metal wire, the metal wire system uses a low dielectric constant. . wk) The insulation layer between the metal and metal wires is based on the value system. The dielectric layer with a low dielectric constant and low resistance and low reliability are developed: ίEmbedded process' to make a high 2 in a integrated circuit device! Explanation of the lamd diagram—f knowing the formation of a double-money structure 2 ^ ^. 凊 Refer to Figure 1 a, and provide a substrate 100, such as half of the mediator i ΐ number ϊ ΐ a cover layer is sequentially formed on the screen bottom 100 〇2 and -low 枓 layer 104. Then, a mask layer 106 is formed on the low-dielectric-constant material layer ι04 with a plurality of trench openings 106a. Next, referring to Figure lb, apply a layer of photoresist on the mask layer 106, 108, and fill the trench openings 6a. Next, a photolithography step is performed on the photoresist layer 108 to form a photoresist layer on the mask layer 106 and the dielectric layer 104.

0702-7942TWfiNVQiDi7. Page 4 550748 V. Description of the invention (2) Photoresist pattern layer 1 08 of the number via (v i a) opening 1 08a. Among them, the location of the mesial hole opening 108a corresponds to the trench opening of the lower mask layer 10; 1a and 0a. However, the photoresist poisoning is caused by the ammonia (amin〇) in the dielectric layer 104, so that the sidewall profile (pr0f) of the photoresist pattern layer 丨 〇8 is better. J 不 Next, please refer to Fig. 1c, using the photoresist pattern layer 008 as a mask, to perform an anisotropic etching on the dielectric layer 104, and transfer the hole pattern of the dielectric layer to the upper half of the dielectric layer 104. " Finally, referring to Figure 1d, strip the photoresist pattern layer. 08. Next, use the mask layer 10 with a trench opening 106a to etch the dielectric layer 04 and use a capping layer. 102 is used as an etch stop layer, and the trench pattern is transferred to the upper half of the dielectric layer 104. At the same time, the hole pattern of the upper half of the dielectric layer 104 is also transferred to the lower half of the dielectric layer 104. The sample 104b and the dielectric hole 104a formed in the dielectric layer 104 constitute a dual damascene structure. After that, the capping layer 102 located under the dielectric hole 104a is removed to expose the substrate 1 〇〇 the surface. ^ Under the influence of the photoresist Qinhua, the via hole profile in the dual damascene structure is not good, which reduces the reliability of the integrated circuit device. Summary of the Invention: Hibiscus The purpose is to provide a method for forming a double mosaic structure, which comprises forming an additional capping layer on the dielectric layer to directly contact the dielectric layer with the photoresist to prevent photoresist poisoning.% Another object of the present invention It is to provide _ 丝 # ..., Xi Shi a Gan $ aw Second, a method of forming a dual mosaic structure, the formation of an anti-refiective layer (ARL) as a cap layer to improve the dual mosaic structure The round is overwhelming.

550748 V. Description of the invention (3) According to the above object, the present invention provides a method for forming a dual mosaic structure. First, a substrate is provided with a dielectric layer thereon. Next, a cap layer and a mask layer having at least one trench pattern are sequentially formed on the dielectric layer. After that, a photoresist layer having at least one interlayer / same pattern is formed on the cover layer and the upper cover layer, and the position of the interlayer hole pattern corresponds to the trench pattern. Next, the via hole pattern is transferred to the upper cap layer and the upper half of the dielectric layer ′ and then the photoresist layer is removed. Next, the trench pattern is transferred to the upper half of the cap layer and the dielectric layer, and the hole pattern of the dielectric layer is transferred to the lower half of the dielectric layer at the same time. Finally, a trench is filled in the dielectric layer with a conductive layer. Detailed description of the preferred embodiment: The method of forming a double damascene structure according to the embodiment of the present invention will be described below with reference to Figures 2a to 2f. First, referring to FIG. 2a, a substrate 200 is provided, such as a semiconductor substrate, and the substrate 200 has a plurality of metal wires 201, such as copper wires. Next, a cap layer 202 is formed on the substrate 200. Thereafter, a dielectric layer 204 is deposited on the capping layer 202 as an intermetal dielectric (IMD). Here, the capping layer 202 is used to prevent the metal wire 201 from being exposed to air to cause oxidation, and to prevent the atoms / ions in the metal wire 201 from diffusing into the dielectric layer 204 and causing leakage current or poor electrical contact. . In this embodiment, the material used for the capping layer 202 is preferably silicon nitride (S i N) or silicon carbide (s 丨 c). In addition, the material used for the dielectric layer 204 is preferably a low dielectric constant material, such as BD @,

After Coral® 'Aurora® and GreenDot® 〇, a cap layer 206 and a mask are sequentially formed on the dielectric layer 204.

0702-7942TWf (N); 91P17; spin.ptd

Page 6 550748 V. Description of the invention (4) Layer 208 and a photoresist layer 212. In this embodiment, the material used for the cap layer 206 may be unoped silicate glass (USG), carbonized carbide or silicon fluoride (SiF), and its thickness is in the range of 300 to 1500 angstroms. The cap layer 204 may be formed by a chemical vapor deposition (CVD) method, in which a silane (Si H4) or a tetraethyl ortho silicate (TEOS) is used as a reaction gas. Furthermore, the mask layer 208 is used to define the groove pattern in the dual damascene process. The preferred material is silicon nitride and the thickness is in the range of 800 to 12 Angstroms. In addition, an anti-reflective layer (ARL) 21, which has a thickness in the range of 2000 to 400 angstroms, can be selectively formed on the cover layer 208, and its preferred material is It is silicon oxynitride (Si ON). Next, referring to FIG. 2b, a photolithography step is performed on the photoresist layer 2 丨 2 to form a plurality of trench openings 212a in the photoresist layer 212. Subsequently, the photoresist layer 21 2 is used as a mask, the anti-reflection layer 2 j is etched with an anisotropic coin, and the lower mask layer 208 is exposed to expose the upper cap layer 206 as an etching stop layer. In this way, the trench opening pattern is transferred to the mask layer 208. Photoresistive sound 2 ^ 2 ': Referring to the & diagram, the conventional photoresist stripping method is used to remove the f-resistance layer 212, such as an oxygen plasma (02 Plasma) ashing method. After that, another anti-reflective layer SiO 2/2 is coated on the anti-reflection layer 210, and then the first blocking layer 214 is covered by n μ to fill the trench opening 212 a. Next, the same is true for the photoresist layer 214 and the top cover layer 210. It is easy to find the photoresist pattern of the anti-reverse ma. The top two have multiple interlayer holes. The position of the (...) opening corresponding to the lower 2:21 interstitial hole opening 214a is the groove opening 212a of the shot 10 and the military curtain layer 208. 550748

Next, please refer to FIG. 2d, using the patterned photoresist layer 2i4 as the t-screen 'anisotropic etching of the cap layer and the dielectric layer 204 under the opening 2Ha of the interlayer to transfer the pattern of the interlayer hole To the upper cap layer 206 and the upper half of the dielectric layer ^ 4. In this embodiment, since the capping layer 206 is formed between the capping layer 208 and the dielectric layer 204, the photoresist layer 214 cannot directly contact the dielectric layer 204 ', thereby preventing the photoresist from poisoning. Furthermore, since the cap layer 206 of the present invention can also be used as an anti-reflection layer, problems such as standing wave effects and reflection nicks can be further avoided. “Next, please refer to FIG. 2e, and also use the conventional photoresist stripping method of the oxygen plasma ashing method to remove the photoresist layer 2 丨 4. Here, the cap layer 206 can protect the dielectric layer 204 from suffering Oxygen plasma attack and damage. After that, the cover layer 208 with a groove pattern covering the top with an anti-reflection layer 210 and the cover layer 002 as an etch stop layer were used. The dielectric layer 204 is engraved to transfer the trench pattern to the upper cap layer 206 and the upper half of the dielectric layer 204 below. At the same time, the original hole pattern in the upper half of the dielectric layer 204 It is also transferred to the lower half of the dielectric layer 204. These trenches 204b and the dielectric hole 204a formed in the dielectric layer 2 ^ 4 form a dual damascene structure. Then 'remove the dielectric hole 204a' The lower capping layer 20 is used to expose the metal wire 201 under the via hole 204a.

Finally, please refer to FIG. 2f, and sequentially remove the anti-reflection layer 20, the mask layer 208, and the cap layer 206 to expose the surface of the dielectric layer 204 having the trenches 204b and the vias 204a. Next, a metal barrier layer 215 is formed on the dielectric layer 204 and its trench 204b and the sidewall of the dielectric hole 204a. Here, the material of the metal barrier layer 2 1 5 is preferably titanium (τ i), button (Ta), or titanium nitride (T i N

550748 V. Description of Invention (6)) and Nitriding Button (T a N). Similarly, the metal barrier layer 2 1 5 is used to prevent the atoms / ions in the metal (not shown) from diffusing to the dielectric layer 2 0 after the subsequent metallization process, resulting in poor electrical contact or leakage. Current. Thereafter, a conductive layer 2 1 6 is deposited on the dielectric layer 2 04, such as a copper metal layer 'and fills its trench 204b and the dielectric hole 2 04a to make electrical contact with the metal wire 2 01. Next, a chemical mechanical polishing (CMP) method is used to polish the excess conductive layer 216 and the metal barrier layer 215 over the dielectric layer 20 4 to form the grooves 204 b and the dielectric layer 204 in the dielectric layer 204. An interconnect is formed in the layer hole 204a. Compared with the conventional method for forming a dual-mosaic structure, the present invention is shaped as follows: the upper layer i is 2 ° 6 to avoid the outline of the mutual structure of the main and non-dielectric layer 204 and the photoresist layer 214. Mind, and then improve the double mosaic Although the present invention has been disclosed in the preferred embodiment as above, the present invention 'anyone who is skilled in this art, can be modified and retouched in a non-limited range, so The spirit of the present invention and the scope of the attached patent application shall prevail. The protection scope of Ming

550748 Brief description of the drawings In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows: Figures 1a to 1d A schematic cross-sectional view of a conventional method for forming a dual-mosaic structure is shown. Figures 2a to 2f are schematic cross-sectional views illustrating a method for forming a dual-mosaic structure according to an embodiment of the present invention. [Explanation of symbols] 100, 20 0 ~ substrate; 102, 202 ~ capping layer; 104, 204 ~ dielectric layer; 104a, 204a ~ via hole; 104b, 2 04b ~ trench; 106, 20 8 ~ mask 108, 212, 214 ~ photoresist layer; 10 8a, 214a ~ via hole opening; 2 01 ~ metal wire; 20 6 ~ cap layer; 2 1 0 ~ anti-reflection layer; 21 2a ~ trench opening; 2 1 5 ~ metal barrier layer; 21 6 ~ conductive layer.

0702-7942TWf (N); 91P17; spin.ptd page 10

Claims (1)

55〇748, Application: Scope I-1 · A method for forming a dual damascene structure, including at least the following steps: providing a substrate having a dielectric layer on the substrate; forming an upper capping layer on the dielectric layer; A mask with at least one groove pattern is formed over the upper cap layer. A photoresist layer having at least one interlayer hole pattern ^ is formed on the mask layer and the upper cap layer, and the position of the via pattern is Corresponding to the trench pattern, the hole pattern of the interlayer is transferred to the cap layer and the dielectric layer. The light is removed halfway. The trench I is simultaneously placed in the dielectric. Said the interlayer hole 3 · If you applied for the gold 4 · If you applied for the base 5 · If you applied for the seal 6 · If you applied for the law method resist layer; Pattern transfer layer hole pattern layer groove to the cap layer And the upper half of the dielectric layer is transferred to the lower half of the dielectric layer; and a conductive layer is filled in the dielectric hole. The square forming the double damascene structure described in item 1 of the patent scope. The metal wire is located below the dielectric bottom including one. The scope of the patent belongs to the wire system. The scope of the patent is the bottom. The scope of the patent. The material of the capping layer. The metal wires forming the dual damascene structure described in item 2 are covered with a capping layer. The method of forming the dual damascene structure described in item 4 is any one of silicon nitride and silicon carbide. The method of forming a dual mosaic structure described in item 1 0702-7942TWf (N); 91P17; spin.ptd page 11 550748 6. Patent application method, wherein the cover layer includes an anti-reflection layer. Method 7: The method of forming a dual damascene structure as described in item 6 of the scope of the patent application, wherein the anti-reflection layer is a silicon oxynitride layer. Method 8: The method of forming a dual damascene structure as described in item 1 of the scope of the patent application further includes the following steps: removing the 4 mask layer and the top layer to expose the surface of the dielectric layer having the trench and the via hole; And a metal barrier layer is formed on the dielectric layer and its trench conforms to the surface of the dielectric hole. 9. Method of forming a dual damascene structure as described in item 8 of the scope of the patent application, wherein the metal barrier layer is composed of any one of titanium, button, titanium nitride, and nitride button. The method of forming a dual damascene structure as described in item 1 of the scope of the patent application, wherein the dielectric layer is a low dielectric constant material layer. , U · The method for forming a dual damascene structure as described in item 1 of the application + patent scope, wherein the cap layer is composed of any one of undoped silica glass, silicon carbide and silicon fluoride. 12. The f method for forming a dual damascene structure as described in item n of the scope of the patent application, wherein the method is formed by a chemical vapor deposition method and is used as a reaction gas. ^ 13. The method of forming a dual damascene structure as described in item n of the scope of the patent application, wherein the cap layer is formed by a chemical vapor deposition method and tetrabasic silicate is used as a reaction gas. 14. Forming a dual mosaic structure as described in item n of the scope of patent application 550748 6. Method of applying for a patent, wherein the thickness of the cap layer is in the range of 300 to 15 Angstroms. 1 5. The method for forming a dual mosaic structure according to item 1 of the scope of the patent application, wherein the mask layer is a nitrided layer. 16 · The method of forming a dual damascene structure as described in item 1 of the scope of patent application, wherein the conductive layer is a copper metal layer. 0702-7942TWf (N); 91P17; spin.ptd Page 13