TW548998B - I2C opto-isolator circuit - Google Patents

Abstract

An opto-isolator circuit for providing isolation between a bi-directional, I2C transmission line and a pair of single-direction transmission lines. The opto-isolator circuit includes a bi-directional port for receiving data from, and providing data to, the bi-directional transmission line. The circuit further includes an output path that has (i) a first buffer for receiving outgoing data from the bi-directional port, (ii) a first opto-isolator for receiving the outgoing data from an output of the first buffer, and (iii) a second buffer for receiving the outgoing data from an output of the first opto-isolator and providing the outgoing data to an output port. The circuit also includes an input path, that has (i) a third buffer for receiving incoming data from an input port, (ii) a second opto-isolator for receiving the incoming data from an output of the third buffer, and (iii) a fourth buffer for receiving the incoming data from an output of the second opto-isolator. The fourth buffer provides the incoming data to the bi-directional port such that characteristics of the incoming data are compatible with I2C characteristics.

Description

548998 V. Description of the invention (1) Background of the invention The present invention relates to a circuit that provides electrical isolation, and particularly relates to an optically isolated circuit (hereinafter referred to as an optical isolation circuit) and its integrated circuit (hereinafter referred to as I 2 C) The communication protocol is compatible. The I 2 c bus is a two-way port and two-wire communication structure. It is developed to provide communication between integrated circuit (IC) devices, which is customary. The I 2C protocol is roughly a master-slave system, in which the master station broadcasts information requests to specific slave stations on a single line, and the slave station continues to monitor the line broadcast to it. When the slave station detects that it is the receiving target, the slave station is at The master station responds to the request a certain time after the transmission has been completed. According to this, only one transmitter uses the line at the same time, and all are under the control and command of the main station. The standard data rate is 100,000 bits per second, and it can be increased to 40,000 per second in fast mode. Bit, as long as it does not exceed the maximum bus capacitance (40 OpF) 'Generally speaking, there is no limit to the number of devices that can be connected to the [2C bus. Figure 1 shows a battery monitoring application in which an I 2C bus is used. In this application, many battery cell modules 20 (such as at least 30 modules) are connected in series to form a high-voltage battery. Each battery cell module 20 includes A voltage unit 22 and a power monitoring module 24 connected to the unit 22. In one embodiment, the voltage unit includes a N1 MH fast cell unit, although other techniques may be used to generate the voltage used. The power monitoring module 24 determines various parameters of the unit 22 and these parameters via j% Huiguang: 0 :: committers, each module provides: data input and output '^ • pulse I / 〇 port 3 4 and area ground 3 6 The data 丨 clock 1 / 〇34 are connected to the area, so in the picture! In the example, many A: \ PTA-203 ~ 2.ptd 548998

The unit modules 20 are connected to different voltage levels, and provide information about the constituent units _ 贝 j. Because the battery module 20 is stacked (that is, connected in series), there are different voltages between the ^ ° #U of the module. For example, suppose that each single 7 ^ 22 produces 10 · 8 祆 = 20 bismuth at the bottom of the battery module in series. The voltage difference between groups 20 was 324 volts. The monitoring module 40 communicates with each module 20 through the I2C bus 42. However, each module 20 operates at different voltage levels, so data 3 2 and 2 cannot be connected in time. Together, so that the data 32 and the clock 34 are isolated from each other through the isolator 50, and their outputs can be connected to a common bus (the figure uses a driver t set to provide isolation between circuits operating at different voltage levels) It is an optical isolator, but the conventional optical isolation circuit is incompatible with the characteristics of the 2C communication protocol. The purpose of the present invention is to substantially overcome the above-mentioned conventional disadvantages and shortcomings. Summary of the Invention The present invention can achieve the above and other objectives. One feature is that it includes an optical isolation circuit that provides isolation between the $ 2 璋 I 2C transmission line and a pair of unidirectional transmission lines. The optical isolation circuit includes a bidirectional port for communicating data with the bidirectional port transmission line. The circuit further includes an output path having (1 ) A first buffer to receive the data output from the bi-directional port, (2) — the first optical isolator to receive the data output from the first buffer, and (3) a second buffer to receive the first output The optical isolator outputs data and provides output data to an output. The circuit also includes an input path that has (1) a third buffer to receive data from the input port, and (2) — a second optical isolator to receive Data output from the third buffer, and (3) a fourth buffer to receive the second optical

548998

Data of the isolator output. The fourth line. ^ ^, Youchong District provides input data to the two-way port to make the characteristics of the input data compatible with the I2C characteristics. ^ 至 又 ^ 乂 In another embodiment of the present invention, f 4W Α Lift: Chinese ^ plus a voltage level corresponding to a logic high is applied to the input port, it is a ^ oblique 寤The ™ port is at a voltage level corresponding to a logic high: 2: When a logic low voltage level is applied to the input port, the bidirectional port is at a voltage level corresponding to a logic low. In another embodiment of the present invention, φ ^ ^ 你 进 # Although the voltage level corresponding to a logic high is applied to the bidirectional port in the ShiJiangYong AJ, φ is combined with mβ $ π af + _ ~ Corresponds to a logic high voltage level, and when a logic xixi emperor is applied ^ Ψ it sp y- 0, ro & _ flip L level is added to the bidirectional port, the output port is corresponding to a low Voltage level. In another embodiment of the present invention, the first buffer includes: a buffer capable of buffering _ ,, and eight electrical connections to the bidirectional port, f) a power connection to the first optical isolator Π f⑺ output should be a logic High state 'reference voltage. (3)-Connection of input power to the pair In another embodiment of the present invention, the second area is constructed and configured as a buffer, including a tri-state buffer, a Siamese structure, and a set-up Narita. When an optical isolator applies a voltage in the state to the rotation of the second buffer zone, the three energy ^ one 2 series south-like high impedance state. When the first optical p ^ σ ~, the output of the red zone is the input voltage from the voltage to the second buffer, the three energy == one of the logic low states of the south state, the output of the two ... / Corresponds to the output port. Moreover, the output of the second buffer area is electrically connected in another embodiment of the present invention. The fourth buffer area includes... (1) a high impedance to connect the input power to the input port 1 = the buffer power is connected to The second optical isolator, a round-by-round electrical connection to the pair

Page 8 A: \ PTA-203-2.ptd 548998 V. Description of the invention (4) The reference voltage should be a logic high state. In another example, in the embodiment, the second buffer area includes a tri-state buffer Γ + and the third buffer area is configured as a second optical isolator to apply a logic high state to the fourth buffer area. The output is at = ... When the -optical isolator is applied-high resistance 1 2 M = =, the k-thousands of the people in the k-zone, the output of the tri-state buffer is at the opposite voltage level, and the output of the tri-state buffer is :: Lost and supplied ::: 2: Transferring the two-way cockroach I2C transmission line to and from the two-way port, the method includes a two-way port to (1) a first intercommunication shell material, the method further includes a The output path also has an optical isolator to receive the data output from the first receiving bidirectional port by V '(2) -the data output from the receiving area of the buffer zone, and (3) -the second main round output port. The method also includes an input route out of the beacon area to receive the data output from the port, "the first, the third, the third buffer, and the third buffer receive the output of the third buffer. The output of the asset = Chongdi District 4-2, ^ Bidirectional to make the characteristics of the rotation data compatible with the I2C characteristics. The rotation data is briefly explained in the attached drawings. The other features can be mentioned in conjunction with the drawings and the following detailed description. The features and the present invention of the present invention are shown in Figure 1 above-the battery monitoring application where w is secondary: Figure 2 shows the I2C optical isolation circuit according to the present invention : Man's Box I also dries page 9A: \ PTA-203-2. Ptd 548998

V. Description of the invention (5) Figure; Figure 3 shows the distribution of the optical isolation circuit to the data line; and Clocks of 3 different units of Guilu and FIG. 4 is a schematic diagram illustrating the preferred embodiment of the optical isolation circuit of FIG. Fig. 2 shows a block diagram of the battery 10 according to the present invention. The first embodiment of the isolation circuit 100 is a circuit for isolating electricity a, and Fig. 3 shows it. Optics; 3,200 materials, 1/034, clocks and data lines received with different light distributions, 4 courts, 1 00, 3 no @Unit 2〇 in Figure 2 'optical isolator 100, including port 1106 , The optical barrier to the car 102 'output port 104 and the output mode, the optical emission signal in the "isolator_", and the two outputs through the light in the first pole type, the optical isolator 100 in the wheel port 106 Connected two; two pass through the optical isolator 10. And the transmission signal, and the 妾 栌 祙 produced a π ", the internal one again to the port 10 2 and output" No. in the two branch type, optical isolator 1 0 0 no action , 102, 104, and 106 are in a preset inactive state. In the more scooter, the preset non-action state is logic high. In the present invention, the signals entering and exiting the 璋 102, 104, and 106 are digital logic, which is sure in other embodiments. The medium signal can be an analog signal or a signal. When the optical isolation circuit 100 operates in the first mode, the first buffer 100 receives the signal from the two-way port 10 02 and drives it into the first optical isolation circuit. In the example, the first optical isolator 108 is a light emitting diode & ed) and 548998. V. Description of the invention (6)

The combination of light and body (this is customary). In this optical isolator, the LED converts the electrical signal into an optical signal, and transmits the optical signal to the photoelectric crystal. The optical package body receives the light. Signal, and then convert it into an electrical signal, and provide a reply electrical signal at the output of the optical isolator. This optical isolator thus provides an isolation gap between the LED and the optoelectronic crystal. Other devices such as this can be used by converting the electrical signal into another form and then converting it back to the electrical signal, or by custom Provide another method of isolation and provide isolation. An example of the isolated state: PS 2 5 0 1 manufactured by NEC. The second buffer 1 1 2 receives the output signal of the first optical isolator 1 1 0 and outputs the Signal to output port 丨 〇4. When the optical isolation circuit 100 is operated in the second mode, the third buffer region 114 receives the serial number of the input port 1 06 and inputs it to the second optical isolator 1 1 6 which has the same as the first optical isolator Similar to 110, the fourth buffer area 118 receives the output signal of the second optical isolator 116 and inputs the signal to the port 102. jv infg ^ When there is no input signal to ~ 璋 102 and input port 106, the optical isolation circuit is operated (also known as idle mode). When the optical isolation power returns to port 102 or input port 106 and no input signal is detected, the light + The isolation circuit 100 drives the bi-directional port 102 and the output port 104 to reach a predetermined level. In the preferred embodiment, the setting of Fs1 means that the corresponding logic high level depends on the special logic family used. ), Although other preset levels can be used to indicate idle status. FIG. 4 is an illustration of a preferred embodiment of the optical isolation circuit 100. The driving circuit 202 is driven again, and the driving circuit is: “low: logic low, or high impedance state, the driving circuit 202

548998

The output is connected to the reference voltage VC C1, which preferably corresponds to a logic high, and the output of the driving circuit 2 0 2 is connected to the LED 2 04 anode 2 03 of the optical isolator 110, and the high impedance enable input 2 0 6 is connected to the bidirectional port 1 02, the cathode 205 of the LED 204 is connected to one end of the resistor 208, and the other end of the resistor 208 is connected to the area ground i (LGl), where LG1 is defined as a 0 volt reference voltage with respect to VCC1. ~ The second buffer area 112 includes a driving circuit 210 having a tri-state output, an NPN bipolar transistor 212, a pull-up resistor 214, and a pull-down resistor 216. The input of the driver 2 10 is connected to the area ground (LG), where LG It is defined as a 0 volt reference voltage with respect to VCC, and the output of the driver 21 is connected to the output port 104. The two impedance enabling 218 are connected to the collector of the transistor 212 and the first terminal of the rising resistor 214, the second terminal of the rising resistor is connected to VCC, and the base of the transistor 212 is connected to the first terminal of the pull-down resistor 2 1 6 and The first end of the optical crystal 2 2 0 in the optical isolator 11 〇. The second terminal of the pull-down resistor 216 is connected to LG, the second terminal of the phototransistor 220 is connected to VCC, and the emitter of the transistor 21 2 is connected to LG. The second buffer area 114 includes a driving circuit 2 2 2 with a tri-state output. The input of the driving circuit 222 is connected to the reference voltage VCc, which preferably corresponds to a logic high, and the output of the driving circuit 2 2 2 is connected to the optical isolator 11. 6 LED224 anode 223, 咼 impedance enable input 228 is connected to input port ιβ, cathode 225 of leD224 is connected to one end of resistor 22 6 and the other end of resistor 226 is connected to LG. The fourth buffer area 118 includes a driving circuit 230 having a tri-state output, an npn bipolar transistor 2 3 2, a pull-up resistor 234, and a pull-down resistor 236. The input of the driver 2 3 0 is connected to LG 1 and the driver 2 3 0 The output is connected to the bidirectional port 102. The high-impedance enable 238 is connected to the collector of transistor 23 2 and the first end of rising resistor 234. The second end of rising resistor 234 is connected to VCC1. The transistor 2 3 2

548998 V. Description of the invention (8) The base is connected to the first end of the pull-down resistor 2 3 6 and the first end of the optoelectronic crystal 2 4 0 in the optical isolator 6. The second terminal of the pull-down resistor 2 3 6 is connected to 1 G1, the second terminal of the photoelectric crystal 2 4 0 is connected to V C C1, and the emitter of the transistor 2 1 2 is connected to 1 g 1. The first terminal of the second rising transistor 242 is connected to the bidirectional port 102, and the second terminal of the second rising transistor 242 is connected to VCC1. In the first mode, when the digital data enters the bidirectional port 102 and leaves the output port 104, the logic low level generates a voltage drop in the pull-up resistor 242, and enables the 咼 impedance state of the buffer 202. Although in a high-impedance state, no current flows into the LED 204, and the photo-crystal 220 is still off. Although the phototransistor 2 2 0 is still off, the transistor 212 is also off, and a negligible voltage drop is generated in the pull-up resistor 214, which in turn maintains the high-impedance enable 2 1 8 of the driving circuit 21 in the inactive state (logic (High), and the driver 2 is activated. The driving driver 2 10 drives 1 G (logic low) to the output 在 in its turn. Therefore, in the first mode, the logic low of the bidirectional port 102 causes the logic low at the output port. In the first mode, the logic high level of the bidirectional port 102 generates a negligible voltage drop on the pull-up resistor 242, and enables the high impedance of the driver 2 02 to be inactive si ', thus causing the driver 2 0 2 action. The actuating driver 203 drives VCC1 to the anode 203 of the output port 204 at its input, so it biases the LED 204 forward and causes it to emit light. The emitted light turns on the phototransistor 220, which in turn turns on the transistor 212. The turn-on of the transistor 212 generates a voltage drop in the rising resistor 214, which is large enough to enable the high-impedance enable 2 into 8 to actuate the driver. The rotation of 2 1 0 becomes a high impedance state. Therefore, in the first mode, the logic high of the bi-directional port input leads to the logic high at the output port 104. 1 mi page 13

I 11 A: \ PTA-203-2.ptd 548998 5. Description of the invention (9) State, the external rising resistance on the output port thus generates a logic high. In 1 in the second mode, when the digital data enters the input port 106 and leaves the bi-directional port 102, the logic low level is 傕 Suilun >, and the card P enables the high-impedance state of the buffer 2-22. Although the buffer area 222 is in the impedance state, the current does not flow into the led 224, and the photo-crystal 240 is still off. Phase phototransistor 24 () is still off, transistor 232 is also off, and a negligible voltage drop is generated in pull-up resistor 2 34, which in turn maintains the high-impedance enable 238 of the driving circuit 230 in a non-operational state (logic high The driver 2 3 0㈣. The driver 23, which operates, drives LG (logic low) to the bidirectional port 102 in the pot input. Therefore, in the second mode, the logic low of the input port 106 causes the logic at the bidirectional port 102. Low. In the first mode, the logic high level of the input port 1 0β makes the high impedance enable 206 of the driver 2 02 in a non-operation state, thereby causing the driver 22 2 to act. The driver 2 2 2 that operates The input drives VCC1 to the anode 2 23 of the LED 224, so the LED 224 is forward biased and causes it to emit light. The emitted light turns on the photo-crystal 240, which in turn turns on the transistor 232, and the conduction of the transistor 232 is in the rising resistance 234 again A voltage drop is generated, which is large enough to enable the high-impedance enable 238 to double into an action-like state, which changes the output of the driver 2 1 0 into a high-impedance-like dimension. The pull-up resistor 242 causes the high-impedance output of the driver 210 to become a logic-high state. , So in the second mode, The logic high of the input port 106 causes the logic high state of the bidirectional port 丨 02. In the third mode (ie, the idle state), the logic high state appears in the bidirectional 璋 1 0 2 and the input 璋 1 0 6 (ie, the idle state). It means that there is no data in the port. As described above, the logic high of the bidirectional port causes a high impedance state at the output port 104, while the logic high of the input port 106 causes a logic high at the bidirectional port port 102.

A: \ PTA-203-2.ptd Page 14 548998 V. Description of the Invention (ίο) The invention can be implemented in other specific forms without violating the spirit or basic characteristics of the invention, so the invention is to be regarded as The comprehensive description is not a limitation. The scope of the present invention is defined by the appended patent application scope, not the above description, and includes various changes with the same meaning and equivalent scope as the patent application scope.

A: \ PTA-203-2.ptd

Claims (1)

548998 6. Scope of patent application 1. A kind of one-way optical isolation circuit on a two-way port I2C transmission line, including ... Seeking, inputting, and communication between springs # a two-way port to communicate with the two-way port transmission line; an output The path includes (i) data from a first buffer, (2) —the first optical ps M ^ receiving output port of the two-way port, and (3), to P Tonglilang to receive the first buffer Output data and provide rotation data to an output port; one of the input paths of the pre-isolator output, including (丨) a third data, (2) — the first _ Benfeng one, receiving the input port output, brother one Light to the isolator to receive the second material, and (3) — the fourth buffer to receive the second shell material; the fourth beam of light to the isolator output The features provided by the four-level red zone of T / L are compatible with the I2C features. Then input data to the port. 2. If the application of the first item of the patent application scope is a logic high voltage vehicle road, in which when a logic high voltage level 11 is applied to the vehicle, the two-way port is corresponding. When applied to the input port, 雔 & $ has a voltage level that should be logic low 3 · ^ ^;! V t ^ should be a logic high voltage M, 隹, and proton isolation circuit, where when the pair-logic high is applied Voltage level quasi-force: when the two-way port is 'exited', that is, when the corresponding is applied to the two-way port, 钤 i and when the corresponding-logic low voltage level 4 is applied Low voltage level. The area includes-three states ;: the right two-study isolation circuit 'where the-buffer bidirectional port, (2)-has a (1) south impedance to make the input electrical connection to the wheeled electrical connection flj I electrical connection to The first optical isolator, and (3) — to a reference voltage corresponding to a logic high state. A: \ PTA ~ 203 ~ 2.ptd Page 16 548998 VI. Application for patent scope 5F The optical isolation circuit of item 1 of the patent scope. The r area of the Fuzhong flute includes-a three-state buffer and its construction and configuration. Second, 'Xianchong-the logic high state of the electric dust to the second buffer; :::: ,,,' the output of the Youba area is in the high impedance state, and when the first —: inch — sad corresponding to a logic high state When the voltage reaches the second buffer zone, the output from the separator, plus the red zone is in the corresponding-logic low state voltage. The output of the second buffer zone is electrically connected to the output port. So, and the three-state 6 "= filed for May patent | The first optical isolation zone of the item! Includes a three-state buffer with (1) a high-impedance four-buffer input port, and the ⑺-output is electrically connected to the second optical The input that is connected to the input is connected to a reference corresponding to a logic high state? Second, and ⑻-7. If the optical isolation circuit of the scope of application for item i of the patent application, the area includes a three-state buffer which is constructed and configured as the first: optical 4-: Add the corresponding-logic high state to the fourth buffering dagger :::: Isolator :, = The output of the punching zone is at a voltage corresponding to a logic high:-: = Isolator applies a high impedance state The wheel to the fourth buffer zone = brother: Shi,; the output of the red zone is at the corresponding-logic low state voltage level Γ and = the output of the evil buffer zone is electrically connected to the bidirectional port. Chun I2C transmission line and-to one-way transmission line to provide a two-way port isolation to communicate with the two-way port transmission line. =: Ϊ́ =, including the ⑴-the first-buffer to receive from the two-way port, 2, (2) —Brother—optical isolator to receive the first output data, and (3) a second buffer to receive the first optical isolator 548998 VI. Patented data and output data provided to an output port; Provide an input path, including (1) a third buffer to receive data output from the input port, (2) — the second optical isolator to Receive the data output from the third buffer, and (3) — the fourth buffer to receive the output from the second optical isolator, where the fourth buffer provides input data to the bidirectional port to make the characteristics of the input data and I 2 C Features are compatible. A: \ PTA-203-2.ptd Page 18