TW548532B - Electronic equipment and computer system - Google Patents

Electronic equipment and computer system Download PDF

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Publication number
TW548532B
TW548532B TW89113177A TW89113177A TW548532B TW 548532 B TW548532 B TW 548532B TW 89113177 A TW89113177 A TW 89113177A TW 89113177 A TW89113177 A TW 89113177A TW 548532 B TW548532 B TW 548532B
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Taiwan
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connector
signal
signals
terminal
patent application
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TW89113177A
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Chinese (zh)
Inventor
Ryoji Ninomiya
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Toshiba Corp
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Publication of TW548532B publication Critical patent/TW548532B/en

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  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

Signal wires corresponding to signals are connected to the connector terminals arranged in an upper row of the connector type #1 as shown in the corresponding figure. Signal wires corresponding to signals are connected to the connector terminals arranged in a lower row of the connector type #2. In this manner, by assigning the connector terminals of the same connector type a plurality of particular signals that must have the same delay amount, skews among the signals can be minimized.

Description

548532 A7 B7 五、發明說明(1 ) 發明的背景 本發明是關於兩者具快速序列介面之電子裝置與電腦 系統。 各種筆記型個人電腦(下文稱爲筆記P C )已經發展 成使用者輕易攜帶且使用電池運作。一些筆記P C被裝配 作爲爲了擴展它們的功能如需要時以擴充單元之安裝。爲 允許筆記P C主機有效地使用擴充單元的資源,連接筆記 P C主機之匯流排至擴充單元之匯流排是重要的。此匯流 排連接可使擴充單元匯流排上之裝置能夠類似於筆記P C 主機中之裝置被處理。 許多個人電腦使用P C I (周邊元件內接)匯流排, 因此,筆記主機與擴充單元係典型地經由設有具如P C I 匯流排的訊號線的群組之多的接腳之相接連接器之筆記 P C主機與擴充單元兩者之匯流排連接在一起而使兩 P C I匯流排可以完全地經由相接連接器連接在一起。 經濟部智慧財產局員工消費合作社印製 --------------摩 i I (請先閱讀背面之L意事項★填βι頁) 此組態,然而,爲裝配相接連接器需要大區域且因此 在減少尺吋與筆記P C主機的厚度上是一缺點。進一步, 筆記P C主機上之連接器裝配位置必需相容於擴充單元上 之接器裝配位置,而使在發展新產品中實際的外殼結構被 限制。 因此,爲經由快速序列介面連接P C I匯流排之技術 有成長的需要。快速序列介面可使筆記P C主機與擴充單 元能夠經由薄韌的序列纜線連接在一起。 然而,製作快速序列介面需要具約1 0倍於P C I匯 i紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ^ 548532 A7 B7 五、發明說明(2 ) 流排時脈的頻率高之高 送多個訊號於筆記p C 符合嚴格的條件是期待 必需維護,例如,在1 與擴充單元間之傳送, 要因爲各訊號係經由連 擴充單元經由纜線連接 通常,作爲連接器 或類似方面的方便決定 斜。這是因爲連接器的 具不同內部結構之端子 。如果訊號有低頻帶這 子結構的反玫果成長更 頻率時脈。因此,製作爲序列地傳 主機與擴充單元之間之系統,必需 的,訊號(歪斜)間之延遲之差異 OOP S以下。爲在筆記P C主機 在連接器周圍防止歪斜是特別地重 接器傳輸,其允許筆記P C主機與 在一起。 之訊號接腳指定典型地係根據製作 ,但對此方法是難以充分地防止歪 端子也許有不同的內部結構且因爲 有不同的接觸長度,電感,或電容 不是多不好,但隨增加頻帶不同端 加有意義。 請 先 閱 讀 背 之 注 項548532 A7 B7 V. Description of the invention (1) Background of the invention The present invention relates to an electronic device and a computer system with a fast serial interface. Various notebook personal computers (hereinafter referred to as notebook PCs) have been developed so that users can easily carry them and operate on batteries. Some notes PC are assembled as an expansion unit to expand their functionality if needed. In order to allow the notebook PC host to effectively use the resources of the expansion unit, it is important to connect the bus of the notebook PC host to the bus of the expansion unit. This bus connection enables the devices on the expansion unit bus to be processed similar to the devices in the notebook PC host. Many personal computers use a PCI (Peripheral Component Interconnect) bus. Therefore, a note host and an expansion unit typically take notes via a docking connector provided with a group of pins having a signal line such as a PCI bus. The buses of the PC host and the expansion unit are connected together so that the two PCI buses can be completely connected together via a docking connector. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -------------- Moi I (Please read the L notice on the back ★ Fill in β page) This configuration, however, is for assembly The connector requires a large area and is therefore a disadvantage in reducing the size and thickness of the notebook PC host. Further, the mounting position of the connector on the PC host must be compatible with the mounting position of the connector on the expansion unit, so that the actual housing structure is limited in the development of new products. Therefore, there is a growing need to connect the PCI bus through a fast serial interface. The fast serial interface allows the notebook PC host and the expansion unit to be connected together via a thin and flexible serial cable. However, the production of a fast serial interface needs to be about 10 times the size of the PCI paper. Applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) ^ 548532 A7 B7 V. Description of the invention (2) High frequency sends multiple signals to the note PC. Strict conditions are expected to be required for maintenance. For example, transmission between 1 and the expansion unit, because each signal is connected through the expansion unit through the cable is usually used as a connector. Or something similar for convenience. This is because the connectors have terminals with different internal structures. If the signal has a low-frequency sub-structure, the anti-rose fruit grows more clockwise. Therefore, to make a serial transmission system between the host and the expansion unit, it is necessary that the difference in delay between signals (skew) is less than OOP S. To prevent skewing around the connector on the note PC host is a special repeater transmission, which allows the note PC host to be together. The signal pin designation is typically based on production, but for this method it is difficult to fully prevent crooked terminals. Maybe they have different internal structures and because of different contact lengths, inductance, or capacitance are not so bad, but with increasing frequency band End addition makes sense. Please read the back note first

再 I 經濟部智慧財產局員工消費合作社印製 發明節要 本發明 的能力之快 爲達成 至少視端子 子之連接器 元之訊號傳 號接線,其 同的延遲量 在此電 的目的 速介面 此目的 結構差 ,一經 輸電路 中多個 建接至 子裝置 是提供適於製作由於訊號中使歪斜縮小 之電子裝置與電腦系統。 ,根據本發明之電子裝置包含一具分成 異而定之兩連接器類型之多個連接器端 由連接器傳輸多個訊號至與來自另一單 ,及--起 訊號的特別 同連接器類 中,考慮連 連接訊號電路與連接器之訊 的訊號之訊號接線必需有相 型的連接器端子。 接器的端子結構,快速訊號 本紙張尺度適用中國國家:標準(CNS)A4規格(210 X 297公釐) 548532 ,’ A7 B7 五、發明說明(3 ) (請先閱讀背面之注意事項再頁) 的特別的訊號必需有相同的延遲量連接至同連接器類型的 連接器端子。此組態在快速訊號中可以縮小化歪斜以穩定 地傳輸這些訊號至另一單元。 根據本發明的另一觀點,作爲多個特別的訊號之訊號 接線有這般的配線型樣其接線在具連接至那裡之各訊號接 線與訊號傳輸電路之間有配線長度的相同的値。在典型的 連接器中,不同的連接器類型的連接器端子被經常交替地 安排,但由使用上述的配線型樣以在訊號接線中設定相同 的配線長度,相同的配線長度可以輕易地設定作爲連接至 同連接器類型的連接器端子之訊號接線。 此外,如果多個訊號包括一群經由連接器傳輸至另一 單元之傳輸訊號與一群經由連接器接收自另一單元之接收 訊號,多個訊號最好分成該群傳輸訊號與該群接收訊號而 使一群傳輸訊號之訊號線係連接至第一連接器類型的連接 器端子,而一群接收訊號之訊號接線係連接至第二連接器 類型的連接器端子。此組態可以在傳輸訊號中與在接收訊 號中使歪斜最小化。 經濟部智慧財產局員工消費合作社印製 此外,如果訊號接線包括至少一序列地傳輸資料之資 料訊號線與一傳輸相當於時脈訊號之時脈訊號線,資料訊 號線與時脈訊號線最好係連接至相同的連接器類型的連接 器端子。 此組態可以在資料與時脈訊號間使歪斜最小化並致使 接收器正確地偵測使用時脈訊號之序列資料。此外,在此 案例中,該群傳送訊號之訊號接線係安排在印刷電路之層 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 548532 A7 B7 五、發明說明(4 ) 且該群接收訊號之訊號接線係安排在印刷電路之不同層以 輕易地設定該群傳送訊號之訊號接線與該群接收訊號之訊 號接線相同的配線長度。 根據進一步本發明的觀點,具包含多位元寬平行傳輸 路徑之匯流排之電腦系統有序列地傳輸在匯流排至外部單 元執行之交易的能力。該電腦系統包含··一具多個分成至 少兩視端子結構差異而定之連接器類型之連接器端子之連 接器’交易的傳輸需求之轉換資訊之平行/序列轉換單元 根據預定的序列轉換時脈自平行資料變成序列資料,一經 由連接器序列地傳輸序列資料與序列轉換時脈至另一單元 之訊號傳輸電路,及連接訊號傳輸電路與連接器在一起之 訊號接線,其中序列資料與序列轉換時脈之訊號接線係連 接至同連接器類型的連接器端子。 此組態透過快速序列轉換可以傳輸在匯流排之交易至 另一單元而使序列資料與序列轉換時脈間之歪斜最小化。 此外,如果平行地經由訊號接線序列地傳輸序列資料 之組態係應用於改進序列轉換效能,第一資料訊號接線, 第二資料訊號接線,及時脈訊號接線最好係連接至同連接 器類型的連接器端子。 根據本發明,在訊號中之歪斜可以最小化以製作快速 介面。特別地,由應用本發明至經由連接器把匯流排連接 在一起之序列介面,筆記P C主機與擴充單元可以經由薄 韌的序列纜線連接在一起。 本發明的額外的目的與優點將在隨後之描述提出,且 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 請先閱讀背面之汝意事項再 頁) 言 經濟部智慧財產局員工消費合作社印製 548532 A7 B7 五、發明說明(5 ) --------------裝--- (請先Η讀背面之·注意事項•再本頁) 自描述中在某種程度上將明顯,或也許由本發明的實施習 得。本發明的目的與優點也許特別地由下文指出之手段與 組合實現並獲得。 圖形的多種觀點的簡要描述 倂入與構成部分規格之附圖將舉例說明本發明的最佳 實施例,與上面給定的一般描述及下面給定的最佳實施例 的詳細描述一起,以解譯本發明的原理。 圖示1是展示根據本發明的一實施例使用在電腦系統 之第一訊號介面區間的組態之圖解; 圖示2 A與2 B是展示使用在實施例之連接器端子結 構之圖解; 圖示3是展示使用在實施例之連接器是如何的合適之 截面圖; ;線- 圖示4是展示使用在實施例之序列轉換控制器的組態 之方塊圖;以及 經濟部智慧財產局員工消費合作社印製 圖示5 /是展示根據實施例使用快速訊號介面之整個相 接系統之方塊圖。 主要元件對照 1 序列轉換控制器 0 a 印刷電路板(P c B ) 0 P C主機 2 連接器 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) :roz 548532 A7 B7 五、發明說明(6 ) 經濟部智慧財產局員工消費合作社印製 1 1 0 連 接 器 A 1 訊 Wi A 2 訊 號 A 3 訊 號 B 1 訊 號 B 2 訊 號 B 3 訊 號 C 1 連 接 器 類 型 # 1 的 端 子 C 2 連 接 器 類 型 # 1 的 端 子 C 3 連 接 器 類 型 # 1 的 端 子 D 1 連 接 器 類 型 # 2 的 端 子 D 2 連 接 器 類 型 # 2 的 端 子 D 3 連 接 器 類 型 # 2 的 端 子 1 〇 3 訊 號 接 線 1 〇 4 訊 號 接 線 1 0 5 訊 號 接 線 1 〇 6 訊 號 接 線 1 〇 7 訊 口— Wi 接 線 1 0 8 訊 號 接 線 2 0 3 連 接 器 類 型 # 1 端 子 2 0 5 絕 緣 基 底 2 0 2 適 合的 部 分 2 0 4 連 接 器 類 型 # 1 的 端 子 1 0 la 序列 轉 換 器 控制 器 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 548532 A7 B7 五、發明說明(7 ) 經濟部智慧財產局員工消費合作社印製 1 〇 lb 序 列 轉 換 器 控 制 器 1 P C I 匯 流 排 2 P C I 匯 流 排 3 0 1 P C I 介 面 區 間 3 0 2 傳 輸 緩 衝 區 3 0 3 平行 / 序 列 轉 換 電 路 3 a 4 平行 / 序 列 轉 換 電 路 3 〇 5 P L L 電 路 3 0 6 差 動 輸 出 緩 衝 丨品 3 0 7 差 動 輸 出 緩 衝 丨品 3 〇 8 差 動 輸 出 緩 衝 3 〇 9 差 動 輸 入 緩 衝 區 3 1 0 差 動 輸 入 緩 衝 3 1 1 差 動 輸 入 緩 衝 3 1 2 序 列 / 平 行 轉 換 電 路 3 1 3 序 列 / 平行 轉 換 電 路 3 1 4 P L L 電 路 3 1 5 接 收 緩 衝 區 A 1 訊 號 A 2 > 訊 Μ C 4 連 接 器 端 子 C 5 連 接 器 端 子 C 6 連 接 器 端 子 A 3 j 訊 號 --------------裝--- (請先閱讀背面之一注意事項,再ί®本頁: 訂: •踌· 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -1U - 548532 A7 B7 五、發明說明(8 ) D 4 連 接 器 類 型 # 2 的 端 子 D 5 連 接 器 類 型 # 2 的 端 子 D 6 連 接 器 類 型 # 2 的 端 子 B 1, 訊 號 B 2, 訊 號 B 3, 訊 □ eg Wl (請先閱讀背面之注 經濟部智慧財產局員工消費合作社印製 發明的詳細描述 本發明的實施例將於下面之圖形描述。 圖示1是展示根據本發明的一實施例使用在電腦系統 之第一訊號介面截面的組態。此電腦系統是一筆記型個人 電腦(p c )其中序列轉換控制器1 0 1製作在裝配在 p c主機1 〇 0當作系統板之印刷電路板上。 序列轉換控制器1 0 1經由連接器1 0 2傳輸與接收 多個快速序列訊號至且自外部單元。擴充單元爲一相接站 或類似物如需要爲了擴充P C主機的功能其可以經由纜線 連接至P C主機1 〇 〇。由連接在纜線上之連接器1 1 0 至PC主機1 〇〇的連接器1 02,PC主機1 0 0可以 使用在相接站之資源。 三訊號A 1至A3自序列轉換控制器1 0 1輸出以高 速操作且必需有相同的延遲量。三訊號B 1至B 3輸入至 序列轉換控制器1 0 1也以高速操作且必需有相同的延遲 量。 連接器1 0 2有多個連接器端子(接腳)。一特定的 意事項·再 裝 -co· 絲- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 548532 A7 B7 五、發明說明(9 ) (請先閱讀背面之注意事項再填一^頁> 連接器結構將在下面的圖示2A,2B,與3描述;連接 器1 02有多個連接器端子在連接器1 1 0適合於它的適 合位置中以兩垂直列排列。此外,在具連接至印刷電路板 (PCB)1 〇〇a之端子之連接器的一側上,連接器端 子的較高列自連接器以線導出,且連接器端子的較低列也 自那裡以線導出。 -在此案例,連接器端子的較高列與連接器端子的較低 列係循序地且交錯地排列,例如,以連接器端子的較高列 的第一,連接器端子的較低列的第一,連接器端子的較高 列的第二,連接器端子的較低列的第二,連接器端子的較 高列的第三,等等的次序。 經濟部智慧財產局員工消費合作社印製 在具這樣端子結構之連接器1 〇 2中,連接器端子的 較高列有不同於連接器端子的較低列的端子結構。此外’ 連接器端子的較高列有接觸長度’電感’與電容不同於連 接器端子的較低列的那些。連接器端子的較高列是同連接 器類型的(連接器類型#1的端子)’而連接器端子的較 低列是同連接器類型的(連接器類型# 2的端子)。在圖 示1中,Cl ,C2,與C3標示排列在較高列之連接器 類型#1的端子,而D1,D2 ’與D3標示排列在較低 列之連接器類型# 2的端子。 相當於訊號Al ’ A2 ’ A3之訊號接線10 3 ’ 1 04,1 〇 5係連接至如圖示所示之連接器類型#1的 端子(;1,02,〇3。相當於訊號31’82’ B3之 訊號接線1 〇 6 ’ 1 0 8 ’ 1 0 9係連接至如圖示所示之 丨本紙張尺度適用中國國家標準(CNS)A4規格⑽x 297公f~717 548532 A7 B7 五、發明說明(1〇 ) 連接器類型# 2的端子Dl ,D2 ,D3。以此方式,由 指定同連接器類型的端子必需有同延遲量之多個特別的訊 號,在訊號中之歪斜可以最小化。 此外,舉例說明的配線型樣被使用以排列作爲訊號 A 1,A2 ,A3 之訊號接線 103,104,105 而 使相同的配線長度設定在序列轉換控制器1〇1與連接器 1 Q 2的連接器端子間。也就是,具序列轉換控制器 1 01與對等之連接器端子間之最大距離之訊號接線 1 0 5係線性地排列如圖示所示,而訊號接線1 〇 3, 104係部分地彎曲以便有如訊號接線1〇5之相同的長 度。 舉例說明的配線型樣也被使用作爲訊號B 1 ,B 2, B 3之訊號接線1 0 6,1 0 7,1 0 8而使接線有相同 的長度。 印刷電路板(P C B ) 1 〇 〇 a有多層配線結構或雙 側的配線結構其中訊號接線1 0 6,1 0 7,1 0 8透過 女口圖示所示之透通孔配置在內層或背面之配線層。以此方 式,由配置作爲傳輸之訊號接線103,104 ,105 與作爲接收之訊號接線106,107,108在分離的 配線層,作爲傳輸之訊號接線103,104,1 05與 作爲接收之訊號接線1 0 6,1 0 7,1 〇 8不需使用如 也許導致歪斜之跳接接線之元件之相同的配線長度可以輕 易地設定。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之L意事項#*填Hi頁) 言 4v> 經濟部智慧財產局員工消費合作社印製 548532 A7 B7 五、發明說明(11 ) (連接器端子結構) 接下來,連接器1 0 2的連接器端子結構將於圖示2 A ,2 B與3中解釋。 圖示2 A槪要地展示連接器1 0 2的內部端子結構, 且圖示2 B如所見自連接器1 0 2的接腳的表面之排列如 何的適合於連接器1 1 0。圖示3是展示連接器1 〇 2與 連接器1 1 0在一起是如何的合適。 參考號碼2 0 3標示在適合於連接器1 1 〇之適合的 部分2 0 2中位於如圖示2 A所示之絕緣基底2 0 5的頂 部表面之連接器類型# 1的端子。參考號碼2 0 4標示在 適合於連接器1 1 0之適合的位置2 0 2中位於如圖示 2 A所示之絕緣基底2 0 5的底部表面之連接器類型# 2 的端子。連接器類型# 1的端子2 0 3與連接器類型# 2 的端子20 4在圖示2B中如所見之適合的部分2 02是 難以致信的,但在連接至P C B 1 0 0 a之端子區間中 ,這些端子係安排成線狀如圖示2 A所示。 在此案例中,位於適合的部分2 0 2較低側之連接器 類型#2的端子204筆直地自連接至PCB 100a 之端子區間向適合的部分2 0 2擴展,而位於適合的部分 2 02之較上側之連接器類型# 1的端子2 0 3在到達適 合的部分2 0 2之前彎曲且因此有較大於端子2 0 4之端 子長度,如圖示2A與3所見。所以,端子20 3與 2 04有不同的感應器成分或類似。 根據此實施例,訊號A 1至A 3在連接器1 0 2內有 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) --------I I I I · ^___ (請先閱讀背面之注意事項**填H頁: 如 δ,·. ;韙· 經濟部智慧財產局員工消費合作社印製 548532 A7 B7 五、發明說明(12 ) 相同的配線長度與配線條件,因此在訊號A 1至A 3中最 小化歪斜。同樣地,訊號B 1至B 3在連接器1 〇 2內有 相同的配線長度與配線條件,因此在這些訊號中最小化歪 斜。 (序列轉換控制器) _接下來,在圖示1中一使用接腳指定與訊號配線之系 統組態的特定範例將於圖示4與5中解釋。 PC主機1 00之PC I匯流排與相接站之P C I匯 流排假設使用快速位元序列介面連接在一起。圖示4展示 提供在P C主機1 〇 〇內側之序列轉換控制器的組態,且 圖示5展示整個相接系統的組態。 如圖示5所示,P C主機與相接站各別有序列轉換控 制器1 0 1 a ,1 0 1 b,而使交易透過序列轉換控制器 1 0 1 a與1 0 1 b間之序列轉換在P C I匯流排1與 P C I匯流排2間傳遞。因爲序列轉換控制器1 〇 1 a與 1 0 1 b本來有相同的組態,P C主機1 0 0之序列轉換 控制器的組態將於圖示4中描述。 如圖示4所示,P C主機1 0 0之序列轉換控制器 1 01(圖示5是101a)包含一PCI介面區間 3 01,一傳輸緩衝區302,平行/序列轉換電路 3 03,30 4,一 PLL電路3 05 ’差動輸出緩衝區 3 06,307,308,差動輸入緩衝區30 9 ’ 3 10,31 1,序列/平行轉換電路312,3 13, 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) ------------I -穿 i I {請先閱讀背面之注意事項再ιΛΡ本頁) 言· · 經濟部智慧財產局員工消費合作社印製 -ΊΟ- 548532 A7 B7 五、發明說明(13 ) 一 PLL電路3 1 4,一接收緩衝區3 1 5。 — — — — — — — — — — — — — - I I (請先閱讀背面之' 注意事巩再本頁) 序歹!1轉換控制器1 〇 1與連接器1 〇 2間之訊號接線 包括構成三對作爲傳輸之差動訊號接線與三對作爲接收之 差動訊號接線之1 2條訊號接線。 P C I介面區間3 〇 1傳輸並接收交易至與自各種連 接在PC主機1〇〇之pc I匯流排1之pc I裝置。資 訊如位址’命令’資料(唯讀),與位元組致使構成交易 從PC I匯流排之PC I裝置傳輸至相接站之PC I裝置 係經由傳輸緩衝區3 0 2傳輸至平行/序列轉換電路 3 0 3,3 0 4。 平行/序列轉換電路3 〇 3,3 0 4操作同步於具由 P L L電路3 0 5逐漸地增加之時脈頻率之快速序列轉換 時脈’以使用預定資料單元轉換構成自平行資料至序列資 料之交易之資訊。 在此案例中,構成交易之資訊分成兩區塊,其同時地 傳送至平行/序列轉換電路3 0 3,3 0 4以致使兩序列 資料序列地傳輸。 經濟部智慧財產局員工消費合作社印製 序列資料自平行/序列轉換電路3 0 3輸出被傳送至 連接器端子C1,連接器1〇2的C2當作訊號A1,由 差動輸出緩衝區3 0 6驅動之該對差動訊號線上之A 1’。 類似地,序列資料自平行/序列轉換電路3 0 4輸出被傳 送至連接器端子C 3,連接器1 0 2的C 4當作訊號A 2 ,由差動輸出緩衝區3 0 7驅動之該對差動訊號線上之 A 2,。 -Ιό- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 548532 A7 B7 五、發明說明(14 ) 藉由差動輸出緩衝區3 0 6,3 0 7平行於序列資料 轉換,來自P L L電路3 0 5之序列轉換時脈被傳送至連 接器102的連接器端子C5 ,連接器102的C6當作 訊號A3 ’由差動輸出緩衝區3 0 8驅動之該對差動訊號 線上之A 3’。連接器端子C 1至C 6都是連接器類型# 1 ,且訊號 A1 ,A1,,A2,A2,,A3,A3,都設有 相同的長度。 自在相接站側上之序列轉換控制器1 〇 1 b傳輸之兩 序列資料與時脈訊號經由都是連接器類型# 2之連接器 1 02的連接器端子D1至D6由三差動輸入緩衝區 3 09,31 0,311接收。也就是,第一序列資料( B 1 ’B1’) 由差動輸入緩衝區309接收,第二序列 資料(B2,B2’) 由差動輸入緩衝區310接收,且 相當於這些訊號資料之時脈爲差動輸入緩衝區3 1 1。訊 號B 1,B 1 ’,B 2,B 2 ’,B 3,B 3 ’之接線都設有 牛目同的長度。 由差動輸入緩衝區3 1 1接收之時脈訊號由P LL電 路3 1 4復原至由相接站側上之序列轉換控制器使用之原 先的序列轉換時脈。經復原的序列轉換時脈接著傳送至序 歹rJ/平行電路3 1 2,3 1 3當作因之運算時脈。第一序 歹[J資料與第二序列資料由序列/平行轉換電路3 1 2, 3 1 3轉換成平行資料,其然後經由接收緩衝區3 1 5傳 送至PCI介面區間301。該PCI介面區間3 01在 P C I匯流排1上執行交易。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閲讀背面 之注意事項再本頁: --弟 經濟部智慧財產局員工消費合作社印製 548532 A7 B7 五、發明說明(15 以此方式, 等時脈訊號線之 小化歪斜,因此 列介面以有效地 雖然,此實 側之連接器的配 器1 0 2 b確實 額外的優點 。所以,以發明 所示與所描述之 造不需分離自如 之一般發明觀 根據此實施例,作 資料線可以當作單 致使P C I匯流排 實現。 施例已經描述有關 線型樣,在圖示5 地使用相同的接腳 與修改將立即地發 較寬闊的觀點是不 個別的實施例。此 由附加的申請專利 念的精神或領域。 爲傳輸兩序列資料與對 元使用以在資料線間最 間之交易由使用快速序 於接腳指定與P C主機 相接站側上提供之連接 指定與配線型樣。 生於技藝中熟練的那些 限於特定的細節及在此 外,各種修改也許被製 範圍與它們的對等物定 請 先 閱 讀 背 意 事 項Re-I printed the invention section by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The ability of the present invention is to achieve at least the connection of the signal transmission signal of the connector element of the terminal. The same delay is described in the purpose of this electrical interface. The purpose of the structure is poor. Once the multiple connections to the sub-devices in the transmission circuit are provided, it is suitable to produce electronic devices and computer systems that reduce the distortion caused by the signal. The electronic device according to the present invention includes a plurality of connector ends divided into two different connector types. The connector transmits a plurality of signals to and from a single connector, and the signals from the same special connector type. , Consider the connection between the signal circuit and the signal of the connector, the signal wiring must have phase-type connector terminals. Connector terminal structure, fast signal This paper size applies to China: Standard (CNS) A4 specification (210 X 297 mm) 548532, 'A7 B7 V. Description of the invention (3) (Please read the precautions on the back first and then the page ) Special signals must be connected to the same connector type connector terminals with the same amount of delay. This configuration minimizes skew in fast signals to stably transmit these signals to another unit. According to another aspect of the present invention, the signal wiring as a plurality of special signals has such a wiring pattern that the wiring has the same wiring length between each signal wiring connected thereto and the signal transmission circuit. In typical connectors, the connector terminals of different connector types are often alternately arranged, but by using the above wiring pattern to set the same wiring length in signal wiring, the same wiring length can be easily set as Signal wiring to connector terminals of the same connector type. In addition, if multiple signals include a group of transmission signals transmitted to another unit via a connector and a group of reception signals received from another unit via a connector, the multiple signals are preferably divided into the group of transmission signals and the group of reception signals. A group of signal wires for transmitting signals are connected to the connector terminals of the first connector type, and a group of signal wires for receiving signals are connected to the connector terminals of the second connector type. This configuration minimizes skew in transmitted signals and received signals. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In addition, if the signal wiring includes at least one data signal line that transmits data in sequence and one clock signal line that transmits a clock signal, the data signal line and clock signal line are best. The connector terminals are connected to the same connector type. This configuration can minimize skew between the data and the clock signal and cause the receiver to correctly detect the sequence data using the clock signal. In addition, in this case, the signal wiring of the group transmission signal is arranged at the layer of the printed circuit. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 548532 A7 B7 V. Description of the invention (4) And the signal wiring of the group receiving signal is arranged at different layers of the printed circuit to easily set the same wiring length as the signal wiring of the group transmitting signal and the signal wiring of the group receiving signal. According to a further aspect of the present invention, a computer system including a multi-bit wide parallel transmission path has a computer system capable of sequentially transmitting transactions executed on the bus to an external unit. The computer system includes a parallel / sequence conversion unit that converts a plurality of connectors that are divided into at least two connector types depending on the structure of the terminals. The transaction information of the transmission requirements of the parallel / sequence conversion unit converts the clock according to a predetermined sequence. From parallel data to serial data, one serially transmits the serial data and serial conversion clock to another unit's signal transmission circuit through the connector, and the signal wiring connecting the signal transmission circuit and the connector together, where the serial data and serial conversion The clock signal wiring is connected to the connector terminals of the same connector type. This configuration minimizes the skew between the sequence data and the sequence conversion clock by transferring transactions on the bus to another unit through fast sequence conversion. In addition, if the configuration of transmitting serial data in parallel through the signal wiring is applied to improve the sequence conversion performance, the first data signal wiring, the second data signal wiring, and the time signal wiring are preferably connected to the same connector type. Connector terminal. According to the present invention, the skew in the signal can be minimized to make a fast interface. In particular, from the application of the present invention to a serial interface that connects the busbars together via a connector, the notebook PC host and the expansion unit can be connected together via a thin serial cable. Additional objects and advantages of the present invention will be presented in the following description, and this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Please read the intentions on the back before the page) Printed by the Consumer Affairs Cooperative of the Property Bureau 548532 A7 B7 V. Description of the invention (5) -------------- Installation --- (Please read the notes on the back side first, and then this page) It will be obvious to some extent from the description, or perhaps learned by the practice of the present invention. The objects and advantages of the present invention may be achieved and obtained in particular by means and combinations indicated below. A brief description of the various perspectives of the drawing, and the drawings of the constituent specifications will illustrate the preferred embodiment of the present invention, together with the general description given above and the detailed description of the preferred embodiment given below, to explain Translate the principles of the invention. Figure 1 is a diagram showing the configuration of a first signal interface section used in a computer system according to an embodiment of the present invention; Figures 2 A and 2 B are diagrams showing the structure of a connector terminal used in the embodiment; Figure 3 is a cross-sectional view showing how the connector used in the embodiment is suitable; Line-Figure 4 is a block diagram showing the configuration of the sequence conversion controller used in the embodiment; and staff of the Intellectual Property Bureau of the Ministry of Economic Affairs The consumer cooperative printed icon 5 / is a block diagram showing the entire interconnection system using the fast signal interface according to the embodiment. Comparison of main components 1 Sequence conversion controller 0 a Printed circuit board (P c B) 0 PC host 2 Connector This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm): roz 548532 A7 B7 V. Description of the Invention (6) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 1 0 Connector A 1 Signal Wi A 2 Signal A 3 Signal B 1 Signal B 2 Signal B 3 Signal C 1 Terminal C 2 for connector type # 1 Terminal C of connector type # 1 Terminal D of connector type # 1 Terminal D of connector type # 2 Terminal 2 of connector type # 2 Terminal D of connector type # 2 Terminal 1 of connector type # 2 〇3 Signal wiring 1 〇 4 Signal connection 1 0 5 Signal connection 1 〇6 Signal connection 1 〇7 Signal port—Wi connection 1 0 8 Signal connection 2 0 3 Connector type # 1 Terminal 2 0 5 Insulating base 2 0 2 Suitable part 2 0 4 Connection Type # 1 Terminal 1 0 la Serial converter controller This paper size is applicable to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 548532 A7 B7 V. Description of the invention (7) Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 1 〇 lb Sequence converter controller 1 PCI bus 2 PCI bus 3 0 1 PCI interface zone 3 0 2 Transmission buffer 3 0 3 Parallel / sequence conversion circuit 3 a 4 Parallel / sequence conversion circuit 3 〇5 PLL circuit 3 0 6 Differential output buffer 丨 Product 3 0 7 Differential output buffer 丨 Product 3 〇8 Differential input buffer 3 〇9 Differential input buffer 3 1 0 Differential input buffer 3 1 1 Differential input buffer 3 1 2 Sequence / Parallel Conversion circuit 3 1 3 Serial / parallel conversion circuit 3 1 4 PLL circuit 3 1 5 Receive buffer A 1 Signal A 2 > Signal M C 4 Connector terminal C 5 Connector terminal C 6 Connector terminal A 3 j Signal- ------------ -Packing --- (Please read one of the precautions on the back, and then this page:: : · This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -1U-548532 A7 B7 V. Description of the invention (8) D 4 terminal of connector type # 2 D 5 terminal of connector type # 2 D 6 terminal of connector type # 2 terminal B 1, signal B 2, signal B 3, signal □ eg Wl (Please read the note on the back for a detailed description of the invention printed by the Intellectual Property Bureau's Consumer Cooperatives of the Ministry of Economic Affairs. An embodiment of the present invention will be described in the figure below. Figure 1 shows a configuration of a first signal interface cross section used in a computer system according to an embodiment of the present invention. This computer system is a notebook personal computer (pc) in which the sequence conversion controller 101 is fabricated on a printed circuit board assembled on the pc host 100 as a system board. The serial switching controller 1 0 1 transmits and receives multiple fast serial signals to and from an external unit via a connector 102. The expansion unit is a docking station or the like. In order to expand the functions of the PC host, it can be connected to the PC host via a cable 100. From the connector 110 connected to the cable to the connector 102 of the PC host 100, the PC host 100 can use the resources of the connecting station. The three-signal A 1 to A 3 self-sequence conversion controller 1 0 1 output operates at high speed and must have the same amount of delay. The three signals B 1 to B 3 input to the sequence conversion controller 1 0 1 also operate at high speed and must have the same amount of delay. Connector 102 has multiple connector terminals (pins). A specific notice · reload-co · silk- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 548532 A7 B7 V. Description of the invention (9) (Please read the notes on the back first Fill in another ^ page > The connector structure will be described in the following diagrams 2A, 2B, and 3; connector 102 has multiple connector terminals in two suitable positions where connector 1 1 0 is suitable for it. In addition, on the side of the connector with the terminal connected to the printed circuit board (PCB) 100a, the higher column of the connector terminal is derived from the connector by a line, and the lower of the connector terminal The columns are also derived there by lines.-In this case, the higher columns of the connector terminals and the lower columns of the connector terminals are sequentially and staggered, for example, the first of the higher columns of the connector terminals, The order of the lower row of connector terminals, the second of the higher row of connector terminals, the second of the lower row of connector terminals, the third of the higher row of connector terminals, and so on. The Consumer Cooperatives of the Ministry of Intellectual Property Bureau printed on the connection with this terminal structure In connector 1 〇2, the upper column of the connector terminal has a terminal structure different from the lower column of the connector terminal. In addition, the higher column of the connector terminal has a contact length 'inductance' and capacitance different from the connector terminal Those in the lower column of the connector. The higher column of the connector terminal is the same connector type (terminal of connector type # 1) 'and the lower column of the connector terminal is the same connector type (connector type # 2 Terminal). In Figure 1, Cl, C2, and C3 indicate the terminal type of the connector type # 1 arranged in the higher column, and D1, D2 'and D3 indicate the connector type # 2 arranged in the lower column. The terminal is equivalent to the signal wiring of signal Al 'A2' A3 10 3 '1 04, 105. It is connected to the terminal (# 1, 02, 03) of connector type # 1 as shown in the figure. Signal connection of signal 31'82 'B3 1 〇 6' 1 0 8 '1 0 9 is connected to the picture as shown in the illustration 丨 This paper size applies the Chinese National Standard (CNS) A4 specification⑽ x 297 male f ~ 717 548532 A7 B7 V. Description of the invention (10) Terminals D1, D2, D3 of connector type # 2. In this way, by The terminals specifying the same connector type must have multiple special signals with the same amount of delay, and the skew in the signal can be minimized. In addition, the illustrated wiring pattern is used to arrange the signals as the signals A 1, A2, A3 Wiring 103, 104, 105 so that the same wiring length is set between the connector terminals of the sequence conversion controller 101 and the connector 1 Q 2. That is, the connector terminals of the sequence conversion controller 101 and the equivalent The maximum distance between the signal wires 105 is linearly arranged as shown in the figure, while the signal wires 105 and 104 are partially bent so as to have the same length as the signal wires 105. The exemplified wiring pattern is also used as the signal wiring of the signals B 1, B 2, and B 3 1 06, 10 7, 108, so that the wirings have the same length. The printed circuit board (PCB) 1 〇〇a has a multilayer wiring structure or a double-sided wiring structure in which the signal wiring 1 06, 1 07, 1 0 8 is arranged through the through hole shown in the female port icon on the inner layer or Wiring layer on the back. In this way, the wirings 103, 104, 105 for transmission signals and the wirings 106, 107, 108 for reception signals are arranged on separate wiring layers, and the wirings 103, 104, 105 for transmission signals are wired to the reception signals 1 0 6, 1 107, 108 can be easily set without using the same wiring length as components that may cause skewed jumper wiring. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the “I” on the back # * fill in the Hi page) 4v > Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 548532 A7 B7 V. Description of the invention (11) (connector terminal structure) Next, the connector terminal structure of the connector 102 will be explained in the drawings 2A, 2B and 3. Figure 2 A shows the internal terminal structure of connector 102, and Figure 2B shows how the arrangement of the pins on the surface of connector 102 is suitable for connector 110 as seen. Figure 3 shows how the connector 102 and connector 110 fit together. The reference number 2 0 3 indicates a terminal of the connector type # 1 on the top surface of the insulating substrate 2 0 5 shown in Fig. 2 A in a suitable part 2 0 2 suitable for the connector 1 1 0. The reference number 2 0 4 indicates the terminal of the connector type # 2 on the bottom surface of the insulating base 2 5 as shown in the figure 2 A in the suitable position 2 0 2 of the connector 1 1 0. The terminal 2 0 3 of connector type # 1 and the terminal 20 4 of connector type # 2 are shown in Figure 2B. The fitting portion 2 02 is unbelievable, but the terminal connected to the PCB 1 0 0 a In the section, these terminals are arranged in a line shape as shown in Figure 2A. In this case, the terminal 204 of the connector type # 2 on the lower side of the suitable section 2 0 2 extends straight from the terminal section connected to the PCB 100a to the appropriate section 2 0 2 and is located on the appropriate section 2 02 The terminal 2 0 3 of the connector type # 1 on the upper side is bent before reaching the suitable part 2 2 and therefore has a terminal length larger than that of the terminal 2 4, as seen in the figures 2A and 3. Therefore, terminals 20 3 and 20 04 have different sensor compositions or similar. According to this embodiment, the signals A 1 to A 3 have the paper size in the connector 102, which is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -------- IIII · ^ ___ (Please read the precautions on the back ** Fill in page H: such as δ, ..; 韪 · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 548532 A7 B7 V. Description of the invention (12) Same wiring length and wiring conditions, Therefore, the skew is minimized in the signals A 1 to A 3. Similarly, the signals B 1 to B 3 have the same wiring length and wiring conditions in the connector 102, so the skew is minimized in these signals. (Sequence conversion Controller) _ Next, a specific example of a system configuration using pin assignments and signal wiring in Figure 1 will be explained in Figures 4 and 5. PC I Bus and PC I Bus and Connection Station The PCI bus is assumed to be connected together using a fast bit sequence interface. Figure 4 shows the configuration of the sequence conversion controller provided inside the PC host 100, and Figure 5 shows the configuration of the entire connected system. As shown in Figure 5, the PC host and the docking station each have a sequence conversion control. 1 0 1 a, 1 0 1 b, and the transaction is transferred between the serial bus controller 1 0 1 a and 1 0 1 b between the PCI bus 1 and the PCI bus 2. Because the serial bus controller 1 〇1 a and 10 1 b originally have the same configuration. The configuration of the sequence conversion controller of the PC host 100 will be described in Figure 4. As shown in Figure 4, the sequence of the PC host 100 0 The conversion controller 1 01 (Figure 5 is 101a) includes a PCI interface section 3 01, a transmission buffer 302, a parallel / sequence conversion circuit 3 03, 30 4, and a PLL circuit 3 05 'differential output buffer 3 06 , 307, 308, differential input buffer 30 9 '3 10, 31 1, serial / parallel conversion circuit 312, 3 13, This paper size applies to China National Standard (CNS) A4 specification (210 X 297 public love)- ---------- I-Wear i I (please read the precautions on the back before reading this page) Words · · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-ΊΟ- 548532 A7 B7 V. Invention Explanation (13) A PLL circuit 3 1 4 and a receiving buffer 3 1 5. — — — — — — — — — — — — — — II (Please read the “Notes on the back” on this page first) Preface 歹! 1 Conversion controller 1 〇1 and connector 1 〇2 signal wiring includes It constitutes 12 pairs of three pairs of differential signal connections for transmission and three pairs of differential signal connections for reception. The PC interface section 301 transmits and receives transactions to and from various pc I devices connected to the pc I bus 1 of the PC host 100. Information such as address 'command' data (read-only), and bytes cause the transaction that constitutes the transaction from the PC I device of the PC I bus to the PC I device of the docking station to be transmitted to the parallel / Sequence conversion circuit 3 0 3, 3 0 4. The parallel / sequence conversion circuit 3 03, 304 operates synchronously with a fast sequence conversion clock having a clock frequency that is gradually increased by the PLL circuit 3 05 to convert from a parallel data to a sequence data using a predetermined data unit. Information about the transaction. In this case, the information constituting the transaction is divided into two blocks, which are simultaneously transmitted to the parallel / sequence conversion circuit 303, 304 so that the two sequences of data are transmitted serially. The output from the Intellectual Property Bureau employee consumer cooperative of the Ministry of Economic Affairs prints the serial data from the parallel / serial conversion circuit 3 0 3 and the output is transmitted to the connector terminal C1. The connector C2 of connector 102 is used as the signal A1 and the differential output buffer 3 0 6 drives A 1 'of the pair of differential signal lines. Similarly, the sequence data is transmitted from the parallel / sequence conversion circuit 3 0 4 to the connector terminal C 3, and C 4 of the connector 10 2 is used as the signal A 2, which is driven by the differential output buffer 3 0 7 For A 2 on the differential signal line. -Ιό- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 548532 A7 B7 V. Description of the invention (14) With the differential output buffer 3 0 6, 3 0 7 parallel to the sequence data Conversion, the sequence conversion clock from the PLL circuit 3 0 5 is transmitted to the connector terminal C5 of the connector 102, and C6 of the connector 102 is used as a signal A3 'the pair of differentials driven by the differential output buffer 3 0 8 A 3 'on the signal line. The connector terminals C 1 to C 6 are all connector type # 1, and the signals A1, A1,, A2, A2,, A3, A3 are all provided with the same length. The two serial data and clock signals transmitted by the serial conversion controller 1 on the side of the docking station are both connector types D2 to D6 of connector 02 of connector type # 2, which are buffered by three differential inputs. Area 3 09,31 0,311 received. That is, the first sequence data (B 1 'B1') is received by the differential input buffer 309, and the second sequence data (B2, B2 ') is received by the differential input buffer 310, which is equivalent to the time when these signal data Pulse is differential input buffer 3 1 1. The wirings of the signals B1, B1 ', B2, B2', B3, B3 'are all provided with the same length. The clock signal received by the differential input buffer 3 1 1 is restored by the P LL circuit 3 1 4 to the original sequence conversion clock used by the sequence conversion controller on the connected station side. The restored sequence conversion clock is then transmitted to the sequence JrJ / parallel circuit 3 1 2 and 3 1 3 as the operation clock. The first sequence 歹 [J data and the second sequence data are converted into parallel data by the serial / parallel conversion circuits 3 1 2 and 3 1 3 and then transmitted to the PCI interface interval 301 via the receiving buffer 3 1 5. The PCI interface zone 3 01 executes transactions on the PCI bus 1. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the notes on the back before printing on this page:-printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 548532 A7 B7 Explanation (15 In this way, the miniaturization of the isochronous signal line is skewed, so the column interface is effectively although, the adapter 1 0 2 b of this real side connector does have additional advantages. Therefore, as shown in the invention and all The general concept of the invention does not need to be separated. According to this embodiment, the data line can be regarded as a single PCI bus implementation. The embodiment has described the line style, using the same pins and modifications in Figure 5 will be Immediately broader perspective is not an individual embodiment. This is based on the spirit or field of additional patent application concepts. For the transmission of two sequences of data and the use of counterparts for the most inter-transaction between data lines, the use of fast order to connect Pin assignments are provided on the station side for connection to the PC host. Connection assignments and wiring patterns are provided. Those skilled in the art are limited to specific details and in addition, various modifications may System range and their peers were given back please first read meaning matters

I 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -18 -I Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized to the Chinese National Standard (CNS) A4 (210 X 297 mm) -18-

Claims (1)

A8B8C8D8 548532 六、申請專利範圍 1·—種電子裝置包含: 第一連接器端子; 具不同於第一連接器端子之端子結構之第二連接器端子; —經由第一與第二連接器端子傳輸多個訊號之訊號傳輸電 路;以及 連接訊號傳輸電路及第一與第二連接器端子之訊號接 線:其中 具預定延遲量或更少之多個訊號的特定某些訊號接線 係連接至第一連接器端子。 2 ·根據申請專利範圍中第1項之電子裝置,其中多 個特定的訊號之訊號接線具有一接線圖樣,使得在該第一 連接器端子與該訊號傳輸電路之間具有相同的配線長度値 〇 3 ·根據申請專利範圍中第1項之電子裝置,其中多 個訊號包括一群經由第一連接器端子傳輸至另一單元之傳 輸訊號與一群經由第二連接器端子接收自另一單元之接收 訊號,以及 一群傳輸訊號之訊號接線連接至第一連接器端子,而 —群接收訊號之訊號接線連接至第二連接器端子。 4 .根據申請專利範圍中第1項之電子裝置,其中一 群傳輸訊號之訊號接線係建構在印刷電路板之層上以及一 群接收訊號之訊號接線係建構在其不同的層上。 5 .根據申請專利範圍中第1項之電子裝置,其中訊 號接線包括至少一序列傳輸資料之資料訊號線與傳輸對應 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -19 - —14 ^ (請先閲讀背面之注,意事項#.填: 言 經濟部智慧財產局員工消費合作社印製 548532 A8B8C8D8 經濟部智慧財產局員工消費合作社印製 夂、申請專利範圍 時脈訊號之時脈訊號線,以及 該資料訊號線與時脈訊號線係連接至第一連接器端子 〇 6·—種具包含多位元寬平行傳輸路徑之匯流排之電 腦系統’該電腦系統序列地傳送在匯流排執行之交易至另 一單元,該電腦包含: -第一連接器端子; 具不同於第一連接器端子之端子結構之第二連接器端子; 平行/序列轉換機構·作爲根據預定的序列轉換時脈 轉換自平行資料變成序列資料之交易的傳輸所需要之資訊 一經由第一與第二連接器端子傳輸多個訊號之訊號傳輸電 路;以及 連接訊號傳輸電路及第一與第二連接器端子之訊號接 線’其中具預定延遲量或更少之多個訊號的特定某些訊號 接線係連接至第一連接器端子。 7 ·根據申請專利範圍中第6項之系統,其中訊號接 線有第一資料訊號接線與第二資料訊號接線作爲經由兩訊 號接線而平行將該序列資料序列傳輸,以及 該第一資料訊號接線,該第二資料訊號接線,與作爲 傳輸該序列傳送時脈之該時脈訊號係連接至第一連接器端 子。 8 ·根據申請專利範圍中第1項之電子裝置,其中第 一與第二連接器端子係相依於第一與第二連接器端子的接 (請先閲讀背面之注意事項再 頁: I ί-------- 言 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公漦) •20- 548532 A8 B8 C8 D8 六、申請專利範圍 觸長度。 9·根據申請專利範圍中第1項之電子裝置,其中第 一與第二連接器端子係相依於第一與第二連接器端子的電 感。 1 〇 ·根據申請專利範圍中第1項之電子裝置,其中 第一與第二連接器端子相依於第一與第二連接器端子的電 容。 1 1 ·根據申請專利範圍中第1項之電子裝置,其中 第一與第二連接器端子相依於第一與第二連接器端子的彎 曲結構。 12·—種電子裝置包含: 建構成兩列之多個連接器端子之連接器; 經由連接器傳輸多個訊號至與自另一單元之訊號傳輸 電路;以及 將該訊號傳輸電路與該連接器連接在一起之訊號接線 ,其中 必需有相同的延遲量之多個訊號的特定某些個訊號接 線係連接至建構在兩列其中之一之連接器端子。 請先閲讀背面之注意事項再 頁) 經濟部智慧財產局貝工消费合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)-21 ·A8B8C8D8 548532 6. Scope of patent application 1. An electronic device includes: a first connector terminal; a second connector terminal having a terminal structure different from that of the first connector terminal;-transmission via the first and second connector terminals Signal transmission circuits for multiple signals; and signal wiring connecting the signal transmission circuits and the first and second connector terminals: certain certain signal wirings in which a plurality of signals with a predetermined delay or less are connected to the first connection Device terminals. 2 · According to the electronic device of the first item in the scope of the patent application, the signal wiring of a plurality of specific signals has a wiring pattern so that the same wiring length is provided between the first connector terminal and the signal transmission circuit. 3. The electronic device according to item 1 in the scope of the patent application, wherein the plurality of signals include a group of transmission signals transmitted to the other unit via the first connector terminal and a group of reception signals received from the other unit via the second connector terminal The signal wiring of a group of transmission signals is connected to the first connector terminal, and the signal wiring of a group of receiving signals is connected to the second connector terminal. 4. According to the electronic device of item 1 in the scope of the patent application, a group of signal wirings for transmitting signals is constructed on the layer of the printed circuit board and a group of signal wirings for receiving signals is constructed on different layers. 5. The electronic device according to item 1 in the scope of the patent application, wherein the signal wiring includes at least one sequence of data transmission lines and transmission corresponding to this paper standard applicable to China National Standard (CNS) A4 specification (210 X 297 mm)- 19-14 ^ (Please read the note on the back, meaning item #. Fill in: Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs, printed by 548532 A8B8C8D8 Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs, signal of patent application scope The clock signal line, and the data signal line and the clock signal line are connected to the first connector terminal. 0 ··· A computer system with a bus including a multi-bit wide parallel transmission path. The computer system serially Transferring transactions performed on the bus to another unit, the computer contains:-a first connector terminal; a second connector terminal having a terminal structure different from the first connector terminal; a parallel / serial conversion mechanism The serial conversion clock converts the information required for the transmission of transactions from parallel data to serial data-via the first and second connectors A signal transmission circuit for transmitting a plurality of signals; and a signal wiring for connecting the signal transmission circuit and the first and second connector terminals, wherein certain certain signal wirings of a plurality of signals having a predetermined delay amount or less are connected to the first A connector terminal. 7 · The system according to item 6 in the scope of the patent application, wherein the signal wiring includes the first data signal wiring and the second data signal wiring as parallel transmission of the serial data sequence via the two signal wiring, and the first A data signal connection, the second data signal connection, and the clock signal that is used to transmit the sequence transmission clock are connected to the first connector terminal. 8 · According to the first item of the scope of the patent application, the electronic device, The first and second connector terminals are dependent on the connection of the first and second connector terminals (please read the precautions on the back and then the page: I ί -------- The paper size applies to Chinese national standards ( CNS) A4 specification (21〇X 297 cm) • 20- 548532 A8 B8 C8 D8 6. The length of the patent application scope. 9. The electronic equipment according to item 1 in the scope of patent application The first and second connector terminals are dependent on the inductance of the first and second connector terminals. 1 〇 According to the electronic device of the first item in the scope of the patent application, wherein the first and second connector terminals are dependent The capacitance of the first and second connector terminals. 1 1 According to the electronic device of the first item in the scope of the patent application, wherein the first and second connector terminals depend on the curved structure of the first and second connector terminals. 12 · —An electronic device includes: a connector configured to form two rows of connector terminals; transmitting a plurality of signals to and from a signal transmission circuit of another unit through the connector; and the signal transmission circuit and the connector Signal wires connected together, in which certain certain signal wires in which multiple signals of the same amount of delay are required are connected to connector terminals constructed in one of two rows. Please read the precautions on the back before printing.) Printed by Shelley Consumer Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs. This paper is sized according to China National Standard (CNS) A4 (210 X 297 mm) -21 ·
TW89113177A 1999-07-07 2000-07-04 Electronic equipment and computer system TW548532B (en)

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US7861013B2 (en) * 2007-12-13 2010-12-28 Ati Technologies Ulc Display system with frame reuse using divided multi-connector element differential bus connector
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