TW544828B - System level package apparatus and its manufacturing method - Google Patents

Abstract

A kind of system level package apparatus and its manufacturing method are provided in the present invention, in which the package is performed sequentially on an integrated passive device (IPD) substrate. At first, the flip chip or wire bonding process is used to mount at least one active device on the first surface of the substrate and form the electric connection. Then, the placing ball process is conducted to form plural solder balls on the first surface of the substrate for mounting to the other electronic apparatus. At last, an encapsulant is formed to cover and protect the active device. In the invention, much more functions are integrated in the same package so as to improve its operation speed and function. In addition, the invention has the advantages such as small package size, increased function, high manufacture-speed and mass production capability.

Description

544828

The present invention relates to an integrated circuit assembly technology, and more particularly, to a system-in-a-package device and a manufacturing method thereof. Background of the invention: According to the advancement of integrated circuit technology, the trend of the level and function improvement of electronic products can be summarized as multifunctional, high-speed, large-capacity, high-altitude, and lightweight. In order to meet these needs, in addition to integrated In addition to the advancement of the open-loop process technology, many new construction technologies and materials have been developed, which are more ugly and small system production needs, and more sophisticated steps to reach the space to quickly close to the same speed. The package of high-density electronic system products is only more than the structure of the large // BGA or CSP, but it also has a group signal transmission function and a structure, such as inside, to increase the functionality of the newly-known electronic structure delivery. The faster the power, the more time the IC may need the product, and the new single small and thick enough to be combined, then deal with it. In addition to the V%, the competition is specially designed for the bloated crystal BGA with a single chip structure. Although technology can relieve the demand of I / 〇 溥, it is still a little insufficient to meet this demand. However, multiple chips need to be integrated in the mold, and even passive components are required for more functions to integrate power. The electronic structure for the role of delicate 1C protection, space telecommunications transmission quality and heat dissipation of the electronic structure to save the thin period, has become the number of pins compared to the BGA want to be included in a group to be rounded up to a limited transfer and mb Job. When it is heavier to improve the various functions of V. Invention Description (2); also because electricity "has begun to integrate capacitors to achieve = faster transfer speed, some electronic construction energy, and even to achieve higher 2 coupling ( de-coupling) is more integrated in the same structure, and the function of the body is normal. Several jc that need to cooperate closely are more sophisticated in the integration and function of multiple ICs. The patent No. 5,784,26 No. 1 Front cable < This type of module, such as the US patent No., is directly mounted on a substrate, and it is connected to at least one active semiconductor element. However, the module's assembly method and circuit Board-forming electricity does not integrate passive components together, but installs active components on the substrate. The module structure relies only on the benefits of the second-level system-level structure. Α,, only after filling the glue Pouting: It is not suitable to be used in the production of structural modules that are shipped separately. • Not only manufacturing = structure, but also no metal shielding (shleldlng) industry second-hand "heat, temperature, temperature structure, can not fully protect the function of each component on it shovel. Therefore, the present invention is aimed at solving the problems mentioned above. The system-level structure of all circuits on the IC and its manufacturing method are lacking. The purpose and summary of the invention with effective grams: The main object of the present invention is to provide a system-level manufacturing method thereof, which directly mounts a number of active components on a 121, integrated passive devices (IPcn). Passive # 反 卜 ， 而

There is no need to install additional passive components such as resistors, capacitors or inductors. The P multi-function is directly integrated in the same structure, making its speed and power ^ will be improved. Li Yue Dagger is more refined

Page 5, the description of the invention (3) The second of the fifth invention is to provide a system-level structure bud and its manufacturing method, which has both small structure size and increased efficiency: characteristics, and At the same time, it has a fast manufacturing speed and a stopping point for mass production. The present invention is a system-level assembly device that provides a kind of tools and a shielding thermal structure. The mosquitoes, mosquitoes, and vocalists said that in order to achieve the above-mentioned purpose, the system-level construction device for the M4 Ah Flute X Month was made in the evening. One of the passive π substrates has at least one main surface mounted to form an electrical connection with the substrate; an encapsulant system is located on the base surface and covers the active component; and a plurality; 1 meaning-surface to use the solder ball As an external contact. Another implementation of the present invention in the Haiji Province is in production: the law system first provides-integrates passive element substrates: = = set, its technology is installed with at least one master first using set crystals or wire shots' to Form the Fu Zhao # + work, carry out the orange type on the surface of the substrate, and then use the vacuum screen printing or dispensing; the implant, and — = colloid, so that it covers the active element ^ 1 by the specific Through the implementation of the examples and the attached buckets, ... Kuya is easy to understand the present invention, and the drawings are more illustrative, which is more effective. Purpose, technical content, characteristics and achieved ^ Drawing number description: ^ Integration passive Element (IPD) substrate 丄 z Passive element 16 forming bumps ^, an active element 20 lead second active element 22 package gel 544828 5. Description of the invention (4) 2 4 Fresh ball 28 Retaining wall 32 Hollow receiving substrate 36 Guide hole 2 6 Solder ball guide hole 34 Hollow ceramic substrate Detailed description: To integrate passive components such as capacitors or inductors directly to W: 'Integrate the surface of the passive element (I PD) substrate here' This achieves the integration of all the circuits and systems on the IC, and the construction. It can effectively overcome the lack of knowledge. Figure f is a schematic illustration of the first embodiment of the system-level configuration device of the present invention. The system-level configuration device includes an integrated passive component soil plate 1 0 above. A plurality of passive components 12 are formed, and the IPD soil plate Η has a first surface and a second surface, and has two active components on the first surface of the substrate ι0, such as a semiconductor wafer, a micro-electromechanical device, and the like. System I or radio frequency device, etc., the first active element 4 is a flip chip mounted on the first surface of the IpD substrate 10 by using a plurality of bumps 16; the second active element is electrically connected thereto;丨 8 uses a plurality of leads 2 0 to form an electrical connection with the I PD substrate 1 0 by wire bonding. Another sealant I colloid 2 2 is formed on the IPD substrate 1 10 by vacuum screen printing or dispensing. The surface to cover the first active element 14 and the second active element 18, the seal-peg colloid 22 can provide mechanical protection, and the elements 14, 18 are subjected to external forces (such as collision, dust, or water and gas temple J. Uncle., And a plurality of solder balls 24 are provided on the first of the IPD substrate 10 Surface,

Page 7 544828 V. Description of the invention (5) And the height of the solder ball 24 is higher than the encapsulation gel 22 as an external history connection. These solder balls 24 are used to mount on other electronic devices and form electrical connections. & The material of the integrated passive component substrate above is selected from the group consisting of Shi Xi, glass, high-resistance silicon and ceramics; it can also be a Micro Electromechanical System (MEMS) The type is a micro-optical electromechanical system (MOEMS) substrate. Soil 〆 In addition, on the first surface or the second surface of the integrated passive element substrate 10 Table 2 :: Yes-shield the metal ㉟ (not shown) to prevent foreign; magnetic interference. And on the second surface of the integrated passive component substrate, a heat dissipation structure can be formed by using a standard, which is a micro-radiation fin to enhance the heat dissipation effect of the device. In addition to the system-level assembly device shown in the first figure, the present invention also has ::: different implementation modes and patterns. % The second picture shows that it is the present invention; the second embodiment: The second implementation: Schematic®, the Fengshang colloid 22 can cover the r element, only the top part of the solder ball 24 is exposed, and the exposed two are added. Grind to make it equal to the encapsulant 22, and another set of solder balls 26 are mounted on the exposed solder balls 24, ^, ..., are external contacts. As shown in the third figure, the two form an electrical connection (made as a retaining wall uam) 28. When the surrounding of the sealing gel 22 is provided by using the supporting wall 28 to provide a closed two to two and then a limited range β; the rest of the structure and the first -Same picture: So

544828

= The fourth embodiment of the system-level installation device of the present invention is schematically illustrated: ^ No, the group of solder balls 24 can be installed on the second and second of the IPD substrate 10, and is electrically connected to the same, and installed. The second meaning of the IPD substrate 10 and the ball 24 are electrically connected to the first surface of the ipd substrate 10 using a number of vias 30. The fifth embodiment of the system, system, charger, and structure is shown in the fifth figure. This system-level assembly device is provided with a negative hollow receiving substrate of the same material around the first surface of the IPD substrate 10 32, which is mounted on the IPD substrate 10 using wafer bonding or other bonding technology, so that the first active element 14 and the second active element 18 are located on the first surface of the I pd substrate 10 and on the hollow receiving substrate 32 in the hollow region, and the encapsulation gel 22 covers the hollow receiving substrate "to completely cover the first active element 14 and the second active element 18; a plurality of solder balls 24 are provided on the surface of the hollow receiving substrate 32 and Form an electrical connection with the IpD substrate 10 to use the set of solder balls 24 to be mounted on other electronic devices and form an electrical connection. In addition, if the hollow receiving substrate 32 is the same material as the IPD substrate 1.0 In addition, ceramic substrates, printed circuit boards, flexible substrates, BT substrates, and FR-4 substrates can also be used; as shown in Figure 6, it is hollowed out directly on a whole ceramic substrate to form a hollow substrate. Area hollow ceramic substrate 34, The ceramic substrate 34 is provided with a guide hole 36 in the middle, so that the solder ball 24 is electrically connected to the IPD substrate 10 using the guide hole 36. Except for the hollow ceramic substrate 34 made of ceramic material, the rest of the structure is the same as the system level of the fifth figure. The construction device is the same, so it will not be described again. Now, the manufacturing method of the present invention will be described with reference to the structure shown in the first figure above. Please refer to FIGS. 7A to 7D, which are the preferred embodiments of the present invention.

544828 V. Description of the invention (7) Sectional cross-sectional view of each step of the gas system, charge, and garment structure; as shown in the figure, the manufacturing method includes the following steps: First, and No .: A / shown in the base plate 10 'It has a plurality of passive 412 :: side substrate 10 No.-the surface has been pre-shaped technology using a plurality of conductive bumps = two as shown in the first' Crystal ^ ^ bump μ Install the first active element 14 on one surface of the IPD substrate 10 and open and close it; and + surface adhere to the second active element: m; It uses a wire bonding method to dissipate the lead wire 20 to the music surface to form an electrical connection. Then, as in step 7, C κι 仏-^ ^-^ # ^ 2; # ^ 5 ^ IPDf10 surface to perform the packaging operation, ^ t t ^ 'on the first PD substrate 1G-encapsulating gel 22 coating two; true ：: After printing or dispensing method, '18, as shown in the seventh D drawing :, =: Move up: the 14 and the second active element 14, 18 are invaded by external forces. ΛΛ1Λ, avoid the active element as a contact 'To provide electrical connection to other devices. Substrate description: manufacturing method The integrated passive element per-configuration provided by the present invention enables the above-mentioned construction steps to be performed by the master. 'Each-the-assembly unit completes the order-the construction; ΐϊί I: seeking steps After the formation of the encapsulating colloid, each system is structured; Π is: cutting 1 is performed at the same time to produce many systems, so the yield can be effectively increased. Substrate Ϊ = pieces are directly installed on-integrated passive components ... " In addition to passive components such as women's resistance, capacitance or inductance, etc., page 10, 544828 5. Description of the invention (8), more functions can be directly integrated in the same structure Installed to make its speed and function more sophisticated. And because the present invention integrates all components in the same package, it has the characteristics of small package size and increased power, and also has the advantages of fast manufacturing speed and mass production. The above-mentioned embodiments are only for explaining the technical ideas and characteristics of the present invention. The purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. When the scope of the patent of the present invention cannot be limited, That is, any equivalent changes or modifications made in accordance with the spirit disclosed in the present invention should still be covered by the patent scope of the present invention. ,

Page 11 544828 Brief description of the drawings Description of the drawings: The first diagram is a schematic diagram of the first embodiment of the system-level assembly device of the present invention. The second figure is a schematic diagram of a second embodiment of the system-level construction device of the present invention. The third figure is a schematic diagram of a third embodiment of the system-level assembly device of the present invention. The fourth figure is a schematic diagram of a fourth embodiment of the system-level assembly device of the present invention. The fifth figure is a schematic diagram of a fifth embodiment of the system-level assembly device of the present invention. The sixth figure is a schematic diagram of a sixth embodiment of the system-level assembly device of the present invention. Figures 7A to 7D are cross-sectional views of the steps of the present invention in the steps of manufacturing a system-level assembly device. ,

Page 12

Claims (1)

544828 Table 2 to 3 sets of 4 sets of seals 5 whole porcelain 6 This gold applies for a patent scope of a system-level structural device, including: integrated passive component (IPD) substrate surface; ^ J active component, which is installed in The substrate forms an electrical connection; + the t-colloid is used to cover the main solder ball and is located on the first other electronic device of the substrate and forms an electrical phase as described in item 1 of the scope of patent application The glow ball can be mounted on the second connection of the substrate. 'As described in item 2 of the scope of the patent application, an electrical connection is formed on one surface of the group of solder balls on the second surface of the substrate. 'As described in item 1 of the scope of the patent application, the gel can cover the group of solder balls and the exposed surface of the glow ball to form the electrical material of the passive component substrate as described in item 1 of the scope of the patent application. It is selected from the group. 'Integrate the first surface layer of the passive element substrate as described in the first patent application scope. As described in item 1 of the scope of the patent application, the first and second surfaces of the substrate are provided with the first and second surfaces, and the moving elements; the surface is used to construct the surface to facilitate the system. Hierarchical structure: equipment ^ use complex derivative system level birch: | and have another group connection. System-level structure & silicon, glass, system-level structure: & or second surface-level system structure; and using the solder ball to install the split, where the substrate forms an electrical device, where the vias and the substrate Device, wherein the solder ball is installed in the device, wherein the high-resistance silicon and ceramic device is further provided with a shielding device, wherein Page 13 ----- 544828 VI. Patent application scope The second surface of the integrated passive component substrate can be formed more. 8. The system-level jn heat dissipation structure described in item 7 of the patent application scope uses etching or electroplating technology. Formed by: Shame placement, wherein the system heat dissipation structure as described in item 7 of the scope of the patent application is a micro-radiation fin. 10, the system, as described in item i of the patent scope of the system level structure, there is a pound around the packaging colloid. , Clothing set =: the active component is installed in a flip chip or wire way ~ ~ Zhiwei among the first $ Φ — * private; from A4 I set 12, as described in the scope of the patent application of the system level structure J active The element is selected from the semiconductor crystal [Micro-Electro-Mechanical System 2: Middle-loading 1 3. The system-level structure system described in item i of the scope of patent application: the first surface of the W substrate is formed by screen printing or dispensing. Cover the active component. 14. A method for manufacturing a system-level mounting device, comprising providing an integrated passive component substrate having a first surface ^ a second table, and mounting at least one active component board on the first surface of the substrate to form an electrical connection; T ^ and performing a ball-planting step, a plurality of solder balls are formed on the first surface of the substrate; vacuum screen printing is performed on the first surface of the substrate, so as to cover the cracked colloid 544828 The active component makes the solder ball protrude from the encapsulation gel as a contact point. 15 · The manufacturing method according to item 14 of the scope of patent application, wherein the active device is electrically connected to the substrate by using a plurality of conductive bumps. 1-6 · The manufacturing method as described in item 14 of the scope of patent application, wherein the active element is electrically connected by coupling leads to the first surface of the substrate by a wire bonding method. 17. The manufacturing method as described in item 14 of the scope of patent application, wherein the material of the integrated passive element substrate is selected from the group consisting of silicon, glass, high-resistance silicon, and ceramics. 18. The manufacturing method according to item 14 of the scope of patent application, wherein a shielding metal layer is further provided on the first surface or the second surface of the integrated passive element substrate. 19. The manufacturing method according to item 14 of the scope of patent application, wherein after the vacuum screen printing step, it further comprises forming a heat dissipation structure on the second surface of the integrated passive element substrate. 20. The manufacturing method according to item 19 of the scope of patent application, wherein the heat dissipation structure is formed by etching or electroplating technology. 2 1. The manufacturing method as described in item 19 of the scope of patent application, wherein the heat dissipation structure is a micro-heat-dissipating Korean body. 2 2 The manufacturing method described in item 14 of the scope of patent application, wherein the active element is selected from a semiconductor wafer, a micro-electro-mechanical system device or a radio frequency device. 2 3. A method for manufacturing a system-level assembly device, including the following steps: providing an integrated passive element substrate having a first surface and a second surface 544828 VI: Scope of patent application Surface, the integrated passive component substrate is provided with a plurality of structural units. On the substrate, at least one piece of the first surface of each structural unit is installed, which is in electrical contact with the substrate. In the ball step, a plurality of fresh balls are formed on the first surface of the substrate. Vacuum screen printing is performed on the first surface of the substrate, so that an encapsulating gel spoon reads the active element, and the solder ball is protruded from the encapsulating gel to As ^ overlay contacts; and ..., cutting is performed with each of the assembly units as a unit. 2 4 · The manufacturing method as described in item 23 of the scope of patent application, wherein the active device is electrically connected to the substrate by using a plurality of conductive bumps. 25. The manufacturing method as described in item 23 of the scope of patent application, wherein the active element is electrically connected by coupling wires to the first surface of the substrate by a wire bonding method. / 26. The manufacturing method according to item 23 of the scope of patent application, wherein the material of the integrated passive element substrate is selected from the group consisting of silicon, glass, high-resistance silicon and ceramics. 27. The manufacturing method as described in item 23 of the scope of patent application, wherein a shielding metal layer is further provided on the first surface or the second surface of the integrated passive element substrate. 28. The manufacturing method as described in item 23 of the scope of patent application, wherein after the vacuum screen printing step, a heat dissipation structure is further formed on the second surface of the integrated passive element substrate. 29. The manufacturing method as described in claim 28, wherein the heat dissipation structure is formed by etching or electroplating technology. Page 16 544828, patent application scope Moshi The manufacturing method as described in item 28 of the patent application scope, wherein the heat dissipation structure is a micro heat dissipation fin. As in the manufacturing method described in claim 23 of the patent scope, the active 70 pieces are selected from a semiconductor wafer, a micro-electro-mechanical system device or a radio frequency device. 32 A system-level assembly device, including:-an integrated passive component (IPD) substrate having a first surface and a second surface; a hollow receiving substrate located around the first surface of the integrated passive component substrate; at least one active A component that is mounted on the first surface of the integrated passive component substrate and is located in the hollow receiving substrate and is electrically connected to the integrated passive component substrate; a packaging gel that covers the active component; and The solder ball is located on the surface of the hollow receiving substrate and forms an electrical connection with the integrated passive component substrate, so as to use the solder ball to be mounted on other electronic devices and form an electrical connection. 3 3. The system-level assembly device described in item 32 of the scope of the patent application, in which 3 the material of the integrated passive component substrate is selected from the group consisting of silicon, glass, high resistance silicon and ceramics. 34. The system-level assembly device described in item 32 of the scope of the patent application, wherein the material of the hollow receiving substrate is selected from the group consisting of a ceramic substrate, a printed circuit board, a flexible substrate, a BT substrate, and a FR-4 substrate. . 35. The system-level assembly device according to item 32 of the scope of patent application, wherein a cover is further provided on the first surface or the second surface of the S-integrated passive component substrate. Page 17 544828 6. Scope of patent application Metal shielding layer. 36. The system-level structural device according to item 32 of the scope of patent application, wherein a heat dissipation structure can be further formed on the second surface of the integrated passive element substrate. 37. The system-level structural device according to item 36 of the scope of patent application, wherein the heat dissipation structure is formed by etching or electroplating technology. 38. The system-level structural device according to item 36 of the scope of application for a patent, wherein the heat dissipation structure is a micro heat dissipation fin. 39. The system-level mounting device according to item 32 of the scope of the patent application, wherein the at least one active component is mounted on the first surface of the integrated passive component substrate in a flip-chip or wire bonding manner. 40. The system-level structure device described in item 32 of the scope of patent application, wherein the active element is selected from a semiconductor wafer, a micro-electro-mechanical system device, or a radio frequency device. 4 1. The system-level assembly device described in item 32 of the scope of the patent application, wherein the encapsulant system is formed on the integrated passive element substrate by vacuum screen printing or screen printing and placed in a vacuum. Surface to cover the active element. Page 18