TW543290B - An circuit for amplifying the capacity - Google Patents

An circuit for amplifying the capacity Download PDF

Info

Publication number
TW543290B
TW543290B TW91101862A TW91101862A TW543290B TW 543290 B TW543290 B TW 543290B TW 91101862 A TW91101862 A TW 91101862A TW 91101862 A TW91101862 A TW 91101862A TW 543290 B TW543290 B TW 543290B
Authority
TW
Taiwan
Prior art keywords
capacitor
output
circuit
current mirror
input
Prior art date
Application number
TW91101862A
Other languages
Chinese (zh)
Inventor
Jing-Meng Liu
Kent Hwang
Cheng-Hsuan Fan
Chao-Hsuan Chuang
Original Assignee
Richtek Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Richtek Technology Corp filed Critical Richtek Technology Corp
Priority to TW91101862A priority Critical patent/TW543290B/en
Application granted granted Critical
Publication of TW543290B publication Critical patent/TW543290B/en

Links

Landscapes

  • Amplifiers (AREA)

Abstract

This invention provides a circuit for amplifying the capacity. It decreases charge current and discharge current of the capacitor through the ratio N of current mirror circuit input/current output to make the capacitor with small capacitance equivalent to the capacitor with large capacitance. Moreover, it can adjust the parameter of the ratio N of the current mirror circuit input/current output and choose appropriately the capacitor with small capacitance to achieve the preferred capacitance/capacitor volume ratio and to fit the needs of the volumetric restriction of the integrated circuit.

Description

543290 五、發明說明(1) 發明所屬之技術領域 本發明係有關於一種電容器,特別是有關於一種等效 放大電容電路裝置,此種等效放大電容電路裝置僅由小體 積與小電容值之電容器提供具大電容值之電容器特性之功 能者。 先前技術 按一般傳統的電容器,電容值的大小必會影響此電容 器體積的大小,電容值越大相對電容器體積相對增大,在 很多應用中尤其以積體電路之應用,電容器體積為設計積 體電路重要的考量關鍵,所以一般積體電路之電容器被限 制於數百Pico-Farads内,以達成積體電路體積之需求, 進而改善方法,如需較大電容值之電容器時,限於體積上 的考量以預留輸出接腳,外接的方式解決電容體積上的技 術問題,但往往受限於腳位的不足,或積體電路使用的容 易性來考量,此改進方式卻面臨到困難,如此現象實可進 一步改善以減少大電容值之電容器體積大之問題,對於成 本上與技術改良的考量,的確實有待相關業者善加改量 者。 發明内容 本案發明人乃以其多年從事電路設計相關領域與產品 之設計與改良,鑑於為達成減少大電容體積之理想特性, 而增加執行困難度與成本,實有積極研發其電路結構的必543290 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a capacitor, and more particularly to an equivalent amplifier capacitor circuit device. This equivalent amplifier capacitor circuit device consists only of a small volume and a small capacitance value. Capacitors provide the function of a capacitor with a large capacitance value. In the prior art, according to the conventional capacitors, the size of the capacitor will affect the size of the capacitor. The larger the capacitor value, the larger the capacitor volume. In many applications, the application of integrated circuits is especially important. Circuits are important to consider. Therefore, the capacitors of integrated circuits are generally limited to hundreds of Pico-Farads in order to meet the volume requirements of integrated circuits, and then improve the method. If a capacitor with a larger capacitance value is required, it is limited to the volume. Considering that the technical problems on the capacitor volume are solved by reserving output pins and externally, it is often limited by the lack of pins or the ease of use of integrated circuits. This improvement method faces difficulties, such a phenomenon. It can be further improved to reduce the problem of large capacitors with large capacitance values. For the consideration of cost and technical improvement, it is really necessary for the relevant industry to improve the quantity. SUMMARY OF THE INVENTION The inventor of this case has been engaged in the design and improvement of circuit design related fields and products for many years. In view of the ideal characteristics of reducing the volume of large capacitors and increasing the difficulty and cost of implementation, it is necessary to actively develop its circuit structure.

543290 五、發明說明(2) 要,乃積極研究改良,遂有本發明之開發。 即,本發明之主要目的,係在提供一種等效放大電容 電路裝置,此等效放大電容電路裝置係透過電流鏡電路輸 入/輸出電流比率為N之特性以降低電容器之充電與放電電 流,以達成小電容值之電容器等效為具大電容特性之電容 器功能者。 本發明之次要目的,係在提供一種等效放大電容電路 裝置,該等效放大電容電路裝置可調整電流鏡電路輸入/ 輸出電流比率為N之參數並適度選取小電容值之電容器, 以達成獲得較佳電容值/電容器體積比率之特性者。 實施方式 本發明一種等效放大電容電路裝置,其主要觀念係由 電容器電容值之特性C,當此電容值較大時充電的時間相 對增長,藉由此特性相對以小電容值之電容器將充電電流 依一定比例下降其充電電流,以減緩電流對於小電容值之 電容器的充電速度,當小電容值之電容器處於放電狀態 時,亦可依一定比例減少其放電電流,以減緩電流對於小 電容值之電容器的放電速度,即可達到以小電容值之電容 器等效為一定比例電容值放大之電容器,達到以小體積達 成大電容值之功能。 請參閱第一圖所示,本發明等效放大電容電路裝置具 有一輸出端及一輸入端101、102,俾連接一輸入控制電路 11、一第一電流鏡電路12、第二電流鏡電路13及一輸出電543290 V. Description of the invention (2) Yes, it is the active research and improvement that led to the development of this invention. That is, the main object of the present invention is to provide an equivalent amplifying capacitor circuit device. The equivalent amplifying capacitor circuit device is to reduce the charging and discharging current of a capacitor through the characteristic of the current mirror circuit input / output current ratio N. A capacitor that achieves a small capacitance value is equivalent to a capacitor function with large capacitance characteristics. A secondary object of the present invention is to provide an equivalent amplifier capacitor circuit device, which can adjust the parameter of the current mirror circuit input / output current ratio to N and appropriately select a capacitor with a small capacitance value to achieve Those who get better characteristics of capacitance value / capacitor volume ratio. Embodiments An equivalent amplification capacitor circuit device of the present invention is mainly characterized by the characteristic C of the capacitor capacitance value. When this capacitance value is large, the charging time is relatively long. Based on this characteristic, a capacitor with a relatively small capacitance value will be charged. The current decreases its charging current according to a certain ratio to slow down the charging speed of the capacitor with a small capacitance value. When a capacitor with a small capacitance value is in the discharging state, it can also reduce its discharge current by a certain ratio to slow down the current for a small capacitance value. The discharge speed of the capacitor can reach a capacitor with a small capacitance value equivalent to a capacitor with a certain proportion of capacitance value amplification, and achieve the function of achieving a large capacitance value with a small volume. Please refer to the first figure. The equivalent amplification capacitor circuit device of the present invention has an output terminal and an input terminal 101 and 102, and is connected to an input control circuit 11, a first current mirror circuit 12, and a second current mirror circuit 13. And an output

543290 五、發明說明(3) 容裝置14,使該輸出端^(^供輪出 帝 人端102供輸人充電電流值者 二具使該輸 銓屮她徨垃兮膂 ;士地而 。豕翰入控制電路1 1係以一 輸出鈿連接泫苐一電流鏡電路12輸入端於一 一輸出端連接該第二電流鏡電路13輸入端於一端點 另該輸入控制電路1 1之二輸入始1 為該輸入端102,該輸入控制電,該輸入端112 端m相連接。翰控f“路11之輸入端⑴與該輸出 5亥輸入控制電路1 1 ’係由一運瞀 XVI ^ΡΜ〇δθθθ M ^ # 22^ - NMO°S^ n # 2^1 =成二本發明該輸入端i 12分別與該運算放大器21負迴授 輸入确212連接、該PMOS晶體元仵22與該NMOS晶體元件23 之源極^目連接,該運算放大器21之—正迴授輸入端牛213 連接讜輸入端111,使該正迴授輸入端213與該輸出端1〇1 相連接,該運具放大器21之一輸出端21丨分別連接該pM〇s 晶體元件22閘極端與一準位調整電壓裝置24之端點24b, 並透過該準位調整電壓裝置24之端點24a與該NMOS晶體元 件23閘極端相連接,該pm〇s晶體元件22汲極端為該輸入控 制電路1 1 一輸出端為端點1 1 3,該輸出端端點1 1 3並與該第 一電流鏡電路12輸入端相連接,該襲08晶體元件23汲極端 為該輸入控制電路11另一輸出端為端點114,該輸出端端 點11 4並與該第二電流鏡電路丨3輸入端相連接。 該第一電流鏡電路12輪出端121與第二電流鏡電路13 輸出端131及該輸入控制電路n之輸入端1丨丨相連接,且形 成連通該輸出電容裝置1 4之一端點1 4 1,該連接點1 4 1連通543290 V. Description of the invention (3) Capacitor device 14 enables the output terminal ^ (^ for the wheel output of Teijin terminal 102 for the input of the charging current value of the person, so that the input terminal can be used only by her; The input control circuit 1 1 is connected with an output 钿 a current mirror circuit 12 input terminal is connected to the second current mirror circuit 13 input terminal at an output terminal and the other input control circuit 1 1 2 input terminal 1 is the input terminal 102, the input control circuit, and the input terminal 112 is connected to the m terminal. The input terminal of the han control f "circuit 11" and the output 5 input control circuit 1 1 'are run by XVI ^ ΡΜ 〇δθθθ M ^ # 22 ^-NMO ° S ^ n # 2 ^ 1 = In the present invention, the input terminal i 12 is respectively connected to the negative feedback input input 212 of the operational amplifier 21, the PMOS crystal element 仵 22 and the NMOS The source of the crystal element 23 is connected. The positive feedback input terminal 213 of the operational amplifier 21 is connected to the input terminal 111, so that the positive feedback input terminal 213 is connected to the output terminal 101. One output terminal 21 of the amplifier 21 is connected to the gate terminal of the pM0s crystal element 22 and the terminal 2 of a level adjustment voltage device 24, respectively. 4b, and is connected to the gate terminal of the NMOS crystal element 23 through the terminal 24a of the level adjustment voltage device 24. The drain terminal of the pMOS crystal element 22 is the input control circuit 1 1 and the output terminal is the terminal 1 1 3, the output terminal 1 1 3 is connected to the input terminal of the first current mirror circuit 12, the 08 crystal element 23 drain terminal is the input control circuit 11 the other output terminal is the terminal 114, the output terminal The terminal 11 4 is connected to the input terminal of the second current mirror circuit 丨 3. The first current mirror circuit 12 and the output terminal 121 of the second current mirror circuit 13 output terminal 131 and the input control circuit n input terminal 1丨 丨 are connected and form a terminal 1 4 1 connected to the output capacitor device 1 4, and the connection point 1 4 1 is connected

發明說明(4) 置該輪出端101;該運算放大器21比 213之輸出端1〇1電 丨卜°,二j與正迴授輸入端 5入端1 〇 2電壓與該輸出電容裝置14 ΐ i i 14 2之/點 輸出電容\ί 11 ί!效放大電容電路裝置處於對該 H !* 4充電或放電狀態,達成騸動嗲PMOS日垆开 件22$該NM0S晶體元件23之功能者。%動WM〇Saa體兀 藉由該輸入端1〇2輸入外部電壓’此外 行比^ i ^以電^透過輸人端1 1 1迴授到該輪人控制電路1 1 ·進 Πϊ;斷m放大電容電略裝置處於電容充 ,以適當驅動該第一電流鏡電路12與第二電 “ ί二一 J之功能者;當該第一電流鏡電路12被驅動時, 10 9^一疋適當比例降低該等效放大電容電路裝置10輸入端 輪^充電電流值;達到減緩充電電流對於該輸出電容 "/之充電時間之功能者;當第二電流鏡電路1 3被驅動 山’係以一定適當比例降低該等效放大電容電路裝置丨〇輸 出端1 〇 1放電電流值,達到減緩放電電流對於該輸出電容 ^,14之放電時間之功能者;該輸出電容裝置14係由微小 電容值之電容器1 42所組成,以達成減少電路體積之功能 者〇 、 本發明等效放大電容電路裝置,當輪入端102電壓高 於該輸出電容裝置14電容器142之端141電壓,該輸出電容 裝置1 4係處於充電狀態,該運算放大器2 1則將低輸出電壓 以驅動該PMOS晶體元件22並截止該NMOS晶體元件23,因該Description of the invention (4) Set the output terminal 101 of the wheel; the operational amplifier 21 is more than the output terminal 101 of 213 °, two j and the positive feedback input terminal 5 input terminal 102 voltage and the output capacitor device 14 ΐ ii 14 2 / point output capacitor \ ί 11 ί! The effective amplifier capacitor circuit device is in the state of charging or discharging the H! * 4 to achieve the function of the automatic PMOS sun opener 22 $ the NM0S crystal element 23 . % Motion WM〇Saa system inputs external voltage through this input terminal 102. In addition, the ratio ^ i ^ by electricity ^ is fed back to the wheel control circuit 1 1 through the input terminal 1 1. The m-amp capacitor capacitor device is in a capacitor charger to properly drive the functions of the first current mirror circuit 12 and the second electric circuit; when the first current mirror circuit 12 is driven, 10 9 ^ 1 is appropriate. Reduce proportionally the charging current value of the input terminal of the equivalent amplifier capacitor circuit device 10; achieve the function of slowing the charging current for the charging time of the output capacitor "/; when the second current mirror circuit 13 is driven A certain proportion of the equivalent amplification capacitor circuit device is reduced. The output current of the output terminal 1 is to reduce the discharge time of the output capacitor for the output capacitor ^, 14. The output capacitor device 14 is composed of a small capacitor value. The capacitor 1 42 is used to achieve the function of reducing the circuit volume. In the equivalent amplification capacitor circuit device of the present invention, when the voltage at the wheel-in terminal 102 is higher than the voltage at the terminal 141 of the capacitor 142 of the output capacitor device 14, the output capacitor Line 14 is set in a charging state, then a low output voltage 21 of the operational amplifier to drive the PMOS transistor element 22 is turned off and the NMOS transistor element 23, because of the

第10頁 543290 五、發明說明(5) ' PM0S晶體元件22導通,該輸入端1〇2電流經由 至該第一電流鏡電路12,該第一電流鏡電路12係\ 輸出電流比,為N/1之電流鏡電路所組成,該輸入端1〇2電 流以達到減湲N倍之電流值向該輸出電容裝置1 4進行充 電’以達到減緩充電電流對於該輸出電容裝置㊉ 間之功能者。 反之,當輸入端102電壓低於該輸出電容裝、置14電容 器142之端141電壓,該輸出電容裝置14係處於&放電狀%態, 該運算放大器2 1則將高輸出電壓透過該準位調整電壓^置 24電壓拉升以驅動該NM0S晶體元件23並截止該!>^晶^元 件2 2 ’因該N Μ 0 S晶體元件2 3導通,該輸入端1 〇 2電流經由 端點1 1 4輸入至該第二電流鏡電路1 3,該第二電流鏡電路 1 3係由輸入/輸出電流比率為Ν / 1之電流鏡電路所组成,該 輸出端1 0 1電流以達到減緩Ν倍之電流值由該輸出電容裝1 1 4進行放笔’以達到減緩放電電流對於該輪出電容裝置1 4 之放電時間之功能者。 " 以上係以分解動作式的行為模式說明,為使熟悉此項 技藝人士月匕更>月是瞭解’而將本發明建立整個電路為一個 負回授係統說明如下: 該準位調整電壓裝置24提供一個跨於節點24a和24b之 間的電位差Vab,且Vab必須大於該PMOS晶體元件2 2的起始 電壓絕對值加上該NMOS晶體元件2 3的起始電壓絕對值,即 Vab> | Vthp | + I Vthn | 。 如此該PMOS晶體元件22和該NMOS晶體元件23即可在正Page 10 543290 V. Description of the invention (5) 'The PM0S crystal element 22 is turned on, and the current at the input terminal 102 passes through the first current mirror circuit 12. The first current mirror circuit 12 \ output current ratio is N / 1 is composed of a current mirror circuit, and the input terminal 102 is charged to the output capacitor device 14 at a current value that is reduced by N times the current value of the output capacitor device 14 to reduce the charging current. . On the contrary, when the voltage at the input terminal 102 is lower than the voltage at the terminal 141 of the output capacitor device 14 and the capacitor 142 is set, the output capacitor device 14 is in the & discharge state, and the operational amplifier 21 passes the high output voltage through the standard. The bit adjustment voltage is set to 24 and the voltage is pulled up to drive the NMOS crystal element 23 and cut off the! > ^ Crystal element 2 2 'Because the N M 0 S crystal element 2 3 is turned on, the current at the input terminal 10 is input to the second current mirror circuit 13 through the terminal 1 1 4, and the second current mirror The circuit 1 3 is composed of a current mirror circuit with an input / output current ratio of N / 1. The output terminal 1 1 current can be reduced by N times the current value. The output capacitor 1 1 4 is used to release the pen. The function of slowing the discharge current for the discharge time of the wheel-out capacitor device 1 4. " The above is a description of the action mode of decomposition action, in order to make those skilled in this art more familiar with the month > the month is to understand the 'the entire circuit of the present invention as a negative feedback system is described as follows: The level adjustment voltage The device 24 provides a potential difference Vab across the nodes 24a and 24b, and Vab must be greater than the absolute value of the starting voltage of the PMOS crystal element 22 plus the absolute value of the starting voltage of the NMOS crystal element 23, that is, Vab > | Vthp | + I Vthn |. In this way, the PMOS crystal element 22 and the NMOS crystal element 23 can be

543290 五、發明說明(6) 常操作下同時導通,而使得整個電路被建立成由該運算放 大器2 1主導的一個負回授系統者。 既然負回授係統已建立,則該運算放大器2 1兩輸入端 212、213的電位會自動調整成同一電位值,亦即負迴授輸 入端212的電位會追隨正迴授輸入端213電位;而負迴授輸 入端2 1 2即是輸入點1 0 2,故可以說此電路輸入點1 0 2的電 位就等於電容1 4 2端點1 4 1的電位,但是從輸入點1 0 2充入 或放出的電流,卻經由電流鏡電路以一比例衰減成原來的 1/N才充入或放出電容142,如此從端點141看進去,就如 同看到一個N倍大於電容142的電容。 該電容值/電容器體積比率(電容值係指本發明等效 放大電容電路裝置之等效電容值;電容器係指電容器142 之體積),其係由該輸出電容裝置14之微小電容值之電容 器1 42 '該第一電流鏡電路1 2與該第二電流鏡電路1 3之輸 入/輸出電流比率N所決定,使用者可藉由適當節整得到所 需之電容值/電容器體積比率以符合積體電路體積限制之 需求者。 綜上所述本發明之等效放大電容電路裝置,此等效放 大電容電路裝置係透過電流鏡電路輸入/輸出電流比率為N 之特性以降低電容器之充電與放電電流,以達成小電容值 之電容器等效為具大電容特性之電容器,並可調整電流鏡 電路輸入/輸出電流比率為N之參數且適度選取小電容值之 電容器,以達成獲得較佳電容值/電容器體積比率,達成 符合積體電路體積限制之需求,該特性產生實用的功效具543290 V. Description of the invention (6) Simultaneous conduction under normal operation, so that the entire circuit is established as a negative feedback system dominated by the operational amplifier 21. Since the negative feedback system has been established, the potentials of the two input terminals 212, 213 of the operational amplifier 21 will be automatically adjusted to the same potential value, that is, the potential of the negative feedback input terminal 212 will follow the potential of the positive feedback input terminal 213; The negative feedback input terminal 2 1 2 is the input point 1 0 2, so it can be said that the potential of the input point 1 2 of this circuit is equal to the potential of the capacitor 1 4 2 terminal 1 4 1, but from the input point 1 0 2 The current charged or discharged is attenuated by the current mirror circuit at a ratio of 1 / N to charge or discharge the capacitor 142, so looking at the terminal 141 is like seeing a capacitor that is N times larger than the capacitor 142. . The capacitance value / capacitor volume ratio (capacitance value refers to the equivalent capacitance value of the equivalent amplification capacitor circuit device of the present invention; capacitor refers to the volume of capacitor 142), which is a capacitor 1 with a small capacitance value of the output capacitance device 14. 42 'The input / output current ratio N of the first current mirror circuit 12 and the second current mirror circuit 13 is determined. The user can obtain the required capacitance value / capacitor volume ratio by proper trimming to meet the product Demanders of bulk circuit volume constraints. In summary, the equivalent amplifying capacitor circuit device of the present invention, the equivalent amplifying capacitor circuit device is to reduce the charging and discharging current of the capacitor through the characteristic of the current mirror circuit input / output current ratio N to achieve a small capacitance value. The capacitor is equivalent to a capacitor with large capacitance characteristics, and the parameter of the current mirror circuit input / output current ratio is N, and a capacitor with a small capacitance value can be selected appropriately to achieve a better capacitance value / capacitor volume ratio and a consistent product. The requirement of the volume limit of the body circuit, this feature produces a practical power tool

第12頁 543290Page 543290

第13頁 543290 圖式簡單說明 為使 貴審查委員能便於瞭解本發明之目的、特徵及 功能獲致更進一步的瞭解茲舉一較佳實施實例,並配合圖 是如下: 第一圖係本發明第一較佳實施實例的電路結構示意 圖。 圖式標號說明 等效放大電容電路裝置…10 輸出端........................101 輸入端........................1 02 輸入控制電路...............11 端點...........................111 端點...........................112 端點...........................113 端點...........................114 第一電流鏡電路............12 輸出端........................121 第二電流鏡電路............13 輸出端........................131 輸出電容裝置...............14 端點...........................141 電容器........................142 運算放大器..................21 輸出端........................211Page 543290 The diagram is briefly explained in order to make it easier for your reviewers to understand the purpose, features, and functions of the present invention. Here is a preferred implementation example, and the accompanying diagram is as follows: The first diagram is the first diagram of the present invention. A schematic circuit diagram of a preferred embodiment. The figure numbers indicate the equivalent amplification capacitor circuit device ... 10 Outputs ... 101 Inputs ... ............... 1 02 Input control circuit ......... 11 End point ......... ......... 111 Endpoint ......... 112 Endpoint ... ............................................................................... .... 114 The first current mirror circuit ............ 12 Output terminal ............ 121 Second current mirror circuit ... 13 Output end ......... 131 Output capacitor device. ........ 14 End point ............... 141 Capacitor ... ..... 142 Operational Amplifier ..... 21 Output ... ........ 211

第14頁 543290Page 543290

第15頁Page 15

Claims (1)

543290 六、申請專利範圍 〜 j 1. 一種等效放大電容電路裝置,其主要係一輸入控制電路 一輸出端連接一第一電流鏡電路,另一輸出端連接一第二 電流鏡電路,該第一電流鏡電路與第二電流鏡電路輸出端 連接一輸出電容裝置,該連接點為該等效放大電容電路裝 置輸出端,該輸入控制電路一輸入端為該等效放大電容電 路裝置輸入端,另一輸入端與該等效放大電容電路裝置輸 出端連接;其主要特徵在於: 該輸入控制電路,係透過輸入端輸入之外部電壓與輸 出端端電壓比較後,以判斷該輸出電容裝置處於電容充電 或放電狀態,以適當驅動該第一電流鏡電路與第二電流鏡 電路,使執行輸入充電電流值、輸出端放電電流值之功能 者; 該第一電流鏡電路,係以一定適當比例降低該等效放 大電容電路裝置輸入端輸入充電電流值,達到減緩充電電 流對於該輸出電容裝置之充電時間之功能者; 第二電流鏡電路,係以一定適當比例降低該等效放大 電容電路裝置輸出端放電電流值,達到減緩放電電流對於 該輸出電容裝置之放電時間之功能者。 2. 如申請專利範圍第1項之裝置,其中該輸入控制電路係 由一運算放大器之負迴授輸入端與一 PM0S晶體元件、一 NM0S晶體元件之源級相連接,該運算放大器之正迴授輸入 端與該第一、二電流鏡電路之輸出端相連接,該運算放大 器輸出端分別連接該PM0S晶體元件閘極端,並透過一準位 調整電壓裝置與該NM0S晶體元件閘極端相連接;該PM0S晶543290 6. Scope of patent application ~ j 1. An equivalent amplifier capacitor circuit device, which is mainly an input control circuit, one output terminal is connected to a first current mirror circuit, and the other output terminal is connected to a second current mirror circuit. An output capacitor device is connected to a current mirror circuit and an output terminal of the second current mirror circuit. The connection point is the output terminal of the equivalent amplifier capacitor circuit device, and one input terminal of the input control circuit is the input terminal of the equivalent amplifier capacitor circuit device. The other input terminal is connected to the output terminal of the equivalent amplifying capacitor circuit device; its main characteristics are: the input control circuit is to determine whether the output capacitor device is in the capacitance after comparing the external voltage input through the input terminal with the output terminal voltage. Charge or discharge state to appropriately drive the first current mirror circuit and the second current mirror circuit to perform the functions of input charging current value and output terminal discharge current value; the first current mirror circuit is reduced by a certain appropriate ratio The charging current value is input to the input end of the equivalent amplification capacitor circuit device, which reduces the charging current. The function of the charging time of the output capacitor device; The second current mirror circuit is a function of reducing the discharge current value of the output terminal of the equivalent amplification capacitor circuit device by a certain proportion to achieve the function of slowing down the discharge time of the output capacitor device. . 2. For the device of the scope of patent application, the input control circuit is connected to the source stage of a PM0S crystal element and an NM0S crystal element by the negative feedback input terminal of an operational amplifier, and the positive return of the operational amplifier The input terminal is connected to the output terminals of the first and second current mirror circuits, and the output terminal of the operational amplifier is respectively connected to the gate terminal of the PM0S crystal element, and is connected to the gate terminal of the NMOS crystal element through a level adjustment voltage device; The PM0S crystal 第16頁 543290 六、申請專利範圍 體元件、NM0S晶體元件之汲極分別與該第一、二電流鏡電 路輸入端相連接。. 3. 如申請專利範圍第2項之裝置,其中該運算放大器比較 負迴授輸入端輸入之外部輸入電壓與正迴授輸入端之輸出 端電壓,以判斷處於對該輸出電容裝置充電或放電狀態, 達成驅動該PM0S晶體元件與該NM0S晶體元件之功能者。 4. 如申請專利範圍第3項之裝置,其中該PM0S晶體元件, 係當該輸出電容裝置處於充電狀態時,達成驅動該第一電 流鏡電路之功能者;該NM0S晶體元件,係當該輸出電容裝 置處於放電狀態時,達成驅動該第二電流鏡電路之功能 者。 5. 如申請專利範圍第2項之裝置,其中該準位調整電壓裝 置,係提供一足夠電位差使一對源極相連接之NM0S及PM0S 晶體元件可同時導通,以建立整個電路為一個負迴授系統 者。 6. 如申請專利範圍第1項之裝置,其中該第一電流鏡電路 係由輸入/輸出電流比率為N / 1之電流鏡電路所組成,以達 到減緩N倍該輸出電容裝置之充電電流之功能者。 7. 如申請專利範圍第1項之裝置,其中該第二電流鏡電路 係由輸入/輸出電流比率為N / 1之電流鏡電路所組成,以達 到減緩N倍該輸出電容裝置之放電電流之功能者。 8. 如申請專利範圍第1項之裝置,其中該輸出電容裝置係 由微小電容值之電容器所組成,以達成減少電路體積之功 能者。Page 16 543290 VI. Scope of patent application The drains of the body element and the NM0S crystal element are connected to the input terminals of the first and second current mirror circuits, respectively. 3. For the device in the scope of patent application, the operational amplifier compares the external input voltage input from the negative feedback input terminal with the output terminal voltage of the positive feedback input terminal to determine whether it is charging or discharging the output capacitor device. State, to achieve the function of driving the PMOS crystal element and the NMOS crystal element. 4. For the device in the third scope of the patent application, the PM0S crystal element is the one that drives the function of the first current mirror circuit when the output capacitor device is in the charging state; the NMOS crystal element is the output When the capacitor device is in the discharging state, it achieves the function of driving the second current mirror circuit. 5. For the device in the second scope of the patent application, the level adjustment voltage device provides a sufficient potential difference to allow a pair of source-connected NM0S and PM0S crystal elements to be turned on at the same time to establish the entire circuit as a negative loop. Granted by the system. 6. The device according to item 1 of the patent application scope, wherein the first current mirror circuit is composed of a current mirror circuit with an input / output current ratio of N / 1, so as to reduce N times the charging current of the output capacitor device. Functional person. 7. The device according to item 1 of the patent application scope, wherein the second current mirror circuit is composed of a current mirror circuit with an input / output current ratio of N / 1 to reduce the discharge current of the output capacitor device by N times. Functional person. 8. The device according to item 1 of the scope of patent application, wherein the output capacitor device is composed of a capacitor with a small capacitance value to achieve the function of reducing the circuit volume. 第17頁 543290 六、申請專利範圍 9.如申請專利範圍第1項或第6項或第7項或第8項之裝置, 其中該電容值/電容器體積比率係由該輸出電容裝置之微 小電容值之電容器、該第一電流鏡電路與該第二電流鏡電 路之輸入/輸出電流比率N所決定,使用者可藉由適當節整 得到所需之電容值/電容器體積比率之功能者。 1 0.如申請專利範圍第1項或第5項之裝置,其中該準位調 整電壓裝置使整個電路成為一個負回授系統,使此等效放 大電容電路輸入端的電位自動等於其内之微小電容器之端 點電位者。Page 17 543290 6. Application scope of patent 9. If the device of the scope of patent application is item 1 or 6 or item 7 or item 8, where the capacitance value / capacity volume ratio is determined by the small capacitance of the output capacitor device The value of the capacitor, the input / output current ratio N of the first current mirror circuit and the second current mirror circuit are determined, and the user can obtain the function of the required capacitance value / capacitor volume ratio through appropriate trimming. 10. The device of item 1 or item 5 in the scope of patent application, wherein the level adjustment voltage device makes the entire circuit a negative feedback system, so that the potential of the input terminal of the equivalent amplification capacitor circuit is automatically equal to a small amount within it. Capacitor terminal potential. 第18頁Page 18
TW91101862A 2002-02-01 2002-02-01 An circuit for amplifying the capacity TW543290B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW91101862A TW543290B (en) 2002-02-01 2002-02-01 An circuit for amplifying the capacity

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW91101862A TW543290B (en) 2002-02-01 2002-02-01 An circuit for amplifying the capacity

Publications (1)

Publication Number Publication Date
TW543290B true TW543290B (en) 2003-07-21

Family

ID=29729875

Family Applications (1)

Application Number Title Priority Date Filing Date
TW91101862A TW543290B (en) 2002-02-01 2002-02-01 An circuit for amplifying the capacity

Country Status (1)

Country Link
TW (1) TW543290B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8816760B2 (en) 2012-03-16 2014-08-26 Upi Semiconductor Corporation Capacitor amplifying circuit and operating method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8816760B2 (en) 2012-03-16 2014-08-26 Upi Semiconductor Corporation Capacitor amplifying circuit and operating method thereof

Similar Documents

Publication Publication Date Title
JP7520716B2 (en) Low Quiescent Current Load Switch
US9274537B2 (en) Regulator circuit
CN105700601B (en) A kind of LDO linear voltage regulators
TWI233543B (en) Fast-disabled voltage regulator circuit with low-noise feedback loop
JP6251316B2 (en) DC-DC converter using low starting power and voltage
JP5225876B2 (en) Power-on reset circuit
US20080218139A1 (en) Voltage regulator circuit and control method therefor
US11966245B2 (en) Voltage reference source circuit and low power consumption power supply system
TW200525868A (en) Power supply apparatus capable of supplying a stable converted voltage
TW200303704A (en) System and method for powering cold cathode fluorescent lighting
TWM422090U (en) Linear regulator and control circuit thereof
TW201222185A (en) Constant-voltage power supply circuit
TW201028814A (en) Method for improving power-supply rejection
CN113741610B (en) Reference voltage circuit and chip
CN114326890B (en) Voltage regulating circuit
CN115877905B (en) RC filter circuit and low dropout linear voltage regulator
TW543290B (en) An circuit for amplifying the capacity
JP3314226B2 (en) Semiconductor integrated circuit device
CN108829174B (en) Linear voltage regulator circuit
CN219018536U (en) Dual-power automatic switching circuit
CN109885122B (en) Current limiting circuit for low-voltage low-dropout LDO
US8872490B2 (en) Voltage regulator
US9229467B2 (en) Bandgap reference circuit and related method
TWI285470B (en) Input circuits including boosted voltages and related methods
CN108541309A (en) Low voltage difference stable-pressure device

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees