541661 五、發明說明（1) 本發明係有關於一種内嵌式記憶體邏輯電路，特別是 有關於一種應用於内嵌式記憶體邏輯電路之三度空間元件 結構及其製作方法。 在習知半導體製程技術中的内嵌式記憶體邏輯電路中 (Embedded-Memory Logic Circuit)是將邏輯（Logic)裝置 與記憶（Memory)裝置同時形成於一晶片上面，此種裝置亦 即所謂的内篏式半導體記憶裝置，例如E R A M ( E m b e d d e d Random Access Memory)裝置 。 但是，隨著積體電路的積集度日益增加，在同一晶片 上的記憶裝置與邏輯裝置混合設置，其彼此間會因製程上 和結構上之不同產生一高度落差值，造成插塞接觸孔深寬 比（aspect ratio)越來越大，無法符合目前内嵌式半導體 記憶體元件之的需求。 有鑑於此 提供一種應用於 構及 區及 高度 憶體 於一 狀矽 面， 表層 其製作方法 凸狀區，俾 差，降低插 為獲致上述 邏輯電路之 半導體矽基 島區，其中 而該凸狀矽 ，該氧化層 為了解決 内嵌式記 ，將記憶 以減少兩 塞接觸孔 之目的， 三度空間 材上定義 該第一凹 島區包括 位於該石夕 上迷問題，本發明主要目的在於 憶體邏輯電路之三度空間元件姓 體與邏輯電路係分別形成在= 個區域（記憶體與邏輯元件）間之 之深寬比。 本發明提出一種應用於内嵌式記 凡件之製作方法，其步驟包括， =，少一第一凹陷區與至少一凸 曰區底部露出該半導體矽基 層和氧化層，其中該石夕層^ 層跟該半導體石夕基材之間，形：541661 V. Description of the invention (1) The present invention relates to an embedded memory logic circuit, and more particularly to a three-dimensional space element structure applied to the embedded memory logic circuit and a manufacturing method thereof. The embedded-memory logic circuit in the conventional semiconductor process technology is a method in which a logic device and a memory device are formed on a chip at the same time. Such a device is also called a so-called Internal semiconductor memory devices, such as ERAM (Embedded Random Access Memory) devices. However, with the increasing degree of integration of integrated circuits, memory devices and logic devices on the same chip are mixedly set, and a height drop value will be generated between them due to differences in process and structure, resulting in plug contact holes. The aspect ratio is getting larger and larger, unable to meet the current needs of embedded semiconductor memory devices. In view of this, a method for fabricating a region and a highly memorable body on a silicon surface is provided. The surface layer is produced by a convex region, which has a low difference and is reduced to a semiconductor silicon-based island region that leads to the above logic circuit. Silicon, the oxide layer is used to solve the problem of embedded memory and to reduce the two plug contact holes. The third concave space defines the first concave island area including the problem of being located on the stone. The main purpose of the present invention is to remember The three-dimensional space element surname of the body logic circuit and the logic circuit are formed in the aspect ratio between the three areas (memory and logic element). The present invention proposes a method for manufacturing an embedded recording device. The steps include: = the semiconductor silicon-based layer and the oxide layer are exposed at the bottom of at least one first recessed area and at least one convex area, wherein the stone layer ^ Between the layer and the semiconductor Shi Xi substrate, the shape:
541661 五、發明說明（2) 至少一第一金氧半導體元件於該凹陷區上，形成至少一第 二金氧半導體元件於該凸狀矽島區上，全面性形成一第一 沈積層，實施一平坦化步驟於該第一沈積層，於該第一沈 積層定義出一第二凹陷區於該第一凹陷區上方，形成至少 一電容結構於該第二凹陷區，而該電容結構藉由一第一接 觸洞來連接於該半導體矽基材表面，全面性形-成一第二沈 積層，於該凸狀矽島區上方定義出一第二接觸洞，其中該 第二接觸洞底部露出該凸狀矽島區表面，且該第二接觸洞 開口位於該第二沈積層表面。 為獲致上述之目的，本發明提出另外一應用於内嵌式 記憶體邏輯電路之三度空間元件結構，包括有，一半導體 矽基材，在該半導體矽基材上定義出至少一第一凹陷區與 至少一凸狀矽島區，其中該第一凹陷區底部露出該半導體 石夕基材表面，而該凸狀石夕島區包括一石夕層和氧化層，其中 該矽層為表層，該氧化層位於該矽層跟該半導體矽基材之 間；一記憶體區，設置於該凹陷區上，包括至少一第一金 氧半導體元件於該凹陷區上，以及至少一電容結構和至少 一第一接觸洞；一邏輯電路區，設置於該凸狀矽島區上， 包括至少一第二金氧半導體元件和至少一第二接觸洞於該 凸狀矽島區上。 為使本發明之上述目的、特徵和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖示說明：541661 V. Description of the invention (2) At least one first metal-oxide-semiconductor element is formed on the recessed area to form at least one second metal-oxide-semiconductor element on the convex silicon island region, and a first deposition layer is comprehensively formed. A planarization step is on the first deposition layer, a second recessed area is defined on the first deposition layer above the first recessed area to form at least one capacitor structure in the second recessed area, and the capacitor structure is formed by A first contact hole is connected to the surface of the semiconductor silicon substrate, and a second deposition layer is comprehensively formed. A second contact hole is defined above the convex silicon island region, and the bottom of the second contact hole exposes the second contact hole. The surface of the convex silicon island region, and the second contact hole opening is located on the surface of the second deposition layer. To achieve the above object, the present invention proposes another three-dimensional space element structure applied to an embedded memory logic circuit, including a semiconductor silicon substrate, and at least one first depression is defined on the semiconductor silicon substrate. And at least one convex silicon island region, wherein the bottom of the first recessed region exposes the surface of the semiconductor stone substrate, and the convex stone island region includes a stone layer and an oxide layer, wherein the silicon layer is a surface layer, the An oxide layer is located between the silicon layer and the semiconductor silicon substrate; a memory region is disposed on the recessed region, and includes at least a first metal-oxide semiconductor device on the recessed region, and at least one capacitor structure and at least one A first contact hole; a logic circuit region disposed on the convex silicon island region, including at least a second metal-oxide semiconductor element and at least one second contact hole on the convex silicon island region. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows:
0503-7088twf ； TSMC2001-0929 ； Jerry.ptd 第5頁 541661 五、發明說明（3) 第1圖至第5圖係為本發明實施例形成應用於内嵌式記 憶體邏輯電路之三度空間元件之流程剖面示意圖。 第6圖係為本發明實施例形成應用於内嵌式記憶體邏 輯電路之三度空間元件之整體結構示意圖。 符號說明： 1 0〜半導體矽基材； 1 2〜第一凹陷區； 1 4〜凸狀矽島區； 1 6〜石夕層； 1 8〜氧化層； 20〜第一金氧半導體元件； 22〜第二金氧半導體元件； 24〜第一沈積層； 26〜第二凹陷區； 2 8〜電容結構； 3 0〜第一接觸洞； 32〜第二沈積層； 3 4〜第二接觸洞； 3 6〜記憶體區； 38〜邏輯電路區。 實施例： 本發明揭露一種應用於内嵌式記憶體邏輯電路之三度 空間元件之製作方法，其步驟包括，如第1圖所示，於一 半導體矽基材10上定義出至少一第一凹陷區12與至少一凸0503-7088twf; TSMC2001-0929; Jerry.ptd Page 5 541661 V. Description of the invention (3) Figures 1 to 5 are three-dimensional elements used in the logic circuit of the embedded memory according to the embodiment of the present invention Process flow diagram. Fig. 6 is a schematic diagram showing the overall structure of a three-dimensional space element applied to an embedded memory logic circuit according to an embodiment of the present invention. Explanation of symbols: 10 ~ semiconductor silicon substrate; 12 ~ first recessed area; 14 ~ convex silicon island area; 16 ~ shixi layer; 18 ~ oxide layer; 20 ~ first gold-oxide semiconductor element; 22 ~ second metal-oxide semiconductor element; 24 ~ first deposited layer; 26 ~ second recessed area; 28 ~ capacitive structure; 30 ~ first contact hole; 32 ~ second deposited layer; 3 ~ 4 ~ second contact Holes; 36 to memory area; 38 to logic circuit area. Embodiment: The present invention discloses a method for fabricating a three-dimensional space element applied to an embedded memory logic circuit. The steps include, as shown in FIG. 1, defining at least one first on a semiconductor silicon substrate 10. The recessed area 12 and at least one convex
0503-7088twf * TSMC2001-0929 ； Jerry.ptd 第6頁 541661 五、發明說明（4) 狀矽f區14 ’其申該 凹陷區! 材1 0表面，而哕几也 κ 口丨路出5玄丰導體矽基 其中該矽層16:表：矽島 包括—矽層16和氧化層18， 體石夕基材ίο之門該乳化層18位於該石夕層16跟該半導 為隔離絕緣。…其中該氧化層18為二氧化石夕層，用來作 該凹S ^ L圖上所二\形成至少-第-金氧半導體元件2〇於 半導體的電曰轉^中4第一金氧半導體元件20為ρ型金氧 一阳_或^^型金氧半導體的電晶體其中之一。形 hi - 氧半導體元件22於該凸狀矽島區上14，其 型S氧半導：的丨體元件22為ρ型*氧半導體的電晶體或Ν 生金軍L千V體的電晶體其中之一。 一坦圖/斤不\全面性形成一第一沈積層2 4，隨後實 ^ -氧化砂V二於该第一沈積層24，其中該第一沈積層24 為一戰化夕、鼠化矽和氮氧化矽其中之一，而 驟為化學機械式研磨法。 十-化y 如第4圖所示，於該第一沈積層24定義出一第二凹陷 區26於該第-凹陷區12上方（該第—凹陷區12在本圖中已 被該弟:沈積層24所填滿，故未標示於本圖中）。 如第5圖所示，形成至少一電容結構28於該第二凹陷 區26 (該第一凹陷區12在第4圖中已被該第一沈積層以所 填滿、，故未標示於本圖中），而該電容結構28藉由一第一 ，觸洞30來連接於該半導體矽基材丨〇表面，全面性形成一 第二沈積層32，於該凸狀矽島區14上方定義出一第二接觸 洞34 ，其中該第二接觸洞34底部露出該凸狀矽島區1 4表面0503-7088twf * TSMC2001-0929; Jerry.ptd Page 6 541661 V. Description of the invention (4) Shaped silicon f-zone 14 'It should be a recessed area! Material 1 0 surface, and a few of them are also κ mouth 丨 exit 5 Xuan The high-conductor silicon-based silicon layer 16: the silicon layer includes: a silicon layer 16 and an oxide layer 18, the gate of the body stone substrate; the emulsified layer 18 is located on the stone layer 16 and the semiconductor is isolated and insulated. … Wherein the oxide layer 18 is a layer of stone dioxide, which is used to form the concave S ^ L on the figure, forming at least a -first-metal-oxide semiconductor element 20 in the semiconductor circuit, the first metal-oxide 4 The semiconductor element 20 is one of the transistors of a p-type metal-oxide-metal oxide or a metal-oxide semiconductor. A shaped hi-oxygen semiconductor element 22 on the convex silicon island region 14 has a type S oxygen semiconductor: The body element 22 is a p-type * oxygen semiconductor transistor or an N-gold army L 1000V body transistor. one of them. A tangram / jinbu \ comprehensively forms a first deposition layer 24, and then oxidizes sand V2 to the first deposition layer 24, where the first deposition layer 24 is a battle chemical, siliconized silicon And silicon oxynitride, the chemical mechanical polishing method. As shown in FIG. 4, a second recessed area 26 is defined on the first deposition layer 24 above the first-recessed area 12 (the first-recessed area 12 has been used by the brother in this figure: The deposited layer 24 is filled, so it is not shown in this figure). As shown in FIG. 5, at least one capacitor structure 28 is formed in the second recessed area 26 (the first recessed area 12 has been filled with the first deposition layer in FIG. 4, so it is not marked in this (In the figure), and the capacitor structure 28 is connected to the surface of the semiconductor silicon substrate by a first, contact hole 30, and a second deposition layer 32 is formed comprehensively, which is defined above the convex silicon island region 14. A second contact hole 34 is formed, wherein the bottom of the second contact hole 34 exposes the surface of the convex silicon island region 14.
541661 五、發明言兒明（5) 於該第二沈積層32 觸洞3 4為填充導電 用於内嵌式記憶體 如弟6圖所示，包 矽基材1 0上定義出 區1 4，其中該第一 面，而該凸狀矽島 矽層1 6為表層，該 材1 0之間，其中該 絕緣。 上，包括至少一第 以及至少一電容結 一金氧半導體元件 半導體的電晶體其 ㈣1該第二接觸洞34開口位 的表面，其中該第一接觸洞3 〇和第二 金屬材料。 至少 第 依據上述製造方法，製作而得之應 邏輯電路之三度空間元件，其主要結才i 括有，一半導體矽基材，在該半導體 凹陷區1 2與至少一凸狀矽島 凹陷區1 2底部露出該半導體矽基材丨〇表 區14包括一矽層16和氧化層18，其中該 氧化層1 8位於該矽層丨6跟該半導體石夕基 乳化層18為一氧化石夕層，用來作為隔離 一記憶體區3 6，設置於該凹陷區i 2 一金氧半導體元件20於該凹陷區12上， 構2 8和至少一第一接觸洞3 〇，其中該第 20為P型金氧半導體的電晶體或n型金氧 中之一。 一邏輯電路區38，設置於該凸狀矽島區14上，包括至 少一第二金氧半導體元件22和至少一第二接觸洞34於該凸 狀石夕島區14上’其中該第二金氧半導體元件22為？型金氧 半導體的電晶體或N型金氧半導體的電晶體其中之_。 利用本發明的方法所形成的應用於内嵌式記憶體邏輯 電路之三度空間元件，其中由於邏輯電路區是以s〇I( Silicon On Insulator)技術設置於凸狀石夕島區上，可以 增加邏輯電路區之電晶體的性％。而且利用本發明的方法541661 V. Inventor (5) In the second deposition layer 32, the contact hole 3 4 is filled with conductivity for embedded memory. As shown in Figure 6, the area 1 is defined on the silicon substrate 10 Among them, the first side, and the convex silicon island silicon layer 16 is a surface layer, between the material 10, wherein the insulation is. The semiconductor transistor includes at least one first and at least one capacitor junction, a metal oxide semiconductor element, a semiconductor transistor, a first contact hole 34 and a second metal material. At least the three-dimensional space element of the corresponding logic circuit produced according to the above manufacturing method includes the following: a semiconductor silicon substrate, in the semiconductor depression region 12 and at least one convex silicon island depression region The semiconductor silicon substrate is exposed at the bottom. The surface region 14 includes a silicon layer 16 and an oxide layer 18, wherein the oxide layer 18 is located on the silicon layer. 6 and the semiconductor stone-based emulsion layer 18 is a silicon oxide. A layer for isolating a memory region 36, disposed in the recessed region i2, a metal-oxide semiconductor device 20 on the recessed region 12, a structure 28 and at least one first contact hole 30, wherein the 20th It is one of a P-type metal oxide semiconductor or an n-type metal oxide. A logic circuit region 38 is disposed on the convex silicon island region 14 and includes at least one second metal-oxide-semiconductor element 22 and at least one second contact hole 34 on the convex stone island region 14. What is the metal-oxide semiconductor element 22? One of the transistors of the N-type metal oxide semiconductor or the N-type metal oxide semiconductor. The three-dimensional space element applied to the logic circuit of the embedded memory formed by the method of the present invention, wherein the logic circuit area is set on the convex Shixi Island area by using SiO (Silicon On Insulator) technology. Increasing the% of the transistor in the logic circuit area. And using the method of the present invention
0503-7088twf ； TSMC2001-0929 ； Jerry.ptd 第 8 頁 541661 五、發明言兒明（6) 可以解決記憶體區和邏輯電路區因製程上和結構上之不同 所產生高度落差值的問題，縮減插塞接觸孔之深寬比 (aspectratio)。 本發明雖以較佳實施例揭露如上，然其並非用以限定 本發明的範圍，任何熟習此項技藝者，在不脫離本發明之 精神矛口範圍内，當可做些許的更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。0503-7088twf; TSMC2001-0929; Jerry.ptd Page 8 541661 V. Inventor's Note (6) It can solve the problem of the height difference between the memory area and the logic circuit area due to the difference in process and structure, and reduce The aspect ratio of the plug contact hole. Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the scope of the present invention. Anyone skilled in the art can make some changes and decorations without departing from the spirit of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.
0503-7088twf ； TSMC2001-0929 ； Jerry.ptd 第9頁0503-7088twf; TSMC2001-0929; Jerry.ptd page 9