TW541503B - Capacitive pressure microsensor and methods for manufacturing the same and methods for signal detecting the same - Google Patents

Capacitive pressure microsensor and methods for manufacturing the same and methods for signal detecting the same Download PDF

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Publication number
TW541503B
TW541503B TW90112023A TW90112023A TW541503B TW 541503 B TW541503 B TW 541503B TW 90112023 A TW90112023 A TW 90112023A TW 90112023 A TW90112023 A TW 90112023A TW 541503 B TW541503 B TW 541503B
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Taiwan
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layer
metal
sensing element
capacitive pressure
metal layer
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TW90112023A
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Chinese (zh)
Inventor
Bruce C S Chou
Ching-Fu Tsou
Ming-Lin Tsai
Yuan-Wei Cheng
Jin-Chern Chiou
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Bruce C S Chou
Chiou Jin Chern
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Abstract

There is disclosed a capacitive pressure microsensor for fingerprint verification, its manufacturing methods, and its signal detecting method. The main configuration of this capacitive pressure microsensor is a parallel-plate capacitor which consists of a first e1ectrode plate and a second electrode plate. The first electrode plate is fixed on a substrate at the bottom of the parallel-plate capacitor, and the second electrode plate is at the upside of the parallel-plate capacitor. The structure of the second electrode plate is a suspended plate which consists of at least one pin. The capacitive pressure microsensor further comprises signal-detecting circuits allocated next to each parallel-plate capacitor. The signal-detecting circuit uses a signal-detecting structure of an ameliorated dynamic random access memory (DRAM) to read signals from each parallel-plate capacitor. Each of the parallel-plate capacitor and its signal-detecting circuit are constructed on the same wafer through the integrated circuit manufacturing process. Through a plural number of capacitive pressure microsensors arranged in a matrix form it can detect the changes of the ridges and grooves of a finger to get a fingerprint image which is then used for identification verification.

Description

541503 五、發明說明(l) 、-----— 【發明之背景】 發明之領域 本發明係關於一種指紋辨” 、 關於一種與積體電路製程相匹配壓力微感測元件,尤其 件,及其製造方法與訊號之數位2容式壓力微感測元 元與讀取處理電路積體化整合,1嗔取架構,以便將感測 ΛΛ 〇 元成系統化晶片製作的目 習知技術之描述 習知的指紋辨識方法,最 壓印在紙上,再利用光學掃描 紋圖形比對,其最大缺點為無 ;此無法滿足越來越多即時認證 電子商務,攜帶式電子產品保 全系統等等。 t老者是利用手指按墨水, 輪入電腦中與資料庫中之指 法達到即時處理的目的,因 的需求,例如:網路認證, 岔’ I C卡個人身分認證,保541503 V. Description of the invention (l), ------ [Background of the invention] Field of the invention The present invention relates to a fingerprint recognition ", to a pressure micro-sensing element, especially a piece, that matches the integrated circuit manufacturing process, And its manufacturing method and digital integration of the digital two-capacity pressure micro-sensing element and the reading processing circuit, and the structure of the 1st acquisition, in order to make the sensing ΛΛ 〇 element into the systematic know-how Describe the conventional fingerprint identification method, which is most embossed on paper and then compared with optical scanning patterns. The biggest disadvantage is none; this cannot meet the increasing number of instant authentication e-commerce, portable electronic product security systems, and so on. The old man uses the finger to press the ink, turns the finger in the computer and the database to achieve the purpose of real-time processing, due to the needs, such as: network authentication, fork 'IC card personal identity authentication, security

生=成ΐ可以作為即時指紋辨識的感測系統應運而 學方式的,請參見美國專利編號4,〇53 .^ ,3〇〇,、電子式的即時指紋辨識系統有屬於壓Health = Cheng can be used as a sensing system for real-time fingerprint identification. Please refer to U.S. Patent Nos. 4,053, 300. Electronic real-time fingerprint identification systems are under pressure.

二:广接觸方式的,請參見美國專利編號4,394,773、 古从Μ Ί 40 0, 6 62、5, 844, 28 7 ;屬於手指靜電感應 工、’請參見美國專利編號4, 42 9, 41 3。 、,其中,光學系統的價格較為昂貴,消耗功率高(光源 =耗^且體積較大(受限光學零組件的尺寸及光學成像所 需固疋距離之安排),使得其不適用於許多攜帶式電子產2: For the wide contact method, please refer to U.S. Patent No. 4,394,773, Gucong M Ί 40 0, 6 62, 5, 844, 28 7; belong to finger electrostatic induction workers, 'see U.S. Patent No. 4, 42 9 , 41 3. Among them, the optical system is more expensive and consumes high power (light source = high power consumption and large volume (restricted optical component size and arrangement of fixed distance required for optical imaging), making it unsuitable for many portable Electronic products

第9頁 5415〇3 五、發明說明(幻 品如筆記型雷 有相•大ί腦及行動 ΙΪ的改善,然而敕人了二極接觸時會有 =二I造電材料的製作=及手指上的汗水白知技術所_ Μ秦 τ衣作的即時 •小與薄 製造容易. 穩定度高 功率消耗低 價格便宜 等要求,以利其應用推 ;上母個人的指紋不同) 【發明概要】 所以,本發明之一 元件’使接觸至此微感 内部電容之電壓變化而 本發明之另一目的 之製造方法,使此 製作於單一晶片上 大幅地降低其製 電話等。至於電 仍有功率消耗大 電流流通),不 不匹配於積體電 影響(靜電感應 指紋辨識系統仍 子式的系統體積上 (電接觸式的感測 易與積體電路製程 路製程),以及易 方式),使得目前 無法同時達到 廣’作為隶佳身分認證使用(生理 目的是提供一種 測元件表 快速地進 是提供一 微感測元件 此一方法不 之製程,更可以 本發明之又 … 取方法,此方法利用 目的是提供一 ,改良式動 讀取架構,讀取此指紋辨識裝置 面之手 行辨識 種電容 得以透 但可簡 造成本 種指紋 態隨機 内之電 電容式壓力微感測 指紋路,可透過其 Ο 式壓力微感測元件 過一積體電路製程 化一指紋辨識骏置 〇 :識裝置之訊號讀 2二己憶體之訊號 谷式壓力微感蜊元Page 9 5415〇3 V. Description of the invention (Phantoms such as note-type mines have a great improvement in brain and action, but when they are in contact with the two poles, there will be = making of two electrical materials = and fingers上 了 汗 白 知 技术 所 _ Μ 秦 τ Clothes made in real-time • Small and thin are easy to manufacture. Stability, high power consumption, low price, and other requirements to facilitate its application; personal fingerprints of the mother are different) [Summary of the invention] Therefore, one of the components of the present invention changes the voltage contacting the micro-inductive internal capacitance, and the manufacturing method of the other object of the present invention makes the manufacturing on a single chip greatly reduce the production of telephones and the like. As for electricity, there is still power consumption and large current flow), which does not match the influence of the integrated electrical system (the electrostatic induction fingerprint recognition system is still based on the sub-system's volume (electric contact-based sensing easy and integrated circuit manufacturing process), and Method), making it currently impossible to achieve wide use at the same time as Lijia ’s identity authentication (physical purpose is to provide a measuring element table to quickly advance is to provide a micro-sensing element. This method is not a process, and it can also be ... Method, the purpose of this method is to provide an improved dynamic reading architecture that reads the fingerprint of the fingerprint recognition device, and the capacitance of the hand recognition type can be transparent, but it can easily result in the capacitive pressure micro-sensing of this fingerprint state randomly. The fingerprint circuit can be processed through an integrated circuit through its 0-type pressure micro-sensing element and a fingerprint recognition unit. 0: The signal of the device is read. 2 The signal of the valley-type pressure sensor.

541503 五、發明說明(3) 件陣列之訊 號,使每 線上,不 發明,此 此基板上 電容旁、用以讀取此 此一平行板電容之結 至每一位元 根據本 板及製作於 極板、介於 及位於第二 電極板位於 弟一電極板 中,此至少 接至懸浮薄 ;力微感測元 壓力微感測 同時, 板上方之至 微米之間。 第一電極 電極板上 此平行板 則為具有 一支連接 板,另一 件之表面 元件,並 製作於此 一微感 受位元 一電容 方之一 平行板 構至少 板與第 方之中 電容之 至少一 腳係用 端則固 更包含 作為一 一電容 少一凸塊之較佳 測元件 線寄生 式壓力 平行板 電容訊 包含一 一電極 央部份 底部且 支連接 以支撐 定於基 一高分 手指接 式壓力 高度範 之訊號得 電容之影 微感測元 電容,與 號之一訊 第一電極 板間之一 之至少一 以正確地傳遞 響。 件包含:一基 位於此 號%取 板、一 平行板 電路。 第二電 空氣間隙,以 凸塊。此第一 固定於基板之上;而此 腳之一懸浮薄板 其 此懸浮薄板,其一端連 板之上。 子保護層 觸面。 微感測元 圍,應介 此一電容式壓 ,用以保護此 件之第二電極 於2微米至1 0 根據本發明,此一雷交4网、丄 為一次彳%芈 g X /谷式壓力微感測元件之製造方法 於2。 、聪包路製程,此η值至少大於等 此電容式壓力微感測元件 驟:沉積一第η-2声合屬„入衣造方法至少包含下列步 層間製作…祝^入曰 曰;1電層;於第η —2層金屬間介電 蝕步驟,以在第2展八,,儿積一鎢金屬膜,並完成回 曰i屬間介電層間構成複數個金屬拴541503 V. Description of the invention (3) The signal of the array, so that each line is not invented. This capacitor next to the capacitor on this substrate is used to read the junction of this parallel plate capacitor to each bit. The electrode plate is located between the second electrode plate and the second electrode plate and is located in the first electrode plate, which is at least connected to the suspension thin film; the force micro-sensing element and the pressure micro-sensing are simultaneously between the top of the plate and the micrometer. The parallel plate on the first electrode electrode plate is a surface element having one connection plate and the other, and is fabricated on the parallel plate structure of at least one of the micro-sensing bit and the capacitor. At least one end of the foot is fixed to include a better measuring element as a capacitor and a less bump. The line parasitic pressure parallel plate capacitor includes a bottom of the electrode central part and is connected to support the base score. The finger-type pressure-height range signal obtains the capacitor's shadow micro-sensing element capacitance, and at least one of the signals between the first electrode plate and the signal transmits the sound correctly. The components include: a base board located at this number, a parallel board circuit. Second electrical air gap to bump. The first is fixed on the substrate; and one of the feet is a floating sheet, and one end of the floating sheet is connected to the board. Sub-protective layer A micro-sensing element should be connected to this capacitive voltage to protect the second electrode of this piece from 2 microns to 10 according to the present invention. The manufacturing method of the pressure micro-sensing element is described in 2. And Congbao road manufacturing process, the value of η is at least greater than the capacitive pressure micro-sensing element: deposition of a η-2 vocal synthesizer is a clothing manufacturing method that includes at least the following steps of interlayer production ... Electric layer; in the η-2 layer intermetal dielectric dielectric etching step, to deposit a tungsten metal film in the second exhibition, and complete the formation of a plurality of metal tethers between the intermetallic dielectric layer

541503 五 發明說明(4) --------- 基枝;沉穑楚 鈦、_棋 弟η — 1層金屬層,此第n-1層金屬層係包含一層 ~層銘人a η 上,去除a二金及一層氮化鈦;透過光阻於預定之位置 介雷P刀面積之第n-1層金屬層;沉積第n-1層金屬間 層’此金屬:、層金屬間介電層上方’沉積第η層金屬 上,去二a層係為一結金屬層;透過光阻於預定之位置 保護層上方 積之第η層金屬層;沉積一層保護層;於 刻角? 土 Α ’透過光阻於預定之位置上定義出一保護層蝕 4 ®,去除巍 及篦η 1昆 ]商内之該保護層、第η-1層金屬間介電層 人示η-1層金屬展知 合全本二、’增之鼠化鈦,以曝露出第η-1層金屬層之鋁 製作至少一、弟1層金屬層之中央部份、保護層上方, 金,纽二产凸塊;選擇性地去除第η- 1層金屬層中之鋁合 之第η — Ί 之鈦金屬,以製作出一空氣間隙,使其上方 至少 φ 間介電層、第n層金屬層及保護層,形成由 屬厣之轴厶居π ί 懸、/予溥板結構,並與第η — 1層金 方,喷灑冷你 _ ν 丁板1^谷,以及,在此元件表面上 噴灑塗佈一鬲分子保護層。 如上所述,根據本& 沉積第η]層金屬層之:,月利用此/藤'更包含下列步驟:在 第η-2層金屬間介電層至一 μ反應式離子蝕刻,回蝕該 塞柱於第η-2層金屬間介電==;以暴露出複數個金屬栓 至少大於0.1微米。 電θ表面,其中,回蝕之深度應 根據本發明,此_於 利用—習用動態隨機存^ 1置之訊號讀取方法乃是 取此裝置所包含之一電容;.3 (DRAM )《電路結構,讀 电奋式壓力微感測元陣列之訊號,此 541503 五、發明說明(5) 存取記憶體 字元線、一 之每一平行 置一金屬氧 容與每一位 電壓傳遞至 方法至少包含下列步驟:配置一習用動態隨機 (dram )之電路結構,包含一組位元線、一組 組位址解碼器;將此電容式壓力微感測元陣列 板電容及每一位元線分別連接上一電流源;配 化半導體開關(Μ 0 S S w i t c h )於每一平行板電 =線之間;再利用此開關將每一平行板電容之 所連接之位元線上。 號讀取方法 )之電路結 元陣列之訊 態隨機存取 、一組字元 元陣列之每 源;配置一 Foil ower 用此P型金 電壓傳遞至 生電容的干 根據本.發明, 乃是利用一改 此二心紋辨識裝置之另一訊 構,讀取此裝置^動悲隨機存取記憶體(DRAM 號,此方法^少^ ^含之一電容式壓力微感測 記憶體(DRAM )=合下列步驟··配置一習用動 線 '一組位址解 ^路結構,包含一組位元線 一平行板電容及务f ;將此電容式壓力微感測 P型金屬氧化半導〜位元線分別連接上一電流 )於每一平行板電'、源極隨輕器(PMOS Source 屬氧化半導體源柘^與每一位元線之間;再利 其所連接之位元綠隨輕器將每一平行板電容之 擾。 、上’以避免每一位元線之寄 關於本發明之 附圖說明之後,脸的特性及優點,在參考下列内容及 :可更清楚明暸。 較佳實施例之% 明541503 Explanation of the Five Inventions (4) --------- Basic branches; Shen Chuchu Titanium, _ Chedi η — 1 metal layer, this n-1 metal layer system contains one layer ~ layer Minga On η, remove a gold and a layer of titanium nitride; pass the photoresist to the n-1th metal layer of the P knife area at a predetermined position; deposit the n-1th intermetallic layer 'this metal :, layer metal Above the interlayer dielectric layer is deposited on the n-th layer of metal, and the second a layer is a junction metal layer; the n-th layer of metal layer deposited on top of the protective layer through a photoresist is deposited; a protective layer is deposited; • Soil A ′ defines a protective layer etch 4 ® at a predetermined position through the photoresist, and removes Wei and 篦 η 1]] The protective layer and the η-1 intermetal dielectric layer in the quotient are shown in the figure. 1 layer of metal exhibition knowledge and combination of two, 'Zengzhi rat titanium, to expose the η-1 metal layer of aluminum to make at least one, younger one metal layer in the central part, over the protective layer, gold, New Zealand Second-generation bumps; selectively remove aluminum η—Ί titanium metal in the η-1 metal layer to create an air gap with at least φ dielectric layers above it, The n-th metal layer and the protective layer form a dangling / prefabricated plate structure dwelling on the axis of the metal, and spray the cold _ ν Ding plate 1 ^ valley with the η-1 layer of gold square, and , Spray a layer of molecular protective layer on the surface of this element. As described above, according to this & deposition of the η] th metal layer: the use of this / vine 'further includes the following steps: in the η-2th intermetal dielectric layer to a μ reactive ion etching, etch back The plug is at the η-2 layer inter-metal dielectric ==; to expose a plurality of metal plugs at least larger than 0.1 micron. The electrical θ surface, in which the depth of etchback should be in accordance with the present invention, the method for reading signals using dynamic random storage ^ 1 is to take one of the capacitors included in this device; .3 (DRAM) "circuit Structure, read the signal of the electric pressure-type pressure micro-sensing element array, this 541503 V. Description of the invention (5) Memory word lines, one metal oxygen capacity in parallel and one voltage transfer to each method At least the following steps are included: a dynamic random circuit structure is configured, including a group of bit lines and a group of address decoders; the capacitance of the capacitive pressure micro-sensing element array board and each bit line Connect a current source separately; distribute a semiconductor switch (M 0 SS witch) between each parallel plate; and then use this switch to connect the bit line of each parallel plate capacitor. No. reading method) circuit state random access of the circuit element array, each source of a group of character arrays; a Foil ower is configured to use this P-type gold voltage to transfer to the capacitor according to the invention. Invention, but Using another message structure that changes the two heart pattern recognition devices, read this device ^ Mobile sad random access memory (DRAM number, this method ^ less ^^^ including one capacitive pressure micro-sensing memory (DRAM ) = Combine the following steps: · Configure a common moving line 'a set of address solution structure, including a set of bit lines, a parallel plate capacitor and service f; this capacitive pressure micro-sensing P-type metal oxide semiconductor ~ The bit line is connected with a current) to each parallel plate, and the source follower (PMOS Source is an oxide semiconductor source) and each bit line; and the bit green connected to it With the light device, the interference of each parallel plate capacitor is avoided. After the 'to avoid each bit line's description of the drawings of the present invention, the characteristics and advantages of the face can be more clearly understood by referring to the following and: % Of the preferred embodiment

第13頁 541503 五、發明說明(6) 之立二才H1 n本發明實施例之指紋辨識裝置部分 ^ ; I i ^ ::微”元件1〇的間距(pitch)M。每J壓力歹微感;個元 的結構主要為一平行板電容20,包含··底部的^ 極;te Γ圖Φ 土-、 u a ·低#的弟一電 反(α中未不)以及上方的第二電極板;而 2:2一的懸第浮的4板結構2〇1,由二支連接腳202支撐;連接腳 = = 仙係與懸 及第-雷二: (圖中未示)’形成於第- 邻八一一:板中間;一凸塊203 ’位於懸浮薄板201的中央 :、,.一;V刀子保護層,覆蓋於整個元件的最表面(圖中 ;不),在每個壓力微感測元件1 〇中,對應於每一平杆把 圖〇2之訊取電路30,製料^ /〇於二p /斤不為一平行板電容2 〇與其訊號讀取電路 t ^5^09^51^ ° w 私路5 0 9及510分別代表用以讀取訊號之一字元 線。此壓力微感測元件之訊號讀取方式稍後再加以說明, 請參見圖3,吾人將就圖丨所示之指紋辨 原理作-詳細之說明。圖3所顯示為圖i之電容 測元件陣列與手指接觸時之剖面圖。,中,壓 ,10的平行板電容20是由第一電極板41G及第二電^板42〇 、、且成’兩個電極板中間為一空氣間隙4 〇 〇。 當手指7 0接觸此壓力微感測元件陣列時,僅有部分感 第14頁 541503Page 13 541503 V. The description of the invention (6) H1 n The fingerprint identification device part of the embodiment of the present invention ^; I i ^ :: micro "pitch 10 of the component 10. Each J pressure is micro. The structure of the element is mainly a parallel plate capacitor 20, including the ^ pole at the bottom; te Γ diagram Φ soil-, ua · low # 's di-electrical inversion (α 中 未 不) and the second electrode above Board; and the 2: 2 one suspension board 4 board structure 201, supported by two connecting feet 202; the connecting foot = = immortal and overhang and the first-Lei II: (not shown in the figure) 'formed in The first-adjacent 811: in the middle of the board; a bump 203 'is located in the center of the suspended sheet 201: ,,, a; V knife protective layer covering the entire surface of the entire component (picture; no), at each pressure In the micro-sensing element 10, corresponding to each of the flat rods, the signal obtaining circuit 30 of FIG. 2 is made of ^ / 〇 at 2 p / kg, which is not a parallel plate capacitor 2 〇 and its signal reading circuit t ^ 5 ^ 09 ^ 51 ^ ° w Private road 5 0 9 and 510 respectively represent a character line used to read the signal. The signal reading method of this pressure micro-sensing element will be described later, please refer to Figure 3, my The fingerprint identification principle shown in Figure 丨 will be explained in detail. Figure 3 shows a cross-sectional view of the capacitive sensing element array of Figure i when it is in contact with a finger. The electrode plate 41G and the second electric plate 42 °, and an air gap of 400 ° is formed between the two electrode plates. When a finger 70 contacts the pressure micro-sensing element array, only a part of it is sensed. Page 14 541503

測元件與指紋凸點40接觸(部分感測元件則是覆蓋於指紋 凹點50,一60下),並感受到來自手指的壓力,此一壓力造 成,測=件的懸浮薄板產生一位移量d (位移量大小視所 承受=壓力而定),進而改變二平行板間的電容值,經由 電路4 T ’即可反應出在此一陣列中,受指紋凸點4 〇接觸 而產生變化之壓力微感測元件丨〇,進而建構出指紋凸點4 0 的形狀分布。習知的指紋辨識即是判別指紋凸點在平面上 的形狀分布’而任兩個指紋凸點的間距約略2 〇 〇〜8 〇 〇微 米’因此壓力微感測元的間距γ必須小於指紋凸點的間 距。同時,指紋辨別主要部分的面積約為丨cra x丨cnl,因此鲁 若Y等於若8 0微米,則必須製作1 2 8 X 1 2 8個感測元才能滿 足要求。 請參見圖4A至4C,其為圖1所示之壓力微感測元件陣 列沿圖1之線B-B之剖面製造程序圖。為了簡化起見,在此 圖中僅繪製單一個壓力微感测元件丨〇之平行板電容2 〇,用 以說明本實施例之壓力微感測元件丨〇之主要結構及其製造 方法。The measuring element is in contact with the fingerprint bump 40 (some of the sensing elements are covered by the fingerprint recess 50, 60 times), and the pressure from the finger is felt. This pressure causes the floating plate of the measuring element to generate a displacement. d (the amount of displacement depends on the pressure = pressure), and then change the capacitance value between the two parallel plates, through the circuit 4 T 'can be reflected in this array, the fingerprint bumps 40 contact with the change The pressure micro-sensing element 丨 0, and then the shape distribution of the fingerprint bump 40 is constructed. The conventional fingerprint recognition is to judge the shape distribution of the fingerprint bumps on the plane ', and the distance between any two fingerprint bumps is about 2000 ~ 800 microns, so the distance γ of the pressure micro-sensing element must be smaller than the fingerprint protrusion The spacing of the points. At the same time, the area of the main part of the fingerprint identification is about cra x cnl, so if Y is equal to 80 micrometers, then 1 2 8 X 1 2 8 sensing elements must be made to meet the requirements. Please refer to FIGS. 4A to 4C, which are manufacturing process diagrams of the pressure micro-sensing element array shown in FIG. 1 along the line B-B of FIG. For the sake of simplicity, only the parallel plate capacitance 20 of a single pressure micro-sensing element 丨 0 is drawn in this figure to illustrate the main structure of the pressure micro-sensing element 丨 0 and the manufacturing method thereof.

(1)如圖4 A所示,為一利用商用次微米 (sub-micron)、n層銘金屬石夕積體電路製程(特別是互補 式金氧半CMOS製程,而且η值至少大於2 )完成之壓力微感 測元件1 0半成品。由於積體電路製程為一習知技術,對於 其詳細製程說明在此即不贅述,僅說明平行板電容壓力為 感測元件之結構及材料屬性如下: 首先’沉積一第η-2層金屬間介電層3〇3 ;於第^2層(1) As shown in FIG. 4A, it is a process using a commercial sub-micron, n-layer metal stone integrated circuit (especially a complementary metal-oxide-semiconductor half-CMOS process, and the value of η is at least greater than 2). The finished pressure micro-sensing element 10 semi-finished products. Since the integrated circuit manufacturing process is a well-known technology, the detailed process description will not be repeated here, and only the structure and material properties of the parallel plate capacitor pressure as the sensing element will be described as follows: First, a η-2 layer intermetallic layer is deposited Dielectric layer 30; on the second layer

第15頁 541503 五、發明說明(8) 金屬間介電層3 〇 3間製作複數個介電層穿孔;沉積一鶴金 屬膜,並完成回蝕步驟,以在第n — 2層金屬間介電層間構 成複數個金屬栓塞柱310 ;再於其表面沉積一第η — 1層金屬 層3 04,此金屬層之結構通常為鈦3〇4a/鋁合金3〇4b/氮化 欽(圖中未示)的三明治結構,其中,此第n—1層金屬層3〇4 ,透過其下方第n —2層金屬間介電層3〇3中之複數個金屬拴 基柱310與其下方之導體連線層(圖中未示)(為金屬層或 多晶矽層)連接。利用微影及蝕刻技術去除部分面積之第 n-I—層金屬層304,以留下預定面積之第η —}層金屬層⑽么。 接者,再於整體表面上覆蓋一第n—i層金屬間介電層3〇5。 後再於第η_1層金屬間介電層3〇5之上沉積第n声金屬 去此卜第〇層金屬層3〇6為一銘金屬層。利'用微影及钱 二===除部分面積之第11層金屬層306 ;於整體表面上製 層3〇ΓΛϋ ’ 影及敍刻技術同時去除部分保護 層304之ί ^ ίη 屬間介電層3〇5及部分第η—1層金屬 ,η7 化鈦,以曝露出鋁合金金屬層304b之蝕刻窗σ 3〇h。再於保護層3〇7中 =到固口 作一高起之凸塊3 08。^ 、 先阻或金屬材料製 米至1。微米之間。 -凸塊308之較佳高度範圍為2微 i £ 合金金屬層/oib而形成,t刻窗口3〇7&去除預先定義的鋁 溫度之下,可以供、Φ 土醋的轧a ,在適當的比例調配及 h逮去除铭材料(>1微米/分)。同時,Page 15 541503 V. Description of the invention (8) Interlayer dielectric layers 3 and 3 are used to make a plurality of dielectric layer perforations; a crane metal film is deposited and an etch-back step is completed to interpose the n-2th intermetallic layer A plurality of metal plugs 310 are formed between the electrical layers; an η-1 metal layer 3 04 is deposited on the surface. The structure of this metal layer is usually titanium 304a / aluminum alloy 304b / nitride (in the figure) (Not shown) sandwich structure, in which the n-1th metal layer 304 passes through the plurality of metal tethered pillars 310 and the conductors below the n-2th intermetal dielectric layer 303 The connection layer (not shown) (a metal layer or a polycrystalline silicon layer) is connected. The lithography and etching techniques are used to remove the n-I-th metal layer 304 in a part of the area so as to leave the n-th} metal layer ⑽ of a predetermined area. Then, an n-i layer intermetal dielectric layer 305 is covered on the entire surface. After that, an n-th acoustic metal is deposited on the η_1-layer intermetal dielectric layer 305, and the 0th metal layer 306 is a metal layer. Use of lithography and money === Dividing the 11th metal layer 306 of a part of the area; forming a layer on the entire surface 30 ΓΛϋ 'Photographic and engraving techniques simultaneously remove part of the protective layer 304 ^ ^ η intergeneric dielectric Layer 305 and a portion of the η-1 layer metal, η7 titanium oxide, to expose the etching window σ 30h of the aluminum alloy metal layer 304b. Then in the protective layer 3007 = to the solid mouth as a raised bump 3 08. ^, First resistance or metal material metric to 1. Between micrometers. -The preferred height range of the bump 308 is formed by 2 microi £ alloy metal layer / oib, the t-cut window 307 & under the predefined aluminum temperature can be supplied, Φ vinegar rolling a, at an appropriate Proportioning and removal of material (> 1 micron / min). Simultaneously,

第16頁 541503 五、發明說明(9) 對於鈦304a有極佳的選擇性,因此可以完成去鋁3〇4b留鈦 304^的選擇性蝕刻技術。而鈦3〇4a即是作為平行板電容 之第一金屬層,其與第n —2層金屬間介電層3〇3及複數個金 屬检塞柱3 10構成平行板電容20之第一電極板41〇。而第η 層金屬層即為此平行板電容2〇之第二金屬層,其與第n — j ^金屬間介電層305及保護層30 7將構成此平行板電容2〇之 第二電極板420,此第二電極板42 0在經過鋁蝕刻之後,將 成為由兩支連接腳2 02支撐之一懸浮薄板結構。 (2)如圖4C所示,為了更進一步保護壓力微感測元 件’ι例如防止灰塵,最後利用喷灑旋佈方式在元件的最表 面製作一高分子保護層3 〇 9,例如聚乙烯胺(p〇丨y丨m i de ), 以形成一封閉腔體的壓力微感測元件。 由以上之說明,吾人應注意到,圖4A至圖4B之製造程 序’及所選用的所有材料及製作方式,是完全相匹配於現 今之各種商用積體電路製程的,而圖4C之製造程序,卻可 以不品要任何光罩製程,以簡化製程,這是本發明最重要 的精神一建立無晶圓廠(fabless)的生產方式(僅需建立 簡單的微機電後段製程),類似I C設計公司之理念,以利 大幅降低成本,增加競爭力。同時,積體化的製程,更容 易整合讀取及處理電路於同一晶片上,完成系統化晶片製 作。 一圖5顯示本發明之另一實施例之製程改良示意圖。圖5 所示結構之製造過程與圖“至4(:幾乎相同的,對於其製作 流私在此不贅述’差別者僅為在前述製程的沈積第n_丨層Page 16 541503 V. Description of the invention (9) It has excellent selectivity for titanium 304a, so it can complete the selective etching technique for removing aluminum 304b and leaving titanium 304 ^. Titanium 304a is the first metal layer of the parallel plate capacitor, and it forms the first electrode of the parallel plate capacitor 20 with the n-2th intermetal dielectric layer 30 and the plurality of metal plugs 3 10. Board 41〇. The ηth metal layer is the second metal layer of the parallel plate capacitor 20, and the n-j ^ intermetal dielectric layer 305 and the protective layer 307 will constitute the second electrode of the parallel plate capacitor 20. After the second electrode plate 420 is etched by aluminum, it will become a suspended thin plate structure supported by two connecting legs 202. (2) As shown in FIG. 4C, in order to further protect the pressure micro-sensing element, for example, to prevent dust, a polymer protective layer 3 09 is formed on the outermost surface of the element by spraying and spinning, such as polyvinylamine. (P〇 丨 y 丨 mi de) to form a pressure micro-sensing element with a closed cavity. From the above description, I should note that the manufacturing process of Figure 4A to Figure 4B and all the materials and manufacturing methods selected are fully compatible with today's various commercial integrated circuit manufacturing processes, and the manufacturing process of Figure 4C However, it is not necessary to require any photomask manufacturing process to simplify the manufacturing process. This is the most important spirit of the present invention. A fabless production method is established (only a simple micro-electromechanical back-end process is required), similar to IC design. The company's philosophy is to greatly reduce costs and increase competitiveness. At the same time, the integrated manufacturing process makes it easier to integrate the reading and processing circuits on the same chip to complete the systematic chip manufacturing. FIG. 5 is a schematic diagram of a process improvement of another embodiment of the present invention. The manufacturing process of the structure shown in FIG. 5 is almost the same as that of the drawings “to 4 (:, its production is not described here. The difference is only the deposition of the n_ 丨 layer in the aforementioned process

第17頁 541503Page 541 503

金屬層304前多-道步驟:利用反應式離子㈣,回触第 層金屬間介電層303至一深度,使複數個金屬栓塞枉 3^0凸出於第n_2層金屬間介電層3〇3表面,其中,回蝕之 沬度應至少大於0. 1微米。此舉對於後續空氣間隙4的形 成過程中,有助於防止懸浮薄板2〇1與底部之第一電極板 410因液體表面張力而吸附在一起。 *以上所述為本發明之電容式壓力微感測元件之結構及 其製造方法,以下吾人將就本發明之電容 件之訊號讀取方式做一詳細之說明。 以Multi-step before the metal layer 304: using reactive ion rhenium, contact the first intermetal dielectric layer 303 to a depth, so that a plurality of metal plugs 枉 3 ^ 0 protrude from the n_2 intermetal dielectric layer 3 〇3 surface, wherein the degree of etchback should be at least greater than 0.1 microns. This will help prevent the suspended thin plate 201 and the first electrode plate 410 at the bottom from being adsorbed together due to the liquid surface tension during the subsequent formation of the air gap 4. * The above is the structure and manufacturing method of the capacitive pressure micro-sensing element of the present invention. We will make a detailed description of the signal reading method of the capacitive element of the present invention below. To

/在本發明中,此一指紋辨識裝置是由複數個電容式壓 力被感別元件排列成之陣列構成。此一結構與一般習用之 動=Ik機存取圮憶體裝置中()之儲存電容排列方式 7相付“因此’習用動恶隨機存取記憶體裝置中(dram )之 儲存笔各5貝取電路是可以應用於本發明的,此為本發明之 一特點’透過dram的數位式讀出架構(習知技術所有的指 、文辨哉衣置皆為類比式的讀出架構),可以免除硬體中類 比/數位的轉換,以及辨識軟體中二元化(binary)的處 理。 明 首先 吾人先就習用之記憶體讀取架構作一簡單之說/ In the present invention, the fingerprint recognition device is composed of an array in which a plurality of capacitive pressures are arranged by the sensing elements. This structure is compatible with the conventional arrangement of storage capacitors in the Ik memory access device (7). Therefore, the storage pen in the random access memory device (dram) is used for 5 pounds each. The circuit can be applied to the present invention, which is one of the features of the present invention. The digital readout architecture through dram (all fingers and text recognition devices in the conventional technology are analog readout architectures), which can be eliminated. Analog / digital conversion in hardware, and binary processing in identification software. First of all, let me make a simple statement about the memory reading architecture that I use.

睛茶見圖6,圖中所示為傳統之記憶體讀取架構,其 中包含儲存電容陣列5 0 0、資料讀寫控制5 0 1、計時器 50 2、行前置解碼器503、閉鎖預防504、列解碼器5〇5、行 解碼器506、讀取放大器508,以及可提升靈敏度之參考元Eye tea is shown in Figure 6, which shows the traditional memory reading architecture, which includes storage capacitor array 5 0 0, data read and write control 5 0 1, timer 50 2, line pre-decoder 503, lockout prevention 504, Column Decoder 505, Row Decoder 506, Read Amplifier 508, and Reference Element to Improve Sensitivity

第18頁 541503Page 18 541503

五、發明說明(π) 5〇7 (dummy cel 1 ),整個DR AM的讀取靈敏度由健存 六 陣列5 0 0、參考元50 7及讀取放大器508所限制。 子”谷 圖7所示為本發明之電容式壓力微感測元件陣列 二、, 細架構圖,其中,為了避免鄰近感測元件間的干择,之^羊 一組奇偶字元線50 9a,50 9b,使其各自交錯打開片设置 位址。 间琢測元件 而由此一指紋辨識裝置之訊號讀取方法,乃是利 習用動態隨機存取記憶體(DRAM )之電路結構,讀取此壯 置所包含之一電容式壓力微感測元陣列之訊號,^方^裳 少包含下列步驟:配置一習用動態隨機存取記憶體(⑽^ )之電路結構,包含一組位元線、一組字元線、一組位土 解碼器;及將此電容式壓力微感測元陣列之每一平行板址 谷及母一位元線分別連接上一電流源;以及配置_金屬= 化半導體開關(MOS Switch)於每一平行板電容與每_氧 元線之間;再利用此開關將每一平行板電容之電壓傳 其所連接之位元線上。 由於位元線5 1 0 ( b i t - 1 i n e )本身對矽基板會形成寄 生電容,因此位元線5 1 0越長、感測元件越多,此寄生1 容越大,而使得感測元件讀取至位元線的電壓訊號大為^降 低。是故,本發明亦將針對此一問題,提出另一種改^ ^ 之訊號讀取方式。 又式 請參見圖8及圖9,圖8所示為本發明之指紋辨識裝置 之另一改良式訊號讀取架構,而圖9則為此改良式訊號讀 取架構之輸入電壓與時間之關係圖。此一新型架構乃是貝用5. Description of the invention (π) 507 (dummy cel 1), the read sensitivity of the entire DR AM is limited by the Jiancun 6 array 500, the reference element 507, and the read amplifier 508. Figure 7 shows a detailed structure diagram of the capacitive pressure micro-sensing element array of the present invention. In order to avoid dry selection between adjacent sensing elements, a set of parity word lines 50 9a , 50 9b, to make each of them alternately open the chip to set the address. The method of reading the signal from a fingerprint recognition device is to use the circuit structure of dynamic random access memory (DRAM) to read. The signal of this capacitive pressure micro-sensing element array is included in this setup. The method includes the following steps: configuring a circuit structure of a conventional dynamic random access memory (⑽ ^), including a set of bit lines , A set of word lines, a set of soil decoders; and each parallel plate address valley and the female bit line of this capacitive pressure micro-sensing element array are connected to a current source respectively; and configuration_metal = A semiconductor switch (MOS Switch) is placed between each parallel plate capacitor and each oxygen line; this switch is then used to pass the voltage of each parallel plate capacitor to the bit line to which it is connected. Since the bit line 5 1 0 (bit-1 ine) itself will form Capacitors are generated, so the longer the bit line 5 1 0 and the more sensing elements, the larger this parasitic capacitance, which greatly reduces the voltage signal read by the sensing element to the bit line. Therefore, the present invention In view of this problem, another modified signal reading method of ^ ^ will also be proposed. Please refer to FIG. 8 and FIG. 9 for the formula. FIG. 8 shows another improved signal reading architecture of the fingerprint identification device of the present invention. Figure 9 shows the relationship between input voltage and time for this improved signal reading architecture. This new architecture is used

第19頁 541503 發明說明 Μ解$位兀線510之寄生電容與電容式壓力微感測元件“ 之電容比例過大,而使得電容式壓力微感測元件丨〇讀取至 位元線51 0的電壓訊號大為降低的問題。 、 新架構將每一條位元線BL 51〇及每一個電容式壓力微 感測元件1 0之平行板電容2〇分別接上電流源及p型金屬氣 化半導體源極隨耦器(PM〇s s〇urce F〇u〇wer ) 5ιι,使 知平行板電谷之第一電極板4丨〇上的電壓正確地傳遞到位 元線上而不受位元線寄生電容的影響。Page 19 541503 Description of the invention The parasitic capacitance of the solution line 510 and the capacitive pressure micro-sensing element "is too large, so that the capacitive pressure micro-sensing element reads to the bit line 51 0 The voltage signal is greatly reduced. The new architecture connects each bit line BL 51〇 and the parallel plate capacitor 20 of each capacitive pressure micro-sensing element 10 to a current source and a p-type metal gasification semiconductor, respectively. Source follower (PM〇s〇urce F〇u〇wer) 5 ι, so that the voltage on the first electrode plate 4 of the parallel plate power valley is correctly transferred to the bit line without being affected by the bit line parasitic capacitance Impact.

$圖8及圖9可知,*此一電容二微感測元件在非讀取 之狀悲下,字兀線50 9與脈衝字元線512 (pulse w〇rd 1 ine )上之輸入電壓將為ov,使連接至平行板電容2〇之p 型金屬氧化半導體(PM0S) 513將維持在開啟之狀態,因 :此第一電極板之接點514與矽基板2 〇〇同時連接至Vdd,使 兩者間電容205兩端無電位差,故不充電,僅使平行板電 f2〇之Ϊ 一電極板與第二電極板間之電容204充電;而在 讀取狀態時,字元線50 9與脈衝字元線512 (pulse w〇rdAs shown in Figure 8 and Figure 9, * This capacitor two micro-sensing element is in a state of non-reading. The input voltage on word line 509 and pulse word line 512 (pulse w 0rd 1 ine) will be Is ov, so that the p-type metal oxide semiconductor (PM0S) 513 connected to the parallel plate capacitor 20 will be maintained in an open state, because the contact 514 of the first electrode plate and the silicon substrate 2000 are simultaneously connected to Vdd, There is no potential difference between the two ends of the capacitor 205 between the two, so it is not charged, and only the capacitor 204 between one electrode plate and the second electrode plate of the parallel plate electric f20 is charged; and in the reading state, the word line 50 9 And pulse character line 512 (pulse w〇rd

ilne)上之輸入電壓將為5V,使PM0S 513關閉,切斷第一 電極板之Vdd電流源,也使反轉器5 2 0由高電位切換為低電 位,則矽基板2 0 0為接地狀態,相連接於接地之平行板電 容第二電極板420。因此,電容2〇4與2〇5之電荷將於第一 電極板與矽基板間進行重新分配,之後,再將其電壓經由 第一電極板之接點514傳遞至p型金屬氧化半導體源極隨耦 器 511 (PMOS Source Follower),由於此一 pM〇s s〇urce(ilne) input voltage will be 5V, make PM0S 513 turn off, cut off the Vdd current source of the first electrode plate, and also make the inverter 5 2 0 switch from high potential to low potential, then the silicon substrate 2 0 0 is grounded In the state, the second electrode plate 420 of the parallel plate capacitor connected to the ground is connected. Therefore, the electric charges of the capacitors 204 and 50 will be redistributed between the first electrode plate and the silicon substrate, and then the voltage will be transferred to the p-type metal oxide semiconductor source through the contact 514 of the first electrode plate. Follower 511 (PMOS Source Follower), because of this pM〇ss〇urce

Follower之放大率接近於!,位於此源極隨耦器5ΐι内之pFollower's magnification is close! , P within 5ΐι of this source follower

541503541503

型金屬氧化半導體5 1 6之閙榀#机R , π & 〕極多而點5 1 7與源極端點5 1 8之電 壓近=二斤以’藉由量測位元線BL 51〇經由端點51: 流向此源極P边耦器511之電壓變化,即可獲知端點51 即第一電極板之電壓值。杲妨,^ ^ ^ 疋故,此一電容式微感測元件之 訊號將可正確地傳遞至位元線BL 5 i 〇上,而不受其寄生電 容之干擾。 圖9所不為此改良式訊號讀取架構之輸入電壓與時間 之關係圖,電谷式Μ感測元件之讀取或非讀取狀態由字元 線5 0 9與脈衝字兀線5 1 2上之輸入電壓控制,量測端點5 i 8 的電壓值,即可獲知端點5 1 7所表示之第一電極板電壓 值。當電谷式被感測元件在非讀取之狀態下,即對第一電 極板與第二電極板間之電容2〇4充電時,字元線5〇9與脈衝 字元線512上之輸入電壓將為〇v,端點51?電壓值同第一電 極板之接點5 1 4為Vdd ;由非讀取狀態切換至讀取狀態前, 脈衝字元線512須提早切換輸入電壓至5V,使pm〇s 513傳 輸穩定的訊號給第一電極板接點5 1 4以提早切斷Vdd,再切 換字元線509上之輸入電壓至5V ;讀取狀態下,電容2 04之 讀出訊號有兩種模式:(1 )指紋凸點使電容2 〇 4受壓,Type metal oxide semiconductor 5 1 6 # 6R, π &] is very many, and the voltage between the point 5 1 7 and the source extreme point 5 1 8 is close to two kilograms, by measuring the bit line BL 51〇 Through the terminal 51: the voltage change to the source P side coupler 511, the voltage value of the terminal 51, that is, the first electrode plate can be obtained. Anyway, ^ ^ ^ 疋 Therefore, the signal of this capacitive micro-sensing element can be correctly transmitted to the bit line BL 5 i 〇 without being affected by its parasitic capacitance. Figure 9 is a diagram of the relationship between the input voltage and time for this improved signal reading architecture. The reading or non-reading state of the electric valley M sensing element is composed of the word line 5 0 9 and the pulse word line 5 1 The input voltage control on 2 measures the voltage value of the terminal 5 i 8 to obtain the voltage value of the first electrode plate represented by the terminal 5 1 7. When the electric valley-type sensed element is in a non-reading state, that is, the capacitor 204 between the first electrode plate and the second electrode plate is charged, the word line 509 and the pulse word line 512 The input voltage will be 0v, and the voltage value at the terminal 51? Is the same as the contact 5 1 4 of the first electrode plate as Vdd; before switching from the non-reading state to the reading state, the pulse word line 512 must switch the input voltage to 5V, so that pm0s 513 transmits a stable signal to the first electrode plate contact 5 1 4 to cut off Vdd early, and then switch the input voltage on the word line 509 to 5V; in the reading state, the capacitance 2 04 reads There are two modes of the output signal: (1) the fingerprint bump makes the capacitor 2 04 be pressed,

Cmp為極大值,則端點5 1 7之第一電極板電壓值為極大值; (2 )指紋凹點使電容204不受壓時,Cmp為極小值,則端 點517之第一電極板電壓值為極小值;dummy電壓值為其平 均值。讀取狀態下所量測之端點5 1 8之電壓變化與端點5 1 7 之電壓變化一致。藉由比較構成此一指紋辨識裝置之每一 個電容式壓力微感測元件之電壓變化,即可得一指紋圖Cmp is the maximum value, then the voltage of the first electrode plate at the terminal 5 1 7 is the maximum value; (2) When the fingerprint pits make the capacitor 204 not under pressure, Cmp is the minimum value, then the first electrode plate at the end 517 The voltage value is a minimum; the dummy voltage value is its average. The voltage change of the terminal 5 1 8 measured in the reading state is consistent with the voltage change of the terminal 5 1 7. By comparing the voltage changes of each capacitive pressure micro-sensing element constituting this fingerprint identification device, a fingerprint image can be obtained

第21頁 541503 五、發明說明(14) 像。 在較佳實施例之詳細說明中所提出之具體實施例僅用 以方便說明本發明之技術内容,而非將本發明狹義地限制 於上述實施例,在不超出本發明之精神與下述之申請專利 範圍的情況下,所作的種種變化實施,仍屬於本發明之範 圍。P.21 541503 V. Description of the invention (14). The specific embodiments proposed in the detailed description of the preferred embodiments are only used to facilitate the description of the technical content of the present invention, rather than limiting the present invention to the above embodiments in a narrow sense, without exceeding the spirit of the present invention and the following In the case of applying for a patent, the various changes made are still within the scope of the present invention.

第22頁 541503 圖式簡單說明 圖1為本發明之一實施例之電容式壓力微感測元件陣 列之立體結構圖; 圖2為本發明之一電容式壓力微感測元件内部之平行 板電容與訊號讀取電路之配置圖; 圖3為圖1之電容式壓力微感測元件陣列與手指接觸時 之剖面圖; 圖4A至4C為圖1所示之電容式壓力微感測元件陣列沿 圖1之線B-B之剖面製造程序圖; 圖5為本發明另一實施例之電容式壓力微感測元件之 改良製程示意圖; 圖6為一習用之動態隨機存取記憶體之讀取架構圖; 圖7為本發明之電容式壓力微感測元件陣列之詳細架 構圖; 圖8為本發明之指紋辨識裝置之改良式訊號讀取架構 圖。 圖9為本發明之指紋辨識裝置之改良式訊號讀取架構 之輸入電壓與時間之關係圖。 符號之說明 10 電容式壓力微感測元件 20 平行板電容 2 0 0 矽基板 201 懸浮薄板Page 541503 Brief Description of Drawings Figure 1 is a three-dimensional structure diagram of a capacitive pressure micro-sensing element array according to an embodiment of the present invention; Figure 2 is a parallel plate capacitor inside a capacitive pressure micro-sensing element according to one of the present invention And signal reading circuit configuration diagram; Figure 3 is a sectional view of the capacitive pressure micro-sensing element array of FIG. 1 in contact with a finger; FIGS. 4A to 4C are along the capacitive pressure micro-sensing element array shown in FIG. FIG. 1 is a manufacturing process diagram of a line BB; FIG. 5 is a schematic diagram of an improved manufacturing process of a capacitive pressure micro-sensing element according to another embodiment of the present invention; FIG. 6 is a reading architecture diagram of a conventional dynamic random access memory Figure 7 is a detailed architecture diagram of the capacitive pressure micro-sensing element array of the present invention; Figure 8 is an improved signal reading architecture diagram of the fingerprint identification device of the present invention. FIG. 9 is a relationship diagram between input voltage and time of an improved signal reading architecture of a fingerprint identification device of the present invention. Explanation of symbols 10 Capacitive pressure micro-sensing element 20 Parallel plate capacitor 2 0 0 Silicon substrate 201 Floating sheet

第23頁 541503Page 23 541503

圖式簡單說明 202 懸浮薄板之連接腳 202a 懸浮薄板之連接腳之第 2 0 2b 懸浮薄板之連接腳之第 203 凸塊 204 平行板電容之第一電極 205 平行板電容之第一電極 30 訊號讀取電路 303 第n-2金屬間介電層 304 第η-1層金屬層 3 04a 鈦 3 04b 紹合金金屬層 305 第η-1層金屬間介電層 306 第η層金屬層 307 保護層 307a 蝕刻窗口 308 凸塊 310 栓塞金屬 310a 金屬凸塊 40 指紋凸點 400 間隙 410 第一電極板 420 第二電極板 50 指紋凹點 500 儲存電容陣列 第24頁 541503 圖式簡單說明 501 資料讀寫控制 5 0 2 計時器 503 行前置解碼器 504 閉鎖預防 5 0 5 列解碼器 50 6 行解碼器 5 0 7 參考元 5 0 8 讀取放大器 5 0 9 字元線 5 0 9 & 奇字兀線 5 0 9b 偶字元線 510 位元線 ? 511 P型金屬氧化半導體源極隨耦器 512 脈衝字元線 513 連接至平行板電容之P型金屬氧化半導體 514 第一電極板之接點 515 第二電極板之接點 516 P型金屬氧化半導體源極隨耦器之P型金屬氧化半 導體 517 源極隨耦器之P型金屬氧化半導體之閘極端點 518 源極隨耦器之P型金屬氧化半導體之源極端點 519 源極隨耦器之N型金屬氧化半導體電晶體 52 0 反轉器 60 指紋凹點The drawing briefly explains 202 the connecting pin of the floating sheet 202a the 2nd 0 2b of the connecting leg of the floating sheet 203 the bump 204 the first electrode of the parallel plate capacitor 205 the first electrode of the parallel plate capacitor 30 signal reading Take circuit 303 n-2 intermetal dielectric layer 304 n-1 metal layer 3 04a titanium 3 04b alloy metal layer 305 n-1 intermetal dielectric layer 306 n metal layer 307 protective layer 307a Etching window 308 Bump 310 Embed metal 310a Metal bump 40 Fingerprint bump 400 Gap 410 First electrode plate 420 Second electrode plate 50 Fingerprint pit 500 Storage capacitor array page 24 541503 Illustration of simple illustration 501 Data read-write control 5 0 2 Timer 503 Row Pre-Decoder 504 Blocking Prevention 5 0 5 Column Decoder 50 6 Row Decoder 5 0 7 Reference Element 5 0 8 Read Amplifier 5 0 9 Word Line 5 0 9 & Odd Line 5 0 9b Even word line 510 bit line? 511 P-type metal oxide semiconductor source follower 512 Pulse word line 513 P-type metal oxide semiconductor connected to parallel plate capacitor 514 Contact 515 of the first electrode plate Electrode plate contact 516 P-type metal oxide semiconductor source follower P-type metal oxide semiconductor 517 P-type metal oxide semiconductor gate extreme point of source follower 518 P-type metal oxide semiconductor source follower Source extreme point 519 N-type metal oxide semiconductor transistor of source follower 52 0 Inverter 60 Fingerprint pit

第25頁 541503Page 541 503

圖式簡單說明 70 BL Cmp Cpb RIE PWL Vdd WL 手指 位元線 平行板電容之第一電極板與第二電極板間之電容 平行板電容之多晶矽層與矽基板間之電容 反應離子蝕刻 脈衝字元線 電流源 字元線Schematic description of 70 BL Cmp Cpb RIE PWL Vdd WL Finger bit line Parallel plate capacitor Capacitance between the first electrode plate and the second electrode plate Capacitance reaction between the polycrystalline silicon layer of the parallel plate capacitor and the silicon substrate Ion etching pulse character Line current source character line

第26頁Page 26

Claims (1)

541503 六、申請專利範圍 1. 一種電容式壓力微感測元件,以作為指紋辨識之用 係包含: 一基 一平 板, 行板電 容,製作於該基板上方,用以感應指紋凹 凸面所施加之壓力,此平行板電容之結構至少包含: 一第一電極板,位於此平行板電容之底部,且固定 於該基板之上; 一第二電 有至少一支連接 腳係用以支撐該 一端則固定於該 一空氣間 間;及至少一凸 一訊號讀 及輸出該平行板 一高分子 作為一手指接觸 極板,位於此平行板電容之上部,係為具 腳之一懸浮薄板,其中,該至少一支連接 懸浮薄板,其一端連接至該懸浮薄板,另 基板上; 隙,位於該第一電極板與該第二電極板之 塊,位於該第二電極板上方之中央部份; 取電路,位於該平行板電容旁,用以讀取 電容所傳遞之訊號;以及 保護層,用以保護此壓力微感測元件,並 面0 2. 如申請專利範圍第1項之電容式壓力微感測元件,其 中,該第一電極板至少包含一第一金屬層,該第二電 極板至少包含一第二金屬層。 3. 如申請專利範圍第2項之電容式壓力微感測元件,其 中,該第一電極板更包含541503 VI. Application for patent scope 1. A capacitive pressure micro-sensing element for fingerprint identification includes: a base, a flat plate, and a line capacitor, which is manufactured above the substrate and used to sense the applied surface of the uneven surface of the fingerprint. The structure of the parallel plate capacitor includes at least: a first electrode plate, which is located at the bottom of the parallel plate capacitor and is fixed on the substrate; a second electrical line has at least one connecting leg for supporting the one end; It is fixed in the air space; and at least one convex one signal reads and outputs the parallel plate. A polymer is used as a finger to contact the electrode plate, which is located above the parallel plate capacitor and is a suspended thin plate with feet. Among them, the At least one connected suspension plate, one end of which is connected to the suspension plate, and on the other substrate; a gap is located in a block between the first electrode plate and the second electrode plate, and is located in a central portion above the second electrode plate; Is located next to the parallel plate capacitor to read the signal transmitted by the capacitor; and a protective layer is used to protect the pressure micro-sensing element, and faces 0 2. The patentable scope of application of the first item capacitive pressure differential sensing element 1, wherein, the first electrode plate comprises at least a first metal layer, the second electrode plate includes at least a second metal layer. 3. For the capacitive pressure micro-sensing element according to item 2 of the patent application scope, wherein the first electrode plate further includes 541503 六、申請專利範圍 一第一金屬間介電層,係介於該基板與該第一金屬 層之間;及 複數個金屬栓塞柱,係製作於該第一金屬間介電層 之間;以及 該第二電極板更包含 一第二金屬間介電層,係位於該第二金屬層下方; 及 一保護層,係位於該第二金屬層上方。· 4. 如申請專利範圍第3項之指紋辨識用壓力微感測元件, 其中,該複數個金屬栓塞柱,係凸出於該第一金屬間 介電層表面,用以在該第一金屬間介電層與該第一金 _屬層間形成複數個金屬凸塊。 5. 如申請專利範圍第1、2、3或4項之電容式壓力微感測 元件,其中該第二電極板上方之該至少一凸塊之較佳 高度範圍為2微米至1 0微米之間。 6. 一種電容式壓力微感測元件之製造方法,此製造方法 係為一次微米η層鋁金屬積體電路製程,至少包含下列 步驟: 沉積一第η-2層金屬間介電層; 於該第η-2層金屬間介電層間製作複數個介電層穿 子L ;541503 6. Scope of patent application: a first intermetallic dielectric layer is interposed between the substrate and the first metal layer; and a plurality of metal plugs are fabricated between the first intermetallic dielectric layer; And the second electrode plate further includes a second intermetal dielectric layer located under the second metal layer; and a protective layer located above the second metal layer. · For example, the pressure micro-sensing element for fingerprint identification according to item 3 of the patent application scope, wherein the plurality of metal plugs are protruded from the surface of the first intermetal dielectric layer and are used for the first metal. A plurality of metal bumps are formed between the inter-dielectric layer and the first metal layer. 5. For the capacitive pressure micro-sensing element according to item 1, 2, 3, or 4, in which the preferred height range of the at least one bump above the second electrode plate is between 2 micrometers and 10 micrometers. between. 6. A method for manufacturing a capacitive pressure micro-sensing element, which is a one-time micron η-layer aluminum metal integrated circuit manufacturing process, which includes at least the following steps: depositing a η-2 layer intermetal dielectric layer; A plurality of dielectric layer penetrators L are made between the η-2 intermetal dielectric layers; 第28頁 541503 六、申請專利範圍 沉積一鎢金屬膜,並完成回蝕步驟,以在該第η-2層 金屬間介電層間構成複數個金屬栓塞柱; 沉積第η-1層金屬層,此第η-1層金屬層係包含一層 欽、一層铭合金及一層氮化鈦; 透過光阻於預定之位置上,去除部分面積之該第η- 1 層金屬層; 沉積第η - 1層金屬間介電層; 於該第η-1層金屬間介電層上方,沉積第η層金屬 層,此金屬層係為一銘金屬層; 透過光阻於預定之位置上,去除部份面積之該第η層 金屬層; 沉積一層保護層; 於該保護層上方,透過光阻於預定之位置上定義出 一保護層蝕刻窗; 去除該蝕刻窗内之該保護層、該第η- 1層金屬間介電 層及該第η-1層金屬層之氮化鈦,以露出該第η-1層金屬層 之鋁合金表面; 於該第η-1層金屬層之中央部份、該保護層上方,製 作至少一凸塊; 選擇性地去除該第η-1層金屬層中之該鋁合金,留下 ® 底部之該鈦金屬,以製作出一空氣間隙,使其上方之該第 η-1層金屬間介電層、該第η層金屬層及該保護層,形成由 至少一支連接腳支撐之一懸浮薄板結構,並與該第η- 1層 金屬層之鈦金屬形成一平行板電容;以及Page 28 541503 6. Apply for a patent to deposit a tungsten metal film and complete the etch-back step to form a plurality of metal plugs between the η-2 intermetal dielectric layer; deposit the η-1 metal layer, The η-1 metal layer includes a layer of metal, a layer of alloy, and a layer of titanium nitride; a part of the area of the η-1 metal layer is removed through a photoresist at a predetermined position; and a layer of η-1 is deposited An intermetal dielectric layer is deposited on top of the η-1 intermetal dielectric layer, and an η metal layer is deposited. The metal layer is a metal layer; a part of the area is removed through a photoresist at a predetermined position The n-th metal layer; depositing a protective layer; defining a protective layer etching window at a predetermined position through the photoresist above the protective layer; removing the protective layer and the η-1 from the etching window Intermetal dielectric layer and titanium nitride of the η-1 metal layer to expose the aluminum alloy surface of the η-1 metal layer; in the central part of the η-1 metal layer, the Above the protective layer, at least one bump is made; and the n-th is selectively removed. The aluminum alloy in 1 metal layer, leaving the titanium metal at the bottom to create an air gap, so that the η-1 intermetal dielectric layer, the η metal layer and the A protective layer, forming a suspended thin plate structure supported by at least one connecting leg, and forming a parallel plate capacitor with the titanium metal of the η-1th metal layer; and 第29頁 541503 六、申請專利範圍 在此元件表面上方,喷灑塗佈一高分子保護層。 7. 如申請專利範圍第6項之電容式壓力微感測元件之製造 方法,其中,此方法更包含以下步驟: 在沉積第η-1層金屬層前,利用反應式離子餘刻,回 蝕該第η-2層金屬間介電層至一深度,以暴露出複數個金 屬栓塞柱。 8. 如申請專利範圍第6或7項之電容式壓力微感測元件之 製造方法,其中,該η值至少大於2。 9. 如申請專利範圍第6或7項之電容式壓力微感測元件之 製造方法,其中,該凸塊係為一光阻或金屬材料。 10. 如申請專利範圍第6或7項之電容式壓力微感測元件之 製造方法,其中,去除該鋁合金之選擇性蝕刻液係為 磷酸、硝酸及醋酸之混合酸液。 11. 如申請專利範圍第6或7項之電容式壓力微感測元件之 製造方法,其中,該高分子保護層之材料係為聚乙烯 胺。 12. 如申請專利範圍第7項之電容式壓力微感測元件之製 造方法,其中,利用反應式離子蝕刻回蝕該第η-2層Page 29 541503 6. Scope of patent application Spraying a polymer protective layer on the surface of this component. 7. The manufacturing method of the capacitive pressure micro-sensing element according to item 6 of the patent application, wherein the method further includes the following steps: before depositing the η-1 metal layer, using reactive ion etching to etch back The n-2th intermetallic dielectric layer has a depth to expose a plurality of metal plugs. 8. If the method of manufacturing a capacitive pressure micro-sensing element according to item 6 or 7 of the patent application scope, wherein the value of η is at least greater than two. 9. The method for manufacturing a capacitive pressure micro-sensing element according to item 6 or 7 of the patent application, wherein the bump is a photoresist or a metal material. 10. The manufacturing method of the capacitive pressure micro-sensing element according to item 6 or 7 of the patent application scope, wherein the selective etching solution for removing the aluminum alloy is a mixed acid solution of phosphoric acid, nitric acid and acetic acid. 11. The manufacturing method of the capacitive pressure micro-sensing element according to item 6 or 7 of the patent application scope, wherein the material of the polymer protective layer is polyvinylamine. 12. The method for manufacturing a capacitive pressure micro-sensing element according to item 7 of the scope of patent application, wherein the η-2 layer is etched back by reactive ion etching 第30頁 541503 六、申請專利範圍 金屬間介電層之該 Λ /衣度至少大於〇· 1微米 13. 一 習用動 裝置所 方法包 構’包 每一位 每一平 容之電 14. -習用動 裝置所 方法包 構,包 每一位 法,此方法係利用- 包含 命记匕體(dRam )之電路結構讀取該 =3之一電容式壓力微感測元陣列之訊號,此 ^ ^白用動態隨機存取記憶體(DRAM )之電路結 :該:ΐ : 3、:組字元線、-.組位址解碼器; 元線二=f力微感測元陣列之每一平行板電容及 π線分別連接上一電流源; 配^ ρ型金屬氧化半導體開 ㈧s 仃板電容與每一位元線之間; ch)於 再利用該p型令屬_ ^ , 壓傳# $ 1 π _屬 半導體開關將每一平行板電 &傳遞至其所連接之位元線上。 種指紋辨識裝詈> 4 π Μ 能 衣置之矾嬈碩取方法,此方法係利用一 悲k機存取記情轉r n D Λ Μ \ 4八 U篮(DRAM )之電路結構讀取該 =含之-電容式壓力微感測 之訊號 配置*習用動態隨德 人一 ’思機存取記憶體(DRAM )之電路結 組字元線、-組位址解碼器; 將:電各式壓力微感測元陣列之每-平行板電容及 70線分別連接上—電流源; 配置一P型金屬氧化半導體源極隨耦器(PM0SPage 30 541503 VI. The scope of the patent application The intermetallic dielectric layer has a Λ / clothing degree of at least greater than 0.1 micron 13. A conventional method of using a mobile device to package 'encapsulates each and every flat electricity 14.- Conventional The method of the moving device is composed of each bit method. This method uses a circuit structure including a dram body (dRam) to read the signal of one of the capacitive pressure micro-sensing element arrays = 3, this ^ ^ White use dynamic random access memory (DRAM) circuit structure: the: ΐ: 3 :: group word line,-. Group address decoder; line two = f force micro-sensing element array each parallel The plate capacitor and the π line are respectively connected to a current source; the ^ ρ-type metal oxide semiconductor switch ㈧ 仃 between the plate capacitor and each bit line; ch) reuse the p-type order _ ^, 压 传 # $ A 1 π _ belongs to a semiconductor switch that transfers each parallel plate & to the bit line to which it is connected. A fingerprint identification device > 4 π Μ can be placed in alum, which is a method to read the circuit structure of rn D Λ Μ \ 48 U basket (DRAM) The = contains-the signal configuration of the capacitive pressure micro-sensing * customary dynamics with the German Renyi's memory access memory (DRAM) circuit grouping character lines,-group address decoder; will: Each parallel-plate capacitor and 70 wires of the pressure micro-sensing element array are respectively connected to a current source; a P-type metal oxide semiconductor source follower (PM0S 541503 六、申請專利範圍 Source Follower)於每一平行板電容與每一位元線之 間; 再利用該P型金屬氧化半導體源極隨耦器將每一平 行板電容之電壓傳遞至其所連接之位元線上,以避免每一 位元線之寄生電容的干擾。541503 VI. Patent application scope Source Follower) between each parallel plate capacitor and each bit line; and then use the P-type metal oxide semiconductor source follower to transfer the voltage of each parallel plate capacitor to its connection Bit lines to avoid the interference of parasitic capacitance of each bit line. 第32頁Page 32
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7715601B2 (en) 2005-08-05 2010-05-11 Himax Technologies Limited Fingerprint acquisition apparatus and method therefor
US7822239B2 (en) 2007-08-10 2010-10-26 Egis Technology, Inc. Fingerprint sensing device having flexible printed circuit board serving as signal transmission structure and the method of manufacturing the same
US7915722B2 (en) 2006-12-26 2011-03-29 Egis Technology Inc. Information sensing device with electroconductive structure and molded body surrounding each other
TWI557625B (en) * 2015-07-31 2016-11-11 映智科技股份有限公司 Capacitive fingerprint identification device and manufacturing method thereof
CN106548116A (en) * 2015-09-22 2017-03-29 神盾股份有限公司 Array sensing device further and its method for sensing
US9824257B2 (en) 2014-03-18 2017-11-21 J-Metrics Technology Co., Ltd. All-flat sensor with exposed colorful member and electronic device using such sensor
CN113467648A (en) * 2021-07-01 2021-10-01 维沃移动通信有限公司 Electronic device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7715601B2 (en) 2005-08-05 2010-05-11 Himax Technologies Limited Fingerprint acquisition apparatus and method therefor
US7915722B2 (en) 2006-12-26 2011-03-29 Egis Technology Inc. Information sensing device with electroconductive structure and molded body surrounding each other
US7822239B2 (en) 2007-08-10 2010-10-26 Egis Technology, Inc. Fingerprint sensing device having flexible printed circuit board serving as signal transmission structure and the method of manufacturing the same
US9824257B2 (en) 2014-03-18 2017-11-21 J-Metrics Technology Co., Ltd. All-flat sensor with exposed colorful member and electronic device using such sensor
TWI557625B (en) * 2015-07-31 2016-11-11 映智科技股份有限公司 Capacitive fingerprint identification device and manufacturing method thereof
CN106548116A (en) * 2015-09-22 2017-03-29 神盾股份有限公司 Array sensing device further and its method for sensing
US10282578B2 (en) 2015-09-22 2019-05-07 Egis Technology Inc. Array sensor and sensing method thereof
CN106548116B (en) * 2015-09-22 2020-09-15 神盾股份有限公司 Array type sensing device and sensing method thereof
CN113467648A (en) * 2021-07-01 2021-10-01 维沃移动通信有限公司 Electronic device

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