TW540106B - Manufacturing process of increasing trench capacitance - Google Patents

Manufacturing process of increasing trench capacitance Download PDF

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TW540106B
TW540106B TW91116434A TW91116434A TW540106B TW 540106 B TW540106 B TW 540106B TW 91116434 A TW91116434 A TW 91116434A TW 91116434 A TW91116434 A TW 91116434A TW 540106 B TW540106 B TW 540106B
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Taiwan
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trench
scope
item
increasing
patent application
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TW91116434A
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Chinese (zh)
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Li-Wu Tsao
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Nanya Technology Corp
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Abstract

The invention provides a kind of manufacturing process for increasing the trench capacitance. The invention is suitable for use in a substrate having a pad layer structure and a trench, and includes the following steps: forming a ring shape insulation layer on the upper part of the trench sidewall; performing the first stage of ion implantation process to implant ions into the trench sidewall in a specified angle for destroying the substrate lattice structure of the trench sidewall uncovered by the ring-shaped insulation layer; performing the second stage of ion implantation process to vertically implant ions into the trench bottom part for destroying the substrate lattice structure of the trench bottom part; and conducting an etching process to remove the destroyed substrate part inside the trench.

Description

540106 五、發明說明,(1) 【發明領域 特 本發明係有關於半導體積體電路之溝槽電容製程 別是有關於一種增加溝槽電容之製程。 王 【習知技術說明】 一般而言’目前廣泛使用之動態隨機存取記憶體 (Dynamic Random Access Memory; DRAM)中的電容哭係 由兩導電層表面(即電極板)隔著一絕緣物質而構為矽 電容器'儲存電荷之能力係由絕緣物質之厚度、電極 ^ 面積及絕緣物質的電氣性質所決定。隨著近年來半: 程設計皆朝著縮小半導體元件尺寸以提高密度之方向_私 展,圯憶體中記憶胞的基底面積必須不斷減少使積^ 能容納大量記憶胞而提高密度,.但同時’記憶胞電容 極板部分必須有足夠之表面積以儲存充足的電荷。 ” 然而在尺寸持續地細微化的情況下,動態隨機存 憶體中的溝槽儲存結點電容(trench storage⑽心 ° capacltance)亦隨著縮小,因此必須設法增加儲存電 維持記憶體良好的操作性能。 因此,有需要發展增加儲存電容的方法,例如蝕 導體基底以j廣大溝槽底部而形成瓶型溝槽(b〇tUe sh^ trenc^i),w已廣泛使用於增加DRAM之儲存電容的方法, 2如藉由增加溝槽底部的寬度以提高表面積形成一瓶型電 容(bottle shaped capacitor)。以下絲aa、, 的製造方法說明如後,首先,心夂第 〇、升瓦型溝槽 自无明參閱第1Α圖,卷於一矽基540106 V. Description of the invention, (1) [Field of the Invention] The present invention relates to a process for manufacturing a trench capacitor of a semiconductor integrated circuit. In particular, it relates to a process for increasing a trench capacitor. Wang [Known Technical Description] Generally speaking, the capacitors in Dynamic Random Access Memory (DRAM), which is currently widely used, are formed by the surfaces of two conductive layers (ie, electrode plates) with an insulating material in between. The ability of a silicon capacitor to store charge is determined by the thickness of the insulating material, the area of the electrode, and the electrical properties of the insulating material. With the recent half year: process design has been toward the direction of reducing the size of semiconductor elements to increase density _private exhibition, the base area of memory cells in the memory must continue to reduce so that the product can accommodate a large number of memory cells to increase the density, but At the same time, the memory cell capacitor plate must have sufficient surface area to store sufficient charge. ”However, in the case of continuous miniaturization, the trench storage node capacitance (capacltance) in the dynamic random memory also shrinks. Therefore, it is necessary to increase the storage power to maintain the good operating performance of the memory. Therefore, there is a need to develop methods for increasing storage capacitance, such as etching a conductor substrate to form a bottle-shaped trench (b0tUe sh ^ trenc ^ i) at the bottom of a large trench. W has been widely used to increase the storage capacitance of DRAM. Method 2, such as forming a bottle shaped capacitor by increasing the width of the bottom of the trench to increase the surface area. The manufacturing method of the following wires aa,, is explained below. From ignorance see Figure 1A, rolled on a silicon base

540106 五、發明說明(2) 底1 0上形成 圖案為蝕刻 一溝槽1 4, 18 ° 然後, 於部分該溝 後,沉積一 並可延伸至 以及非等向 如此,即形 上。 一塾層(pad layer)12圖案,然後以該墊層。 罩幕,利用乾蝕刻方式而於該矽基底丨〇中曰 該溝槽14具有—上部周圍部16與—下部周圍部 請參閱第1B圖,例如先沉積—光阻層(未圖示 才曹1 4内而覆蓋住該溝槽丨4之下部周圍部丨8。之 複aa石夕犧牲層2 0於該溝槽1 4上部周圍邱彳β 該塾層12上。然後再除去該光阻層 性去除位於該墊層12上方的複晶石夕犧牲層2〇。 成複晶矽犧牲層20於溝槽14之上部周圍部16 接者,進行一濕蝕刻製程(亦稱wet bottle蝕刻製 牙=),以氨水或稀釋氫氣酸溶液(dllute HF s〇luti〇n)等 向性蝕刻未被複晶石夕犧牲層20保護的溝槽14下側之矽基底 ^ ’而形成類似瓶狀的溝槽14之下部周圍部22, ⑶ 戶厅示。 然而上述製程所須步驟複雜’需以分別之製程先形成 /木溝槽再製作瓶型溝槽,由於蝕刻製程會形成錐形溝槽, 而無法形成深溝槽,且會有氫氣體產生等問題,而增加製 程的困難度及增加製程時間且不利於大量生'產。 另一傳統形成瓿型溝槽的方式主要係採用非等向性乾 蝕刻(anisotropic dry etching)方法,但是上述方法會 有設備及姓刻劑之限制且可能會造成溝槽側壁形成袋狀^和 硬罩幕厚度等製程上之問題。乾餘刻方法將溝瓚底部擴大540106 V. Description of the invention (2) The pattern formed on the bottom 10 is to etch a trench 14, 18 °. Then, after part of the trench, deposit one and extend to and anisotropy, that is, shape. A pad layer 12 pattern, and then the pad layer. The mask is formed on the silicon substrate by dry etching. The trench 14 has—an upper peripheral portion 16 and a lower peripheral portion. Please refer to FIG. 1B. For example, a photoresist layer is deposited first (not shown). 14 inside and covers the trench 丨 4 and the lower peripheral part 丨 8. The complex aa stone evening sacrificial layer 2 0 is on the upper part of the trench 1 4 Qiu 彳 β on the 塾 layer 12. Then the photoresist is removed. The sacrificial polycrystalline sacrificial layer 20 located above the cushion layer 12 is removed in a layered manner. A polycrystalline silicon sacrificial layer 20 is formed on the upper part of the trench 14 and the peripheral part 16 is connected to a wet etching process (also known as wet bottle etching). Tooth =), the silicon substrate under the trench 14 that is not protected by the polycrystalline sacrifice layer 20 is isotropically etched with ammonia or dilute hydrogen acid solution (dllute HF solutin) to form a bottle-like shape The surrounding area of the lower part of the groove 14 is 22, ⑶ it is shown in the hall. However, the steps required for the above process are complicated. 'A separate process is required to form a wood groove first, and then a bottle groove is formed. Due to the etching process, a tapered groove is formed. Deep trenches cannot be formed, and there will be problems such as generation of hydrogen gas, which increases the difficulty of the process and Adding process time is not conducive to large-scale production. Another traditional method of forming the ampoule groove is to use anisotropic dry etching, but the above method has restrictions on equipment and last name etchants. May cause process problems such as the formation of pockets on the side walls of the trench and the thickness of the hard cover. The dry-etching method will enlarge the bottom of the trench

540106 五、發明說明(3) 的方式的效 有鑑於 之製程,特 自動選擇性 夠有效地擴 本發明 墊層結構及 上部形成一 離子以特定 絕緣層所覆 離子植入製 底部之基底 基底部分。 果有限,並 此’本發明 別是利用離 飯刻,適用 大溝槽底部 知1供一種增 溝槽之基底 環狀絕緣層 之入射角度 i之溝槽側 程,將離子 晶格結構; 且較難以控 的主要目係 子植入破壞 於動態隨機 而增加DRAM 加溝槽電容 ’包括下列 ;施行第一 植入此溝槽 壁之基底晶 垂直植入此 以及蝕刻去 制。 提供一 晶格結 存取記 的儲存 之製程 步驟: 階段離 侧壁, 格結構 溝槽底 除受到 種增加 構及使 憶體的 電容。 ,適用 於此溝 子植入 以破壞 »施行 部,以 破壞之 溝槽電容 用磷酸來 電容,能 於一具有 槽側壁之 製程,將 未被環狀 第二階段 破壞溝槽 溝槽内之540106 V. Description of the invention (3) The effect of the method of the invention is based on the process. It is automatically and selectively enough to effectively expand the cushion structure of the invention and the upper part to form an ion implanted with a specific insulating layer. . If the results are limited, the present invention uses the engraving method to apply the ion side lattice structure to the groove side distance of the incident angle i of the ring-shaped insulating layer for increasing the base of the trench. The uncontrollable main objective is to increase the DRAM and the trench capacitance by destroying the dynamic randomness, including the following; the first implantation of the base crystal of this trench wall is vertically implanted and the etching is performed. Provide a manufacturing process for the storage of the lattice junction memory. Steps are: step away from the side wall, the lattice structure, and the trench bottom is subject to an increase in the structure and capacitance of the memory. It is suitable for this trench implantation to destroy the »Executive part to destroy the trench capacitor. Capacitor with phosphoric acid can be used in a process with trench sidewalls, which will not damage the trench in the second stage.

其他目的、特徵、和優點能更明 實施例,並配合所附圖式,作詳 為讓本發明之上述和 顯易懂,下文特舉出較佳 細說明如下: & 實施例Other objects, features, and advantages can make the embodiments clearer, and in conjunction with the accompanying drawings, to make the above and the present invention more understandable, the following are particularly preferred and detailed descriptions are as follows: & Examples

半導底1:參Λ第二圖’在-基底,例如:是㈣構成的 1 η 9接士今拥& ^成一由氮化物層1 〇 4和墊氧化物層 f成之墊層結構106。例如是以熱氧化法(thermal 0X1 ajion形成厚度大約為1〇〇埃的墊氧化物層d m於墊氧化物二02上用化學氣相沉積法形成一氮化物層 曰ί υ z上。然後,利用微影程序形成一光阻Semiconducting base 1: Refer to the second picture 'in-base', for example: a 1 η 9 contactor formed by ㈣ is formed into a pad structure composed of a nitride layer 104 and a pad oxide layer f 106. For example, a thermal oxidation method (thermal 0X1 ajion) is used to form a pad oxide layer dm with a thickness of about 100 angstroms on the pad oxide 202 and a nitride layer is formed by chemical vapor deposition. Then, Photolithography

0548-8141TWF(N);90060;ycchen.ptd0548-8141TWF (N); 90060; ycchen.ptd

540106540106

Ξ ί (未顯不)於氮化物層1 〇 4上。接著,卩光阻圖案作為 丨去除未被光阻圖案覆蓋之氮化物層104和位於 ,、底下的墊氧化物層1〇2,形成一由氮化物層1〇4和墊氧、化 物層1 〇 2構成之墊層結構1 〇 6。然後,以光阻圖案和墊層結 作為钱刻罩幕,*刻去除未被墊層、结構106覆蓋之基 底100,例如利用反應離子蝕刻法(Reactive Ι〇ηΞ ί (not shown) on the nitride layer 104. Next, the photoresist pattern is used to remove the nitride layer 104 and the underlying pad oxide layer 102, which are not covered by the photoresist pattern, to form a nitride layer 104 and a pad oxygen and compound layer 1. 〇2 structure of the cushion structure 〇6. Then, the photoresist pattern and the pad layer are used as a mask to remove the substrate 100 that is not covered by the pad layer and the structure 106, for example, using a reactive ion etching method (Reactive Ion).

Etching; R ιΕ),而蝕刻出一溝槽工〇8。之後,將光阻去 除’其結果如第2A圖所示。Etching; R E), and a trencher is etched. Thereafter, the photoresist is removed ', and the result is shown in Fig. 2A.

、刀八人,參如、第2 B圖’於溝槽丨〇 8侧壁之上部形成一環 狀%緣層(⑶Uar 〇xide)1 1〇,環狀絕緣層i ι〇例如利用氧 法或化學氣相沈積法以形成一氧化物層1 1 0。環狀絕緣 二i 〇之、製程包括應用現行之各種形成方法,例如利用保 護層及犧牲層結構來形成環狀絕緣層,但並無一定之限 然後,请麥照第2C圖,施行第一階段離子植入製程 一 將離子以特疋之入射角度植入溝槽1 〇 8之側壁,以破 =被環狀絕緣層110戶斤覆蓋之溝槽1〇8側壁之基底1〇〇之 曰^ σ結構。為了使整個未被環狀絕緣層丨丨〇所覆蓋之溝槽 ^8側壁之晶格結構能全面性地被破壞,此時可將基底1〇〇 it由=旋轉0度、90度、180度及27 0度分別進行四次離子 入衣私。離子植入製程所使用之離子,例如是磷離子、 石申離子或屬於鈍氣離子的氬離子或其他純氣的料,以特 1的入射角度植入溝槽108之側壁,此特定的角度約與法 線成〇 - 45度,料植入的能量會因離子的種響與重量的Eighteen people, see for example, Figure 2B. 'A ring% margin layer (⑶Uar × ide) 1 1〇 is formed on the upper part of the side wall of the trench 丨 〇8, and the ring-shaped insulating layer i ι〇, for example, using the oxygen method Or chemical vapor deposition to form an oxide layer 1 1 0. The process of ring insulation 2 i 〇 includes the application of various existing formation methods, such as the use of protective layer and sacrificial layer structure to form the ring insulation layer, but there is no certain limit. Then, please Mai according to Figure 2C, the first Stage I ion implantation process: Ions are implanted into the sidewall of the trench 108 at a special incident angle, and the substrate 100 of the sidewall of the trench 108 is covered by a ring-shaped insulating layer 110 kg. ^ σ structure. In order to completely destroy the lattice structure of the trench ^ 8 sidewall not covered by the ring-shaped insulating layer, the substrate 100it can be rotated from 0 °, 90 °, 180 ° at this time. Degrees and 270 degrees were carried out four times into the private clothing. The ions used in the ion implantation process, such as phosphorus ions, Shishen ions, or argon ions or other pure gases that are passive ions, are implanted into the sidewall of the trench 108 at a special incident angle. This specific angle About 0-45 degrees from the normal, the energy of the material implantation will be affected by the ion response and weight.

540106 五、發明說明(5) 不同而有差異,約為5KeV〜60KeV之間,離子植入劑量為 1E12 至 1E16 atoms/cm2 之間。 然後’清參照第2 D圖’施行第二階段離子植入製程 1 1 2,將離子以垂直植入溝槽丨〇 8之側壁,以破壞溝槽丨〇 8 底部之基底1 0 0之晶格結構。離子植入製程所使用之離 子,例如是磷離子、砷離子或屬於鈍氣離子的氬離子或其 他鈍氣的離子,離子植入的能量會因離子的種類與重量的 不同而有差異,約為5 K e V〜6 0 K e V之間,離子植入劑量為 1E12 至 1E16 atoms/cm2 之間。 請參照第2 E圖,經由上述第 及弟一階段無子植入製 程後,會在溝槽108内未被環狀絕緣層11〇所覆蓋之基底 1 0 0部分形成晶格結構被破壞之區域丨丨4。接著,可使用稀 釋氫氟酸溶液(dilute HF s〇iution)來清洗基底1〇()。 最後,請參照第2F圖,蝕刻去除溝槽丨〇8内未被環狀 絕緣層11 0所覆盍之基底1 〇 〇部分被破壞之區域丨丨4,因被 破壞之區域11 4之晶格已因為離子的撞擊而毀壞,於進行 此姓刻製程時,會有自動選擇性效果而完全去除被破壞之 區域Π4,姓刻劑可使用磷酸來進行飯刻。 藉由實驗來證明本發明之六# ^ αλ- 〇 a ^ o r, 十知乃灸功效,請參照第3A及3B圖, 顯示未經過及經過氬離子栢来 : 丁值入及磷酸蝕刻後之溝槽之掃瞄 式電子顯微鏡照片。第3B圖中婉矾—协7 & η # a _ _ ^ 口 τ經過虱離子植入及磷酸蝕刻 後之溝槽I度為201微米,輕莖β同 ,^ 竿乂弟3Α圖中原本未經過氬離子540106 V. Description of the invention (5) It varies from 5KeV to 60KeV, and the ion implantation dose is between 1E12 and 1E16 atoms / cm2. Then "clearly refer to Figure 2D" to perform the second stage ion implantation process 1 12 to implant the ions vertically into the sidewall of the trench 丨 〇8 to destroy the crystal at the bottom of the substrate 100 Lattice structure. The ions used in the ion implantation process are, for example, phosphorus ions, arsenic ions, or argon ions that are passive ions or other passive ions. The energy of ion implantation will vary depending on the type and weight of the ions. The ion implantation dose is between 5 K e V and 60 Ke V, and the ion implantation dose is between 1E12 and 1E16 atoms / cm2. Please refer to FIG. 2E. After the above-mentioned first and first stage sonless implantation process, the lattice structure of the substrate 100 which is not covered by the ring-shaped insulating layer 110 in the trench 108 will be damaged. Area 丨 丨 4. Next, the substrate 10 () may be cleaned using a dilute HF solution. Finally, please refer to FIG. 2F, and remove the part of the substrate 100 that is not covered by the ring-shaped insulating layer 11 0 in the trench etched by etching. The grid has been destroyed due to the impact of ions. When this last name carving process is performed, there will be an automatic selective effect to completely remove the damaged area Π4. The last name carving agent can use phosphoric acid for meal carving. The effect of the present invention # ^ αλ- 〇a ^ or by the experiment is demonstrated by experiments. Please refer to Figures 3A and 3B to show that it has not undergone and passed the argon ion palladium: Ting value and phosphoric acid etching Scanning electron microscope photo of trench. In Figure 3B, the vanadium-Xie 7 & η # a _ _ ^ mouth τ after lice ion implantation and phosphoric acid etching, the groove I degree is 201 microns, the light stem β is the same, ^ the original 3D Without argon ion

植入及填酸餘刻之溝槽宽声1 Q q W —,^ 見度193微米多出8微米,證明本發 明可貫際增加溝槽之表面積。 #The width of the trench after implantation and acid filling is 1 Q q W —, ^ The visibility is 193 micrometers and 8 micrometers more, which proves that the present invention can consistently increase the surface area of the trenches. #

0548-8141TWF(N);90060;ycchen.ptd 第8頁 540106 五、發明說明(6) 【本發明之特徵及優點】 本發明之增加溝槽電容之製程與習知技術相比較,本 發明的方法的優點至少有:(1).本發明的製程較習知技術 簡單。(2).晶格結構被破壞之區域,可以很容易地以填酸 來自動選擇性去除。(3).本發明製程無須增加額外之化學 品、製程及設備且容易大量生產。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍内,當可作各種之更動與潤飾,因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。0548-8141TWF (N); 90060; ycchen.ptd Page 8 540106 V. Description of the invention (6) [Features and advantages of the invention] Compared with the conventional technology, the process of increasing the trench capacitance of the invention is The advantages of the method are at least: (1). The manufacturing process of the present invention is simpler than conventional techniques. (2). The area where the lattice structure is destroyed can be easily and selectively removed by filling with acid. (3). The process of the present invention does not need to add additional chemicals, processes and equipment and is easy to mass produce. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

05488141TWF(N);90060;ycchen.ptd 第9頁 540106 圖式簡單說明 第1 A至1 C圖係顯示傳統形成瓶型溝槽之方法的製程剖 面圖。 ,第2 A至2F圖係根據本發明實施例之增加溝槽電容之製 程剖面圖。 第3 A圖係顯示未經過氬離子植入及磷酸蝕刻後之溝槽 之掃瞄式電子顯微鏡照片。 第3B圖係顯示經過氬離子植入及磷酸蝕刻後之溝槽之 掃瞄式電子顯微鏡照片。 【符號說明】 1 0 0〜半導體基底; 1 0 6〜墊層結構; 1 0 2〜塾氧化物層; 1 0 4〜氮化物層; 1 0 8〜溝槽; 11 0〜環狀絕緣層; 111〜第一階段離子植入製程; 1 1 2〜第二階段離子植入製程; 1 1 4〜晶格結構被破壞之區域。05488141TWF (N); 90060; ycchen.ptd Page 9 540106 Brief Description of Drawings Figures 1 A to 1 C are cross-sectional views showing the process of the traditional method of forming a bottle groove. 2A to 2F are cross-sectional views of a process for increasing trench capacitance according to an embodiment of the present invention. Figure 3A is a scanning electron microscope photograph showing the trench without argon ion implantation and phosphoric acid etching. Figure 3B is a scanning electron microscope photograph showing the trench after argon ion implantation and phosphoric acid etching. [Symbol description] 100 to semiconductor substrate; 106 to pad structure; 102 to hafnium oxide layer; 104 to nitride layer; 108 to trench; 110 to ring insulation layer 111 ~ 1st stage ion implantation process; 1 12 ~ 2nd stage ion implantation process; 1 1 4 ~ area with damaged lattice structure.

0548-8141TWF(N);90060;ycchen.ptd 第10頁0548-8141TWF (N); 90060; ycchen.ptd Page 10

Claims (1)

540106 六、申請專利範圍 溝槽電 包括下 壁之上 段離子 壁,以 結構; 段離子 槽底部 到破壞 利範圍 係矽基 1. 及溝槽之 於該 施行 度植入該 側壁之基 施行 底部,以 蝕刻 2.如 程,其中 3 ·如 程,其中 離子、砷 種增加 基底, 溝槽側 第一階 溝槽側 底晶格 第二階 破壞溝 去除受 申請專 該基底 申請專利範圍 第一或第二階 離子或鈍氣離 谷之製程’適用於一呈古 X丨止时 具有墊層結構 列步驟: ^ 部形成一環狀絕緣層; 植入製程’將離子以特定之入射角 破壞未被環狀絕緣層所覆蓋之溝ί 植入製程,將離子岙古姑 *卞茔直植入該溝样 之基底晶格結構;以及 曰 之溝槽内之基底部分。 第1項所述之增加溝槽電容之製 底。 第1項所述之增加溝槽電容之製 段離子植入製程所使用之離子是磷 〇 4 ·如申請專利範圍第1項所述之增加溝槽電容之製 程,其中該特定入射角度係約與法線成〇至4 5度。 5 ·如申請專利範圍第1項所述之增加溝槽電容之製 程,其中第一或第二階段離子植入製程中,離子植入能量 為5至60KeV之間。 6 ·如申清專利範圍弟1項所述之增加溝槽電容之製 程’其中弟一或第二階段離子植入製程中,離子植入劑量 為 1E12 至 1E16 atoms/cm2 之間。 7 ·如申請專利範圍第1項所述之增加溝槽電容之製 程,其中蝕刻去除受到破壞之溝槽内之基底部會係使用磷540106 VI. The scope of the patent application trench electricity includes the upper ion wall of the lower wall to structure; the bottom of the ion channel to the destruction range is silicon-based. 1. The bottom of the trench is implanted into the side of the sidewall of the base. Etching 2. Rucheng, where 3. Rucheng, in which the ion and arsenic species increase the substrate, the trench side first order trench side bottom lattice second order destruction trench removal is subject to the application for the substrate application patent scope first or The process of the second-order ion or inert gas leaving the valley is suitable for a step with an underlayer structure when it is ancient X 丨: a ring-shaped insulating layer is formed at the ^ part; the implantation process is to destroy ions at a specific incident angle. The trench covered by the ring-shaped insulating layer is implanted in a process of implanting ions of the gu gu * tomb directly into the trench-like base lattice structure; and the base portion in the trench. The substrate for increasing trench capacitance as described in item 1. The ion used in the ion implantation process for increasing the trench capacitance as described in item 1 is phosphorus. The process for increasing trench capacitance as described in item 1 of the patent application scope, wherein the specific incident angle is about 0 to 45 degrees from normal. 5. The process for increasing trench capacitance as described in item 1 of the scope of patent application, wherein in the first or second stage ion implantation process, the ion implantation energy is between 5 and 60 KeV. 6 · The process for increasing trench capacitance as described in item 1 of Shen Qing's patent scope, where the first or second stage ion implantation process, the ion implantation dose is between 1E12 and 1E16 atoms / cm2. 7 · The process for increasing trench capacitance as described in item 1 of the scope of the patent application, wherein the removal of the substrate in the damaged trench by etching will use phosphorus 0548-8141TWF(N);90060;ycchen.ptd 第11頁 540106 六、申請專利範圍 "一 酸來完成。 8 ·如申請專利範圍第1項所述之增加溝槽電容之梦 程,其中該環狀絕緣層是氧化物層。 才 9 ·如申請專利範圍第1項所述之增加溝槽電容之穿』 程,其中於施行第二階段離子植入製程之後,更包括衣使 豨釋氫氟酸’谷液(dilute HF solution)來清洗該基底 1 0 ·如申請專利範圍第1項所述之增加溝槽電容=制 程,其中該施行第一階段離子植入製程,更包括將該^广 沿轴心旋轉〇度、90度、18〇度及27〇度分別進行四次離1& 植入製程。 1 1 · 一種增加溝槽電容之製程,適用於一具有墊層結 構及溝槽之基底,包括下列步驟: 曰' ° 於該溝槽側壁之上部形成一環狀絕緣層; 施行第一階段離子植入製程,將離子以特定之入射角 度植入該溝槽側壁,以破壞未被環狀絕緣層所覆蓋之溝槽 側壁之基底晶格結構; 施行第^階段離子植入製程,將離子垂直植入該溝槽 底部,以破壞溝槽底部之基底晶格結構;0548-8141TWF (N); 90060; ycchen.ptd Page 11 540106 6. Scope of patent application " One acid to complete. 8. The dream process for increasing trench capacitance as described in item 1 of the patent application scope, wherein the ring-shaped insulating layer is an oxide layer. 9) The process of increasing the trench capacitance as described in item 1 of the scope of the patent application, wherein after the second stage ion implantation process is performed, it further includes a dilute HF solution ) To clean the substrate 1 · The trench capacitance increase process as described in item 1 of the scope of the patent application, where the first stage ion implantation process is performed, and the rotation of the substrate along the axis of the axis by 0 °, 90 ° Degrees, 180 degrees, and 270 degrees, respectively, four implantation procedures. 1 1 · A process for increasing trench capacitance is applicable to a substrate having a pad structure and a trench, including the following steps: ′ ° forming a ring-shaped insulating layer on the upper part of the trench sidewall; performing the first stage ion The implantation process implants ions into the sidewall of the trench at a specific incident angle to destroy the base lattice structure of the trench sidewall that is not covered by the ring-shaped insulating layer. Implanted at the bottom of the trench to destroy the base lattice structure at the bottom of the trench; 使用稀釋氫氟酸溶液來清洗該基底;以及 使用填酸姓刻去除受到破壞之溝槽内之基底部分。 12 ·如申請專利範圍第11項所述之增加溝槽電容之製 程,其中該基底係矽基底。 13·如申請專利範圍第n項所述之增加溝槽電容之製 程’其中第一或第二階段離子植入製程所使用冬離子是磷Use a dilute hydrofluoric acid solution to clean the substrate; and use acid filling to remove the substrate portion in the damaged trench. 12 The process for increasing trench capacitance as described in item 11 of the scope of patent application, wherein the substrate is a silicon substrate. 13. The process for increasing trench capacitance as described in item n of the scope of the patent application, wherein the winter ion used in the first or second stage ion implantation process is phosphorus 540106 六、申請專利範圍 離子、砷離子或鈍氣離子。 1 4 ·如申請專利範圍第1 1項所述之增加溝槽電容之製 程,其中該特定入射角度係約與法線成0至4 5度。 1 5 ·如申請專利範圍第1 1項所述之增加溝槽電容之黎』 程,其中第一或第二階段離子植入製程中,離子植入能旦 為5至60KeV之間。 1 6 ·如申請專利範圍第1 1項所述之增加溝槽電容之制 程,其令第一或第二階段離子植入製程中,離子植入劑&量 為 1E12 至 1E16 atoms/cm2 之間。 1 7·如申請專利範圍第1 1項所述之增加溝槽電容之製 程,其中該環狀絕緣層是氧化物層。 t 1 8·如申請專利範圍第1 1項所述之增加溝槽電容之製 程,其中該施行第一階段離子植入製程’更包括將該基底 沿轴心旋轉〇度、9 0度、1 8 0度及2 7 〇度分別進行四次離子 植入製程。540106 6. Scope of patent application Ion, arsenic ion or passivation ion. 1 4 · The process for increasing trench capacitance as described in item 11 of the scope of patent application, wherein the specific incident angle is approximately 0 to 45 degrees from the normal. 15. The process of increasing trench capacitance as described in item 11 of the scope of patent application, wherein in the first or second stage ion implantation process, the ion implantation energy is between 5 and 60 KeV. 16 · The process for increasing the trench capacitance as described in item 11 of the scope of the patent application, which makes the amount of ion implantation agent in the first or second stage ion implantation process 1E12 to 1E16 atoms / cm2. between. 17. The process for increasing trench capacitance as described in item 11 of the scope of patent application, wherein the ring-shaped insulating layer is an oxide layer. t 1 8 · The process for increasing trench capacitance as described in item 11 of the scope of patent application, wherein the first stage of ion implantation process' further includes rotating the substrate along the axis by 0 degrees, 90 degrees, 1 Four ion implantation processes were performed at 80 degrees and 270 degrees.
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