TW536791B - Trench flash memory device and the method of fabricating the same - Google Patents

Abstract

A method of fabricating a trench flash memory device, where the method includes forming a patterned mask layer on the substrate and using it as the mask for form a trench in the substrate. Next, a source region is formed in the substrate around near the bottom of the trench, and followed by forming a tunnel oxide layer, a floating gate, a gate dielectric layer and a control in the trench. After removing the mask layer to expose the substrate, a drain region is further formed in the substrate. In this invention, since the trench flash memory device has a cylindrical shape with the tunnel oxide layer, the floating gate and the gate dielectric layer wrapping around the control gate, therefore the overlap area between the floating gate and the control gate is increased, resulting in a higher gate coupling rate (GCR), a lower required operation voltage and a higher device operation speed and efficiency.

Description

536791 V. Description of the invention (1) The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a trench type flash memory and a method for manufacturing the same. Memory, as its name implies, is a semiconductor device used to store data or data. As the functions of computer microprocessors become more and more powerful, and the programs and calculations performed by software become more and more large, the demand for memory will become higher and higher. In order to manufacture large-capacity and cheap memory to meet this demand The technology and process of making memory components have become the driving force for semiconductor technology to continue to challenge high accumulation. For example, flash memory components have become a personal computer and electronics because they can store, read, and erase data multiple times, and the stored data will not disappear even after the power is turned off. A memory element widely used in devices. A typical flash memory device is generally designed to have a stack gate structure, which includes a tunnel oxide layer and a polycrystalline floating gate for storing electrical derivatives. ) 'Dioxide oxide / nitride oxide / oxide oxide (0N0) structure dielectric layer and a polycrystalline silicon control gate (Control Gate) for controlling data access. When programming or erasing the flash memory device, an appropriate voltage is applied to the source region, the drain region, and the control gate, respectively, so that electrons are injected into the polycrystalline silicon floating gate, or electrons are removed from the polycrystalline silicon. Pull out the floating gate. Generally speaking, the electron injection modes commonly used in flash memory devices can be divided into Channel Hot-Electron Injection (CHEI) and F-N pass-through (Fowler-Nordheim

90691 w fp td Page 5 536791 V. Invention > Ming (2) T u η ne 1 ing) mode and so on, and the programming and erasing operation modes of the components change with the way of electron injection and extraction . In the operation of flash memory, the larger the gate-coupling ratio (GCR) between the floating gate and the control gate, the lower the operating voltage required for its operation. The operation speed and efficiency of flash memory will be greatly improved. The methods for increasing the gate closing ratio include increasing the overlap area between the gate and the control gate (0ver 1 ap Area), and reducing the dielectric layer between the floating gate and the control gate. Thickness, and increasing the dielectric constant of the dielectric layer between the floating gate and the control gate (Die 1 ectric constant; k), etc. However, as integrated circuits are becoming smaller with higher integration, The development of modernized devices requires that the memory cell size of flash memory devices be reduced to increase their accumulation. Among them, reducing the size of the memory cell can be achieved by reducing the gate length of the memory cell and the interval between the data lines. However, a smaller gate length shortens the channel length under the tunneling oxide layer, which easily causes abnormal electrical penetration between the drain and source (Punch T hr ught), which will seriously affect Electrical performance of this memory cell. In addition to itb, in the flash memory manufacturing process, the lithography process also has the problem of the so-called §1 key size, which limits the reduction of memory cell size. In view of this, an object of the present invention is to provide a trench-type flash memory and a method for manufacturing the same, which can reduce the size of a memory cell and increase the degree of component accumulation by forming a memory cell in the trench. Another object of the present invention is to provide a trench type flash memory and a method for manufacturing the same, which can increase the overlapping area of the floating gate and the control gate, and

9069twl ptci Page 6 536791 V. Description of the invention (3) Increasing the gate coupling rate between the floating gate and the control gate, reducing the working voltage required for operation, and improving the speed and efficiency of component operation. Another object of the present invention is to provide a trench type flash memory and a manufacturing method thereof, which can control the depth of the trench to obtain a longer vertical channel length, and can avoid problems caused when the size of general components is reduced. The invention provides a trench flash memory manufacturing method. The method is to form a patterned mask layer on a substrate, and then use the patterned mask layer as a mask to form a trench in the substrate. A source region is formed in the substrate. Then, a tunneling oxide layer is formed in the trench, and a first conductor layer is formed in the trench, and the upper surface of the first conductor layer is lower than the surface of the substrate. Thereafter, a conformal gate dielectric layer is formed on the first conductor layer, a second conductor layer is formed on the substrate, and the second conductor layer fills the trench. Next, the second conductor layer outside the trench is removed to expose the surface of the patterned mask layer, and the mask layer is removed to expose the surface of the substrate. After that, > and polar regions are formed in the substrate around the top of the trench. The step of forming the source region at the bottom of the trench according to the present invention is to form a conformal doped insulating layer in the trench first, and form a first photoresist layer at the bottom of the trench. The trench is full and a portion of the doped insulating layer is exposed. Then, the doped insulating layer not covered by the first photoresist layer is removed, leaving the doped insulating layer around the bottom of the trench, and a capping layer is formed on the sidewall of the trench. After the first photoresist layer is removed, a thermal process is performed to diffuse the dopants in the doped insulating layer into the substrate to form a source region. After that, the doped insulating layer at the bottom of the trench and the capping layer on the sidewall of the trench are removed. A cap layer is formed on the top side wall of the trench to block heat

9069ΐ \ νΓ. Ptd page 7 536791 V. Description of the invention (4) During the process, the dopant diffusion in the doped insulating layer prevents the source region from diffusing too much, but can be limited to the area surrounding the bottom of the trench. In addition, the step of forming a first conductive layer with an upper surface lower than the substrate surface in the trench according to the present invention is to form a second photoresist layer in the trench first. A portion of the first conductor layer is exposed. Then, the first conductive layer not covered by the second photoresist layer is removed, and the second photoresist layer is removed. Since the upper surface of the first conductor layer (floating gate) is lower than the surface of the substrate, it is easier to form a continuous second conductor layer (control gate) in subsequent processes. In addition to itb, before the step of forming the tunneling oxide layer, the present invention further includes a repairing process to repair the damage caused by the etching process on the sidewall and the bottom of the trench. The step of this repairing process is a thermal oxidation process. A lining oxide layer is formed on the exposed trench surface to repair the damage caused by the engraving process, and then the lining oxide layer is removed. In addition, the present invention further includes forming a first conductive type first well region connected to the source region in the substrate, forming a second conductive type second well region on the first conductive type first well region, and forming a second conductive type well region on the substrate. A third well region of the first conductivity type is formed through the second well region of the second conductivity type and connected to the first well region of the first conductivity type. The ice invention is that after forming a trench in the substrate, a source region is formed on the substrate around the bottom of the trench. Next, a tunneling oxide layer, a floating interlayer, a gate dielectric layer, and a control gate are sequentially formed in the trench, and a drain region is formed on the base substrate around the top of the trench. Then the well area is used to connect the source area, and the area around the trench between the drain area and the well area is used as the channel area. Thanks to this

9069twf.pt d p. 8 536791 V. Inventor's Note (5) The memory cell of the trench flash memory of the invention is columnar, that is, the tunnel oxide layer, the floating gate and the gate dielectric layer The control gate is surrounded by the surrounding. Therefore, the overlapping area of the floating gate and the control gate can be increased, and the gate coupling ratio between the floating gate and the control gate can be increased to reduce the operating voltage required for operation. Improve component operation speed and efficiency. The present invention further provides a trench flash memory. The trench flash memory is composed of a substrate having a trench, a gate structure, a source region, and a drain region. The gate structure is arranged in the trench, and the gate structure is provided with a tunneling oxide layer, a floating gate, a gate dielectric layer and a control gate in this order from the outside to the inside, and the tunneling oxide layer, The floating gate and the gate dielectric layer surround the control gate. The source region is disposed in a substrate around the bottom of the trench. The drain region is disposed in a substrate around the top of the trench. Moreover, the trench type flash memory of the present invention further includes: a deep η-type well region disposed in the substrate and connected to the source region, and a ρ-type well region disposed on the deep η-type well region, and disposed on the substrate. The middle and through ρ-type well area and the deep η-type well area are connected to the η-type well area. The memory cell of the trench flash memory of the present invention has a columnar three-dimensional structure, that is, a tunneling oxide layer, a floating gate, and a gate dielectric layer are surrounded by a gated J gate, so it can be increased. The overlap area of the floating gate and the control gate increases the gate coupling rate of the floating gate and the control gate to reduce the operating voltage required for operation and increase the speed and efficiency of component operation. In addition, the channel area of the trench flash memory of the present invention is set in the substrate surrounding the trench (vertical channel area), so the component migration can be increased, and the channel can be accurately controlled by controlling the depth of the trench.

9069twΓ. Pt ci Page 9 536791 V. Description of the invention (6) The length can avoid the problems caused when the component size is reduced. In addition, the columnar memory cell structure can increase the current density and improve the efficiency of the programming / erasing operation of the memory elements. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Symbols of the drawings: 1 00, 2 0 0, 3 0 0: substrate 1 02: pad oxide layer 1 04: mask layer 1 0 6, 1 2 6: trench 1 0 8, 1 0 8 a: doped insulating layer 1 1 0, 1 2 0: light Barrier layer 1 1 2: Cap layer 1 1 4, 1 3 0: Doped region 1 1 6, 3 1 4 ·· Tunneling oxide layer 1 18, 1 18a, 124: Conductor layer 122 > 318: Gate Dielectric layer 1 2 8, 3 2 4 • Isolation structures 132, 202, 302: Deep η-type well area 1 34, 3 04: ρ-type well area 1 36, 3 22: Channel area 138, 312 ·· η type Well area 2 0 4: Active area

9069twf ptd Page 10 536791 V. Inventing Peng Zhiming (7) 2 0 6, W0, Wi, W2 •• Character line 2 0 8: Memory cell 2 1 0, D0, Di, D2: Data line 3 0 6 : Gate structure 3 0 8: Source region 3 1 0 > and Pole region 3 1 6: Floating gate 3 2 0: Control gate

Qnl, Qn2, Qn3, Qn4, Qn5, Qn6, Qn7, Qn8, Qn9 Lu Jiyi's cell implementation Figures 1A to 1I show a trench flash according to a preferred embodiment of the present invention A cross-sectional view of the manufacturing process of a memory device. First, please refer to FIG. 1A to provide a substrate 100, such as a semiconductor silicon substrate. A pad oxide layer 102—a masking layer 104 is sequentially formed on the surface of the substrate 100, and then patterned by a lithography process. The cover layer 104 and the pad oxide layer 102 form an opening (not shown) that exposes the substrate 100. The material of the pad oxide layer 102 is, for example, silicon oxide, and a method of forming the pad oxide layer 102 is, for example, thermal oxidation. The material of the mask layer 104 is, for example, silicon nitride, and a method of forming the mask layer 104 is, for example, a chemical vapor deposition method (Chemical Vapor Deposition, CVD). Then, using the mask layer 104 as a mask, An etching process is performed to form a plurality of trenches 106 in the substrate 100. A method for etching the trench 100 in the substrate 100 includes a dry etching method, such as a reactive ion etching method. Next, a conformal doped insulating layer 108 is formed on the substrate 100.

9069 twf.ptd Page 11 536791 V. Description of the invention (8) The material of the doped insulating layer 1 08 is, for example, a oxidized stone layer doped with erbium ions, and the method of forming the doped insulating layer 108 is, for example, to The method of in-situ (I η-S itu) doping ions is formed by chemical vapor deposition. Then, a photoresist layer 1 10 is formed at the bottom of the trench 1 06. The photoresist layer 1 10 does not fill the trench 1 06 after the etch back, and the surface of the photoresist layer 〇0 is located on the substrate. Below the surface. The step of forming a photoresist layer 1 1 0 on the bottom of the trench 106 is, for example, firstly coating a photoresist layer (not shown) on the substrate 丨 00, and then performing a cashback process to remove the substrate 1 0 0 The photoresist layer on the surface and part of the photoresist layer in the channel 106, leaving only the photoresist layer at the bottom of the channel 106, held by 110 °. Please refer to Figure 1B to remove the non-photoresist layer The part covered by 1 10 is doped with the insulating layer 008, and only the bottom of the trench 206 is left with the insulating doped layer 10 8 a. The method of removing the doped insulating layer is, for example, a wet etching method, using buffered hydrofluoric acid (Buffei < HF, BHF) or diluted hydrofluoric acid (Diluted H F 'D H F) as an etchant. Then, remove the photoresist layer 丨 丨 〇 at the bottom of the trench 丨 〇 6 and form a capping layer on the sidewall of the trench 106 丨 ^^^

Layer). The material of the capping layer 12 is, for example, tetrakis-ethyl-o-silicic acid (J2ra Ethyl 0. Silicate, TEOS) / ozone (〇3) as a reaction gas source = formed by a chemical vapor deposition method Silicon oxide. Please refer to FIG. 1C to perform a thermal process on the substrate 100 to diffuse the impurities in the doped layer 108a into the substrate 100 at the bottom of the trench 106. The doped region 1 1 4 'This doped region 11 4 is used as a trench flash memory. In addition, since the cap layer 11 2 is formed on the sidewall of the trench 10 6, the diffusion of the dopant in the impurity insulating layer 108a is prevented, so that the doped region 丨 4 does not

536791 V. The invention of Er Erming (9) caused the expansion script to be too large, but it could be limited to the range surrounding the bottom of the trench 106. Then, the doped insulating layer 108 and the cap layer 1 12 at the bottom of the trench 106 are removed. The method for removing the doped insulating layer 1 0 8 a and the cap layer 1 1 2 at the bottom of the trench 1 0 6 is, for example, a crystalline #etching method, which uses buffered hydrofluoric acid or diluted hydrofluoric acid as a post-etching agent. . After the steps of removing the doped insulating layer 10 8 a and the cap layer 1 12 at the bottom of the Sindor trench 106, a repair process is performed to repair the sidewall 106 and the bottom of the trench 100 caused by the etching process. The damage process, such as the advanced thermal oxidation process, forms a linear layer (not shown) on the exposed trench 106 surface to repair the damage caused by the remaining process. Then remove the liner oxide layer. Please refer to Fig. 1D, and form a conformal dielectric layer 1 16 on the substrate 100 to cover the trench 106. The material of the dielectric layer 1 16 is, for example, silicon oxide, and a method for forming the dielectric layer 1 16 by, for example, a thermal oxidation method or a low-pressure chemical gas phase sinking spear method. This dielectric layer 116 is used as a tunneling oxide for flash memory. A conformal conductive layer 118 is formed on the substrate 100. The material of this conductive layer 1 18 is, for example, doped polycrystalline silicon. The thickness is, for example, about 500 angstroms, and the method of forming the conductive layer 1 18 by 3 is, for example, a method of doping ions in the field, and forming the spear U by a chemical vapor deposition method. After that, another photoresist layer (not shown) is coated on the substrate 100, and then an etching process is performed to remove the photoresist layer on the surface of the substrate 100 and the photoresist layer in some of the trenches 106, and then to the trenches. A photoresist layer 120 is formed in 106, and the upper surface of the photoresist layer 120 is lower than the top surface of the substrate 100 t.

9069twf. Pt cl Page 13 536791 V. Description of the invention (10) Next, referring to FIG. 1E, the conductor layer covered by the photoresist layer 120, the spear, the substrate 100 and the body layer 1 1 8 a in the trench 106, Remove some of the conductors and leave the method in the trench only. The conductive layer 1 1 8 a is a method such as dry etching. For example, the conductive layer 1 1 8 a (floating gate 1 type flash memory floating gate. This is easy to manufacture in subsequent processes.) The upper surface is lower than the surface of the substrate. After removing the photoresist layer 120, the conductor layer (control gate) of the conductor Q. The deformed dielectric layer 1 2 2, this dielectric ^ 丨 2 3 ( A layer of co-silicon / silicon oxide, etc. is formed on the gate), and the thickness of the material is 2 Å. For example, the method of forming the silicon oxide / nitride layer 122 is, for example, == 60 angstroms / 70 angstroms / 6 angstroms The dielectric layer 1 2 2 is a trench type flash memory chemical vapor deposition method. The material of the dielectric layer 1 2 2 can also be a gate dielectric layer of oxygen ^. Of course, please refer to Section 1 F for details. Figure, Yu / Xi layer, silicon oxide / silicon nitride layer, etc. 1 2 4 fills the trench 1 06. Another conductor layer silicon is formed on this conductor drawer ^ bottom 100, and this conductor layer 1 24 is used as a trench. The material of the channel is, for example, the step of doping polycrystalline silicon to form the conductor layer 12. For example, the control gate of the second fast memory is used. The chemical vapor deposition method is used on the substrate. Type, ^ π a, form a conductor layer (not shown), and then using a chemical mechanical polishing method (Chemical trench fill on the lower L μ ... 1 ϋ 0

Meehan i cal Polishing (CMP) removes part of the conductor layer and the dielectric layer 116 other than the trench 106 until the surface of the mask layer 104 is exposed. Next, please refer to FIG. 1G. An isolation structure 1 2 8 is formed on the substrate. The isolation structure 1 2 8 is, for example, a field oxide layer or a shallow trench isolation structure. The isolation structure 1 2 8 is used to define an active area. And the isolation structure 1 2 8 is, for example, a strip-shaped layout. In this embodiment, the isolation structure 1 2 8 is a shallow trench.

9069t \ vf .ptd Page 14 536791 V. Description of the invention (11) The isolation structure is described as an example. The step of forming the isolation structure 1 2 8 is, for example, first patterning the mask layer 10 and the pad oxide layer 102 using lithography and etching techniques, and then using the patterned mask layer 104 as a mask, A trench 1 2 6 is etched into the substrate 100 adjacent to the memory cell. The etching method is, for example, plasma etching (Plasma Etching). Then, an insulating layer (not shown) is formed on the substrate 100 to fill the trenches 1 2 6. The material of this insulating layer is, for example, silicon oxide, and the method of forming the edge layer is, for example, firstly using tetraethyl-o-ortho-acid S / ozone as a reactive gas source, and then forming a silicon oxide layer by chemical vapor deposition Then, a densification process is performed to make the structure of the oxidized stone layer more dense, and then a chemical mechanical polishing process is performed using the mask layer 106 as a polishing stop layer until the surface of the mask layer 106 is exposed. Then, referring to the first figure, remove the mask layer 104 to expose part of the surface of the pad oxidation layer 102. The removal method includes an isotropic etching method such as a wet etching depression. It uses the pad oxide layer 102 as an etch stop layer, and uses hot phosphoric acid; the capacitor liquid is used as an etching solution for wet etching to etch until the surface of the pad oxidation layer 102 is exposed. Next, the hafnium oxide layer 102 is removed to expose the surface of the substrate 100. Methods for removing a part of the pad oxide layer 102 include an isotropic etching method such as a wet etching method, which uses a base substrate 100 as an etching stop layer and a hydrofluoric acid solution as a wet etching etching. The liquid is etched until the surface of the substrate 100 is exposed. In addition, when removing the cover layer 106 and the pad oxide layer 102, part of the isolation structure 1 2 8 is also removed so that the upper surface of the isolation structure 1 2 8 is lower than the surface of the conductor layer 1 2 4 and the conductor A part of the dielectric shoulder 1 1 6 on the top side wall of the layer 1 2 4 is also removed, so that the conductor layer 1 2 4 (control gate) protrudes from the trench 106.

9069iw f.pt d page 15 536791 V. Inventor's Note (12) ---- Connect = Please refer to the figure, the conductor layer 124 is used as the screen, and an ion implantation = clothing right is placed around the V body layer 124 A doped region 1 3 0 is formed on the substrate, and this doping F] Q n is like a drain region and a T m " drain region. The implanted dopant 3 works, and the d! Channel flashing workmanship M Α ^ such as As Kun (As) ions, the implantation energy is about 50 仟 electrons, the implantation dose is 4 X 101 is about 5 atoms / cm². Next, the bottom 1 forms a deep n-type well region 132, and the deep n-type well region I "connects the doped region 114 in the substrate. However, a P-type well region 134 is formed on this well region 132. Therefore, in the substrate 100 around the sidewall of the trench 106, the region between the doped region 130 and the deep n-type well region 132 is used as a channel flash region. An n-type well region 138 is formed in the substrate 100 that penetrates the p-type well region 134 and is connected to the deep n-type well region 132. The subsequent process of completing the flash memory is well known to those skilled in the art, To repeat. Figure 2 is a circuit diagram showing the split gate flash memory of the present invention. Name Figure 2 shows a plurality of memory cells Qnl to Qn9, data lines DG to data lines D2, and word lines. WG to word line ^. Among them, word line WG is connected to the control gates of memory cells Qnl, Qn2, Qn3, and word line 1 is connected to memory cells Qn4,

The control gates of Qn5, Qn6, and the word line ^ are connected to the control gates of memory cells Qn7, Qn8, and Qn9. The source regions of memory cells Qni to Qn9 are connected to the common ground (Comm ο η Ground). Data line D0 is connected to the drain regions of memory cells Qnl, Qn4, Qn7, data line Di is connected to the drain regions of memory cells 1, Qn5, Qn8, and data line 02 is connected to the drain regions of memory cells Qn3, Qn6, and Qn9. FIG. 3 is a top view showing the split gate flash memory of the present invention. FIG. 0

Hidden 1

MSI

9069twl ptcl Page 16 536791 V. Description of the invention (13) Please refer to FIG. 3 The present invention separates the gate flash memory from the substrate 2 0, the isolation structure 2 0 2, the active area 2 0 4 and the word line 2 0 6, memory cell 2 0 8 is composed. The isolation structure 202 is disposed in the substrate 200 to define the active area 204. The word line 206 is disposed on the substrate 200 'and is perpendicular to the active area 204. The memory cell 208 is disposed below the base line 2000 of the word line 206 across the active area 208, and the memory cell 208 is disposed in the trench of the base 208. The two active cells set in the same active area 204 and the polar area are lightly connected to the data line 2 10. FIG. 4 is a cross-sectional view showing the structure of a trench flash memory according to the present invention, and FIG. 4 is a cross-sectional view taken along the line I-Γ in FIG. 3. Please refer to FIG. 4. The flash memory of the present invention is composed of a substrate 3 0 0, a deep n-type well area 3 0 2, a p-type well area 3 0 4, a gate structure 3 0 6, and a source area 3 0 8 , Drain region 3 1 0, and n-type well region 3 1 2. The gate structure 3 0 6 is formed in the trench 3 1 3 of the substrate, which is controlled by a tunnel oxide layer 3 1 4, a floating gate 3 1 6, and a gate dielectric layer 3 1 8 from the outside to the inside. The gate electrode 3 2 0 is formed, and the tunnel oxide layer 3 1 4, the floating gate electrode 3 1 6 and the gate dielectric layer 3 1 8 surround the control gate electrode 3 2 0. The deep n-well region 302 is located in the basement 300. The p-well area 304 is located in a deep n-well area. The gate structure 306 is located in the substrate 300, and the gate structure 306 penetrates through the P-type well area 304 and the deep n-type well area 302. The source region 308 is located in a deep n-type well region 300 around the bottom of the gate structure 306. The drain region 3 10 is located in the substrate 300 around the top of the gate structure 306, and the area between the drain region 31 and the deep n-type well region 338 is used as the channel region 3 2 of the trench flash memory. The n-type well region 312 penetrates the p-type well region 304 and is connected to the deep n-type well region 302.

9069twf.ptd Page 17 536791 V. Inventor (14) According to the embodiment of the present invention, the present invention forms a trench in a substrate, and then forms a source region in the substrate around the bottom of the trench. Next, a tunnel oxide layer, a floating gate, a gate dielectric layer, and a control gate are formed in the trench, and a drain region is formed in a substrate around the top of the trench. Then, the well area is used to connect the source area, and the area around the trench between the drain area and the well area is used as the channel area. Because the memory cells of the trench flash memory of the present invention have a columnar three-dimensional structure, that is, the tunneling oxide layer, the floating gate, and the gate dielectric layer surround the control gate, so the present invention and Compared with the conventional stacked gate type flash memory, the overlap function of the floating gate and the control gate can be increased, and the gate coupling rate of the floating gate and the control gate can be increased, which reduces the operation of the bamboo gate. The required operating voltage improves the speed and efficiency of component operation. Moreover, the channel area of the trench flash memory of the present invention is set in a substrate surrounding the outside of the Pan channel (vertical channel area), so the rhyme of the component set can be increased, and the depth of the channel can be controlled accurately by controlling the depth of the channel. Controlling the length of the channel can avoid problems caused when the component size is reduced. In addition, the columnar memory cell structure can increase the current density and improve the efficiency of the programming / erasing operation of the memory elements. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and age of the present invention. The protection scope of the present invention 31 shall be determined by the scope of the attached patent application.

9069 twf. P t cl Page 18 536791 Brief description of drawings Figures 1A to 1I are cross-sectional views of the manufacturing process of the trench flash memory device of the present invention. FIG. 2 is a circuit diagram of a trench flash memory according to the present invention. FIG. 3 is a top view illustrating a trench flash memory according to the present invention. FIG. 4 is a cross-sectional view showing a structure of a trench flash memory according to the present invention.

9069t \\ f .ptd Page 19

Claims (1)

536791 VI. Scope of patent application 1. A method for manufacturing a trench flash memory, the method includes the following steps: exposing a substrate; forming a patterned mask layer on the substrate; and patterning the mask The curtain layer is a mask, which forms a trench in the substrate; a source region is formed in the substrate around the bottom of the trench; a tunneling oxide layer is formed in the trench; a first conductor layer is formed in the trench An upper surface of the first conductor layer is lower than the surface of the substrate; a conformal gate dielectric layer is formed on the first conductor layer; a second conductor layer is formed on the substrate, and the second conductor layer is filled Fill the trench; remove the second conductor layer and the gate dielectric layer outside the trench to expose the surface of the patterned mask layer; remove the patterned mask layer to expose the surface of the substrate; And forming a drain region in the substrate around the top of the trench. 2. The method of manufacturing a trench-type flash memory as described in item 1 of the scope of the patent application, wherein the step of forming the source region in the substrate around the bottom of the trench includes: forming one of the conformals in the trench A doped insulating layer; forming a first photoresist layer at the bottom of the trench, the first photoresist layer not filling the trench and exposing a portion of the doped insulating layer; removing the first photoresist layer The doped insulating layer, leaving a bit 9069twf.pt d page 20 536791 6. The patent application scope is the doped insulating layer around the bottom of the trench; forming a capping layer on the sidewall of the trench: removing the first photoresist layer; performing a thermal process To diffuse the dopant in the doped insulating layer into the substrate to form the source region; and remove the doped insulating layer at the bottom of the trench and the cap layer on the sidewall of the trench. 3. The method for manufacturing a trench flash memory as described in item 2 of the scope of the patent application, wherein the material of the doped insulating layer includes arsenic ion-doped oxidized fossils. 4. The method for manufacturing a trench-type flash memory as described in item 1 of the scope of patent application, wherein the step of forming a first conductor layer in the trench and the upper surface of the first conductor layer is lower than the surface of the substrate The method includes: forming a second photoresist layer in the trench, the second photoresist layer not filling the trench and exposing part of the first conductor layer; removing the first photoresist layer not covered by the second photoresist layer; A conductive layer; and removing the second photoresist layer. 5. The method for manufacturing a trench type flash memory as described in item 1 of the scope of patent application, wherein the tunnel oxidation is formed in the trench after the step of forming the source region in the substrate around the bottom of the trench. Before the step of layering, a repair process is performed. 6. The method for manufacturing a trench-type flash memory as described in item 5 of the scope of the patent application, wherein the repair process includes: performing a thermal oxidation process to form a sidewall and a surface of the trench. 9069twl ptd Page 21 536791 6. Scope of patent application: a liner oxide layer; and remove the liner oxide layer. 7. The method for manufacturing a ditch flash memory as described in item 1 of the scope of the patent application, further comprising: forming a first conductive type first well region in the substrate that is connected to the source region; A second conductivity type second well region is formed on the first conductivity type first well region; and a force is formed in the substrate to penetrate the second conductivity type second well region and connect to the first conductivity type first well region. A first conductivity type third well region. 8. The method for manufacturing a trench-type flash memory as described in item 1 of the scope of patent application, wherein the patterned mask layer and the substrate further include a pad oxidation. 9. The method for manufacturing a trench-type flash memory as described in item 1 of the patent application scope, wherein the step of removing the mask layer to expose the surface of the substrate is followed by forming the drain in the substrate on top of the trench. Before the step of polar region, it further includes forming an isolation structure in the substrate to define an active region. 10. A trench-type flash memory, the trench-type flash memory includes: a substrate having a trench in the substrate; a gate structure disposed in the trench, and the gate structure being A through oxide layer, a floating gate electrode, a gate dielectric layer and a control gate electrode are sequentially arranged in the trench from the outside to the inside. 9069 twf. Pt cl Page 22 536791 VI. Application for a patent-specific floating gate and the gate dielectric layer surround the control gate; a source region is located at the bottom of the trench In the surrounding substrate; and-; and the polar region 'the > and the polar region are disposed in the substrate around the top of the ditch. The channel-type flash memory described in item 10 of the scope of patent application , Which further includes:-a first conductive type first well region, the first conductive type first well region being disposed in the substrate and connected to the source region;-a second conductive type second well region, the first A second-conductivity-type second well region is disposed on the first-conductivity-type first well region; and-a first-conductivity-type third well region is disposed in the substrate and runs through the substrate The second well type of the second conductivity type is connected to the first well type of the first conductivity type. 1 2. The trench-type flash memory according to item 11 of the scope of patent application, wherein the first conductive type first well area includes a deep n-type well area. 1 3. The trench-type flash memory according to item 11 of the scope of patent application, wherein the second conductive type second well area includes a p-type well area. 14. The trench-type flash memory according to item 11 of the scope of patent application, wherein the first conductive type third well area includes an n-type well area. 1 5. The trench type flash memory according to item 10 of the patent application scope, wherein the gate dielectric layer includes a silicon oxide / silicon nitride / silicon oxide layer. 16. The trench type flash memory according to item 10 of the patent application scope, wherein the top of the floating gate is lower than the surface of the substrate. 9069twf .pt ci p. 23 536791 90691 w f.p t d p.24