TW533577B - Circuit structure for connecting bonding pad and ESD protection circuit - Google Patents
Circuit structure for connecting bonding pad and ESD protection circuit Download PDFInfo
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- TW533577B TW533577B TW91110706A TW91110706A TW533577B TW 533577 B TW533577 B TW 533577B TW 91110706 A TW91110706 A TW 91110706A TW 91110706 A TW91110706 A TW 91110706A TW 533577 B TW533577 B TW 533577B
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Description
533577 案號 91110706 修」 五、發明說明(1) -- 本發明是有關於一種連接焊墊(p a d )與靜電放恭 ^ (Electrostatic Discharge protection, 保 口又 protection)電路的電路結構,且特別是有關於一 接焊墊與靜電放電保護電路的電路形成多層路斤一種將連533577 Case No. 91110706 Repair "V. Description of the invention (1)-The present invention relates to a circuit structure that connects a pad and an electrostatic discharge circuit (Electrostatic Discharge protection, protection and protection) circuit, and in particular A circuit related to a bonding pad and an electrostatic discharge protection circuit forms a multilayer circuit.
UulUple paths)的結構,並藉由多層路^ ^六、 元件的靜電放電保護能力。 、刀’以增加 靜電放電為自非導電表面之靜電 成1C中之半導體與其它電路組成之損:動的現象’其會造 走的人體,於相對濕度(RH)較高的情 二例如在地毯上行 有幾百至幾千伏的靜態電塵,而在=下,可檢剛出约帶 二;:檢測出约帶有-萬伏以上的靜。度較低的情況 測試積體電路的儀器ΪΪ屋。而封裝積體 接觸到3日!電壓。當上述的帶電體(人㊣產生約幾百至 將有可向晶片放電,此靜' 機器或儀器) 因此,ί曰了曰i::;:電路損壤或=電之瞬間功率 種防制靜電放電=:放電損傷晶片ϊ:。 利用硬H Ρϋί t的方法便因應而生。@的積體電路,各 尤體防制靜電放電, 取常見的羽立aUulUple paths) structure, and through the multilayer path ^ ^ six, the component's electrostatic discharge protection capabilities. "The knife 'is to increase the electrostatic discharge from the static electricity on the non-conducting surface to the damage of the semiconductor and other circuits in 1C: the phenomenon of movement', which will cause the human body to be removed. In the case of high relative humidity (RH), for example, There are several hundred to several thousand volts of static electric dust on the carpet, and under =, about two bands can be detected just before:: Statics with about -10,000 volts or more are detected. Cases with low degree of equipment Squatter for testing integrated circuits. The packaged body is exposed to 3 days! Voltage. When the above-mentioned charged body (the human being generates about several hundred to be able to discharge to the wafer, this static machine or instrument) Therefore, I said: i ::;: circuit damage or = instantaneous power control of electricity Electrostatic discharge =: discharge damage wafer ϊ :. The method using hard H Ρϋί t was born accordingly. @ 的 体 体 电路 , Especially prevent static discharge, take the common feather stand a
ClrcUlt)與每— 也就疋在内部略見的白知作法是 的靜電放電保護;::俾:rr晶片;:卜 ;1«^ % ^ t Λδ;% ^ ° ^(〇n'chip) 之半導體二接的剖面圖,且第^到靜電放電 立體圖’並且β 靜電放電保護f @圖所繪示為習知 .^ 在弟2圖中省略絕緣層的;^間之電路連接的ClrcUlt) and each—that is, the white-disc approach that I saw a little in the inside is the electrostatic discharge protection :: 俾: rr wafer;: Bu; 1 «^% ^ t Λδ;% ^ ° ^ (〇n'chip) A cross-sectional view of the semiconductor connection, and the ^ to the electrostatic discharge perspective view 'and β electrostatic discharge protection f @ The drawing is shown as a conventional. ^ In the figure 2 the insulating layer is omitted; the circuit connection between the ^
----- °在第1圖盥笼 86I^wfl.ptc 533577 --案號9H10706_"碎 > 月丨/曰 修正 五、發明說明^ ^~" -- 2圖中’焊墊1 〇 〇係形成於半導體元件的最上層,且靜電放 電保護電路118設置於基底50中。由焊墊1〇〇往下連接2序 為栓基1〇2、導體層104、栓塞1〇6、導體層1〇8、检塞 110 ‘體層112 ’其中導體層112如第1圖所示的具有延伸 導線1 1 2 a,此延伸導線1 1 2 a延伸至靜電放電保護電路丨! 8 的汲極116上方,並藉由接觸窗(c〇ntact)114使延伸導線 1 1 2 a與設置於基底5 0的汲極1 1 6電性連接。尚且,在焊塾 1 0 0與基底5 0間具有一絕緣層1 3 0,此絕緣層1 3 〇將上述的 電路結構包覆其中。 在上述第1圖與第2圖中,當產生靜電放電現象時,靜 電係由焊墊1 0 0經上層電路流至靜電放電保護電路1丨8内, 亦即是經由焊墊100、栓塞102、導體層104、栓塞1〇6、導 體層1 08、栓塞1 1 〇、導體層1 12與延伸導線丨12a流至靜電 放電保護電路118的汲極116,並由靜電放電保護電路118 保護内部電路不受靜電放電的破壞。 然而’在第1圖與第2圖的結構中,靜電係經由單層金 屬(亦即疋指延伸導線1 1 2 a )的路經流動至靜電放電保護電 路1 1 8 ’當流經的電流過大時,延伸導線1 1 2 a有可能會被 過大的電流燒壞,而使得靜電放電保護電路1 1 8失效。習 知避免延伸導線1 12a被燒壞的方法,係將延伸導線丨12a的 線寬加寬或是將延伸導線1 1 2a的厚度w加厚。然而,如果 延伸導線1 1 2 a的厚度W受到限制,則延伸導線1 1 2 a只能以 加見導線的方法解決問題。而在半導體元件愈趨縮小與高 集積化的現今製程中,線寬的增加意味著製程裕度----- ° In the first picture, the cage 86I ^ wfl.ptc 533577-Case No. 9H10706_ " Broken > Month 丨 / Revision V. Description of the invention ^ ^ ~ "-2 The 〇〇 system is formed on the uppermost layer of the semiconductor element, and the ESD protection circuit 118 is provided in the substrate 50. The connection from the solder pad 100 to the bottom 2 is the plug base 102, the conductor layer 104, the plug 106, the conductor layer 108, and the plug 110 'body layer 112'. The conductor layer 112 is shown in Fig. 1 Has an extension wire 1 1 2 a, and this extension wire 1 1 2 a extends to the electrostatic discharge protection circuit 丨! Above the drain 116 of 8 and through a contact window 114, the extension lead 1 1 2a is electrically connected to the drain 1 1 6 disposed on the substrate 50. Furthermore, there is an insulating layer 130 between the solder pad 100 and the substrate 50, and the insulating layer 130 covers the above-mentioned circuit structure. In the above first and second figures, when an electrostatic discharge phenomenon occurs, the static electricity flows from the bonding pad 100 through the upper circuit to the electrostatic discharge protection circuit 1 丨 8, that is, through the bonding pad 100 and the plug 102. , Conductor layer 104, plug 106, conductor layer 1 08, plug 1 1 10, conductor layer 1 12 and extension wire 丨 12a flow to the drain 116 of the ESD protection circuit 118, and the interior is protected by the ESD protection circuit 118 The circuit is not damaged by electrostatic discharge. However, in the structure of FIG. 1 and FIG. 2, the static electricity flows to the electrostatic discharge protection circuit 1 1 8 through the path of a single layer of metal (that is, the extended wire 1 1 2 a). When it is too large, the extension lead 1 1 2 a may be burned by an excessive current, and the electrostatic discharge protection circuit 1 1 8 may fail. The conventional method for avoiding the burnout of the extension wire 1 12a is to widen the line width of the extension wire 12a or increase the thickness w of the extension wire 1 12a. However, if the thickness W of the extension wire 1 1 2 a is limited, the extension wire 1 1 2 a can only be solved by adding a wire. In today's processes where semiconductor devices are becoming smaller and more integrated, the increase in line width means process margin.
8618twfl.ptc 第7頁 _ 案號 91110706 友、發明說明(3) (window)的降低,並不 因此,本發明的目 保護電路之電路結構, 力。 本發明的另一目的 邊電路之電路結構,能 度。 本發明提供一種連 ,構,此電路結構包括 塞、第一導線、複數條 '層以不同高度平行 i性連接焊墊與相鄰焊 之導體層。第一導線係 f且電性連接至靜電放 向度平行設置於第一導 線各別電性連接至不同 修正 利於元件的集積化。 的在提出一種連接焊墊與靜 能夠增加元件的靜電放電保 在提出一種連接焊墊與靜電 夠縮小導線的線寬,以增加 接焊墊與 :複數層 第二導線 設置於焊 墊之導體 電性連接 電保護電 線與焊墊 高度之導 連接第一導線與相鄰第一導線之 靜電放 導體層 與複數 墊與基 層,並 至最靠 路汲極 之間, 體層。 第二導 相鄰之第二導線 綜上所述,本發明 第二導線組成之多層路 流,流經每一條路徑的 見’並且導線的厚度亦 此在線路設計上具有更 此外,由於在電路 電保護 '複數 層第二 底之間 電性連 近基底 °第二 其中每 而且第 線,並 係在電路結構中形成由 徑,由於電流能夠經由 電流減小,導線可以形 可以因應製程的需要加 大的可變性與自由度。 結構中形成多層路徑, 電路 層第 栓塞 。第 接每 之導 導線 〜條 二栓 電性 苐一 多層 成較 以調 電放電 護能 放電保 製程裕 之電路 一栓 。其中 一栓塞 一相鄰 體層, 以不同 第二導 塞電性 連接每 導線與 路徑分 小的線 整,因 在其中 因此8618twfl.ptc Page 7 _ Case No. 91110706 The description of the invention (3) (window) is not reduced. Therefore, the purpose of the present invention is to protect the circuit structure and strength of the circuit. Another object of the present invention is the circuit structure and capability of a side circuit. The invention provides a connection structure. The circuit structure includes a plug, a first wire, and a plurality of 'layers' which connect the pads and adjacent conductor layers in parallel at different heights. The first lead wire f is electrically connected to the electrostatic radiation in parallel, and the first lead wires are electrically connected to different corrections, which facilitates the integration of the components. I propose a connection between the pad and the static electricity that can increase the component's electrostatic discharge. I propose a connection between the pad and the static enough to reduce the wire width of the wire, in order to increase the pad and the: The conductors electrically connecting the heights of the electrical protection wires and the bonding pads connect the electrostatic discharge conductor layer of the first lead and the adjacent first lead, the plurality of pads and the base layer, and the body layer. As mentioned above, the second conductive wire adjacent to the second conductive wire is a multi-layer circuit composed of the second conductive wire of the present invention, which flows through each path. The thickness of the conductive wire also has more advantages in circuit design. The electrical protection 'multiple layers are electrically connected between the second bottom and the second. Each second and third line is formed in the circuit structure. Since the current can be reduced by the current, the wire can be shaped to meet the needs of the process. Increased variability and freedom. A multilayer path is formed in the structure, and the circuit layer is plugged. The lead wires of each connection are ~ 2 bolts. Electrically, a multi-layered one is used to adjust the electrical discharge, protect the energy, and discharge the circuit. One of them plugs an adjacent body layer and uses a different second plug to electrically connect each wire to a small line of the path.
修正丨 * 533577 _ 1-Fix 丨 * 533577 _ 1-
、号务曰月 曰月(4) iw一”一一一——“一·— ·——一,一J 一條導線(路徑)斷線的時候,由於尚具有其他的電流通 路’因此能夠避免靜電放電元件的失效’增強靜電放電的 保護能力。 為讓本發明之上述目的、特徵、和優點能更明顯易 懂,下文特舉較佳實施例,並配合所附圖式,作詳細說明 如下: 圖不之標不說明· 50、1 50 :基底 1 0 0、2 0 0 :焊墊 102 、106 >110 、202 、206、210 、210 > 2 2 0 、224 : 栓塞 104、 112a 114、 116、 118、 130、 212a W、 108 >112 :延伸導線 214 21 6 21 8 230 > 222 、W2 20 4、2 08、21 2 :導體層 接觸窗 汲極 靜電放電保護電路 絕緣層 、2 2 6 ·導線 W3 :厚度 較佳實施例 第3圖所繪示為本發明較佳實施例之半導體元件的焊 墊到靜電放電保護電路間之電路連接的剖面圖,以及第4(4) iw one "one one one one"-"one · · · · one, one J, one wire (path) is broken, because there are other current paths, so it can be avoided Failure of electrostatic discharge components' enhances the protection of electrostatic discharge. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings, as follows: The symbols in the figures are not described. 50, 1 50: Substrate 1 0 0, 2 0 0: pads 102, 106 > 110, 202, 206, 210, 210 > 2 2 0, 224: plugs 104, 112a 114, 116, 118, 130, 212a W, 108 > 112: extension wire 214 21 6 21 8 230 > 222, W2 20 4, 2, 08, 21 2: conductor layer contact window drain electrostatic discharge protection circuit insulation layer, 2 2 6 wire W3: thickness preferred embodiment FIG. 3 is a cross-sectional view showing a circuit connection between a pad of a semiconductor device and an electrostatic discharge protection circuit according to a preferred embodiment of the present invention, and FIG.
8618twf1.ptd 第9頁 5335778618twf1.ptd Page 9 533577
圖所纟胃不為本發明較佳實施例之半導體元件的焊墊到靜電 放電保護電路間之電路連接的立體圖。 凊同時爹照第3圖與第4圖。本發明之連接焊墊2 〇 〇與 靜電放電保瘦電路2 1 8的上層電路結構包括:栓塞2 〇 2、導 體層204、栓基206、導體層208、栓塞21〇、導體層212、 作為延伸導線的導線2 1 2 a、接觸窗2 1 4、栓塞2 2 0、作為擬 真(dummy)導線的導線22 2、栓塞224以及作為擬真導線的 導線22 6。 在第3圖與第4圖中,焊墊2〇〇同樣的係形成於半導體 元件的最上層’且靜電放電保護電路218係設置於基底ι5〇 中。由焊塾200往下連接依序為栓塞2〇2、導體層2〇4、栓 塞2 06、導體層208、栓塞210、導體層212、以及延伸至靜 電放電保護電路218的汲極216上方的導線212a。並且,導 線212a再藉由接觸窗214與基底150中的靜電放電保護電路 218的沒極216電性連接。其中,上述栓塞202、導體層 2 04、栓塞2 0 6、導體層2 0 8、栓塞21 0、導體層212與導線 2 1 2 a的材質例如是銅金屬。 接著’請繼續參照第3圖與第4圖,在上層電路中設置 導線22 2、22 6,此導線2 22、22 6係作為本發明之擬真導線 使用。在第3圖與第4圖中,導線222係與導體層208電性連 接’並藉由栓塞220與延伸導線212a電性連接,而導線226 則與導線20 2電性連接,並藉由栓塞224與導線2 22電性連 接。其中栓塞2 2 0、導線2 22、栓塞2 24與導線22 6的材質例 如是銅金屬。The stomach shown in the figure is not a perspective view of the circuit connection between the pad of the semiconductor element and the electrostatic discharge protection circuit in the preferred embodiment of the present invention.凊 At the same time, my father took pictures 3 and 4. The upper circuit structure of the connection pad 2000 and the electrostatic discharge thinning circuit 2 18 of the present invention includes: a plug 2 02, a conductor layer 204, a plug base 206, a conductor layer 208, a plug 21, and a conductor layer 212. Lead wires 2 1 2 a of extension wires, contact windows 2 1 4, plugs 2 2 0, wires 22 as dummy wires, plugs 224, and wires 22 6 as pseudo wires. In FIG. 3 and FIG. 4, the same pad 200 is formed on the topmost layer of the semiconductor element ', and the ESD protection circuit 218 is provided on the substrate ι50. The connection from the solder joint 200 in sequence is the plug 202, the conductor layer 204, the plug 202, the conductor layer 208, the plug 210, the conductor layer 212, and the drain electrode 216 extending above the electrostatic discharge protection circuit 218. The lead 212a. In addition, the conductive line 212a is electrically connected to the electrode 216 of the ESD protection circuit 218 in the substrate 150 through the contact window 214. The materials of the plug 202, the conductor layer 204, the plug 206, the conductor layer 208, the plug 208, the conductor layer 212, and the lead 2 1 2a are, for example, copper metal. Next, please continue to refer to FIG. 3 and FIG. 4, and set wires 22 2, 22 6 in the upper circuit, and these wires 2 22, 22 6 are used as the realistic wires of the present invention. In FIGS. 3 and 4, the lead 222 is electrically connected to the conductor layer 208, and is electrically connected to the extension lead 212a through the plug 220, and the lead 226 is electrically connected to the lead 202, and is connected through the plug. 224 is electrically connected to the lead 2 22. The materials of the plug 2 2 0, the lead 2 22, the plug 2 24, and the lead 22 6 are, for example, copper metal.
8618twfl.ptd 第10頁 533577 事> /y 五、發明說明(6) .............. …二」— 尚且,在焊墊2 0 0與基底1 5 0間具有一絕緣層2 3 0,此 絕緣層2 3 0將上述的電路結構包覆其中。 在上述第3圖與第4圖的結構中,當導線2 22、2 2 6的材 質與導體層相同時,則擬真導線2 2 2、2 2 6能夠分別與導體 層2 0 8、2 0 4於同一製程中同時形成,因此,架構此擬真導 線並不會使半導體元件的製程步驟增加。尚且,由於導線 與導體層同材質,因此可將導線222與導體層208,以及導 線222與導體層2 0 8視作相同的導體層。 由上述第3圖與第4圖的結構可以得知,當產生靜電放 電現象,靜電流入電路結構時,電流具有3條路徑可供流 動,亦即是電流可以經由導線2 2 6、導線2 2 2與導線2 1 2 a, 使得電流能夠經由此3條導線組成的多層路徑分流流動。 因而能夠避免習知的電流過大導致斷線的問題。尚且,此 種結構在其中一條導線(路徑)斷線的時候,由於尚具有兩 條導線可供電流流動,因此能夠避免靜電放電元件的失 效。 並且,由於電流分流的效應,流經導線2 2 6、2 2 2與導 線2 12a的個別電流較小,導線22 6、222與導線2 12a的個別 的線寬可以形成較習知小的線寬,因此在電路設計上具有 更大的可變性與自由度,進而有利於提升半導體元件的集 積度。 上述係對導線之線寬能夠縮小加以說明,然而本發明 亦可應用於縮小或調整導線的厚度,請再參照第3圖與第4 圖,於圖中導線21 2a、導線222與導線22 6分別為厚度&、8618twfl.ptd Page 10 533577 Things > / y V. Description of the Invention (6) .............. ...... Two "— Moreover, the pads 2 0 0 and the substrate 1 5 0 There is an insulating layer 230 in between, and the insulating layer 230 covers the above circuit structure. In the structures of the above FIG. 3 and FIG. 4, when the materials of the wires 2 22 and 2 2 6 are the same as those of the conductor layer, the imaginary wires 2 2 2 and 2 2 6 can be respectively connected with the conductor layers 2 0 8 and 2 0 4 are formed at the same time in the same process. Therefore, constructing this imaginary wire does not increase the process steps of the semiconductor device. Moreover, since the wire and the conductor layer are made of the same material, the wire 222 and the conductor layer 208, and the wire 222 and the conductor layer 208 can be regarded as the same conductor layer. It can be known from the structures of Figs. 3 and 4 that when static discharge occurs and static electricity flows into the circuit structure, the current has three paths to flow, that is, the current can pass through the wires 2 2 6 and 2 2 2 and the lead 2 1 2 a, so that the current can flow through the multilayer path composed of the 3 leads. Therefore, it is possible to avoid the problem of disconnection caused by the excessively large current. Moreover, when one of the wires (paths) is disconnected in this structure, since there are still two wires for current flow, the failure of the electrostatic discharge element can be avoided. In addition, due to the effect of current shunting, the individual currents flowing through the wires 2 2 6, 2 2 2 and the wire 2 12 a are small, and the individual line widths of the wires 22 6, 222 and the wire 2 12 a can form smaller wires than conventional ones. Wide, so it has greater variability and freedom in circuit design, which is conducive to improving the integration of semiconductor components. The above description is that the wire width can be reduced. However, the present invention can also be applied to reduce or adjust the thickness of the wire. Please refer to FIGS. 3 and 4 again. In the figure, the wires 21 2a, the wires 222, and the wires 22 6 Thickness &,
8618twfl.ptd 第11頁 5335778618twfl.ptd Page 11 533577
qi > IV 五、發明說明(7) w2、w3,其中至少一個以上的導線厚度總和可大於或是等 於一預定導線厚度w S。此處所謂的預定導線厚度W S係指設 計者依實際製程需要,於設計上所決定的厚度,例如可以 是能夠承受電流的最小厚度。qi > IV V. Description of the invention (7) w2, w3, in which at least one or more of the total wire thicknesses may be greater than or equal to a predetermined wire thickness wS. Here, the predetermined wire thickness W S refers to a thickness determined by the designer in design according to actual process requirements, and may be, for example, a minimum thickness capable of withstanding current.
如上所述,當在線寬的限制條件下,此預定厚度W S無 法使用一層導線形成時,則能夠藉由複數層的導線厚度 (此處可由I、W2、W3…延伸至相對應層數的W η )組合以達到 預定導線厚度Ws,例如是Ws二Wi + W2,或是Ws二Wi + W2 + 。並且此預定導線厚度W s與複數層的導線厚度(Wi、W 2、W3、"Ιη)的關係、導線的層數等,可由設計者依製程 上的實際需要決定,例如可為Ws 2 W! + W2,或是Ws ^ + W2 + W3,或是Ws S Wi + W2,甚或是Ws ^ W, + W2 + W3…等種種情形。因此,本發明能夠就導線寬度以及導 線厚度兩方面,因應製程設計上的需要加以調整,因而能 夠更增電路設計上的可變性與自由度。 再者,上述的擬真導線甚或是導體層的材質並不限定 於銅金屬,亦可以採用銅金屬以外的材質,例如是擴散區 電阻器或是多晶矽,以增加靜電放電保護電路的保護能 力5亦或是能夠採用任何有利於增加靜電放電保護電路保 護能力的元件。 此外,上述的擬真導線與導體層亦不限定於同時使用 相同的材質,亦可以視實際製程的需要,分別使用不同或 是部分相同的材質。例如是在一個具有多層路徑的電路結 構中,同時具有銅金屬、多晶矽與擴散區電阻器所形成的As mentioned above, when the predetermined thickness WS cannot be formed with one layer of wire under the limitation of the line width, it can be extended by a plurality of layers of wire thickness (here, it can be extended from I, W2, W3, ... to W of the corresponding number of layers). η) are combined to achieve a predetermined wire thickness Ws, such as Ws two Wi + W2, or Ws two Wi + W2 +. Moreover, the relationship between the predetermined wire thickness W s and the wire thickness of multiple layers (Wi, W 2, W3, " Ιη), the number of wire layers, etc. can be determined by the designer according to the actual needs of the process, for example, it can be Ws 2 W! + W2, or Ws ^ + W2 + W3, or Ws S Wi + W2, or even Ws ^ W, + W2 + W3 ... and so on. Therefore, the present invention can adjust both the width of the wire and the thickness of the wire according to the needs of the process design, so that it can increase the variability and freedom of circuit design. Furthermore, the material of the above-mentioned imaginary wire or even the conductor layer is not limited to copper metal, and materials other than copper metal may also be used, such as a diffused area resistor or polycrystalline silicon to increase the protection capacity of the electrostatic discharge protection circuit. 5 Or it can use any component that is helpful to increase the protection capacity of the electrostatic discharge protection circuit. In addition, the above-mentioned imaginary wires and conductor layers are not limited to use the same material at the same time, and different or partially the same materials can be used respectively according to the needs of the actual process. For example, it is formed in a circuit structure with multilayer paths, which has copper metal, polycrystalline silicon, and diffused resistors.
8618twfl. ptd 第12頁 533577 五、發明說明(8) … 擬真導線。 尚且,上述的上層電路結構係以形成3層的導體層以 及2層的擬真導線做說明,然而導體層與擬真導線的層數 並不限定於較佳實施例中所揭露的層數,而能夠依照製程 的實際需要做調整。 綜上所述,本發明係在電路結構中形成多層電流路 徑,由於電流能夠經由多層路徑分流,流經每一路徑的電 流減小,導線的線寬可以形成較小的線寬,並且導線的厚 度亦可以因應製程的需要加以調整,因此在在線路設計上 具有更大的可變性與自由度,進而有利於提升半導體元件 的集積度。 並且,由於在電路結構中形成多層路徑,因此在其中 一條導線(路徑)斷線的時候,由於尚具有其他的電流通 路,因此能夠避免靜電放電元件的失效,增強靜電放電的 保護能力。 另外,上述多層路徑的構築,可以採用銅金屬以外的 材質,例如是電阻或是多晶矽等的其他材質,以進一步增 加靜電放電保護電路的靜電放電保護能力。 此外,上述多層路徑的構築,由於能夠相容於習知的 半導體元件製程中,因此並不會使得製程的步驟數增加, 亦即是不會增加製程的成本。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍内,當可作各種之更動與潤飾,因此本發明之保護8618twfl. Ptd Page 12 533577 V. Description of the invention (8)… a realistic wire. Moreover, the above-mentioned upper circuit structure is described by forming three layers of conductor layers and two layers of imaginary wires. However, the number of layers of conductor layers and imaginary wires is not limited to the number of layers disclosed in the preferred embodiment. And can be adjusted according to the actual needs of the process. In summary, the present invention forms a multi-layer current path in a circuit structure. Since the current can be shunted through the multi-layer path, the current flowing through each path is reduced, and the line width of the wire can be formed into a smaller line width. The thickness can also be adjusted according to the needs of the process, so it has greater variability and freedom in circuit design, which is conducive to improving the integration of semiconductor components. In addition, because a multilayer path is formed in the circuit structure, when one of the wires (paths) is broken, there are other current paths, so it can avoid the failure of the electrostatic discharge element and enhance the electrostatic discharge protection ability. In addition, the above-mentioned multilayer path may be constructed of materials other than copper metal, such as resistors or other materials such as polycrystalline silicon, to further increase the electrostatic discharge protection capability of the electrostatic discharge protection circuit. In addition, the construction of the above-mentioned multi-layer path is compatible with the conventional semiconductor device manufacturing process, so it does not increase the number of process steps, that is, does not increase the cost of the process. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention Protection
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8618twfl.ptd 第14頁 533577 案號 91110706 %年)月|(/日 修正 圖式簡單說明 圖式之簡卓說明·· 第1圖所繪示為習知之半導體元件的焊墊到靜電放電 保護電路間之電路連接的剖面圖; 第2圖所繪示為習知之半導體元件的焊墊到靜電放電 保護電路間之電路連接的立體圖; 第3圖所繪示為本發明較佳實施例之半導體元件的焊 墊到靜電放電保護電路間之電路連接的剖面圖;以及 第4圖所繪示為本發明較佳實施例之半導體元件的焊 墊到靜電放電保護電路間之電路連接的立體圖。8618twfl.ptd Page 14 533577 Case No. 91110706% year) month | (/ day correction diagram brief explanation brief illustration of the diagram ·· Figure 1 shows the pads of conventional semiconductor components to the electrostatic discharge protection circuit A cross-sectional view of a circuit connection between two circuits; FIG. 2 illustrates a perspective view of a circuit connection between a conventional pad of a semiconductor device and an electrostatic discharge protection circuit; and FIG. 3 illustrates a semiconductor device of a preferred embodiment of the present invention A cross-sectional view of the circuit connection between the solder pad and the electrostatic discharge protection circuit; and FIG. 4 is a perspective view of the circuit connection between the pad of the semiconductor device and the electrostatic discharge protection circuit according to a preferred embodiment of the present invention.
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TW91110706A TW533577B (en) | 2002-05-22 | 2002-05-22 | Circuit structure for connecting bonding pad and ESD protection circuit |
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TW91110706A TW533577B (en) | 2002-05-22 | 2002-05-22 | Circuit structure for connecting bonding pad and ESD protection circuit |
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