TW531834B - Method of fabricating an ultra-shallow junction - Google Patents

Abstract

A method of fabricating an ultra-shallow junction on a semiconductor wafer. The method starts with providing an electric field in a predetermined direction for the semiconductor wafer, performing a pulsed plasma doping process to periodically attract an ion plasma onto the semiconductor wafer to form an ultra-shallow junction atop the source and drain, and performing a spike annealing process to activate ions implanted in the ultra-shallow junction.

Description

531834 V. Description of the invention (l) --- --- Field of the invention The present invention is very strong μ, which is known as a card for making an ultra shallow junction on a semiconductor wafer. JL? ± \ ζ A method for making a source and a light extension (s 〇urce / drai η extensi ο n) 3, make & >, 丄% shallow junction. Background: In the process of very large scale integration (VLS I), in order to effectively and accurately control the content and distribution of dopants in semiconductor wafers and reduce thermal budge, almost all of them are currently The doping process is performed by an ion implantation method. As the design size of electronic components continues to shrink, the future development direction of ion implantation technology is mainly focused on how to form a shallow junction process technology and how to use nanometer process technology to make metal oxide semiconductors ( Light-doped drain (LDD), source, and end of metal-oxide semiconductor (MOS) transistors. Please refer to FIG. 1 to FIG. 4, which are schematic diagrams of a method for making a shallow junction surface 29, 31 on a semiconductor wafer 10 surface. As shown in Fig. 1, the conventional method is to perform a conventional gate process on the surface of the substrate 12 of the semiconductor wafer 10 to form a gate 14. The gate electrode 14 includes a gate oxide layer 16 provided on the surface of the substrate 12, a polycrystalline silicon layer 18 provided on the surface of the gate oxide layer 16, and two side walls 20 provided on the gate 14 two vertical side walls. on.

Page 4 531834 V. Description of the invention (2) As shown in Figure 2, then use the side wall 20 as a mask, and follow the direction shown by the arrow 22, that is, the direction perpendicular to the base 2 An ion implantation process to form a doped region (not shown) on the surface of the substrate 12 outside the sidewall 20, and then perform a rapid thermal processing (RTP) process to make the doped region The dopants are driven into the substrate 2 to form a source 24 and a drain 26 respectively in the substrate 12 on both sides of the gate 14. As shown in FIG. 3, another ion distribution process is performed according to the direction shown by arrow 28. Since the ion distribution direction 28 and the gate electrode 4 form an inclination angle q, the implanted ions can be avoided on the substrate. A channel effect is generated in the silicon crystal structure of 2 and a shallow junction doped region 29 is formed on the surface of the substrate 12 on the gate 14 side. Subsequently, an ion distribution process is performed on the surface of the other side of the gate 14 on the other side of the gate 14 according to the direction shown by the arrow 30. The ion distribution direction 30 also forms an inclination angle q with the gate 14, A shallow junction doped region 31 is formed on the substrate 12 on the other side of the gate electrode 14. In order to obtain a uniform dopant concentration between the shallow junction surface and 31, different directions can be used again, for example, the inclination angle q is between 30 ° and 60 °, and other ion distribution process is performed. As shown in the figure As shown in FIG. 4, a heat treatment is finally performed on the surface of the substrate 12 so that the ions in the implanted shallow junctions 29 and 31 undergo lateral diffusion (lateral d 1 ffus 1 on), and are adjacent to the source 24 and the drain, respectively. A source extension 32 and a drain extension 34 are formed in the substrate 26.

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V. Invention Description (3)

The conventional method uses an ion beam beam generated by an ion implanter to scan the semiconductor wafer 10 inclined at an angle, so that the ion beam is implanted in the substrate 12 to collide with Shi Xi atom, thereby destroying the crystal. The Shi Xi structure also generates interstitial in the base 12, that is, shallow junctions 29 and 31 are formed (the depth of which is usually about 300 to 600 angstroms). Later, by increasing the temperature of the heat treatment, the ions can be diffused laterally through the gaps of the shallow junctions 29, 31. As the accumulation of semiconductor elements increases, the depth of the shallow junction is also relatively reduced. Therefore, the implantation energy of the ion beam must be reduced in the process to meet the depth of the shallow junction. However, reducing the ion beam energy must reduce its ion current (b e a in c u r r e n t), and reducing the ion current will slow down its implantation speed, which will lead to prolonged production time and production cost. In addition, the method of implanting ions using a tilt angle is more likely to encounter the problem of uneven ion distribution and cost wastage caused by multiple implants. At the same time, it is easy to cause ions to overly enter the area under the gate and affect the electrical performance of the device. SUMMARY OF THE INVENTION Therefore, the object of the present invention is to provide a method for manufacturing an ultra-shallow junction to meet the requirement of increasing the component accumulation degree. In the method of the present invention, a gate, a source, and a drain of a plurality of N M 0 S transistors are formed on a substrate of the semiconductor wafer, and then a pulsed plasma doping is performed on the semiconductor wafer using an electric field in a predetermined direction. Miscellaneous processes

Page 6 531834 V. Description of the invention (4) (pulsed plasma doping process) 'so that an ion beam is intermittently added to the surface of the semiconductor wafer' to form the super shallow junction on the source and non-electrode surfaces. Finally, a rapid tempering process is performed to activate the ions in the super shallow junction. Since the present invention uses an electric adsorption principle to add an ion plasma to the surface of a semiconductor wafer, its dose stays almost entirely at the depth near the source and drain surfaces, so that subsequent heat treatments do not cause the super shallow junctions The doped ions tend to a depth beyond the requirements, which can effectively suppress the lateral diffusion of ions. In addition, using this heat treatment to heal in § the crystalline structure of the substrate surface can also effectively save thermal budget. Detailed description of the invention Please refer to FIGS. 5 to 10, which are schematic diagrams of a method for making an ultra shallow junction 72 according to the present invention. As shown in FIG. 5 ', the semiconductor wafer 40 includes a P-type substrate 42. As shown in FIG. The method of the present invention first performs a conventional gate process' on the surface of the substrate 4 2 to form a gate 44 of an N MOS transistor. The gate electrode 44 includes a gate oxide layer 46 disposed on the surface of the substrate 4 2, a polycrystalline stone layer 48 disposed on the surface of the gate oxide layer 46 and two side walls 50 disposed on the gate electrode 4 4. Two vertical sidewalls. As shown in FIG. 6, the side wall 50 is used as a mask ’according to the direction shown by the arrow 5 2, that is, an ion distribution value is performed in a direction perpendicular to the substrate 4 2.

Page 7 531834 V. Description of the invention (5) The process 'uses N-type dopants such as arsenic (As) or other VA group atoms' to control its dopant concentration to be about lxl0Hcm-2 to 5xl0i5cm-2, and its The implantation energy is about 50 ~ 150KeV to form a two-doped region (not shown) on the surface of the substrate 42 outside the sidewall 50. Subsequently, a rapid heat treatment process is performed to allow the dopants in the doped region to enter the substrate 42 so that the source 5 4 and the non-polar 5 6 of the MS transistor are formed in the substrate 42 on both sides of the gate 44. . Next, as shown in FIG. 7, the semiconductor wafer 40 is placed in a pulsed plasma doping device 60 to perform a pulsed plasma doping process. The pulse type plasma doping equipment 60 is placed in a vacuum reaction chamber, which includes a wafer holder 62 'for horizontally holding the semiconductor wafer 40, and the two parallel electrode plates 64 and 66, respectively. The lower two are placed on the wafer holder 62 to provide a uniform electric field E of the semiconductor wafer 40, and the direction is the same as the arrow M. Subsequently, an ion plasma 70, such as an antimony (Sb +) plasma or water ion-in-water, is injected into the pulse plasma doping equipment 60, and the dosage of the ion plasma 70 is between 10 and 5 to 1. 〇1 ^ _2, and ^ misf are set between 20 OeV ~ 10KeV. Since the implanted handyman + y " b / eight < ion plasma 70 is electrically positive, it is attracted to the surface of the semiconductor wafer 40 due to its "movement f" in the vacuum reaction chamber. 0 ~ Alarm By controlling the supply time period (cvc 丨 & + λ π time) of the electric field E,

The ion plasma 70 is intermittently adsorbed to the surface of the semiconducting u_J and the solar panel 40. As shown in FIG. 8, when an electric field E is generated by the electrode plates 64 and 66, ions can be adsorbed on the surface of the semiconductor wafer 40, and no electricity is generated on the electrode plates 64 and 66.

531834

Each time, the ion plasma 70 can no longer be adsorbed to the semiconductor wafer 40, but the ions that have previously adsorbed to the surface of the semiconductor wafer 40 can react with the substrate 42 for a sufficient time, thereby promoting doping of the substrate 42. :: Uniformity. In other embodiments of the invention, the pulse plasma doping process is performed by controlling the time period of the ion plasma 70 injection, for example, using an implant to intermittently inject the ion plasma 70 into the air. Inside the Anti-Kung Palace, Shou Yi Chong-style doped eyes #. A reaction until the inner ridge reaches a pulse

As shown in FIG. 9, the surface of the final plasma 4 2, that is, the source 5 4 and the miscellaneous region 7 2, has a depth of the interface of about 5 lines—a rapid tempering process. The active edge of the ion forms a source extension 74 to> T> τ. The surface of the base drain electrode 56 on the two sides of the side wall 50 of the ion 70 forms an ultra shallow junction 100 to 300 angstroms (a). After that, it is heated again in an instant (about 1000 ~ 120.00). (:) 's are replaced by the source 5 4 and the drain and 7 6 respectively, as shown in Figure 10.

Wafer 4 & sub-plasma 70 is added to the semiconductor 5 6 π using an electrical adsorption principle, so its agent almost stays in the vicinity of the source 5 4 and in the drain ^ # heteroII degree, also makes Subsequent heat treatment will not cause the son of the super shallow junction 72 to reach a depth beyond the requirements, ... effectively suppress the ion crystal structure factory. In addition, 'using this heat treatment to heal the m-plane junction of the substrate' can also effectively save the thermal budget.

Page 9 531834 V. Description of the invention (7) Compared with the conventional method of making shallow junctions, the present invention uses the electric adsorption of a quantity of ion plasma to make ions intermittently doped to The surface of the wafer thus provides a uniform and relatively low resistance contact surface between the source and the drain. In addition, the present invention does not need to reduce the dopant energy. It is also necessary to use the ion implantation method of the inclination angle, that is, to meet the requirements of the depth of the SIA-roadmap (SIA-roadmap) interface (0 · 丨 micron, process The junction depth should be between 200 and 400 angstroms), so not only can the component accumulation be improved, but also effects such as pUnch through and short channel effects can be avoided. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.

Page 10 531834 Brief description of the diagrams Brief description of the diagrams Figures 1 to 4 are schematic diagrams of a conventional method for making a shallow junction. Figures 5 to 10 are schematic illustrations of the method for making an ultra-shallow junction according to the present invention. 10 Semiconductor wafer 12 Substrate 14 Gate 16 Gate oxide layer 18 Polycrystalline silicon layer 20 Side wall 22, 28 ^ 30 Ion distribution Process 24 source 26 sink 29 ^ 31 shallow junction 32 source extension 34 sink extension 40 semiconductor wafer 42 substrate 44 gate 46 gate oxide 48 polycrystalline silicon layer 50 side 52 ion layout process 54 source 56 sink Electrode 60 Pulse Plasma Doping Device 62 ^ 64 Electrode Plate 66 Wafer Holder 68 Electric Field Direction 70 Ion Plasma 72 Ultra Shallow Junction 74 Source Extension 76 Drain Extension

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Claims (1)

531834 6. Application Patent Scope 1. A method for making an ultra-shallow junction on the surface of a semiconductor wafer. The substrate of the semiconductor wafer is provided with a plurality of gates and source and sink electrodes of NMOS transistors. The method includes the following steps: providing an electric field in a predetermined direction of the semiconductor wafer; performing a pulsed plasma doping process, so that an ion plasma is intermittent Added to the surface of the semiconductor wafer to form the super shallow junction on the source and drain surfaces; and a spike annealing process is performed to activate the ions in the super shallow junction to activate the substrate . 2 · The method according to item 1 of the patent application scope, wherein the super shallow junction is used as a source extension and a drain extension 'to provide the source and the > and extremely low Resist the contact surface and avoid situations such as punch through and short channel effect ° 3 · As in the method of the first item of the patent application, wherein the ion plasma is an antimony ion (antimony , Sb +) plasma. 4. The method according to item 1 of the scope of patent application, wherein the pulsed plasma doping process system controls the time period of the ion plasma injection (cyc 1 6 ^ i ^ e) so that the ion plasma is intermittent Obtained by adsorption to the surface of the semiconductor wafer Page 12 531834 VI. Scope of patent application Sufficient response time to form uniform super shallow junction. 5. The method according to item 1 of the patent application, wherein the pulsed plasma doping process controls the time period of the electric field supply so that the ion plasma is intermittently adsorbed on the surface of the semiconductor wafer to obtain a sufficient response. Time to form a uniform super shallow junction on the surface of the semiconductor wafer. 6. The method according to item 1 of the patent application scope, wherein the thickness of the super shallow junction is about 100 to 300 angstroms (angstrom, A). 7. The method according to item 1 of the patent application, wherein the dopant energy of the pulse plasma doping process is about 200 eV ~ 1 OKeV, and the concentration of the dopant is about 1015-1017 cm-2. 8. The method according to item 1 of the scope of patent application, wherein the rapid tempering process is an instant heating method with a zero holding temperature time, and the temperature is controlled between 1 000 and 12 00 ° C. Page 13