TW530195B - Alignment error calculating method, alignment measuring apparatus and yield analytic apparatus - Google Patents

Abstract

For the purpose of readily getting hold of relationship between alignment errors and the yield of products and reducing the time required for analysis of the yield, alignment errors are measured in five to nine shots (4) on a semiconductor wafer (3), and from the result of this measurement, linear factors of alignment errors (array shift (X0, Y0), array axial magnification (Xp, Yp), array axial rotation (Y(theta), X(theta)), shot axial magnification (Xm, Ym) and shot axial rotation (Xc, Yc) are calculated. Then, using two equations, DeltaX=X0+XpX-Y(theta)Y+Xmx-Ycy, DeltaY=Y0+YpY+X(theta)X+Ymy+Xcx using these linear factors (where (X, Y) is coordinates of the center of the shot (4) when setting the origin at the center of the substrate, and (x, y) is coordinates of points for characteristic evaluation when setting the origin at the center of the shot (4)), alignment errors (DeltaX, DeltaY) of resist patterns in all shots (4) on the semiconductor wafer (3) are calculated. Then, by comparing the result of the alignment error calculation with a result of characteristic evaluation of semiconductor devices, the yield of the semiconductor devices is analyzed.

Description

530195 V. Description of the invention (i) Background of the invention The present invention relates to an alignment error calculation method, an alignment measurement device, and a yield analysis device, and is particularly suitable for the relationship between the alignment error and the alignment error and the characteristic evaluation. analysis. Description of Related Art In the process of manufacturing an impedance pattern using a scanning type exposure device, such as a semiconductor lithography process, alignment measurements are derived to view the alignment of the pattern formed in a previous step. Traditionally, as shown in FIG. 1, in order to save the reading time of the product, such alignment measurement is only performed on a few exposures or wafers (hereinafter collectively referred to as exposures) 102, such as five to nine exposures On a semiconductor wafer 101 instead of all exposures or wafers on the semiconductor wafer 101. A result of this measurement is shown in Table 1. Table 1

X

Y Number of measured points 36 Maximum (/ zm) 0.2 0.026 Minimum (// m) 0.099 -0.064 Average (// m) 0.147-0.022 3 a (nl) (/ zm) 0.088 0.064 1 Average 1 + 3 (7 (// m) 0.234 0.085 As shown in Table 1, the alignment error is controlled using an alignment measurement with only a minimum number of exposures of 102, such as several exposures of 1.02. Measured value

Page 6 530195 V. Description of the invention (2) Calculated statistical value (I mean I + 3 σ). This method of controlling misalignment is a standard method for misalignment. The advantage of the decimal method is that the speed control alignment error. However, it is difficult to grasp the relationship between the misalignment of bismuth and the yield of semiconductor devices due to the fact that the traditional method does not measure all. That is, in order to examine the yield of an analysis yield product, and to analyze the relationship between the evaluation results of the misalignment of the exposure, the alignment error between the patterns must be re-measured for the Feng 1 102. In addition, since the measurement of the alignment error is derived using the box marks at the corners, a difference occurs in the alignment measurement. Therefore, traditional methods need to be analyzed. OBJECTS AND SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method, an alignment error measuring device and a yield analysis device, and obtain a minimum measurement result from an alignment error and provide a reduction in the time required for the yield analysis. According to a first aspect of the present invention, a method is provided, which is characterized by: setting a plurality of unit areas on a substrate; measuring and forming a target measurement point during a first drawing printing process on the substrate, and the square exposure Alignment error, the difference between the possible factors between the evaluation results, and the yield of the semiconductor device. There are many differences between the four points of the exposure or the wafer and the characteristic evaluation points. Time to do yield and sort the alignment error calculation method, can grasp the relationship between the alignment error yield, a second figure related to an alignment error calculation scheme

Page 7 530195 V. Explanation of the invention (3) and the second pattern is composed of M unit regions selected from the unit region; and one of the M unit region alignment errors is used. The measurement results are used to calculate the alignment error of the second pattern in N unit regions. According to a second aspect of the present invention, there is provided an alignment measurement device that is planned to set a plurality of unit areas on a substrate, and includes an alignment measurement device to measure a first pattern formed on the substrate. An alignment error of a second pattern, and constructing the second pattern in M unit regions selected from the unit region, including: using the alignment error obtained from the M unit regions by the alignment measurement device A measurement result, a device for calculating an alignment error of the second pattern in N unit regions. According to a third aspect of the present invention, a yield analysis device is provided to analyze the yield of a semiconductor device formed on a substrate, including: setting a plurality of unit regions on the substrate; and aligning a measurement device to measure and An alignment error of a second pattern related to a first pattern formed on the substrate, and the second pattern is formed in M unit regions selected from the unit region; an alignment measurement device to utilize the The alignment measurement device obtains a measurement result of the alignment errors of the M unit areas, and calculates the alignment errors of the second pattern in the N unit areas. The characteristic evaluation device evaluates the semiconductors in the N unit areas. Characteristics of the device; and a yield analysis device, the second figure calculated by the alignment error calculation device

530195 V. Description of the invention (4) A calculation result of the alignment error and an evaluation result of the characteristics of the semiconductor device evaluated by the characteristic evaluation device to analyze the yield. In a typical method of the present invention, a measurement result of the alignment error in the second pattern measured in M unit regions is used to calculate the alignment of the second pattern in all unit regions in a substrate. error. In a typical method of the present invention, the alignment error in the second pattern in N unit areas is calculated using a linear factor calculated from a measurement result of the alignment error in M unit areas. .

In a typical method of the present invention, the alignment error in the second pattern in N unit areas is selected from the group consisting of array displacement, array axis magnification, array axis rotation, and axis magnification of one unit area. And the axis rotation of the unit area, the center coordinates of the unit area on a substrate, and multiple factors among a group of coordinates of an evaluation point in the unit area. In a typical practice of the present invention, the unit area is an area of a single wafer formed on a substrate. In a preferred method of the present invention, the substrate is a semiconductor substrate, such as a Si substrate or a sintered substrate, and the unit area is an area of a single semiconductor device wafer formed on the semiconductor substrate.

In a typical method of the present invention, the second pattern is caused by using an exposure device, and the unit area is a single exposure area exposed by the exposure device. Further, in the present invention, the second pattern is usually an impedance pattern transferred by an exposure device, and the unit area is a single exposure of the impedance pattern exposure. Further, in the present invention,

Page 9 530195 V. Description of the invention (5) The exposure device is preferably a scanning type exposure device, but any other appropriate exposure device can also be used. In a typical method of the present invention, the number of unit areas M for which an alignment error measurement is made is .5 $ M S 9. That is, the alignment error measurement in the second pattern is performed on 5 to 9 unit areas on the substrate, and the result of the alignment error measurement is used to make N unit areas or all on the substrate Calculation of area alignment errors. According to the invention with the specifications outlined above, since the alignment errors of N unit areas on a substrate are calculated from the measurement results of the alignment errors of M unit areas using an alignment error measuring device, it is possible to measure the The alignment error of the smallest unit area between a plurality of unit areas is calculated as "the alignment error of the second pattern in any unit area on the substrate, and the alignment error can be easily controlled. The above and other aspects of the invention The objectives, features, and advantages will become more apparent in the following detailed description, read in conjunction with the related drawings. Brief Description of the Drawings Figure 1 shows a vector diagram in the form of a conventional alignment measurement device. FIG. 2 is a diagram explaining an alignment error measurement method according to a specific embodiment of the present invention; FIGS. 3A to 3C are diagrams explaining one according to the present invention A diagram of a linear factor of a specific embodiment; FIGS. 4A and 4B are diagrams explaining a linear factor according to a specific embodiment of the present invention;

Page 10 530195 V. Description of the invention (6) FIG. 5 is a diagram explaining an example of an alignment error calculation according to a specific embodiment of the present invention; FIG. 6 is a diagram showing a specific embodiment according to the present invention. FIG. 7 is a diagram showing a characteristic evaluation result of a pattern on a semiconductor wafer according to a specific embodiment of the present invention; 8 is a block diagram of an alignment error measurement device according to a specific embodiment of the present invention;

FIG. 9 is a diagram showing a GUI display showing a calculation result of nine exposure alignment errors on a semiconductor wafer according to a specific embodiment of the present invention; FIG. 10 is a diagram showing one according to the present invention A specific embodiment shows a graphical representation of a GUI display as a dialog box for inputting internal coordinates of exposures; FIG. 11 is a diagram showing alignment errors of all exposures displayed on a semiconductor wafer according to a specific embodiment of the present invention A diagram of a calculation result of a GUI display; FIG. 12 is a vector diagram showing a calculation result based on an alignment error of all exposures on a semiconductor wafer according to a specific embodiment of the present invention A graphic representation of a GUI display;

FIG. 13 is a block diagram showing the specifications of an η yield analysis system according to a specific embodiment of the present invention; and FIG. 14 is an example showing an example of the relationship between a characteristic evaluation result and an alignment error calculation result. Output chart. Description of preferred embodiments

Page U 530195 V. Description of the Invention (7) Hereinafter, a specific embodiment of the present invention will be explained with reference to the drawings. In all the drawings describing this specific embodiment, the same or equivalent parts or elements are marked with the same reference numerals.

First explained is a method for calculating an alignment error according to the specific embodiment of the present invention. In the alignment error calculation method according to this embodiment, the alignment error is measured on an impedance pattern formed by lithography using a scanning type exposure device, for example, in a method that already has a semiconductor device manufacturing process The semiconductor wafer is formed in a predetermined pattern. This alignment error measurement on the impedance pattern was made for only five to nine exposures on the semiconductor wafer to save product read time. In this specific embodiment, as shown in FIG. 2, the nine exposures 2 (parts of the daytime hatching in FIG. 2) on the semiconductor wafer 1 are used to measure the alignment error. A single exposure 2 includes one to six wafer regions. A result of this measurement is shown in Table 2.

Table 2 Number of XY measured points 36 36 Maximum value (" m) 0.200 0.026 Minimum value (/ zm) 0.099 -0.064 3 σ (// m) 0.088 0.064 1 Mean | + 3σ (μπι) 0.234 0.085 Array Displacement (Vm) 0.147 -0.022 Array axis magnification (μm) 0.100 -0.100 Array axis rotation (ppm) 0.500 0.200 Exposure axis magnification (ppm) -0.700 -0.700 Exposure axis rotation (ppm) 0.300 0.300

Page 12 530195 V. Description of the invention (8) As shown in Table 2, the alignment error measurement of the impedance pattern according to the present invention is performed for nine vertices of the exposure 2 as shown by hatching in FIG. 2. That is, the number of measured points totals 36 out of nine exposures. Figure 2 shows the results of the alignment error measurements at these 36 points in the form of a vector.

It can be known from Table 2 that the alignment errors of the nine exposures 2 displayed on the semiconductor wafer 1 by hatching range from the maximum value of 0.2 0 0 // m to 0.09 9 / zm in the X-axis direction. The minimum value and the range in the Y-axis direction from the maximum value of 0.026 / zm to the minimum value of -0.064. Further, the factors of | mean | + 3σ shown in Table 2 include so-called linear factors such as array displacement, array axis magnification, array axis rotation, exposure axis magnification and exposure axis rotation, and so-called non- The linear factor is represented by random errors. The linear factor among the above-mentioned factors of the average value I + 3 σ is explained more specifically as follows. Figs. 3A to 3C graphically show the linear factors related to the semiconductor wafer 1, and Figs. 4A and 4B graphically show the linear factors related to an exposure 2. In Figs.

Figure 3 A shows that the array displacement is one of the linear factors. As shown in FIG. 3A, the array displacement is a linear factor and is composed of an X-axis error amount (X array displacement) XQ and a Y-axis error amount (Y array displacement) YG of the entire semiconductor wafer 1. In this specific embodiment, it can be known from Table 2 that the X array displacement XQ is 0.14 7 / z m, and the Y array displacement Y 0 is 0. 0 2 2 // m. Figure 3B shows the array axis zoomed to one of the linear factors. As shown in FIG. 3B, the array axis magnification is a ratio in which the center of the semiconductor wafer 1 is enlarged or reduced in the radial direction of the semiconductor wafer. Also, the array axis magnification is

Page 13 530195 V. Description of the invention (9) A linear factor is composed of an X-axis array axis magnification (X-array axis magnification) xp and a Y-axis array axis magnification (Y-array axis magnification) Yp. In this specific embodiment, it can be known from Table 2 that the X array axis magnification Xρ is 0. 100 ppm, and the Y array axis magnification γ p thereof is -0.10.1 p p m. The p p m used here is a unit of change 0. 1 // m every 10 cm 〇 Figure 3C shows that the array axis rotation is one of the linear factors. As shown in Figure 3C, the rotation of the array axis is the ratio of the deviation of the semiconductor wafer in the rotation direction with its center as the origin, and is a linear factor, which is determined by an X-axis offset ratio (X-array axis rotation) X ( Θ) and a Y-axis offset ratio (Y array axis rotation) Y (Θ). In this specific embodiment, it can be known from Table 2 that the X array axis rotation X (0) is 0.5 ppm, and the Y array axis rotation Y (0) is 0.2 0 Oppm. FIG. 4A shows the exposure. The beam axis is enlarged to one of the linear factors. As shown in FIG. 4A, the exposure axis magnification of a single exposure 2 is a linear factor, which is the ratio of the enlargement or reduction of an exposure 2 in the X-axis direction (X exposure axis magnification) Xm and an exposure 2 at The ratio of enlargement or reduction in the Y-axis direction (Y-exposure-axis enlargement) Ym. In this specific example, it can be known from Table 2 that the X exposure axis magnification Xm is -0.700 ppm, and the Y exposure axis magnification YmS-0.70 0 ppm. FIG. 4B shows that the exposure axis rotates as one of the linear factors. As shown in FIG. 4B, the rotation of the exposure axis is a ratio of the deviation of the center of the exposure 2 in the rotation direction, and is a linear factor, which is offset by an X axis (X exposure axis rotation) Xc and a Y axis deviation (Y The exposure axis rotates) Yc. In this specific embodiment, it can be known from Table 2 that the X exposure axis is rotated by X. It is 0.300 ppm, and its Y exposure axis rotation Yc is 0.300 ppm.

Page 14 530195 V. Description of Invention (ίο) Next, the alignment error of all exposures 2 on the semiconductor wafer 1 based on the results of the alignment error measurement shown in Table 2 is calculated. The calculation of the alignment error is based on the individual exposure 2 (hereinafter referred to as a characteristic evaluation point) on the semi-circle 1 at the measurement point based on the evaluation of the characteristics of the semiconductor device. That is, the calculation of the alignment error from Equations (1) and (2) shown below is first derived, using the linearity factor calculated from the results of the alignment error measurements shown in Table 2. Δ χ = 〇〇 + ΧρΧ-Υ (Θ) Y + Xmx-Y〇y (1) Δ Υ-Υ〇 + ΥρΥ + χ (0) X + Ymy + Xcx (2) Equation (1) is used to Calculate the x-axis alignment error Δ X 'and Equation (2) is used to calculate the Y-axis alignment error ΔΥ. In equations (1) and (2), X and γ are used to calculate the coordinates of the center position of an exposure 2 with the error ^, and X and y are the coordinates of characteristic evaluation points within an exposure. Here we use equations (1) and (2) to explain an example of alignment error calculation. In this calculation example, the exposure 4 surrounded by a circle on the semiconductor wafer 3 shown in Fig. 5 is selected as the calculation of the Y-axis alignment error. For easier understanding, it is assumed here that Y0 = 0, 1 // m, Yp = 2ppm, 2) 0, γ, 0, xc = 0, and the size of the exposure 4 is 20mm X 20mm. When the center of the semiconductor wafer 3 is set At the origin, the Y-axis coordinate of the characteristic evaluation point of Exposure 4 selected for the calculation of the alignment error is 50 mm. Then, the Y-axis alignment error ΔY of the characteristic evaluation point of the exposure 4 is calculated from equation (2) as: ΔYY〇 + YpY + X (^) X + Ymy + Xcx = 0.1 + (2/1 0 0 0 0 0 0) X 5 0 0 〇〇 + 〇 + 0 + 〇 = 〇. 2 # m

530195 V. Description of the invention (11) As the above calculation example, the X-axis alignment error ΔX and the Y-axis alignment error Δ Y · are calculated for all exposures 2 on the semiconductor wafer 1 shown in FIG. 2. In this specific example, using the number of linear factors shown in Table 2, the X-axis alignment error △ X and the Y-axis alignment error AY are calculated for all exposures 2 on the semiconductor wafer 1 shown in FIG. 2. Each of them. A result of this calculation is shown in Figure 6. As shown in FIG. 6, in the individual exposures 2 displayed on the semiconductor wafer 1, the upper value is the X-axis alignment error ΔX, and the lower value is the Y-axis alignment error Δ γ. On the other hand, in order to compare with the calculated value of the impedance pattern alignment error calculated by the alignment error calculation i method according to the present embodiment, the characteristics of a semiconductor device having a pattern by using the impedance pattern are Evaluation. The evaluation of this characteristic is completed at a predetermined characteristic evaluation point of the individual exposure 2. One result of this evaluation is shown in Figure 7. In FIG. 7, "0K" is displayed in the exposure 2 area evaluated as having good characteristics, and "NG" is displayed in the exposure 2 area evaluated as being poor. In this specific embodiment, out of -52 areas of 2 exposures, 25 areas of 2 exposures were evaluated as bad, and the product yield was 27/52. Next, by comparing the calculated values of the alignment errors of all the exposures 2 on the semiconductor wafer 1 shown in FIG. 6 with the evaluation of characteristic evaluation points in the area of all the exposures 2 on the semiconductor wafer 1 shown in FIG. 7 As a result, it can be known that the evaluation of the internal characteristics of the exposure 2 on the semiconductor wafer 1 shown in FIG. In this way, the relationship between the alignment error and the characteristic evaluation results of all the exposure 2 regions on the semiconductor wafer 1 can be understood, and the yield can be analyzed. This ,

Page 530195 V. Description of the invention (12) This is particularly effective for the future in the straight line < τ < μ such as 3 0 0 _ semiconductor wafer ^ gradually increasing semiconductor wafers' example is explained next | & 呌 ΐ 方 呌 ΐ仏 疋 应用 Apply the alignment error 22 according to the present embodiment, the two alignment measurement devices are green, and the alignment measurement device 10 according to the present embodiment includes the following: Six, u, the control section 12, the combination of the call storage section q formed by ROM, RAM and VRAM, and the input section 15. ， CRT display part 1 4 (cathode radiation tube) ’The alignment measurement Qiu Ba] e

The alignment error σP knife 11 疋 is used to measure a picture on the semiconductor wafer 1. The control section 1 9 I performs various arithmetic operations. $ ϋ Controls the entire alignment device 10 ′ and can generate social services. The decisive part I of the side health storage section 1 3 is not only used to store data for measurement = it is an operating system of the alignment measurement device 10 and so on. For example, VRAM or others are stored in the storage section 13. For example, at Yau Tak Chuen. ， Domain storage domain ’The image data generated by the controller 12 is more than one thousand? -The image data stored in the VRAM of the storage section 13 is displayed β Γ π τ Γ PI P knife 14. In this case, the graphic display of the image data (the graphic Weitian Mingba, the hairy candle — the text user; | surface) graphic display. The image data by the control portion 12 and the portion 13 include, for example, image data of a window, a cursor, and two images. In this alignment measurement device 10, f1, a variety of image data is displayed on the display portion 14's quasi-presentation: then the strong man appears. In addition, the control section 1 2 is planned to control the alignment measurement section 11 to measure five to nine exposures #, to ′, and the remote display section 1 4 shows that the alignment measurement device i 1

Page 17 530195 V. Description of the invention (13) The predetermined information among various information output is displayed as a GGI. What is explained next is a method for measuring the alignment error of an impedance pattern formed on the semiconductor wafer 1 and calculating the alignment error of all the exposures 2 and, more specifically, referring to a G U I display. First, in the alignment measurement section 11, similar to the case of alignment error measurement, the alignment error of the impedance pattern formed on the semiconductor wafer 1 is measured. In this specific embodiment, as shown in FIG. 9, the alignment error is measured on the nine wafers (the shaded portion in FIG. 9) on the semiconductor wafer 1. The results of this measurement can be displayed in the G U I display 2 0 as a vector graph. The GUI display shown in Figure 9 is explained in more detail. That is, according to the specific embodiment, the GUI display of the alignment measurement device 10 is prepared on the window 21 to display the semiconductor wafer 1, for example, a coordinate button 22 to open a dialog box for inputting as if After explaining the internal coordinates of the exposure, a vector diagram displays a button 2 3 to display an alignment error measurement result. With respect to the nine measured exposures 2, an estimated result vector displays a button 2 4 to display on the semiconductor wafer 1 An estimated result of the alignment error (△ X, △ Υ) of all the exposures 2 on the above, and an estimated value display button 25 shows an estimated result of the alignment error (△ X, △ Υ) in numerical values as shown in Fig. 6 Shown the same way. In the GUI display 20, when the coordinate button 22 is passed through a mouse (not shown), for example, it is provided to the input part 15 of the alignment measurement device 10, and when clicked, as shown in FIG. 10 The dialog boxes 2 6 shown are displayed. This dialog box 2 6 includes exposure internal coordinate input sections 2 7, 2, 8, 2, 9, 30, 3 1 to input the coordinates of the characteristic evaluation points of the exposure 2, and check buttons 2 7 a, 2 8a, 29a. , 30a, 31a are provided to the left. In this dialog box 26

Page 18 530195 5. In the description of the invention (14), two offset blocks 3 2, two exposure blocks 3 3, and two estimated value display blocks 3 4 are provided. The square on the left is the X-axis coordinate, and the square on the right is the Y-axis coordinate. To the right of the exposure block 3 3, a calculation button 35 is provided. Next, the exposure internal coordinates of the characteristic evaluation point are input through a keyboard (not shown), for example, provided in the input part 15 of the alignment measurement device 10, and entered in the exposure internal coordinate input of the dialog box 26. Part 2 7. In this specific embodiment, since the characteristic evaluation point is set at the origin (center) of the exposure 2, for example, after 0 is input to the two input parts of the internal coordinate input part 27 of the exposure, the left The check button is clicked with, for example, a mouse. After that, based on the measurement results of the nine exposures 2 measured by the alignment measurement section 11 and the internal coordinate input box 2 that was entered into the exposure The internal coordinates of the exposure of the characteristic evaluation point of 7 and the alignment errors of all the exposures on the semiconductor wafer 1 are calculated. The time required to do such an alignment error calculation is a few seconds. After that, if necessary, the estimated value display button 25 shown in Fig. 9 is clicked with a mouse as mentioned above. The results are shown in FIG. 11. The calculation results of the alignment errors (Δ X, Δ Y) of the characteristic evaluation points of all the exposures 2 on the semiconductor wafer 1 are indicated by numerical values in the same manner as in FIG. 5. GUI display 20 in window 21. In addition, if necessary, the estimated result vector shown in FIG. 9 shows that by the sister 2 4 was clicked with a mouse. The results are shown in Fig. 12. The alignment errors (△ X, △ Y) of the characteristic evaluation points of all the exposures 2 on the semiconductor wafer 1 are calculated.

Page 19 530195 V. Description of the invention (15) As a result, the window 2 1 displayed in the GUI display 2 0 is a vector graph. As explained above, by integrating the alignment measurement device 10 with the calculation of the alignment error function of the control section 12 and the exposure of the internal coordinates of the input characteristic evaluation points, it is possible to realize that the alignment measurement device can By using a result of the alignment error measurement of the five to nine exposures on the semiconductor wafer 1 by the alignment measurement portion 11, the alignment errors of all the exposures on the semiconductor wafer 1 are calculated. As a result, the development of semiconductor devices such as optimization of design rules and yield analysis can be effectively achieved, and the time required to develop and design semiconductor devices can be significantly reduced. Explained next is another apparatus example using the alignment error calculation method according to the present embodiment. Fig. 13 shows a yield analysis system having an alignment error calculation function according to this embodiment. As shown in FIG. 13, the yield analysis system according to this embodiment includes a host computer 4 1, a defect inspection device 4 2, a focused scanning electron microscope (CD-SEM) 43, and an alignment measurement machine 44 The characteristic evaluation device 45, the analyzer 46, the terminal device 47, and the printer 48 are connected by a cable 49. The host computer 41 is a server of a device connected via the cable 49. The defect inspection device 42 is used to inspect the presence or absence of a pattern defect formed on a substrate. CD-SEM 43 is an electron microscope that measures the line width of small patterns on a cover film or semiconductor wafer. The analysis device 46 is a device that analyzes a semiconductor device formed on the semiconductor wafer 1. The terminal device 47 is a device that controls the host computer 41. The printer 48 is used to output predetermined information on, for example, paper.

530195 V. Description of the invention (16) The alignment measurement machine 44 is a device similar to the alignment measurement device, and is planned to have an alignment error of five to nine exposures 2 on the semiconductor wafer 1 Measure, measure the alignment error at 20 to 36 points, and calculate the alignment error of all exposures 2 on the semiconductor wafer. The characteristic evaluation device 45 is a device for evaluating characteristics of a semiconductor device formed on the semiconductor wafer 1.

Among the yield analysis systems having the above explained specifications, the alignment measurement device 44 first measures the alignment errors within five to nine exposures 2, similar to the measurement in the above-explained alignment error calculation method. Thereafter, in the alignment measurement machine 44, the alignment error is calculated from the results of the alignment error measurement using equations (1) and (2) from all the exposures 2 on the semiconductor wafer 1. come out. On the other hand, among the characteristic evaluation devices 45, the characteristics of the semiconductor device formed on the semiconductor wafer 1 are evaluated. In this specific embodiment, for example, the impedance to the voltage is evaluated. Next, information on the internal coordinates of the exposure of the characteristic evaluation point by the characteristic evaluation device 45 is provided to the alignment measurement device 44. After that, the alignment measurement device 44 calculates the alignment error at the individual characteristic evaluation points of all exposures on the semiconductor wafer 1 to be evaluated.

Thereafter, the host computer 41 is provided with information on the characteristic evaluation results of all the exposures 2 on the semiconductor wafer 1 and information on the calculation results of the alignment error, the characteristic evaluation results and the calculation results of the alignment error. The relationship between them is calculated and output. The output of a calculation is shown in Figure 14. In Fig. 14, the part with good impedance to the voltage is colored and shown, and

Page 21 530195 V. Description of the invention (17) The part with unsatisfactory impedance to the voltage is shown with a slash. · It can be seen from FIG. 14 that among the semiconductor devices whose calculation results have an alignment error of 0 / z m, 100% of the devices having a good impedance to the voltage accounted for 100%, and all semiconductor devices had sufficient impedance to the voltage to be confirmed. It can also be known from FIG. 14 that among the semiconductor devices whose calculation results have an alignment error of-, about 20% of the devices have a good impedance to the voltage, and 80% of the semiconductors have a poor impedance to the voltage. In addition, regarding semiconductor devices each having an alignment error of -0.02 ym, -0.04 // m, -0.06 / zm, and -0.08 / zm, the ratio of semiconductor devices having sufficient resistance to voltage impedance can be known in the same manner. As explained above, since the host computer 41 has an alignment measurement device 4 4 and a characteristic evaluation device 4 having an alignment error calculation function by the alignment error calculation method according to the specific embodiment of this ___ Establishing a connection between 5 makes it possible to obtain the relationship between the calculation result of the alignment error and the result of the characteristic evaluation, and therefore, the yield can be easily analyzed. Therefore, 'misalignment' measures alignment errors within only nine exposures on the semiconductor wafer 1, it is possible to realize that the yield analysis system can analyze the alignment errors of all exposures 2 on the semiconductor wafer 1. And the yield of semiconductor devices. As explained above, according to the present embodiment, due to the alignment errors (ΔX, ΔY) in all exposures on the semiconductor wafer 1, only the nine exposures 2 on the semiconductor wafer 1 Calculated from the alignment error measurement results. Therefore, the relationship between the calculation result of the alignment error of the exposure 2 and the characteristic evaluation result of the semiconductor device formed on the semiconductor wafer 1 __ can be known. As a result, the design rules for developing a semiconductor device can be effectively determined, and the yield of the final product through a semiconductor device manufacturing process can be effectively divided-

Page 22 530195 V. Explanation of the invention (18). In addition, by calculating the alignment error of all exposures 2 on the semiconductor wafer 1 using the obtained relationship, the characteristic evaluation of the semiconductor device generated on the semiconductor wafer 1 can be expected, and the manufacturing yield of the product Can be understood. Although a preferred embodiment of the present invention is described with reference to the related drawings, it should be understood that the present invention is not limited to this specific embodiment, and various changes and improvements can be made by those skilled in the art without departing from the attached The scope or spirit of the invention within the scope of the patent application. For example, the numerical values indicated in the explanation of this specific embodiment are merely examples, and any other appropriate numerical values may be used if necessary. In addition, for example, the results of the alignment error measurement shown in this specific embodiment are merely examples, and there is no doubt that the present invention can be similarly applied even when the measurement causes different values. Further, in the specific embodiments explained above, the CRT is used as the display section 14 to display the GU I display 20. However, a liquid crystal display (LCD) is also available. Further, for example, a device such as a touch panel that combines the display portion 14 and the input portion 15 so that the user can directly touch the screen with one finger to click, select, or issue a command can also be used. . As described above, according to the present invention, since the alignment errors in the N unit regions are calculated from the measurement results of the alignment errors in the M unit regions, the number of unit regions that actually do the alignment error measurement can be minimized Moreover, the alignment errors of all unit regions on a substrate can be calculated and estimated without measuring the alignment errors in all of these unit regions. As a result, it is possible to grasp the misalignment in all unit areas on the substrate and

Page 23 530195 V. Description of the invention (19)

Page 24

Claims (1)

530195 t. Patent application scope 1. A method for calculating an alignment error, which is characterized by: setting a plurality of unit areas on a substrate; measuring the alignment error of a second pattern related to a first pattern formed on the substrate, And constructing the second pattern in M unit regions selected from the unit region; and using a measurement result obtained from the alignment errors of the M unit regions to calculate an alignment error of the second pattern in N unit regions . 2. The method for calculating the alignment error of item 1 in the scope of the patent application, wherein the alignment error of the second pattern is used as a result of an alignment error measurement of the second pattern obtained from the M unit regions, Calculated in all unit areas on this substrate. 3. The method for calculating the alignment error of item 1 of the patent application range, wherein the alignment error of the second pattern in the N unit areas is measured by an alignment error obtained from the M unit areas. The calculated linear factor is calculated. 4. The alignment error calculation method of item 1 in the scope of patent application, wherein the alignment error of the second pattern in the N unit areas is selected from the group consisting of array displacement, array axis magnification, and array axis. Rotation, axis magnification of a unit area, axis rotation of the unit area, center coordinates of the unit area on a substrate, and multiple factors among a group of coordinates of an evaluation point in the unit area are calculated. 5. The alignment error calculation method according to item 1 of the patent application range, wherein the second pattern is caused by using an exposure device, and the unit area is an exposure area provided by the exposure device. Page 25 530195 6. Scope of patent application 6. The method for calculating the alignment error of item 5 of the scope of patent application, wherein the exposure device is a scanning type exposure device. 7. The method for calculating the alignment error according to item 1 of the patent application, wherein the early region is a wafer region formed on the substrate. 8. An alignment measurement device, which is planned to set a plurality of unit areas on a substrate, and includes an alignment measurement device to measure the alignment of a second pattern related to a first pattern formed on the substrate And the second pattern is formed in M unit regions selected from the unit region, and includes: using a measurement result obtained from the M unit region alignment errors by the alignment measurement device to calculate in N A device for aligning the second pattern in the unit area. 9. For an alignment measurement device according to item 8 of the scope of patent application, wherein the alignment error of the second pattern is made using an alignment error measurement result of the second pattern obtained from the M unit regions, Calculated in all unit areas on this substrate. 10. The alignment measurement device according to item 8 of the scope of patent application, wherein an alignment error of the second pattern in the N unit areas is utilized for an alignment error obtained by the M unit areas. Calculated by the linearity factor calculated by the measurement results. 1 1. The alignment measurement device according to item 8 of the patent application, wherein the alignment error of the second pattern in the N unit areas is selected from the group consisting of array displacement, array axis magnification, and array Axis rotation, axis magnification of a unit area, axis rotation of the unit area, a center coordinate of the unit area on a substrate, and one of the coordinates of an evaluation point in the unit area Page 26 530195 VI. Calculated by multiple factors in the scope of patent application. 12. The alignment measurement device according to item 8 of the patent application, wherein the second pattern is caused by an exposure device, and the unit area is an exposure area provided by the exposure device. 13. The alignment measuring device according to item 12 of the patent application scope, wherein the exposure device is a scanning type exposure device. 1 4. The alignment measurement device according to item 8 of the patent application scope, wherein the unit area is a wafer area formed on a substrate. 1 5. — A yield analysis device for analyzing the yield of < semiconductor devices formed on a substrate, including: setting a plurality of unit areas on the substrate; 'alignment measurement device to measure and form An alignment error of a second pattern related to a first pattern on the substrate, and the second pattern is formed in M unit regions selected from the unit region; an alignment measurement device is utilized to utilize the pair The quasi-measuring device is obtained from a measurement result of the alignment errors of the M unit areas, and calculates the alignment errors of the second pattern in the N unit areas; and a characteristic evaluation device to evaluate the semiconductor device in the N unit areas Characteristics; and a yield analysis device, a calculation result of the alignment error of the second pattern calculated by the alignment error calculation device, and an evaluation result of the characteristics of the semiconductor device evaluated by the characteristic evaluation device, Analyze yield. 16. The yield analysis device according to item 15 of the scope of patent application, wherein the alignment error of the second pattern is used by the M unit area obtained from the 530195 VI. Scope of patent application An alignment error measurement result of the second pattern is calculated in all unit areas on the substrate. 1 7. The yield analysis device according to item 15 of the scope of patent application, wherein the alignment error of the second pattern in the N unit areas is utilized as an alignment error obtained by the M unit areas. Calculated by the linearity factor calculated by the measurement results. 1 8. The yield analysis device according to item 15 of the scope of patent application, wherein the alignment error of the second pattern in the N unit areas is selected from the group consisting of array displacement, array axis magnification, and array The axis rotation, a unit area, the axis magnification of the unit area, the axis rotation of the unit area, the center coordinates of the unit area on a substrate, and multiple factors among a group of the coordinates of an evaluation point in the unit area are calculated. 19. The yield analysis device according to item 15 of the patent application scope, wherein the second pattern is caused by an exposure device, and the unit area is an exposure area provided by the exposure device. 20. The yield analysis device according to item 19 of the patent application scope, wherein the exposure device is a scanning type exposure device. 2 1. The yield analysis device according to item 15 of the scope of patent application, wherein the unit area is a wafer area formed on the substrate. Page 28