TW526605B - Method of forming an amorphous layer of a semiconductor structure using a high energy beam - Google Patents

Abstract

High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. To further relieve strain in the accommodating buffer layer, at least a portion of the accommodating buffer layer is exposed to a high energy beam anneal process to cause the accommodating buffer layer to become amorphous, providing a true compliant substrate for subsequent layer growth.

Description

526605 A7 B7 V. Description of the invention (1) This patent application has been filed in US Patent Application No. 09/689583, filed on October 1, 2000. Field of the Invention The present invention is generally related to a method for forming a semiconductor device. It is related, in particular, to a method of using a high-energy light beam to form an amorphous layer to facilitate subsequent growth of a single crystal material. BACKGROUND OF THE INVENTION The vast majority of semiconductor discrete devices and integrated circuits are manufactured using silicon as a material, at least in part due to the availability of low-cost, high-quality single-crystal silicon substrates. Other semiconductor materials, such as so-called synthetic semiconductor materials, have physical properties including a wider band gap and / or higher mobility than silicon, or direct band gaps that make these materials very suitable for specific semiconductor devices. Unfortunately, the cost of synthetic semiconductor materials is usually much higher than silicon, and it is not as easy to form large wafers as silicon. Gallium arsenide (GaAs) (the most accessible synthetic semiconductor material) The maximum diameter of a wafer is only about 150 millimeters (mm). In contrast, the largest shardable wafers available have a diameter of approximately 300 mm, and the most widely used is 200 mm. The cost of a 150 mm GaAs wafer is many times higher than the corresponding shredded wafer. Other synthetic semiconductor material wafers are more difficult to obtain and cost more than GaAs. Because synthetic semiconductor materials have suitable properties, and because they are currently generally expensive and less capable of obtaining large volume forms, attempts have been made to grow synthetic semiconductor material films on heterogeneous substrates for many years. However, in order to achieve the best characteristics of synthetic semiconductor materials, a single crystal form with high crystalline quality is required. -4- The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 526605 A7 B7. 5. Description of the invention ( 2) Membrane. For example, attempts have been made to grow single crystal synthetic semiconductor material layers on germanium, silicon, and various insulators. These attempts have not been successful because the lattice mismatch between the main crystal and the grown crystals has resulted in poor crystal quality of the resulting thin film of the synthetic semiconductor material. If high-quality single crystal thin film of synthetic semiconductor materials can be obtained at low cost, it will help to manufacture various semiconductor devices on the film at low cost, which is lower than manufacturing such devices on large-volume wafers of synthetic semiconductor materials. The cost is also lower than the cost of manufacturing such devices in an epitaxial film of such materials on a large volume wafer of synthetic semiconductor materials. In addition, if a thin film of a high-quality single-crystal synthetic semiconductor material can be embodied on a large-volume wafer such as a silicon wafer, the best characteristics of silicon and synthetic semiconductor materials can be used to realize an integrated device structure. Therefore, there is a need for a semiconductor structure that can provide a high-quality single-crystal synthetic semiconductor film over another single-crystal material, and a method for manufacturing such a structure. The drawings briefly explain the present invention will be explained by examples, but the present invention is not limited to the related drawings, wherein similar references represent similar elements, and in which: Figures 1, 2, 3, 9, and 10 show Sectional views of the device structure of various specific embodiments of the present invention; Figure 4 graphically shows the relationship between the maximum film thickness available and the lattice mismatch between the main crystal and the growing crystal overlay; Figure 5 shows that TF includes a single crystal form to accommodate South resolution Transmission Electron Micrograph of the structure of the buffer layer; This paper is scaled to the Chinese National Standard (CNS) A4 (210 x 297 mm) 526605 A7 _____B7 V. Description of the invention (3) FIG. 6 shows an X-ray diffraction spectrum of a structure containing a single-crystal containing buffer layer; FIG. 7 shows a high-resolution transmission electron micrograph of a structure containing an amorphous oxide layer; and FIG. 8 shows a Diffraction diffraction spectrum of a structure containing an amorphous oxide layer. Those skilled in the art should understand that the components in the figures are made for simplicity and clarity and are not necessarily to scale. For example, compared to other components, the dimensions of the components in the figure may be excessively enlarged to facilitate easier understanding of specific embodiments of the present invention. DETAILED DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic sectional view of a part of a semiconductor structure 20 according to a specific embodiment of the present invention. This semiconductor structure is suitable for growing a single crystal thin film (such as a synthetic semiconductor) on a substrate. Floor). The semiconductor structure 20 includes a single crystal substrate 22, a receiving buffer layer 24 containing a single crystal material, and an annealing cap layer 30. In this article, the term "single crystal form" should have the meaning commonly used in the semiconductor industry. The term "single crystal form" shall represent materials that are single crystals or substantially single crystals, and shall include materials with a relatively small number of defects (such as dislocations commonly found in substrates of silicon or germanium silicide or mixtures, etc.), and The epitaxial layer of such materials often found in the semiconductor industry. At the same time, the term "annealing" shall mean any method (X-ray, electron beam, ion beam, etc.) that can change the crystalline structure (for example, from a single print to an amorphous shape). According to a specific embodiment of the present invention, the structure 20 further includes an amorphous intermediate layer 28 located between the substrate 22 and the valley buffer layer 24. Structure 2 can also include

526605 Description of the invention A template layer (not shown) is interposed between the holding buffer layer and a subsequent growth mask layer. Alternatively, the layer 30 can be used simultaneously as a mask and a template for growing a single-layer layer on the holding buffer layer. As will be explained in detail below, the template layer = helps to initiate growth of a single crystal layer on the containing buffer layer. The amorphous middle ^ helps to reduce the strain in the receiving buffer layer, and thereby assists the qualitative receiving buffer layer. Long back ~ day 0 port day According to a specific embodiment of the present invention, the substrate 22 is a single crystal semiconductor wafer, preferably a large diameter single crystal semiconductor wafer. The material of the wafer may belong to Group… of the periodic table, and is preferably a material of Group IVA. Group ... Examples of semiconductor materials include 胄, ytterbium, mixed europium germanium, mixed dream and carbon, mixed f, germanium and carbon, and the like. The substrate 22 is preferably a wafer containing silicon or germanium, and is preferably a high-quality single crystal silicon wafer as used in the semiconductor industry. The containing buffer layer 24 is preferably an epitaxially grown single crystal oxide or nitride material on a base substrate. According to a specific embodiment of the present invention, the amorphous intermediate layer 28 is grown on the substrate 22 and is located between the substrate 22 and the growing accommodating buffer layer 24, which is oxidized during the growth of the accommodating buffer layer 24.材料 22。 Substrate 22. The amorphous intermediate layer is used to reduce the strain that may occur in the single crystal receiving buffer layer due to the difference in the lattice constant between the substrate and the buffer layer. In this context, the 'lattice constant' represents the distance between unit atoms measured on the surface plane. If the amorphous intermediate layer does not mitigate such strains, the strains can cause defects in the crystalline structure within the containment buffer layer. Next, defects in the crystalline structure in the accommodating buffer layer will make it difficult to achieve a high-quality crystalline structure in a thin film deposited or formed on the accommodating buffer layer. The containing buffer layer 24 is preferably selected to be compatible with and cover the crystal of the base substrate. This paper is suitable for standard S, S, and A4 specifications (210X297).

Pretend

526605 A7 _____B7 V. Description of the invention (5) ^ Forming a semiconductor material (for example, a layer of single crystal synthetic semiconductor material) crystal 5 single crystal oxide or nitride material. For example, such a material may be an oxide or nitride that has an I-lattice structure that matches the substrate and a semiconductor material that is subsequently added to it. Materials suitable for containing the buffer layer include oxidized metals, such as earth test metal salt, earth test metal capric acid salt, alkaline earth metal phosphonate, alkaline earth metal tantalate, alkaline earth metal ruthenate, earth test metal salt , Soil test metal salt, soil test metal lock base feed metal (alkalme earth metal tin-based per ovskites), soil test metal aluminate, lanthanum aluminate, lanthanum oxide milling and thorium oxide. In addition, various kinds of nitrides such as gallium nitride, aluminum nitride, and boron nitride can be used as the storage buffer layer. These two materials have a large alpha 卩 damage to the insulator, although (for example) total ruthenate is a conductor. Generally speaking, these materials are metal oxides or flat gold nitrides. In particular, these metal oxides or metal nitrides have a perovskite structure and include at least two different metal elements. In some specific applications, metal oxides or metal nitrides may include three or more different metal elements. " The amorphous intermediate layer 28 is preferably an oxide formed by oxidizing the surface of the substrate 22, especially silicon oxide. The thickness of the amorphous intermediate layer 28 is sufficient to reduce the strain caused by the mismatch between the lattice constants of the substrate 22 and the buffer layer 24. Generally, the thickness of the amorphous intermediate layer 28 is about 5 to 5 nm. The annealing cap layer 30 may include any material that can prevent an unnecessary degradation of the layer 24 (or its component) during an annealing process. According to various embodiments of the present invention, the layer 30 comprises a single crystal material, such as a single crystal semiconductor material. For example, the right single-crystal synthetic semiconductor layer is formed on the containing buffer layer. 8-This paper size is applicable to China National Standard (CNS) A4 specification (210X297 public copy) 526605 A7 ___ B7______ 5. Description of the invention (6) 24, The layer 30 may include a thin layer of the single crystal synthetic semiconductor layer. FIG. 2 shows a cross-sectional view of a portion of a semiconductor structure 40 according to another embodiment of the present invention. The structure 40 is similar to the semiconductor structure 20 described above, except that an additional single-crystal synthetic semiconductor material layer 26 is formed on the annealing cap layer 30. According to one aspect of this embodiment, the structure 40 may include an additional buffer layer between the template layer 30 and the synthetic semiconductor material layer overlying it. When the lattice constant of the Gona buffer layer cannot properly match the covered single crystal material layer, an additional buffer layer formed of, for example, a semiconductor or synthetic semiconductor material is used to provide lattice compensation. According to the requirements of specific semiconductor structures, from ππA and VA group elements (III-V semiconductor composites), mixed ΙΠ_ν compounds, Π (Α and b) and VIA elements (π _νΐ semiconductor composites), and The material of the synthetic semiconductor layer 26 (and the buffer layer) is selected from the mixture. Examples include gallium (GaAs), gallium indium arsenide (GaInAs), gallium- (GaA1As), indium (InP), sulfide (CdS), mercury telluride (CdHgTe), zinc sulfide ZnSe), zinc sulfur selenide (ZnSSe), and the like. A suitable template material is chemically bonded to a selected part on the surface of the containing buffer layer 24, and provides a site for subsequent synthetic semiconductor layer 26 epitaxial growth accumulation (nucieation). Materials suitable for the template are discussed below. Fig. 3 shows a schematic sectional view of a part of a semiconductor structure 314 according to another exemplary embodiment of the present invention. Structure 34 is similar to structure 4 except that structure 34 includes an amorphous buffer material 36 formed by one of layers 28 and 24. As described in detail below, non--9 can be formed in a similar manner as described above. -This paper size applies to Chinese National Standard (CNS) A4 (210X 297 mm) 526605 A7 B7

V. Description of the invention (7) The crystalline material 36 is formed by first forming a containing buffer layer and a

A > layer is provided in Part 38. The rows of the amorphous material 36 are formed on the substrate of the structure 3 4 to conform to the standard substrate for subsequent processing, for example, the formation of the synthetic semiconductor layer 26 and a single crystal form in the second part 40. An oxide material that can be used to form devices such as waveguides. The layer 30 can be used as an annealing cover when the material 36 is formed, or it can be used as a template for the subsequent formation of the semiconductor layer 26. According to this specific embodiment, the thickness of layer 30 is sufficient to provide a template suitable for growing layer 26 (at least a monolayer is grown), and thin enough to allow layer 26 to form a substantially defect-free epitaxial semiconductor. composite. The following non-limiting, illustrative examples illustrate various combinations of materials available in structures 20, 40, and 34 according to various alternative embodiments of the present invention. These 70 full marks are used for illustration, and the present invention is not limited to these exemplified real examples. 1 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 526605 A7 Description of the invention (8. According to the present invention In a specific embodiment, the single crystal base material 22 is a omnidirectional silicon substrate. The silicon substrate may be, for example, used to make a complementary metal oxide semi-conductor (CM). S) The silicon substrate commonly used in integrated circuits has a diameter of about 200 to 300 mm. According to this specific embodiment of the present invention, the "inner buffer layer 24 疋 SrzBa ^ zTiO3 single crystal layer, where z Is within the range, and the amorphous intermediate layer is a silicon oxide (SiOx) layer formed on the interface between the silicon substrate and the containing buffer layer. Z 値 is selected to obtain a closely matched corresponding subsequent layer ( For example, one or more of the lattice constants of layer 2 6). The thickness of the containing buffer layer is in the range of about 2 to 10 (11111), and preferably about 10 mn: In general, It is hoped that the thickness of the valley buffer layer is sufficient to isolate subsequent formation Layers and substrates to achieve the desired electronic and optical properties. Layers thicker than 100 generally provide fewer advantages and add unnecessary costs; however, thicker layers can still be made if needed The thickness of the amorphous intermediate layer of silicon oxide is in the range of about 0.5 to 5 nm, and preferably about 5 to 2.5. According to this embodiment of the present invention, the material layer 26 is a gallium arsenide ( GaAs) or A1GaAs layer, with a thickness of about 1 nm to about 100 micrometers (μιη), and preferably a thickness of about 0.05 μm to 10 μιη. The thickness usually depends on the application for which the layer is intended It depends. In order to promote the epitaxial growth of gallium arsenide or aluminum gallium arsenide on a single crystal oxide, a template layer will be formed by covering the oxide layer. The template layer is preferably Ti_As, Sr-O-As, Sr- 1 to 10 monolayers of Ga-0 or S r-A1-〇. With preferred examples, it has been proven that 1 to 2 monolayers of Ti-As or Sr-Ga-O can successfully grow GaAs layers Example 2 -11-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) A7 B7 Explanation (9) According to a further specific embodiment of the present invention, the single crystal substrate 22 is a silicon substrate as described above. The accommodating buffer layer 24 is a gill or barium zirconate or a three-dimensional or orthorhombic phase. Single crystal oxide, and the amorphous intermediate layer is a silicon oxide layer formed on the interface between the silicon substrate and the containing buffer layer. The thickness of the Gona buffer layer is in the range of 2 to 100 nm. And preferably at least 5 nm in thickness to ensure sufficient crystallization and surface quality, and is composed of a single crystal form SrZr〇3, BaZr03, SrHf03, BaSn03 or BaHf03, for example, grown at a temperature of about 700 C A BaZrO3 single crystal oxide layer. The lattice structure of the resulting crystalline oxide exhibits a rotation of 45 degrees relative to the silicon lattice structure of the substrate. The containment buffer layer formed from these zirconate or osmate materials is suitable for growing synthetic semiconductor materials in an indium phosphide (InP) system: the synthetic semiconducting moon bean material of layer 26 has a thickness of, for example, approximately Indium hafnium (InP), indium gallium (InGaAs), indium arsenide (AiinAs), or aluminum phosphide steel (AlGalnAsP) from 1.0 nm to 10 μm. The template layers suitable for this structure are zirconium-kun (Zr_As), cone- 嶙 (Zr_p), 铪 KHf-As), 铪 -scale (Hf_p), wrong · oxygen KS (0_As), total-oxygen-嶙 ( Sr-0-P) ,! 1 to ι0 monolayers of shell-oxygen-gentle (Ba-〇-As), indium-gill-oxygen (1114), or barium oxyphosphorus (Ba-〇_p) and preferably these materials One of them has 1 to 2 monolayers. By way of example, as far as the barium zirconate-containing buffer layer is concerned, the surface is terminated with 1 to 2 monomolecular layers of a hammer, and then Kun to 2 monolayers are deposited to form a Zr-As template. Then, a single-crystal layer of a synthetic semiconductor material using a copper halide system as a material is grown on the template layer. The lattice structure of the produced synthetic semiconductor material is relative to the lattice structure of the containing buffer layer. -12- This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 526605 A7 ________B7 V. Description of the invention (1 〇) 's 45 degree rotation, and the lattice of the unmatched (100) Inp is less than 25%, and preferably less than about 1.0%. Example 3 According to a further specific embodiment of the present invention, a structure suitable for growing epitaxial film of a material is provided on a silicon substrate. As mentioned above, the substrate is preferably a silicon wafer. A suitable material for containing the buffer layer is SrxBai χΤ〇3, where X is in the range of 0 to 1, the thickness is about 2 to 100 nm, and preferably it is about 5 to 15 nm. H-V]: Synthetic semiconductor materials may be, for example, zinc selenite (ZnSe) or zinc thioselenate (ZnSSe). Suitable template layers for this material system include zinc to oxygen (211-〇) i to 10 monomolecular layers, followed by 1 to 2 monomolecular layers of excess zinc, followed by zinc selenite on the surface Acid salt. Alternatively, the template layer may be, for example, sharp-sulfur (Sr-S) through a single molecular layer, followed by ZnSeS. Example 4 This embodiment of the present invention is an example of the structure 40 shown in FIG. 2 and includes an additional buffer layer (not shown) between the containing buffer layer and the layer 26. The substrate 22, the single crystal oxide layer 24, and the single crystal synthetic semiconductor material layer 26 may be similar to the corresponding items described in Example 1. The additional buffer layer is used to relax the strain, which is caused by the mismatch between the lattice of the buffer layer and the single crystal material of layer 26. The buffer layer may be a layer of germanium or GaAs, an aluminum gallium arsenide (AlGaAs), an indium gallium phosphide (InGaP), an aluminum gallium phosphide (AlGaP), an indium gallium arsenide (InGaAs), or an aluminum phosphide. Strain-compensated superlattice of indium (A1Inp), gallium phosphorous arsenide (GaAsP), or indium gallium phosphide (InGaP). According to an aspect of this specific embodiment, the buffer layer includes a • 13-applicable towel @ a home standard (CNS) A4 specification (210 X 297 public love) 526605 A7

χ 1. · X super-Ingrid, where χ 値 is in the range of 0 to i. According to another aspect, the buffer layer includes an InyGaiyp superlattice, where y is within the range of 0 to 1,1. By changing X 値 or y 値 (as the case may be): the lattice constant will then change from bottom to top across the superlattice to generate the basic oxygen: Match. The composition of other materials, such as those listed in the above description, can also be used to manipulate the lattice constant of the additional buffer layer with a similar formula. The thickness of the superlattice is about 50 to 500 nm, and preferably about 100 to 200. The template of this structure can be the same as that described in the example. Alternatively, the buffer layer may be a single crystal form of germanium having a thickness of 1 to 50 nm, and preferably a thickness of about 2 to 20 nm. In the process of using a germanium buffer layer, a template layer of germanium-gill (Ge_Sr) or germanium-titanium (Ge_Ti) with a thickness of about a single molecular layer can be used to

It serves as an assembly site for the post-growth single crystal material layer. An oxide layer is formed by covering a single molecular layer gill or a single molecular layer titanium as a gathering site for subsequent deposition of single crystal germanium. The monomolecular gill or monolayer titanium provides a cluster site where the first monolayer germanium can bond. Example 5 This example also illustrates materials suitable for use in the structure 40 shown in FIG. 2. The base material 22, the containing buffer layer 24, the single crystal synthetic semiconductor material layer 26, and the template layer 30 may be the same as the corresponding items described in Example 2. In addition, an additional buffer layer is interposed between the containing buffer layer and a layer covering the single crystal material. The additional buffer layer (a single crystalline material) may be, for example, a graded layer of indium gallium (InGaAs) or indium aluminum (InAlAs). According to an aspect of this specific embodiment, the buffer layer includes InGaAs, which is -14- this paper size applies Chinese National Standard (CNS) A4 specifications (210X 297 mm) 526605 A7 B7 V. Description of the invention (12) Copper The composition is between 0 and about 47%. The thickness of the additional buffer layer is preferably about ˜30 nm. Changing the buffer layer composition & GaAs to inGaAs can provide lattice matching between the base single crystal form oxide material and the single crystal form synthetic semiconductor material cover layer. Such buffer layers are particularly useful if the lattice between the containment buffer layer 24 and the single crystalline material layer 26 is mismatched. Example 6 This example k is provided as an exemplary material useful in the structure 34, as shown in FIG. The base material 22, the template layer 30, and the single crystal material layer 26 may be the same as the corresponding items described in the example process. The amorphous material 36 is an amorphous shape suitably formed by a combination of an amorphous intermediate layer material (for example, the material of layer 28 as described above) and a buffer layer material (for example, a material of layer two as described above). Oxide layer. For example, the amorphous layer 36 may include a combination of SiO ^ SrzBa ^ TiO3 (where z is in the range of 0 to j), which is at least partially combined or mixed during the annealing process to form an amorphous oxide in the region 38 of the structure 34物 材料 36。 Material 36. The thickness of layers 24, 28, and 36 will vary depending on the application and may vary depending on factors such as the desired isolation characteristics of the layers, the type of material containing layer 26, and the like. According to an exemplary aspect of the specific embodiment, the thickness of the seed material 36 is about 2 nm to about 100 nm, preferably about 2 to 10 nm, and most preferably about 5 to 6 nm. Referring back to FIGS. 1 to 3, the substrate 22 is a single crystal substrate such as a single crystal silicon substrate. The crystal structure of a single crystal substrate is characterized by its lattice constant and its orientation. Similarly, the accommodating buffer layer 24 is also a single crystalline material, and the crystal lattice of the single crystalline material is characterized by a lattice constant and a crystal direction. Rong-15- This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 526605 A7 _ B7__ V. Description of the invention (13) The lattice constants of the nanobuffer layer and the single crystal substrate must closely match, Alternatively, when a certain crystal direction is rotated with respect to another crystal direction, it is necessary to achieve a matching of a substantially lattice constant. In this article, there are sufficient similarities between the "substantially equal" and "substantially matched" tables of TF lattice constants' enough to grow a South-quality crystal layer on the base layer. Fig. 4 shows the function of the mismatch between the thickness of the growing crystal layer of the South Crystal Quality achievable in 7F and the lattice constants of the main crystal and the growing crystal. Curve 42 describes the boundaries to crystalline quality materials. The area to the right of curve 4 2 represents the layer containing a large number of imperfections. Due to the matching of the lattices, an epitaxial layer of infinite thickness and high quality can be grown on the main crystal in theory. As the lattice constant mismatch increases, the thickness of the achievable, high-quality crystalline layer decreases rapidly. For example, as a reference point, if the lattice constant mismatch between the main crystal and the growth layer exceeds about 2%, a single crystal epitaxial layer exceeding about 20 nm cannot be formed. According to a specific embodiment of the present invention, the substrate 22 is a single crystal silicon wafer with a direction of (100) or (111), and the containing buffer layer 24 is a gill barium titanate layer. The way to achieve a substantially matching lattice constant of these two materials is to direct the crystal orientation of the titanate material relative to the crystal orientation of the silicon substrate wafer 4 5. Spin. In this example, if the thickness is thick enough, the silicon oxide layer included in the amorphous intermediate layer 28 structure is used to reduce the strain of the titanate single crystal layer, because the strain of the titanate single crystal layer will As a result, the lattice constants of the main 4 wafer and the growing titanate layer do not match. As a result, according to a specific embodiment of the present invention, a high-quality, thick single-crystal layer titanate layer can be achieved. Please refer to Figures 2 to 3. Layer 26 is an epitaxially grown single crystal material layer, and -16- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) 526605 A7 B7 V. Description of the invention (14) The crystalline material is characterized by a lattice constant and a crystal orientation. According to a specific embodiment of the present invention, the lattice constant of the layer 26 is different from the lattice constant of the substrate 22. In order to achieve an epitaxially grown single crystal layer of high crystal quality, the accommodating buffer layer must have high crystal quality. In addition, in order to achieve a layer 2 6 of high crystal quality, it is desirable that the main crystal (in this case, the main crystal is a single-crystal-containing buffer layer) and the lattice constant of the growing crystal are generally matched. With the correct selection of materials, the crystal constant of the growing crystal will be rotated relative to the main crystal, so that the lattice constants can be roughly matched. If the growth crystal is gallium arsenide, aluminum gallium arsenide, zinc selenite, or zinc sulfenite, and the containment buffer layer is single crystal SrxBa ^ TiCb, the lattice constants of these two materials can be achieved. Up-matching, where the crystal direction of the growth layer is rotated 4 5 with respect to the direction of the main single crystal oxide. . Similarly, if the main crystal material is gill or barium hammered acid salt or gill or barium osmium salt or barium hafnium oxide, and layer 26 is indium phosphide or indium gallium indium or indium aluminum arsenide, the crystal can be achieved. The lattice constants are roughly matched by rotating the direction in which the crystal layer is grown relative to the direction of the main oxide crystal 4 5. . In some cases, a crystalline buffer layer between the main crystalline oxide and the growth layer can be used to reduce strain in the growing single crystal layer, as small differences in lattice constants can cause strain. Thereby, better crystal quality of the single crystal layer can be achieved. The following describes a method of manufacturing a semiconductor structure such as the structure shown in FIGS. 1 to 3 according to a specific embodiment of the present invention. The method begins with a single crystal semiconductor substrate comprising silicon or germanium. According to a preferred embodiment of the present invention, the semiconductor crystal substrate is a silicon crystal circle having a direction of (00). The substrate is preferably oriented along the axis, or at most about -17 away from the axis. This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 526605 V. Description of the invention Some have a bare surface, although the other Π of the substrate has other structures, as described below. In this article, the term has been used to remove the surface of the substrate to remove oxides and chromatin materials. 4 It is highly reactive, and it is easy to form natural oxides. The term "naked" intentionally includes such compounds. It is also possible to intentionally grow thin oxide oxides on semiconductor substrates, and such growth oxides It is not necessary for the method according to the present invention. In order to cover the single crystal substrate by epitaxial growth of a single crystal oxide layer, the natural oxide layer must be removed first to expose the crystal structure of the base substrate. The following method is best It is performed by molecular beam epitaxy (MBE) #, although other methods of epitaxy can also be used according to the present invention. By first thermally depositing a thin layer in the MBE device Gill, barium, a combination of gill and barium or Other soil inspection metals or combination of soil inspection metals can remove natural oxides. In the case of using gills, the substrate is then heated to about 75 ° β (:, which makes the gills react with the natural silicon oxide layer. The gill system is used for To decompose silicon oxide, and the surface without silicon oxide. The resulting surface includes gills, oxygen, and silicon, and presents a neat 2x1 structure. The neat 2xl structure forms a template for the orderly growth of single crystal oxides Cover layer. The template provides the necessary chemical and physical properties to gather a crystal-grown cover layer. According to an alternative embodiment of the present invention, the natural silicon oxide can be converted and the surface of the substrate can be prepared to grow a single crystal oxide layer. The method is to deposit a soil test metal oxide such as strontium oxide, barium oxide or barium oxide on the surface of the substrate by MBE at a low temperature, and then heat the structure to about 750 ° C. At this temperature, the oxidation The solid state reaction with natural silicon oxide results in natural oxygen-18. This paper size applies to China National Standard (CNS) A4 (210X 297 mm)

526605 A7 B7 V. Description of the invention (16) Silicon reduction and leaving an ordered 2 X 1 structure with strontium, oxygen and silicon on the surface of the substrate. Again, a template is formed in this manner to subsequently grow an ordered single crystal oxide layer. According to a specific embodiment of the present invention, after removing the oxidized debris on the surface of the substrate, the substrate is cooled to a temperature in the range of about 200 to 800 ° C, and the template layer is grown by molecular beam system crystal growth. “Acid layer. The MBE method opens the gate in the MBE device (beginning with exposure to total, oxygen, and oxygen sources. The ratio of gill to titanium is approximately 丨 1. The partial pressure of oxygen is initially set to a minimum of 値, which is beneficial to approximately 0.33 per minute. The speculative gill titanate is grown to a growth rate of 0.05 nm. After the initial initiation of the growth of strontium titanate, the partial pressure of oxygen is increased to greater than the initial minimum 値. Overpressure of oxygen will cause the base substrate and growth An amorphous silicon oxide layer is grown on the interface between the gill titanate layers. The growth of the silicon oxide layer is due to the diffusion of oxygen through the growing strontium titanate layer to the surface of the base substrate which causes a chemical reaction between oxygen and silicon. Interface. The gill titanate grows into an ordered single crystal form and has a crystallographic orientation that rotates 5 to 5. relative to the base substrate with an ordered 2 X 1 crystal structure. Otherwise, there may be money in the gill titanate layer. Because the lattice constant between the substrate and the growing crystal is slightly mismatched, the amorphous silicon oxide intermediate layer can slow down such strains. After the total salt layer has grown to the desired thickness, then borrow From the template layer The single crystal gill titanate is covered to promote the subsequent growth of the epitaxial layer of the desired material. For the subsequent growth of the gallium arsenide layer, the way to cover the growth of the gill titanate single crystal layer is as follows: Layer monolayer 鈇, nodal monolayer 鈇 -oxygen, or total to 2 monolayer _ oxygen to stop the growth. In the formation -19- This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 public) (Centi) 526605 five A7 B7, description of the invention (17) After this cover layer, arsenic is then precipitated to form a T i-A s bond, T i-0-A s bond, or Sr-0-As. Any one Both can form a template suitable for the deposition and formation of a gallium arsenide single crystal layer. After the template is formed, gallium is then introduced to produce a chemical reaction with Kun and gallium arsenide. Alternatively, gallium can be deposited on the cover layer to form Sr · 0 _ G a is bonded, and arsenic that reacts with gallium is introduced to form GaAs 0 Figure 5 shows a high-resolution transmission electron micrograph (TEM) of a semiconductor material manufactured according to the present invention. Single crystal The SrTi03 containing buffer layer 24 is epitaxially grown on a silicon substrate 22. During the growth process, an amorphous interface layer 28 is formed to reduce the strain caused by the lattice mismatch. Then, an appropriate template is used to epitaxially grow the GaAs synthetic semiconductor layer 26 on the layer 24. Figure 6 An X-ray diffraction spectrum showing a structure including one of the GaAs synthetic semiconductor layer 26 grown on the silicon substrate 22 using the containing buffer layer 24. The peak of the spectrum indicates that the containing buffer layer 24 and the GaAs synthetic semiconductor layer 26 are both single crystals and It is in the direction of (100). As mentioned above, the structures of the present invention may include an additional buffer layer between the receiving buffer layer and the layer 26. In this case, a buffer layer covering the template layer is formed before the single crystal layer 26 is deposited. If the buffer layer is a synthetic semiconductor superlattice, such a superlattice can be deposited on the template as described above by, for example, MBE. If a germanium layer is used instead of the buffer layer, the above method will be modified to cover the gill titanate single crystal layer with the last gill layer or titanium layer, and then deposit germanium to facilitate a chemical reaction with the gill or titanium . A germanium buffer layer can then be deposited directly on this template. Pretend

Line -20- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 526605

Description of the invention (18 FIG. 3 < Structure 34 may be formed by growing a containment buffer layer, forming an amorphous oxide layer on the substrate 22, and growing a layer 26 on the containment buffer layer, as above The exposure buffer layer and the amorphous oxide layer are then exposed to a high-energy beam (for example, an X-ray, ion, or electron beam annealing procedure) so that the crystalline structure of the storage buffer layer is sufficient to change from a single crystal to a non-crystalline one. The crystalline form # is formed by forming an amorphous layer, so that the combination of the amorphous oxide layer and the current amorphous susceptor buffer layer forms a single #crystalline oxide material 36. According to the present invention, the material 36 is the containing buffer layer and area The amorphous oxide layer in 38 is formed by the annealing process of exposing the high energy beam (in the case of protecting the local 40 from the energy beam). The local 40 can avoid contact with the energy beam in various ways. For example, it can simply scan the area Above part 38, expose part 38 to the energy beam. Or 'may form a mask on part 40' to protect part 40 from the energy beam. Appropriate The cover material depends on the type of energy beam. For example, when performing the annealing process using an -ion beam, suitable masks include oxides such as oxygen cuts, nitrides such as nitrogen cuts, and semiconductor devices. Metals. Similarly, suitable materials for masking materials, such as giant, tungsten, and gold, are used during the beating-X-ray or electron beam annealing process. There are several advantageous reasons for using high-energy beam annealing techniques. Especially for annealing The technology enables the material 36 to be formed without exposing the entire structure M to the j heat source. Only one round of Shao 38 needs to be exposed to energy and strike the beam first. In addition, high-energy # beam annealing can promote various Layers (for example, # +, J layer 24, which is typically • 21-this paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) 526605

It contains materials with a higher atomic weight than the other layers) and has a favorable energy absorption. When electron or ion beams are used to form layer 36, the annealing process (at least the county) is caused by charged particles (eg, electrons or ions) striking the atoms in layer 24 and / or layer 28, causing these layers to become amorphous. The charged sub-beam is focused to focus most of the beam energy on a layer to be annealed, or on a specific region of the -layer. In addition, in the case of an electron beam annealing procedure, a layer containing heavier atoms is more likely to absorb its energy. Therefore, when m contains heavier atoms such as gills and / or titanium, layer 24 will absorb more energy than materials containing GaAs). In this case, the electron beam can be used to cause layer 24 to become amorphous, while layer 26 maintains a single crystal form. Fig. 7 shows a high-resolution transmission electron micrograph of a semiconductor material manufactured according to the embodiment of the present invention shown in Fig. 3. According to this embodiment, the single crystal SrTi03 nano-buffer layer is epitaxially grown on the silicon substrate 22. As mentioned above, during this growth process, an amorphous interface layer is formed. Next, a GaAs layer 26 is formed on the containing buffer layer, and the containing buffer layer is annealed to form an amorphous oxide material 36. Fig. 8 shows an X-ray diffraction spectrum of a structure including a GaAs synthetic semiconductor layer 26 and an amorphous oxide material 36 formed on a silicon substrate 22. The peak 値 of the spectrum indicates that the GaAs synthetic semiconductor layer 26 is a single crystal and is formed in the (0) direction. The non-peak 値 near 40 to 50 degrees indicates that the material 36 is amorphous. The method described above illustrates a method for forming a semiconductor structure by a molecular beam epitaxial growth method, wherein the semiconductor structure includes a silicon substrate, a cover oxide layer, and a single crystal gallium arsenide semiconductor layer. Can also be used for chemical vapor deposition (CVD), -22- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)

Pretend

V. Description of the invention (20) metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy (MEE), atomic layer epitaxy (ALE), Physical vapor deposition (PVD), chemical solution deposition (CSD), pulsed laser deposition (PLD), etc. are used to perform this method. In addition, by a similar method, other single crystal form buffer layers can be grown, such as soil test metal salt, soil test hammer salt, soil test metal salt, soil test salt, Soil test metal vanadate, soil test metal nail salt, soil test metal salt, tin-based perovskites (tin-based perovskites), steel chain salt, hafnium oxide, and oxidation disorder. In addition, by similar methods such as MBE, other 111-V and II-VI single-crystal composite semiconductor layers can be deposited to cover the single-crystal oxide-containing buffer layer. Each variation of the worm-crystal growing material uses an appropriate template to facilitate the start of growth of the relevant material. For example, if the containment buffer layer is an alkaline earth metal zirconate, the oxide can be covered by a thin hammer layer. After the deposition of zirconium, the Kun or Phosphorus to be chemically reacted with the hammer is deposited as a precursor for the deposition of InGaAs, KunAl, or InP, respectively. Similarly, if the single crystal oxide containing buffer layer is an alkaline earth metal osmium salt, the oxide layer may be covered by a thin rhenium layer. After the deposition of thorium, arsenic or phosphorus to be chemically reacted with thorium is then deposited as a precursor for growing layers of indium gallium, indium aluminum arsenide, or indium phosphide, respectively. In a similar method, gill titanate can be covered with gill or gill cum oxygen layer, and barium titanate can be covered with barium or gill cum oxygen layer. Deposition-23- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 526605 A7 Description of the invention (2! ^ The following items < then deposit arsenic or chemical reaction with the covering material Phosphorus' to form a template for depositing a layer of synthetic semiconductor material, wherein the layer of synthetic semiconductor material is clad with indium gallium, kunhuan or hafnium steel. "Figure 9 shows a device structure according to a further specific embodiment of the invention The device structure 50 includes a single crystalline semiconductor substrate 52, which is preferably a single male silicon wafer. The single crystalline semiconductor substrate 52 includes "and" two regions. In general, the dotted line 5 6 The indicated electronic semiconductor component is (at least partially) formed in area 53. The electronic component may be a resistor, a capacitor, an active semiconductor component such as a pole or transistor, or a complementary metal oxide Semiconductor (CM0s) integrated circuits, such as integrated circuits. For example, the electronic semiconductor component 56 may be a CMOS integrated circuit, set to perform digital signal processing, or to implement a silicon integrated circuit that is quite suitable Another function. Electronic semiconductor components in region 53 can be formed by conventional semiconductor processing that is well known and widely implemented in the semiconductor industry. Once the device 56 is formed, at least a portion of the surface of region 53 and the region 54 The surface will remove the layers that may be formed or deposited in the region during the processing of the semiconductor device 56 to provide a bare silicon surface. It is well known that bare silicon surfaces are highly reactive, and natural materials can form quickly on bare surfaces. Silicon oxide layer. Barium or barium and oxygen layer will be precipitated on the natural oxide layer on the bare surface, and will react with the oxidized surface to form a first template layer (not shown). According to a specific implementation of the present invention For example, a single crystal oxide material 58 is formed by a molecular beam worm crystal growth process to cover the template layer. A reactant including barium, titanium, and oxygen is precipitated on the template layer to form a single crystal oxide layer. First, during the deposition, the partial pressure of oxygen is maintained close to that of barium and -24 · _______— This paper is compliant with China National Standard (CNS) A4 (210X 297 mm) 526605 A 7 '_______ B7 V. Description of the invention (22) The minimum required for complete reaction of titanium to form a single crystal lock salt layer. Then, the partial pressure of oxygen is increased to provide oxygen overpressure and allow oxygen to grow normally. The single crystal oxide layer diffuses. The oxygen diffused through the barium titanate layer chemically reacts with the silicon on the surface to form a silicon oxide at the interface between the silicon substrate and the single crystal oxide. Crystalline material 57. According to a specific embodiment of the present invention, the step of depositing a single crystal oxide layer is terminated by depositing a second template layer 60, which may be 1 to 10 layers of single molecules Layer of titanium, barium, gill, barium and oxygen, titanium and oxygen, or gill and oxygen. Then, a single crystal semiconductor material layer 64 is deposited by a molecular beam epitaxial growth process to cover the second template layer. The first step in depositing layer 64 is to deposit a layer of arsenic on the template. After the first step, gallium and arsenic are deposited to form a single crystal form of gallium arsenide. According to an aspect of this specific embodiment, after the semiconductor layer 60 is formed, the single crystal form of the region 54 and the oxide layer between the substrate 52 and the acid layer are exposed to a high energy beam annealing. In the process; the osmium salt and oxide layer are formed into an amorphous oxide material 62. Next, another synthetic semiconductor layer 66 is epitaxially grown on the layer 64, and the above-mentioned technique related to the layer 64 is used to form a synthetic semiconductor layer 67. Alternatively, the above annealing process may be performed after the additional synthetic semiconductor layer 66 is generated. However, it is preferred to form the amorphous layer 62 before growing the layer 66, as it provides a substrate that is justified for the growth of the layer 66. The material deposited in layer 66 in region 53 may contain more defects than the material in layer 66 in region 54. Any strain in layers 60, 64 in region 53 is not mitigated through an annealing process. . According to a further specific embodiment of the present invention, the paper size indicated by the dotted line 6 8 -25- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 526605 V. Description of the invention (a with two semiconductor components The system is (at least partially) formed on the synthetic semiconductor layer 66. The semiconductor component 68 can be formed by conventional processing steps in the fabrication of gallium arsenide or other Group III-ν synthetic semiconductor material devices. The semiconductor component 68 may be Any active or passive component, and preferably a semiconductor laser, an electromagnetic radiation (e.g., light from infrared to far ultraviolet radiation) emitting device, an electromagnetic radiation detector (such as a light detector), A heterojunction bipolar transistor (HBT), a high-frequency MESFET, or other components that take full advantage of the physical properties of synthetic semiconductor materials. Metal conductors indicated by line 70 can be formed; this is beneficial to electrical coupling devices 68 and Device 56 to build an integrated device in this manner. The integrated device includes at least a component formed in a silicon substrate and a single crystal structure. A device formed in a semiconductor material layer. Although the structure 50, which has been described as an example, is a structure formed on a silicon substrate 52, and has a barium (or gill) titanate layer and a gallium arsenide layer 66, but similar devices described elsewhere in this publication: single crystal substrates, oxide layers, and other single crystal synthetic semiconductor layers can be used to make similar devices. ^ As described above, according to a specific embodiment of the present invention The local radon is not exposed to an annealing process, so the material 58 still maintains its single crystal form. The single crystal material 58 can be used to form, for example, a device (such as a device) formed between the substrate 5 2 56) A wave guide with another device. FIG. 10 shows a diagram of a semiconductor structure 72 according to another embodiment of the present invention. The structure 72 includes a single crystal semiconductor substrate 74, such as Single-crystal wafers containing regions 75 and 76. The traditional silicon device processing technology commonly used in the semiconductor industry will be used to form regions 7 5 indicated by dashed lines 7 8 26- This paper standard applies to China® standards ( CNS) A4 specification (210 X 297 mm) 526605 A7 ______B7 V. Description of the invention (24) Electronic components. The method steps similar to the above are used to form a single crystal oxide material 9 6 and an intermediate amorphous silicon oxide material 9 8 to cover On the substrate 74. A template layer 80 and a single crystal semiconductor layer 8 2 are formed next to cover the single crystal oxide layer. Then, the single crystal oxide and the oxide are oxidized. The silicon thin film is exposed to a high-energy beam annealing process to form an amorphous oxide material 84 in the region 76. An additional single crystal form is formed by steps similar to the method steps described above for forming the single crystal oxide material. The oxide layer 86 covers the layer 82, and an additional single crystal semiconductor layer 90 is formed to cover the single ej-shaped oxide layer 86 by a method similar to that used to form the layer 82. The single crystalline oxide layer 86 may be desirably exposed to an additional annealing process to make its material amorphous. However, according to various viewpoints of this specific embodiment, the layer 86 still maintains the form of its single crystal form. According to a specific embodiment of the present invention, at least one of the layers 82 and 90 is formed from a synthetic semiconductor material. The semiconductor device indicated by the dashed line 9 2 will be formed on at least one portion of the semiconductor layer 8 2 by a common name. According to a specific embodiment of the present invention, the semiconductor device 92 may include a field effect transistor. To a certain extent, the gate dielectric of the field effect transistor is formed by a single crystal oxide layer 86. In addition, a single crystal semiconductor layer 90 can be used to build the gate electrode of the field effect transistor. According to a specific embodiment of the present invention, a single crystal semiconductor layer 82 is formed from a family composition, and the semiconductor component 92 is a radio frequency (RF) amplifier that fully utilizes the high mobility physical characteristics of the material of the πΐ-V group component. According to a still further specific embodiment of the present invention, the electrical interconnection indicated by the line 9 4 electrically interconnects the component 78 and the component 92. -27 · This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 526605 A7 B7 V. Description of the invention (25) Obviously, these products have the product of synthetic semiconductors and Group IV semiconductors. The specific embodiments of the body circuit are used to explain the specific embodiments of the present invention, rather than to limit the present invention. There are other combinations of diversity and other specific embodiments of the invention. For example, synthetic semiconductor parts can include light-emitting diodes, photodetectors, diodes, and so on, while Group IV semiconductors can include digital logic, memory arrays, and most parts that can be formed on traditional MOS integrated circuits structure. By using specific embodiments of the present invention, it is now easier to combine devices suitable for operation with synthetic semiconductor materials and other components suitable for operation with Group IV semiconductor materials or easily formed and inexpensive. This reduces equipment, reduces manufacturing costs, and increases yield and reliability. Although not illustrated, in the process of forming only synthetic semiconductor electronic components on a wafer, a single crystal Group IV wafer may be used. As such, the wafer is essentially a "processing" wafer used during the manufacture of a synthetic semiconductor electronic component within a single-crystal composite f-conductor layer that covers the wafer. Thus, electronic components can be formed in a III-V or II-VI semiconductor material on a wafer having a diameter of at least about 200 mm and possibly at least about 300 mm. By using this type of substrate, relatively low-cost “handling” wafers overcome the fragile nature of synthetic semiconductor wafers by placing such wafers on a relatively more durable and easily manufactured base material. Therefore, an integrated circuit can be formed so that all electrical components can be formed in a synthetic semiconductor material, especially all active electronic devices, even if the substrate itself can include a Group IV semiconductor material. Compared to relatively small and more fragile, traditional synthetic semiconductor wafers, the manufacturing cost of synthetic semiconductor devices can be reduced because large substrates can be processed more economically and easily. -28- This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm)

Line 526605 A7 I —___ B7_, _ V. Description of the Invention (26) In the foregoing specification, the invention has been described with reference to specific embodiments. However, those skilled in the art should understand the various modifications of the present invention and can easily modify them without departing from the scope of the present invention provided by the scope of patent application below. Therefore, the specifications and drawings should be regarded as illustrations, not as limitations, and all such modifications are within the scope of the present invention. The foregoing has described advantages, particular advantages, and problem solutions for particular embodiments. However, any advantage, advantage, or solution that results in or more significant advantage, advantage, problem solution, or any element should not be construed as a key, necessary item, or basic function or element of any or all patented scope. The terms "including," "including," or any other variation thereof, are used herein to encompass non-proprietary inclusions, such that a program, method, article, or device that includes a list of components includes not only those components, but also It also includes other elements not explicitly listed, or inherent to such processes, methods, articles, or devices. -29- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

526605 A8 B8 C8 Wide ____D8 6. Scope of patent application 1 * A method for manufacturing a semiconductor structure, the method includes the following steps: • providing a single crystal semiconductor substrate; epitaxial growth of a single crystal receiving buffer layer, Covering the single crystal semiconductor substrate; forming an amorphous oxide layer between the single crystal semiconductor substrate and the single crystal oxide layer in the step of growing the worm crystal; and describing the single crystal Part of the nanobuffer layer is exposed to a high-energy beam annealing process to form an amorphous buffer material. 2. The method for manufacturing a semiconductor structure, as described in the first item of the patent application scope, further comprising the step of forming an annealing cap layer. 3. The method for manufacturing a semiconductor structure, as described in the first item of the patent application scope, further comprising the step of forming a mask on the single crystal receiving buffer layer. 4. The method for manufacturing a semiconductor structure according to item 1 of the patent application scope, further comprising the step of forming a single crystal layer over the cap layer. 5. The method for manufacturing a semiconductor structure according to item 1 of the patent application scope, further comprising the step of forming a first template layer on the single crystal semiconductor substrate. 6. The method for manufacturing a semiconductor structure according to item 1 of the patent application scope, further comprising the step of forming a semiconductor device in at least a part of the single crystal semiconductor substrate. 7. The method for manufacturing a semiconductor structure according to the scope of the patent application, wherein the step of forming an amorphous oxide layer includes exposing at least a part of the single crystal form buffer layer to an ion beam annealing process in. -30- 526605 A8 B8 C8 Patent scope — ^-— 8. If the method of manufacturing a patent application item 丨 method of semiconductor structure, and the step of forming an amorphous oxide layer, including at least ,, The single crystal receiving buffer layer is exposed to-electron beam annealing ^ sequence ^ wound 9. Such as the manufacturing method of the patent application 丨 method of semiconductor structure ^ method, wherein the step of forming an amorphous oxide layer, including at least A portion of the single crystal form containing buffer layer is exposed to a x-ray beam annealing procedure ^ 10 · A method of manufacturing a semiconductor structure having a single crystal layer formed on a substrate, the method The method includes the following steps: providing a single-crystal semiconductor substrate; growing a single-crystal receiving buffer layer in a crystal system to cover the single-crystal semiconductor substrate; and in the step of growing the worm-crystal, the single-crystal semiconductor substrate is grown. Forming an amorphous oxide layer between the material and the single crystal form oxide layer; generating a cover layer on the single crystal form holding buffer layer; and at least a part of the single crystal form holding buffer layer is formed by high Beam annealing procedure annealed to form an amorphous buffer material 4. 11. The method of claim 10, further comprising forming a mask on the mask layer. 1 2. The method of manufacturing a semiconductor structure according to item i 0 of the patent application scope, wherein the annealing step includes exposing at least a portion of the single crystal form containing buffer layer to an ion beam annealing process. 13. The method of manufacturing a semiconductor structure according to item 10 of the patent application, wherein the annealing step includes exposing at least a portion of the single crystal form containing buffer layer to an electron beam annealing process. , -31-This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm). 14. The scope of patent application, such as the method of manufacturing a semiconductor structure under item 10 of the patent scope, includes the following steps. At least a portion of the single crystal form accommodates the buffer layer during an exposure beam annealing process. 1 5. 16. 17. 18. C8 D8-a method of a semiconductor device, the method includes the following steps; ^ a single crystal group IV semiconductor substrate; the crystal worm grows a single crystal receiving buffer layer to cover the A single crystal semiconductor substrate; in the step of growing the series of crystals, forming an amorphous silicon oxide layer between the single crystal group IV semiconductor substrate and the single crystal oxide layer; A synthetic semiconductor layer is formed on the nano-buffer layer; and at least one part of the single-crystal containing buffer layer is annealed by a high-energy beam annealing process to form an amorphous buffer material. For example, the method for forming a semiconductor device according to item 15 of the patent application, wherein the annealing step includes exposing at least a part of the single crystal form buffer layer to an ion beam annealing process. For example, the method for forming a semiconductor device according to item 15 of the patent application, wherein the annealing step includes exposing at least a part of the single crystal form accommodating buffer layer to an electron beam annealing process. · The method for forming a semiconductor device as described in claim 15 of the patent application, wherein the annealing step includes exposing at least a portion of the single crystal form buffer layer to an X-ray beam annealing process. -32- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)