TW525236B - Floating gate structure and manufacturing of flash memory - Google Patents

Abstract

A flash memory floating gate having high capacitor coupling ratio and its self-aligned diffusion manufacturing method and its structure are provided. First, a substrate having a first trench is provided to form a first insulated material in the first trench. The first insulated material protrudes the substrate surface. Then, a second trench is formed in the substrate. Second, a second insulated layer is formed on the substrate and conformally form a first conduction layer on the first and second insulated layers. Furthermore, sidewall spacers are formed on the first conduction layer of two sides of the second trench and then a second conduction layer is formed on the sidewall spacers and the first conduction layer. Finally, a part of the first and second conduction layers are simultaneously removed to form a plug conduction layer among the sidewall spacers and liner conduction layers on the surfaces of the second trenches.

Description

525236 V. Description of the invention (1) [Field of the invention] The present invention relates to a fast structure, and particularly to a manufacturing method and a structure thereof. BACKGROUND OF THE INVENTION In flash memory, one of the important factors for coupling. When the flash memory strongly affects the value obtained from the self-controlling gate, the floating gate voltage is larger, because the constant coupling efficiency is defined as the coupling self-coupling. For a capacitor, the coupling efficiency can be compared with the capacitance of the memory cell. Control gates need to have a large overlap efficiency. Flash memory floating gate manufacturing method and booster Π coupling efficiency floating gate manufacturing efficiency The efficiency is the voltage of the floating gate during the operation of the body that affects the performance of the flash memory. The more efficient the coupling, the better the fast memory will perform. Controls the floating gate voltage of the gate voltage. It is defined as the ratio of electricity between the floating gate and the control gate. It can be seen that the floating gate and the area in order to obtain a larger coupling. Consider Figure 1, which shows a cross-sectional view of the structure of a floating gate that is used to describe a conventional flash memory. As shown in Figure 1, reference number 20 indicates a base, reference number 25 indicates a sloping edge layer, reference number 29 indicates an inner insulation layer, and reference numbers 31 and "represent a floating gate and a control gate, respectively. In the above conventional flash memory, the overlapping area of Guangxian 31 and control gate 32 is only on both sides and the upper surface, as shown in the / f line, which cannot provide high coupling efficiency, which results in flash memory I The definition and access speed are not good. While reducing the thickness of the inner insulating layer 29 to mention the non-V efficiency, there will be a data retention limit ^. And the thickness of the second light-emitting gate oxide layer to improve the coupling efficiency, Will lower Fowler = floating σ / sound then wear (

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525236

Fow1er-Nordhe i At this time, as the record is reduced, the efficiency is high and the efficiency is not good. In order to increase the control gate, it is a flash memory. Lowering the width and the height of the lifting and floating memory system] Here, the above-mentioned system of the flash memory system is listed below, and the effective electrical low between the floating gates in the form of tunneling, FN tunneling indicates its process memory device. Reduced size reduces floating gates and control gates. Capacitive coupling efficiency The stylized capacitance of the flash memory makes the capacitor an important lesson in the process and the coupling efficiency increases. )effectiveness. For example, the surface area can also cause coupling and access, which can be increased. Therefore, the main object of the present invention is to provide a method for manufacturing a floating gate of a memory body. The purpose of this kind of self-alignment is to provide manufacturing methods. In the above-mentioned flash memory step of the present invention, first, a substrate insulator is provided to protrude the insulator. Secondly, spacers are formed on the base layer and sacrificial insulating sidewall spacers on the second conductor layer, and at the same time, a part of the plug conductor layer is removed on the trench surface. Forming a first substrate surface The bottom surface sequentially forms layers. Next, a second trench sidewall is spaced from the second conductor to the first between the sidewalls and is secondly isolated from the substrate, and a part of the first conductor on both sides and the first conductor layer and part of the first spacer are removed. Between the objects and the body, the grooves form the edge layer and the insulation layer. A conductive type can increase the _ quasi-floating gate < the floating gate system I & has an inner 'and the first Two trenches and one leading edge layer are formed on the upper surface. Finally, the body layer is shaped like this layer

0503-7271TWF; TSMC2001-1286; ythsieh.ptd page 5 525236 5. Description of the invention (3) Among them, the above process of combining the pad conductor layer and the plug conductor layer, because the lithography process is not used, constitutes this The floating gate structure in the manufacturing method of the invented flash memory device, therefore, the formation of the floating gate of the present invention has the characteristics of self-alignment. Compared with the traditional flash memory floating gate manufacturing method, the above-mentioned flash memory floating gate manufacturing method according to the present invention has the following advantages: (1) due to the additional side wall area of the floating gate of the present invention It overlaps with the control gate, so the area of overlap between the traditional floating gate and the control gate is increased by 4 times, which can increase the coupling efficiency. (2) Because the floating gate of the present invention has high coupling efficiency, it can reduce the applied voltage on the control gate to perform the programmable and erasable functions of the flash memory. [Simplified description of the drawing] Fig. 1 shows the structure of a conventional floating gate; Figs. 2A to 9A are top views, and Figs. 2B to 9B are XX 'sectional views, and Figs. 2C to 9C are YY 'sectional view shows a method for manufacturing a floating gate according to an embodiment of the present invention. [Symbol description] 2 0 to the substrate; 2 1 to the first insulator; 22 to the first trench; 23 to the active region; 2 4 to the second trench; 2 5 to the second insulating layer; Through insulation layer; 2 6 ~ first conductor layer; 2 6 '~ pad conductor layer; 2 7 ~ sacrificial insulation layer;

0503-7271TWF; TSMC2001-1286; ythsieh.ptd Page 6 525236 V. Description of the invention (4) 27 '~ side wall spacer; 28 ~ second conductor layer; 2 8' ~ plug conductor layer; 2 9 ~ inner layer insulation Layers; 3 0 to the third conductor layer; 3 1 to the floating gate; 3 2 to the control gate. [Detailed description of the invention] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments and the accompanying drawings for detailed description as follows: [Example Please also refer to Figures 9A, 9B, and 9C, which respectively show the top view, the XX 'sectional view, and the YY' sectional view of the structure of the floating gate of the flash memory device of the present invention. The floating gate structure of the present invention includes: a substrate 20 having a first groove 2 2 in the substrate 20; a first insulator 21 located in the first groove 22 and protruding from the surface of the substrate 20 A second trench 24 is located in the first insulator 21 on the substrate 20; a second insulating layer 25 is located on the surface of the substrate 20; a pad conductor layer 2 6 'is compliantly located in the A side wall and a bottom of the second trench 24, and the pad conductive layer 26 'located on the side wall of the second trench 24 extends upward; and a plug conductive layer 28' located in the second trench 24, It is connected to the pad conductor layer 26 ′ at the bottom of the second trench 24, and is separated from the pad conductor layer 26 ′ at the side wall of the second trench 24. Please refer to FIGS. 2 to 9, which show a method for manufacturing a floating gate having the flash memory device of the present invention in an embodiment of the present invention. Among them, Figs. 2A to 9A are top views, and Figs. 2B to 9B and 2C to 9C are sectional views taken along XX 'and YY' in Figs. 2A to 9A, respectively.

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▲ As shown in Figures 2A, 2B, and 2C, it shows the initial steps of the present invention. In the figure, 'Firstly, the substrate 2 is provided. It is a semiconductor material (such as a P-type silicon substrate with an N-type well). . Secondly, a shallow trench isolation (STI) process is used to isolate the active region 23, and a first insulator (eg, an oxide layer) 21 is formed in the first trench 22, and the first insulator 21 protrudes. On the surface of the substrate 20, a second trench 24 is formed on the substrate 20 :. As shown in FIGS. 3A, 3B, and 3C, a second insulating layer 25 is formed on the surface of the substrate 20 to a thickness of about 50 angstroms to about 105 angstroms. After that, a first conductive layer 26 is formed on the surface of the first insulator and the second insulating layer 25 in compliance with a thickness of about 200 angstroms to 400 angstroms. Next, a sacrifice insulating layer 27 having a thickness of about 100 angstroms to 500 angstroms is compliantly formed on the first conductor layer 26. Among them, the first insulating layer 25 is used as the material of the subsequent gate oxide layer (g & seven g oxide), so it is usually at a high temperature such as 900. It is formed by a thermal oxidation process such as a dry oxidation method under an environment of 0 °. The first conductive layer 26 may be a polycrystalline silicon layer, for example, silicon methane (SiZ) is the main reactant, and is generated by a low-pressure chemical vapor deposition (LPCVD) process. The sacrificial insulating layer 27 (tetra-ethyl-ortho-silicate, 1E0S) can be used as the main reactant, and is generated by a low pressure chemical vapor deposition (LPCVD) process. As shown in FIGS. 4A, 4B, and 4C, the sacrificial insulating layer 27 is etched back by anisotropic etching, and the controlled etching depth is stopped on the first conductor layer 26 to form sidewall spacers 27. Two sidewalls 24 of the two trenches are formed on the first conductive layer 26.

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~ Hi, 50, a second conductive layer 28 having a thickness of about 100 angstroms is formed on the first conductive layer 26 and the side wall spacer 27, and the mg is connected to the first conductive layer 26 . Wherein, the second conductive layer 28 may be a chemical Z: ′, for example, a silicon reactant (SiH4) is used as a main reactant, and is generated by a low-pressure dry emulsion deposition (LPCVD) process. As shown in Figures 6B and 6C of the study, etch back or chemical mechanical polishing (CMP) is used ^ 1 4 At the same time, part of the second conductor layer 28 and part of the first conductor layer 26 are removed to Guidance =, the guide layer 28 'is between the side wall spacers 27', and a V-body layer 26 is formed on the surface of the second trench 24. Among them, since the above-mentioned process does not use the lithography process', the pad-layer 26 and the plug-in conductor layer 28 are combined to form the floating gate structure in the flash memory structure of the present invention. Therefore, the floating gate of the present invention has the characteristics of self-alignment. .As shown in Figures 7A, 7B, and 7C, using fluorinated acid (HF) or (buf to factory o xide etchant, BOE) etching solution to remove sidewall spacers and part of the first insulator 21, so that the plug The conductive layer 28 and the pad conductive layer 26 are exposed. Among them, the pad conductive layer 26 located on the side wall of the second trench 24 extends upward, and the plug conductive layer 28 is located in the second trench 24 and is connected to the pad conductive layer 26 at the bottom of the second trench 24. And a distance from the pad conductor layer 2 6 on the side wall of the second trench 24. As shown in FIGS. 8A, 8B, and 8C, the inner insulating layer 29 and the third conductor layer 30 are sequentially and compliantly formed on the plug conductor layer 28 and the pad conductor layer 26, |. The inner insulating layer 29 can also be a silicon oxide / silicon nitride / oxygen " fossil evening layer

525236 V. Description of the invention (7) (its thickness is about ~ 60A / ~ 60A / ~ 60A), and the third conductor ~ body layer 30 can use silarane (SiH4) as the main reactant, borrowing / low pressure chemical gas A phase deposition (LPCVD) process forms a polycrystalline silicon layer. As shown in Figures 9A, 9B, and 9C, the lithographic etching process is used to define the third conductive layer 30, the inner insulating layer 29, the plug conductive layer 28 ', and the pad conductive layer 26', so that the third conductive layer 30 turns A gate pattern for a word line control, and the plug conductor layer 2 8 ′ and the pad conductor layer 2 6 ′ are converted into floating beer 3 1. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

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Claims (1)

525236 VI. Scope of patent application1. A flash memory device manufacturing method is applicable, including the following steps: providing a substrate with a first trench in the substrate; forming a first insulator in the first trench And the first insulator protrudes from the surface of the substrate and forms a second trench on the substrate; a second insulating layer, a first conductor layer, and a sacrificial insulating layer are sequentially formed on the surface of the substrate; a portion of the sacrificial insulation is removed Forming a sidewall spacer on the first conductor layer on both sides of the second trench; forming a second conductor layer on the sidewall spacer and the surface of the first conductor layer; and The guide should be divided into two parts, and the two layers of the object partition, the second wall of the guide, the second side Hai Hai = mouth = mouth, when the layer is removed, the plug is inserted with the forming surface and the second groove. In the description of its French side, the 11th paragraph Fan Li specially requested to apply as 2 steps. The next thing is enclosed by a margin, and the second part is the side of the liner and the body guide septum. And the layer except The guide plug body should be guided in a layered manner in the third layer of the layer body and the layer edge insulation layer, and the layer body above and above the layer body. The reason is that the inner body should be guided, the three-layer body should be guided, and the third layer should be engraved, and the base layer should be carved. The gate is set to be a layered body guide. The general outline of the range and profitable layer please refer to the application such as #. 41 3 The base silicon of the French law 0503-7271TWF; TSMC2001-1286; ythsieh.ptd page 11 525236 6. Application scope of patent 4. The method described in item 1 of the scope of patent application, wherein the first insulator, the second insulation layer and the sacrificial insulation layer are formed It is an oxide layer. 5. The method according to item 1 of the scope of patent application, wherein the first conductor layer, the second conductor layer and the third conductor layer are polycrystalline silicon layers. 6. The method according to item 1 of the scope of patent application, wherein the plug conductor layer and the pad conductor layer are polycrystalline silicon layers. 7. The method according to item 1 of the scope of patent application, wherein the inner insulating layer is an oxide / nitride / oxide layer. 8. A floating gate structure comprising: a substrate having a first groove therein; a first insulator located in the first groove and protruding from a surface of the substrate; a second groove located in the substrate The first insulator on the substrate; a second insulating layer on the substrate surface; a pad conductor layer compliantly located on the sidewall and bottom of the second trench, and the pad on the sidewall of the second trench The conductor layer extends upward; and a plug conductor layer is located in the second trench, is connected to the pad conductor layer at the bottom of the second trench, and is connected to the pad conductor layer on the side wall of the second trench. Separated by a distance. 9. The floating gate structure according to item 8 of the scope of patent application, wherein the first insulator and the second insulating layer are oxides. 10. The floating gate structure according to item 8 of the scope of the patent application, wherein the pad conductor and the plug conductor layer are polycrystalline silicon layers. 0503-7271TWF; TSMC2001-1286; ythsieh.ptd page 12