522404 A7 7947twf.doc/009 五、發明說明（/ ) 本發明是有關於一種記憶體測試架構與方法，且特別 是有關於一種外加式記憶體內建自我測試架構與方法。 就目前記憶體在開發階段檢測記憶體所需要之測試架 構通常爲:請參考第1圖，繪示的是習知一種記憶體測試架 構。其中，將受測的記憶體4置於承載盤（load board)02上， 使用記憶體測試機台（Memory TeSter)01以輸出測試式樣 (test pattern)之信號對記憶體4做測試；或是請參考第2圖， 繪示的是習知的另一種記憶體測試架構。其中，將受測的 記憶體6內建一個自我測試電路（On Chip Memory Built In Self Test)，位於承載盤l〇上，且以數位測試機3提供簡 單的命令信號給此記憶體6內建之自我測試電路5做測 試，而內建的自我測試電路5產生測試式樣的信號給記憶 體6。 其中，使用記憶體數位測試機台1對記憶體4作測試， 機台本身就需要花費到數千萬元，所以使用此測試方法所 需的成本太高。而使用將記憶體6內建自我測試電路5(M-BIST)的方式，雖然所需的成本較低（數位測試機台3約花 費數百萬），但卻有以下缺點： 1· 當測試電路內建於記憶體中時，若是在開發的階段， 所以如果記憶體本身有錯誤或是測試電路本身有錯誤，都 會使得數位測試機台認爲記憶體本身有錯誤，所以除錯 (debug)並不容易。 2· 當量產本身具有內建自我測試電路之記憶體時，此記 憶體之操作會受到內建之自我測試電路所影響。也就是說 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂--------- 經濟部智慧財產局員工消費合作社印製 522404 7947twf.doc/009 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（>) 內建之自我測試電路會影響此記憶體的操作性能，如記憶 體內部電路之延遲時間（delay time)，而造成記憶體在操 作上速度變慢。 有鑑於此，本發明提出一種記憶體測試架構’可以降 低測試時所需之成本，並不需在記憶體中內建自我測試電 路，且可程式化修改所需之測試式樣。以達到最佳的測試 時間（test time)以及最大的錯誤覆蓋（Fault coverage)。 本發明提出一種外加式記憶體內建自我測試架構，記 億體內建自我測試架構係以數位測試機對置於承載盤上之 受測元件作測試，而外加式記億體內建自我測試架構則包 括：記憶體以及測試1C。記憶體位於承載盤上。測試1C亦 位於該承載盤上，而測試1C分別電性連接數位測試機與記 憶體，且測試1C用以接收數位測試機之命令信號而產生測 試式樣信號對記憶體作寫入與讀取之動作，並送出檢測信 號至數位測試機。 本發明另外提出一種外加式記憶體內建自我測試方 法’此外加式記憶體內建自我測試方法係爲數位測試機對 置於承載盤上之測試1C與記憶體作測試，其步驟包括：首 先將該測試1C與該數位測試機做電性連接。然後將記憶體 與測試1C做電性連接。而測試IC接收數位測試機所送出 之數位命令信號。使得測試1C產生一測試式樣信號來對記 憶體做寫入與讀出之動作。最後由測試1(：送數位之檢測信 號至數位測試機。522404 A7 7947twf.doc / 009 V. Description of the Invention (/) The present invention relates to a memory test architecture and method, and in particular to an external memory built-in self-test architecture and method. At present, the test structure required for testing the memory during the development phase of the memory is usually as follows: Please refer to FIG. 1, which shows a known memory test structure. Wherein, the tested memory 4 is placed on a load board 02, and the memory test machine 01 (Memory TeSter) 01 is used to output a test pattern signal to test the memory 4; or Please refer to FIG. 2, which shows another conventional memory test architecture. Among them, an on chip memory built-in self test circuit (On Chip Memory Built In Self Test) is built in the tested memory 6, which is located on the carrier disk 10, and the digital test machine 3 provides a simple command signal to the built-in memory 6 The self-test circuit 5 performs the test, and the built-in self-test circuit 5 generates a test pattern signal to the memory 6. Among them, using the memory digital test machine 1 to test the memory 4, the machine itself costs tens of millions of yuan, so the cost of using this test method is too high. However, the method of using the built-in self-test circuit 5 (M-BIST) of the memory 6 has the following disadvantages, although the required cost is relatively low (the digital test machine 3 costs about millions): 1. When testing When the circuit is built in the memory, if it is in the development stage, if the memory itself is wrong or the test circuit itself is wrong, the digital test machine will think that the memory itself is wrong, so debug It's not easy. 2. When mass-producing a memory with a built-in self-test circuit, the operation of this memory will be affected by the built-in self-test circuit. In other words, 3 paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) ----- Printed by the Employees ’Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 522404 7947twf.doc / 009 A7 B7 Printed by the Employees’ Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The Invention Note (>) The built-in self-test circuit will affect this The operating performance of the memory, such as the delay time of the internal circuit of the memory, causes the memory to operate at a slower speed. In view of this, the present invention proposes a memory test architecture, which can reduce the cost required during the test, does not require a built-in self-test circuit in the memory, and can programmatically modify the required test patterns. To achieve the best test time and maximum fault coverage. The invention proposes an internal memory self-testing architecture. The internal memory self-testing architecture uses a digital tester to test the component under test on a carrier disk. The external memory self-testing architecture includes : Memory and test 1C. The memory is located on the carrier disk. Test 1C is also located on the carrier disk, and Test 1C is electrically connected to the digital tester and the memory, and Test 1C is used to receive the command signal of the digital tester to generate a test pattern signal to write and read the memory. And send the detection signal to the digital tester. The present invention also proposes an internal memory self-test method for external memory. In addition, the internal memory self-test method for external memory is a digital tester testing the test 1C and the memory on a carrier disk. The steps include: firstly Test 1C is electrically connected to the digital tester. Electrically connect the memory to test 1C. The test IC receives the digital command signal from the digital tester. The test 1C is caused to generate a test pattern signal for writing and reading to the memory. Finally, test 1 (: sends a digital detection signal to the digital tester.
綜上所述，本發明將自我測試電路做在單一的測試IC 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------•裝 -------訂--------- (請先閱讀背面之注意事項再填寫本頁) 522404 7947twf.doc/009 A7 B7 五、發明說明（今） (請先閱讀背面之注意事項再填寫本頁) 中，數位測試機以數位信號致能此測試1C對受測記憶體做 測試式樣信號之寫入與讀出◦本發明可以使得受測時所需 之成本降低，但不需將內建自我測試電路於記憶體中，而 能達成依據記憶體所需受測之範圍，做測試式樣信號之調 整，來測試記憶體且不影響記憶體在量產後操作之性能。In summary, the present invention uses a self-test circuit as a single test IC. 4 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). ------- Order --------- (Please read the precautions on the back before filling this page) 522404 7947twf.doc / 009 A7 B7 V. Description of the invention (today) (Please read the back first Note on this page, please fill in this page again). The digital tester enables the test 1C to write and read the test pattern signal to the memory under test with digital signals. The invention can reduce the cost required for the test. However, it is not necessary to integrate the built-in self-test circuit in the memory, but can achieve the test range signal adjustment based on the required test range of the memory to test the memory without affecting the performance of the memory operation after mass production.
爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下Z 圖式之簡單說明： 第1圖繪示的是習知之一記憶體測試架構； 第2圖繪示的是習知之另一記憶體測試架構；以及 第3圖繪示的是本發明之一較佳實施例之示意圖。 標號說明 經濟部智慧財產局員工消費合作社印製 1 :記憶體測試機台 2，10，11 :承載盤 3，7 :數位測試機 4，6 :記憶體 5:自我測試電路 8 :測試1C 較佳實施例 本發明係以將記憶體內建自我測試電路做在獨立之測 試1C中，利用數位測試機以發出命令信號的方式，控制此 測試1C將測試式樣信號寫入記憶體，此測試1C再從受測 記憶體中讀出所儲存的資料，經由測試1C讀出資料的結果 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 522404 A7 B7 7947twf.d〇c/〇〇9 五、發明說明（4) 來判斷受測記憶體是否正常，並送出其檢測信號至數位測 試機。 請參照第3圖，繪示的是依照本發明之一較佳實施例 之示意圖。 而本發明之數位測試機在本實施例中’則爲採用數位 輸入輸出之數位測試機7，此數位測試機7相對於第1圖中 習知之記憶體測試機台1便宜的多。 本實施例之記憶體測試架構爲：將受測之記憶體4以 及沏|試IC 8置於承載盤11上，以連接線分別連接受測之記 憶體4與測試1C 8，並以此數位測試機7控制測試IC 8。 其中，此數位測試機7輸出命令信號以控制測試1C 8， 使得此具有自我測試電路功能之測試1C 8中之一測試式樣 信號寫入受測的記憶體4中，然後從受測的記憶體4中讀 出所儲存的資料。 例如，對受測之記憶體4寫入0 〇 0 〇 ·…之測試式樣信 號，然後再從受測之記憶體1中讀出0 〇 〇 〇·…之測試式樣 信號，如果每個記憶胞都能正確的寫入以及讀出〇，那就表 示此受測之記憶體4對此測試式樣信號做寫入與讀出的動 作爲正常。 如果受測之記憶體4在寫入〇〇〇〇....測試式樣信號， 而測試1C 8便無法讀出與原來寫入相同之〇 〇 〇 〇...·測試 式樣信號時，在作完此測試式樣信號的寫入與讀出後，測 試1C 8會輸出檢測信號給數位測試機7。因此，當對記憶 體4做完所需之測試式樣信號的寫入與讀出後，便可以淸 -----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 1 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公^ 522404 7947twf·d〇c/〇〇9 A7 ____ B7__ 五、發明說明（f ) 楚的瞭解此受測之記憶體4是否正常。 最後根據此測§式1C 8 ’判斷此記憶體4是否完全正常， 並將判斷結果輸出一檢測信號至數位測試機7。 由於本實施例之測試1C 8爲一種可程式之邏輯電路， 也就是說可將測試式樣信號程式化入此測試IC 8中，因 此，本發明實施例中之記憶體測試架構9，可以依據受測之 記憶體4所需之測試要求來決定程式化至此測試IC之測試 式樣信號之數目與形式。 一般使用的測試式樣信號有兩種類型，一種是9n類 型，一種是14η類型。9n類型與14η類型代表的意義爲：9n 類型之測試式樣信號較14η類型所之測試式樣信號來的 少，也就是說9ri類型所集合之測試式樣信號所能測試出記 憶體4故障的類型少於14η類型之測試式樣信號所能測試 出記憶體4故障的類型，所以使用14ri類型能檢測出有故 障的記憶體數量較多，而能提高錯誤覆蓋(Fault coverage) 的比例。 但使用9n類型之測試式樣信號來測試記憶體04所需 之時間卻小於使用14n類型之測試式樣信號來測試記憶體 4 〇 因此，本發明之較佳實施例中，測試IC 8就可以依照 受測記憶體所需之測試條件來選擇使用911類型或是14η類 型之測試式樣信號。 綜上所述，本發明以數位測試機以及可程式化之測g式 1C將測試式樣信號寫入記憶體或是從記憶體中讀取，並輸 7 本纸張尺度適用中關家標準（CNS)A4規格咖X 297公爱） (請先閱讀背面之注意事項再填寫本頁) 一裝！ I訂·！ ！ 經濟部智慧財產局員工消費合作社印製 522404 ^47twf.doc/009 A7 B7 五、發明說明（b ) 出具有最後測試結果之檢測信號給數位測試機。如此一 來，不但測試機台的成本降低，且使用者也可以選擇最佳 的測試時間以及錯誤覆蓋。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 -----------裝----！訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, a detailed description of the following Z drawings is described in detail: FIG. 1 FIG. 2 illustrates a conventional memory test architecture; FIG. 2 illustrates another conventional memory test architecture; and FIG. 3 illustrates a schematic diagram of a preferred embodiment of the present invention. Symbol description: Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 1: Memory test machine 2, 10, 11: Carrier disk 3, 7: Digital test machine 4, 6: Memory 5: Self-test circuit 8: Test 1C. The preferred embodiment of the present invention is to build a self-test circuit in the memory in an independent test 1C, and use a digital tester to send a command signal to control the test. 1C writes the test pattern signal to the memory. This test 1C then Read the stored data from the tested memory, and read the data through the test 1C. 5 The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 522404 A7 B7 7947twf.d〇c / 〇09 V. Description of the invention (4) To determine whether the tested memory is normal and send its detection signal to the digital tester. Please refer to FIG. 3, which illustrates a schematic diagram according to a preferred embodiment of the present invention. The digital tester of the present invention is a digital tester 7 using digital input and output in this embodiment. This digital tester 7 is much cheaper than the conventional memory tester 1 in the first figure. The memory test structure of this embodiment is as follows: the tested memory 4 and the test IC 8 are placed on the carrier plate 11, and the tested memory 4 and the test 1C 8 are connected by a connection line, and the number is The tester 7 controls the test IC 8. Among them, the digital tester 7 outputs a command signal to control the test 1C 8 so that one of the test pattern signals of the test 1C 8 with a self-test circuit function is written into the memory 4 under test, and then from the memory under test 4. Read the stored data. For example, write a test pattern signal of 0 〇 〇 ... to the memory 4 under test, and then read a test pattern signal of 0 〇〇〇 ... from the memory 1 under test, if each memory cell Both can be written and read correctly, it means that the test of the test pattern signal by the memory 4 under test is normal. If the tested memory 4 is writing the 0000 .... test pattern signal, and the test 1C 8 cannot read the same 0000 ... as the test pattern signal, After writing and reading the test pattern signal, the test 1C 8 will output a detection signal to the digital tester 7. Therefore, after writing and reading out the required test pattern signals to the memory 4, you can ----------- install -------- order --- ------ (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 public ^ 522404 7947twf · D〇c / 〇〇9 A7 ____ B7__ 5. Description of the invention (f) I understand whether the tested memory 4 is normal. Finally, according to the test § 1C 8 'to determine whether the memory 4 is completely normal, and A judgment signal is output to the digital tester 7. Since the test 1C 8 of this embodiment is a programmable logic circuit, that is, the test pattern signal can be programmed into the test IC 8, so the present invention The memory test structure 9 in the embodiment can determine the number and form of the test pattern signals programmed to this test IC according to the test requirements required for the tested memory 4. There are two types of test pattern signals that are generally used. One is 9n type, the other is 14n type. 9n type and 14n type generation The meaning is: 9n type test pattern signal is less than 14n type test pattern signal, that is to say, 9ri type test pattern signal can test the memory 4 fault type is less than 14η type test pattern The signal can test the type of memory 4 fault, so using the 14ri type can detect a larger number of faulty memories, and can increase the proportion of fault coverage. However, using 9n type test pattern signals to test The time required for the memory 04 is less than the time required to test the memory 4 using a 14n type test pattern signal. Therefore, in the preferred embodiment of the present invention, the test IC 8 can be selected according to the test conditions required by the tested memory. Use 911 type or 14η type test pattern signal. In summary, the present invention uses a digital tester and a programmable test g-type 1C to write the test pattern signal to or read from the memory, and Enter 7 This paper size is applicable to Zhongguanjia Standard (CNS) A4 size coffee X 297 public love) (Please read the precautions on the back before filling this page) One pack! I order! !! Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 522404 ^ 47twf.doc / 009 A7 B7 V. Description of the invention (b) The detection signal with the final test result is given to the digital tester. In this way, not only the cost of the test machine is reduced, but also the user can choose the best test time and error coverage. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. ----------- install ----! Order --------- (Please read the precautions on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Employee Consumer Cooperatives This paper is printed in accordance with China National Standard (CNS) A4 (210 X 297) %)