此電路料鐘錢校正電路及—種用於實現 正味導更特職，本發日縣有關於一種校 之作用比失真（duty喊distQrtion)的 i ίίί正電路，及—種在其上整合有如此之-種^ 抆正電路的半導體裝置。 時鐘信號校正電路係用於校正時鐘信號的仙比失真。 正電6路=示如此之電路的典型結構。所描繪的時鐘信號校 U =包3-分鮮1Q、—輯元件陣列η、一選擇器 _ '互斥OR(職）陣列13。該分頻器1Q把—約定之 i遲號的頻率除以二，產生一分頻器輸出信號。該 一 陣列11包含數個串聯地連接的延遲元件俾可提供 號，、=发每級為r，給該分頻11輸出信號。該等最終信 擇琴破—稱為"延遲輸出信號"c(1)至c(m)，被供應到該選 個些信號c(1)至c(m)把該分頻器輸出信號的半 它 月間相等地細分成η個部份，因此該選擇器12會把 D匕鬥發送到該XOR陣列13作為"選擇器輸出信號"d⑴至 閘t致能它們中之—者。該職陣列13包含數個X0R η對該分頻器輸出信號和該等選擇器輸出信號D(1)至 D(m)執行互斥〇R運作。 、為了提供具有希望之作用比的時鐘信號，以上之習知電 路運作如下。該輸入時鐘信號係首先被導向該分頻器俾 可供應一半_頻率分別器輸出信號至該延遲元件陣列丄工、 選擇器12、和X〇R陣列13。藉由其之串接的延遲單元， 該延遲元件陣列li產生數個具有相對於前面之信號連續地 第4頁 521498 A7 ------- B7 五、發明説明（~-- 較大之延遲之經延遲的信號。該等延遲元件的該等輸出然 , 後被供應至該選擇器12作為延遲輸出信號c(1)至U(i)' 。這表示該分頻器輸出信號的半個週期期間在r的固定間 ’ 隔下被平均地細分成η個部份。當那些信號c(1)| 5被發送至該X0：R陣列13作為該等選擇器輸出信號D(1)至 D(m)時，該選擇器僅致能從D(1)至D(m)中所選擇之 一特定的信號。該X0R陣列13對該分頻器輸出信號和該 4選擇器輸出#號D(l)至D(m)執行互斥OR運作。在兮 分頻器輸出信號的高位準周期期間，當被致能的選擇器^ 10出信號是為高時，該最終的信號變成低，而當被致能的選 擇器輸出信號是為低時，該最終的信號變成高。 ' 以上所述之時鐘信號校正電路能夠根據哪個選擇器輸出 信號被_致能來提供希望的作用比至該輸入時鐘信號。然而 ，如此之一種習知電路不夠準確，而且不適於整合成小的 15 裝置。 有鑑於刚面所述’本發明之目的是為提供一種時鐘信號 喔齡 权正電路’除了提供南度準確的作用比之外，其係夠簡單 來被整合成小的裝置。本發明之另一目的是為提供一種半 導體裝置，其實現如此之一種時鐘信號校正電路。 20 為了達成以上之目的，根據本發明的一特徵，一種校正 輸入時鐘信號之作用比失真的時鐘信號校正電路被提供。 這電路包含下面的元件：一分頻器，其把輸入時鐘信號的 頻率除以一自然數η，藉此產生一經分割的時鐘信號；一相 位偵測器，其確認該經分割之時鐘信號的相位；一延遲單 第5頁 本紙張尺度適用中國國家標準（CNS) A4规格（210X297公釐） .......................裝..................tri:..............線· (請先閲讀背面之注意事項再填寫本頁) 521498 五、發明説明（厶） 元緩分割之時鐘信號之經確認的相位來把 -延遲加至該經分割之時鐘相位來把 的時鐘信號；及一邏輯運算^, 一！延遲之經分割 信號和經延遲之經分^之^ 藉由對該經分割之時鐘 5輸出時鐘信號。°時鐘信號執行邏輯運算來產生— 再者，根據本發明的另一 之作用比失真的時鐘作味、，一種杈正輸入時鐘信號 面的元件：-輸入電3 =路被提供。這電路包含下 ，其校正兮祐接收少*其接收一時鐘信號；一校正電路 L〇，其把具有由該校正電^作用比失真…輸出電路 ;及一通知電路，其通知之作用比的時鐘信號輸出 作用比已被校正。”他電路該被接收之時鐘信號的 _卜根據本發明之又另一特徵，一 供，在該半導體裝置上，一❹μ 士导體裝置被批 一種扠正輸入時鐘信號之作用比 L5失真的時鐘信號校正電路被整合。這時鐘信號校正電路包 含:面的元件：—分頻器，其把輸入時鐘信號的頻率除以 一甘Ϊ數η，藉此產生—經分割的時鐘信號；—相位偵測器 ，其確認該經分割之時鐘信號的相位；一延遲單元，其藉 由根據該經分割之時鐘信號之經確認的相位來把一延遲加 20至該經分割之時鐘信號來產生一經延遲之經分割的時鐘信 號，及一邏輯運算器，其藉由對該經分割之時鐘信號和經 延遲之經分割之時鐘信號執行邏輯運算來產生—輸出時鐘 信號。 别 本發明之以上和其他目的、特徵和優點將會由於下面配 第6頁 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） ............%…； f請先閲讀背¾之ii意事^再填寫本頁) •訂— •樣· 521498This circuit is equipped with a clock correction circuit and a special service for realizing positive taste guidance. The present day county has a positive circuit with a school's role than distortion (duty called distQrtion), and a type integrated on it. This is a kind of semiconductor device for a positive circuit. The clock signal correction circuit is used to correct the Sin ratio distortion of the clock signal. 6 positive circuits = shows the typical structure of such a circuit. The depicted clock signal calibration U = package 3-1Q,-element array η, a selector _ 'mutual exclusion OR (job) array 13. The frequency divider 1Q divides the frequency of the agreed i-delay number by two to generate a frequency divider output signal. The array 11 includes a plurality of delay elements connected in series, which can provide signals, and each stage is r, and outputs signals to the frequency division 11. These final choices are broken-called " delayed output signals " c (1) to c (m), which are supplied to the selected signals c (1) to c (m) to output the frequency divider. The signal is subdivided into n parts equally during the month, so the selector 12 will send the D dagger to the XOR array 13 as the " selector output signal " d⑴ to the gate to enable one of them— . The job array 13 includes a plurality of XOR η to perform mutually exclusive OR operations on the frequency divider output signal and the selector output signals D (1) to D (m). In order to provide a clock signal with a desired effect ratio, the above conventional circuit operates as follows. The input clock signal is first directed to the frequency divider, which can supply a half-frequency divider output signal to the delay element array operator, the selector 12, and the XOR array 13. With the delay units connected in series, the delay element array li generates a number of signals having continuous relative to the previous signal. Page 4 521498 A7 ------- B7 V. Description of the invention (~-larger Delayed delayed signals. The outputs of the delay elements are then supplied to the selector 12 as delayed output signals c (1) to U (i) '. This represents half the output signal of the divider. During the period, it is divided into n parts evenly at the fixed interval of r. When those signals c (1) | 5 are sent to the X0: R array 13 as the selector output signal D (1) To D (m), the selector enables only one specific signal selected from D (1) to D (m). The X0R array 13 outputs the frequency divider output signal and the 4 selector output # D (l) to D (m) perform mutually exclusive OR operation. During the high level period of the frequency divider output signal, when the enabled selector ^ 10 output signal is high, the final signal becomes Low, and when the output signal of the enabled selector is low, the final signal becomes high. 'The clock signal correction circuit described above is capable of outputting according to which selector. The signal is enabled to provide the desired effect ratio to the input clock signal. However, such a conventional circuit is not accurate enough and is not suitable for integration into small 15 devices. In view of the foregoing, the object of the present invention is In order to provide a clock signal, the age-righting circuit is simple enough to be integrated into a small device in addition to providing an accurate function ratio in the south. Another object of the present invention is to provide a semiconductor device that achieves this. A clock signal correction circuit. 20 In order to achieve the above object, according to a feature of the present invention, a clock signal correction circuit that corrects the distortion of the input clock signal is provided. This circuit includes the following components: a frequency divider, It divides the frequency of the input clock signal by a natural number η, thereby generating a divided clock signal; a phase detector that confirms the phase of the divided clock signal; a delay sheet, page 5 is applicable to this paper size China National Standard (CNS) A4 specification (210X297 mm) ..................... ..... tri: .............. line · (Please read the precautions on the back before filling in this page) 521498 V. Description of the invention (元) The clock signal of the slow-divided clock signal is added to the divided clock phase-delay; And a logical operation ^, one! The delayed divided signal and the delayed divided ^^ are output by outputting a clock signal to the divided clock 5. The clock signal is generated by performing a logical operation-further, according to the present invention Another effect is that the clock is distorted. It is a component that is input to the clock signal side:-input power 3 = way is provided. This circuit includes the following: a correction circuit that receives less clock signals; it receives a clock signal; a correction circuit L0 that has an output circuit that is distorted by the correction ratio; and a notification circuit that reports the effect ratio The clock signal output ratio has been corrected. According to yet another feature of the present invention, one circuit is that a μμs conductor device is approved to have a cross-input clock signal that is more distorted than L5 on the semiconductor device. The clock signal correction circuit is integrated. The clock signal correction circuit includes the following components:-a frequency divider, which divides the frequency of the input clock signal by a gage number η, thereby generating-a divided clock signal;-a phase A detector that confirms the phase of the divided clock signal; a delay unit that generates a time delay by adding a delay of 20 to the divided clock signal based on the confirmed phase of the divided clock signal A delayed divided clock signal, and a logic operator which generates-outputs a clock signal by performing a logical operation on the divided clock signal and the delayed divided clock signal. Purpose, characteristics and advantages will be due to the following page 6 This paper size applies Chinese National Standard (CNS) A4 specifications (210X297 mm) ............% ... f Please Read the back ¾ of things ^ ii intended to fill out this page) • Order - • · 521,498 samples
五、發明説明（4 ) 5V. Description of the invention (4) 5
«I ίο 合附圖的描述而變得明白，該等附圖描繪作為舉例說明 本發明之較佳實施例。 第1圖是為本發明時鐘信號校正電路的概念圖； 第2圖是為顯示第i圖之時鐘信號校正電路之運作 時序圖； 、 第3圖是為本發明第一實施例的方塊圖； 第4圖提供在第3圖中所示之延遲元件陣列的細節； 第5圖提供在第3圖中所示之邊緣偵測器的細節； 第6圖提供在第3圖中所示之經延遲之信號選擇器的 細節； 第7圖是為顯示第3圖之第一實施例之運作的時序圖 之 ........................裝…… (請先閲讀背面之注意事项再填寫本頁) 第8圖顯示在第3圖中之延遲元件陣列的另一結構； 第9圖顯示在第3圖中之延遲元件陣列的又另一結構 15 20 •訂· 第10圖是為本發明第二實施例之時鐘信號校正電路的 方塊圖； 第11(A)和11(B)圖說明在第10圖之電路中具有_ 分數校正器的原因，描繪很有可能之延遲輸出信號能夠被 找到的情況（第11 (A)圖）及如此之信號無法被找到的另一 情況（第11 (B)圖）； 第12圖顯示在第10圖中所示之分數校正器的細節； 第13圖是為本發明第三實施例之時鐘信號校正電路的 方塊圖； 第7頁 本紙張尺度適用中國國家標準（_) A4規格（210X297公爱） 521498 五、發明説明（5 ) 5 10 15 20 ;第14圖提供在第13圖中所示之作用比仙器的細節 方塊t5及圖是為本發明第四實施例之時鐘信號校正電路的 =i6g圖顯示一習知時鐘信號校正電路的結構。 發月的較佳實施例現在將會配合該等附圖在下面作描 被描2電圖路是=本發明之_信號校正電路的概錢。該 5! 2 I遲早兀 及一邏輯運算器23。該分頻 °，葬此產Γ約定之輸入時鐘信號的頻率除以η(η:自然數） "俜經分__錢。在這裡，該名詞"自然數 係^任何的正整數，*包括零。 =相㈣測n 21確麟經分狀時鐘㈣的相位。該 U2根據該經確認的時鐘相位來延遲該經分割的時 == 產生一經延遲之經分割的時鐘信號。該邏輯 ° 猎對該經分割之時鐘信號和該經延遲之經分割 之時鐘信號施加-邏輯運算來產生—輸出時鐘信號。、u ，了作為例證目的’在第2圖與隨後的圖式中係假設 該刀頻器2G被構築俾可把其之輸人信號除以二（即，n_2) °京^=2而言’以上的時鐘信號校正電路將會如在第2圖 之時序圖中所示般運作。 、第2圖顯示四個在第！圖之時鐘信號校正電路之主要 部份中的㈣。請參閱部份⑻，該輸人時鐘信號具有τ的 述 第8頁 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公楚）«I ίο It becomes clear in conjunction with the description of the drawings, which are depicted as illustrations of preferred embodiments of the invention. Fig. 1 is a conceptual diagram of a clock signal correction circuit according to the present invention; Fig. 2 is a timing chart showing the operation of the clock signal correction circuit of Fig. I; and Fig. 3 is a block diagram of the first embodiment of the present invention; Figure 4 provides details of the array of delay elements shown in Figure 3; Figure 5 provides details of the edge detector shown in Figure 3; Figure 6 provides details of the warp shown in Figure 3 Details of the delayed signal selector; Figure 7 is a timing chart showing the operation of the first embodiment of Figure 3 ... ..Install ... (Please read the precautions on the back before filling this page) Figure 8 shows another structure of the delay element array in Figure 3; Figure 9 shows the structure of the delay element array in Figure 3. Another structure 15 20 • Order • FIG. 10 is a block diagram of a clock signal correction circuit according to a second embodiment of the present invention; FIGS. 11 (A) and 11 (B) illustrate that the circuit in FIG. 10 has _ The cause of the fractional corrector, depicting the case where it is likely that a delayed output signal can be found (Figure 11 (A)) and another case where such a signal cannot be found (Figure 11 (B)); Figure 12 shows the details of the fractional corrector shown in Figure 10; Figure 13 is a block diagram of a clock signal correction circuit according to a third embodiment of the present invention; The paper size applies the Chinese national standard (_) A4 specification (210X297 public love) 521498 V. Description of the invention (5) 5 10 15 20; Figure 14 provides the details shown in Figure 13 that are more detailed than the box t5 and FIG. I6g is a diagram of a clock signal correction circuit according to a fourth embodiment of the present invention, showing the structure of a conventional clock signal correction circuit. The preferred embodiment of the moon will now be described in conjunction with these drawings. The electric circuit is described as the approximate cost of the signal correction circuit of the present invention. Sooner or later, the 5! 2 I and a logic operator 23. The frequency division °, the frequency of the input clock signal agreed upon by this product is divided by η (η: natural number) " 俜 经 分 __ 钱. Here, the term "natural number" is any positive integer, * including zero. = Phase ㈣ Measure the phase of n 21 true Lin via the fractal clock ㈣. The U2 delays the divided time according to the confirmed clock phase == generates a delayed divided clock signal. The logic ° applies a logical operation to the divided clock signal and the delayed divided clock signal to generate and output a clock signal. , U, for the purpose of illustration 'In Figure 2 and subsequent figures, it is assumed that the knife frequency 2G is constructed, and its input signal can be divided by two (that is, n_2). 'The above clock signal correction circuit will operate as shown in the timing diagram in Figure 2. Figure 2 shows four in the first! Figure ㈣ in the main part of the clock signal correction circuit. Please refer to part ⑻, the input clock signal has the description of τ page 8 This paper size applies to China National Standard (CNS) A4 (210X297)
.訂— (請先閲讀背面之注意事項再填寫本頁) ·*· 521498 A7 _ B7 五、發明説明（€> ) 週期時間，該週期時間具有高時間tl和低時間t：2，其中 、 ，t2係比tl大。該分頻器2〇把如此之輸入時鐘信銳分割 成一半-頻率信號，如在第2圖的部份（B)中所示。這彳士號 • ，被稱為經分割的時鐘信號，具有2T的週期時間。 5 該相位偵測器21藉由測量其之下降邊緣位置來確認該 經分割之時鐘信號的相位。該時鐘相位資訊（即，該下 ^ 緣位置）然後被供應至該延遲單元22。藉由這資訊，該延 遲單元22選擇一適當的延遲來產生一經延遲之經分割的時 鐘信號，如在第2圖的部份（C)中所示。在本例子中，該經 10 延遲之經分割的時鐘信號（C)相對於該原來之經分割之時鐘 信號（B)具有T/2的延遲時間。 更特別地，該相位偵測器21檢查該經分割的時鐘信號 在一相-對於該原來之經分割之時鐘信號具有若干延遲時間 之信號的升緣處是為高抑或是低。以遞增 15相同的運作，該相位偵測器21確認時鐘二== > 點，在該特定的點處’該經分割之時鐘信號的降緣被觀察 。該相位偵測器21現在通知該延遲單元22於該點的延遲 時間，其必須與該原來之輸入時鐘信號的週期時間τ相等 2〇 。該延遲單元22然後以一與該被通知之延遲時間τ之一半 〇，的延遲時間構築自己’藉此提供一半_週‘遲給該經 刀割的時鐘信號。這導致在第2圖之部份（c)中所示之經延 遲之經分割之時鐘信號的結果。 “該邏輯運算器23在該原來之經分割的時鐘信號（B)與 經延遲之經分割的時鐘信號（C)之間執行互斥〇R°運算。該 —第9頁 紙張尺度適^準（CNS) A4規格（210X297公釐)"' (請先閲讀背面之注意事項再填寫本頁) -裝丨 命 :線丨 521498 A7 B7 五、發明説明（1 5 10 15 20 最終的輸出信號係被顯示於第2 _部份⑼。回想該 遲之經分割的時鐘信號（c)係被延遲τ/2。這半〜週期延 致使該最終的輸出時鐘信號（D)具有1:1的作用比（或 5 0%) 〇 本發明之以上的實施例藉著下面的手段來校正—約定 輸入時鐘信號的作用比失真：（a)確認—經分割之時鐘 該經分割之時鐘信號係、藉由把—約定之輸入^鐘 域除以二來被產生，（b)藉著參相經相之相位來提供 一半-週期延遲給該經分割的時鐘信號來產生—經 ς 號’及(c)藉著對該經延遲之經分割的時鐘信 破與該原來之經分割的時鐘信號執行—皿運算來產生一 輸出時鐘信號。該輸入時鐘信號的週期時間係 經分割-之時鐘㈣的相位來被測量，而且一精確 週^ 延遲係從該經測量的週期時間產生。為了這原因 比能夠被準確和有效地校正。 Μ ▲雖然第！圖之以上的說明係假設該分頻胃2〇把其 入L號的頻率除以二，本發明不應被限制於該特定的因數 。該分頻器20亦可以被構絲把該輸人頻率除以任何其他 =目。在稍後的情況中’該時鐘信號校正電路能夠轉換 一輸入時鐘信號的週期時間。 、再者，不受限於一個半-週期周期，該延遲單元22可 以產生任何用於把該經分割之時鐘信號移位的延遲量。藉 由這樣構築該延遲單元22，要獲得5〇%以 二 作用比會是有可能的。 U的 第10頁 本紙張尺度適财關家標準（CNS) Α4規格（210X297公釐） ..........…4…： (請先閱讀背面之注意事项再填寫本頁) •訂· -% 521498 五、發明説明（g ) 5 10 15 20 r合、閱第3至9圖所示，本發明之—更特定的實 二被描述°帛3圖是為本發明第-實施例之時鐘信號校 正電路的方塊圖。被描繪的電路具有—分頻器4q、一延遲 兀件陣列50、一邊緣偵測器6〇、—經延遲之信 7〇、一 XOR 閘 8〇。 ° #該分頻器40把-約定之輸人時鐘信制頻率除以二， 错此把-分頻H輸出錢供應職他的械方塊。該延遲 疋件陣列50包含數個串聯地連接來把該分頻 遲的延遲元件。在這裡，每—延遲元件具“的固定^ 而該等最終信號係被稱為延遲輸出信號^該延遲元件陣列 50把某些延遲輸出信號提供到其他的電路方塊如下：信號 C(1)至c(p)到邊緣偵測器6〇，而信號F(l)至F(q)^經 延遲的_信號選擇器70。 第4圖顯示該延遲元件陣列5Q的詳細結構。該被描繪 的延遲元件陣列5〇包含數個（m)延遲元件51(1)至51(m) ，，第一元件51(1)從該分頻器4〇接收分頻器輸出信號 。每一元件具有Γ的固定延遲時間並且把其之經延遲的輸 出傳送到下一個元件。在該m個延遲元件當中，第一组的 延遲元件51(1)至SKg-D#有與外部連接，僅把它們的 輸出供應到稍後的級。第二組的延遲元件51 (g)到 51(h) (g h)把它們的輸出供應到該經延遲的信號選擇器 7〇。那些q個信號（q=h-g+i)被稱為延遲輸出信號F(1) 至F(q)。第三組的延遲元件51(h+l)至51(i-l)沒有與 外部連接，僅把它們的輸出供應到下一個元件，如同第一 ........................裝…… (請先閲讀背面之注意事項再填窝本頁) 、τ. :線· 第11頁.Order — (Please read the notes on the back before filling out this page) · * · 521498 A7 _ B7 V. Description of the invention (€ >) Cycle time, this cycle time has a high time t1 and a low time t: 2, of which ,, T2 is larger than tl. The frequency divider 20 divides such an input clock signal into half-frequency signals, as shown in part (B) of FIG. 2. This falcon, known as a divided clock signal, has a cycle time of 2T. 5 The phase detector 21 confirms the phase of the divided clock signal by measuring its falling edge position. The clock phase information (ie, the lower edge position) is then supplied to the delay unit 22. With this information, the delay unit 22 selects an appropriate delay to generate a delayed divided clock signal, as shown in part (C) of FIG. 2. In this example, the 10-delay divided clock signal (C) has a delay time of T / 2 with respect to the original divided clock signal (B). More specifically, the phase detector 21 checks whether the divided clock signal is high or low at a rising edge of a phase-signal having a delay time with respect to the original divided clock signal. With the same operation in increments of 15, the phase detector 21 confirms the clock two == > point at which the falling edge of the divided clock signal is observed. The phase detector 21 now informs the delay time of the delay unit 22 at this point, which must be equal to the cycle time τ of the original input clock signal 20. The delay unit 22 then constructs itself with a delay time one and a half of the notified delay time τ ', thereby providing half a week's clock signal to the warped clock. This results in the delayed divided clock signal shown in part (c) of FIG. 2. "The logical operator 23 performs a mutually exclusive OR ° operation between the original divided clock signal (B) and the delayed divided clock signal (C). The -page 9 paper size is appropriate (CNS) A4 specification (210X297 mm) " '(Please read the precautions on the back before filling this page) -Installation: Lifeline: 521498 A7 B7 V. Description of the invention (1 5 10 15 20 Final output signal Is shown in part 2 _. Recall that the late divided clock signal (c) is delayed by τ / 2. This half-period delay causes the final output clock signal (D) to have a ratio of 1: 1. Function ratio (or 50%) 〇 The above embodiments of the present invention are corrected by the following means-the contract ratio of the input clock signal is distorted: (a) confirmation-the divided clock, the divided clock signal system, It is generated by dividing the agreed-upon input ^ clock range by two, (b) by providing the phase of the reference phase and the phase to provide a half-period delay to the divided clock signal. c) By breaking the delayed divided clock signal with the original divided clock signal Line-to-plate operation to generate an output clock signal. The cycle time of the input clock signal is measured by the phase of the divided clock ㈣, and an exact cycle ^ delay is generated from the measured cycle time. For this reason The ratio can be accurately and effectively corrected. ▲ Although the above description of the figure! Assumes that the frequency division 20 divides the frequency of its entry into the L number by two, the present invention should not be limited to this particular factor. The frequency divider 20 can also be constructed by dividing the input frequency by any other means. In a later case, the clock signal correction circuit can convert the cycle time of an input clock signal. Furthermore, it is not affected by Limited to one half-period period, the delay unit 22 can generate any delay amount for shifting the divided clock signal. By constructing the delay unit 22 in this way, to obtain 50% by two action ratio would be It is possible. Page 10 of U. Paper Size Standard (CNS) Α4 Specification (210X297mm) .......... 4 ...: (Please read the precautions on the back first (Fill in this page) • Order ·-% 521498 、 Explanation of the invention (g) 5 10 15 20 r Figures 3 to 9 of the present invention, the more specific real second of the present invention is described. Figure 3 is the clock signal correction circuit of the first embodiment of the present invention. Block diagram. The circuit being depicted has-a frequency divider 4q, a delay element array 50, an edge detector 60,-a delayed letter 70, and an XOR gate 80. ° #The frequency divider 40-The agreed input clock signal frequency is divided by two. Otherwise, the -division H output is supplied to other mechanical blocks. The delay file array 50 contains several serially connected to divide the frequency division later. Delay element. Here, each delay element has a "fixed ^" and these final signals are called delayed output signals ^ The delay element array 50 provides some delayed output signals to other circuit blocks as follows: signal C (1) to c (p) to edge detector 60, and signals F (l) to F (q) ^ delayed_signal selector 70. Fig. 4 shows the detailed structure of the delay element array 5Q. This depicted The delay element array 50 includes a plurality of (m) delay elements 51 (1) to 51 (m). A first element 51 (1) receives a frequency divider output signal from the frequency divider 40. Each element has Γ And delay the output to the next element. Among the m delay elements, the delay elements 51 (1) to SKg-D # of the first group are externally connected and only output them Supply to a later stage. Delay elements 51 (g) to 51 (h) (gh) of the second group supply their outputs to the delayed signal selector 70. Those q signals (q = h- g + i) are called the delayed output signals F (1) to F (q). The delay elements 51 (h + l) to 51 (il) of the third group are not connected to the outside, only their output Supply to the next component, as the first .......................... (Please read the precautions on the back before filling in the page) , Τ .: Line · page 11
521498 A7 --------B7______ 五、發明説明（吁） 組的元件51 (I}至Sl (g—U 一樣。第四組的延遲元件 5工（i)至51 (m)把它們之經延遲的輸出供應到該邊緣偵測 器60。這些p個延遲輪出信號（p=m-i + 1)被標號為c(1) 至 C(p) 〇 5 請再次參閱第3圖所示，該邊緣偵測器6〇藉由對該等 延遲輸出信號C(l)至C(p)與其之分頻器輸出信號施加互 斥-OR運作來確認該分頻器輸出信號的降緣（稍後描述）。 該邊緣偵測器6〇藉著發送偵測信號來通知該經延遲之信號 選擇器70該相位偵測結果。 1〇 第5圖顯示該邊緣偵測器60的細節。該被描繪的邊緣 偵測器6〇包含數個D-型正反器61 (1)至61 (p)和X〇R閘 62(1)至62(p-l)。該等〇_型正反器61(1)至61(p)的 時鐘輸入端（CK)係由從該延遲元件陣列50供應的該等延 遲輸出信號C(l)至（p)驅動，而它們的資料輸入端（⑴係 15 共同地連接至該分頻器輸出信號。每兩個相鄰之正反器的 輸出端（Q)係連接至對應之X〇R閘62⑴至π (p — D的輸 入端。那些XOR閘62 (1)至62 (p-l)的輸出被發送至該經 延遲的信號選擇器70，分別以：)（1)至^(pq)標示。那些 信號D(l)至被稱為偵測信號。 2〇 請再次參閱第3圖所示，該經延遲的信號選擇器7〇根 據從該邊緣偵測器6〇接收的偵測信號D(1)至來 選擇該等經延遲之輸出信號Fd)至F(g)中之一者。第6 圖顯示該經延遲之彳§號選擇器7〇的詳細結構。被描繪的選 擇器70包含下面的元件：一第一組^輸入N〇R閘7〇(1) 第12頁 本紙張尺度適用中國國家標準（⑽）A4規格（21〇X297公爱) ~ ..............................# (請先閲讀背面之注意事項再填窝本頁) •、可丨 %· 521498 A7 B7 五、發明説明（/C?) 5 10 15 20 至70(S)、一第二組2-輸入N0R閘71(1)至7i(s)、及 一多-輸入NOR閘72。 第一組NOR閘70(1)至70(8)對每兩個連續的偵測信 號D(n)與D(n+1)執行邏輯〇R運算，其中，打範圍從工 到Ρ-2。這些NOR閘70 (1)至70 (S)以負邏輯輸出結果， 該等結果然後被供應到該第二組NOR閘(1)至(s)俾 與該等延遲輸出信號F(1)至（q)作邏輯〇R運算。它們之 經反相的結果係由該多-輸入N0R閘72所〇R&反相。 第7圖是為顯示該第一實施例之運作的時序圖。請首 先參閱部份（A)所示，該分頻器40接收具有τ之週期:間 的輸入時鐘信號。該分頻器4〇把這信號除以二，藉此產生 一分頻器輸出信號，如在第7圖的部份（Β)中所示。由於其 之構成_的延遲元件51(1)至5：L(m)，該延遲元件陣列5〇 產生一串經延遲的信號，其具有連續地以τ之增加量增加 的延遲時間。在該等信號之中是為由第四組延遲元件51(i) 至51(m)所產生的延遲輸出信號C(l)至c(p)至 C(p)的升緣連續地觸發在該邊緣偵測器60内之對應的D_ 型正反器61(1)至61(p)，使它們於不同時序閂鎖相同的 分頻器輸出信號。 請參閱第7圖的部份（F)到（H)，三個連續的延遲輸出 L號C(b-l),c(b),和C(b+1)被顯示。如第7圖所示， 當該延遲輸出信號C^b-D變成高時，該分頻器輸出信號 (B)是為高，而在下一個信號c(b)的升緣處它依然是為高 。然而’在第三個信號C(b+1)變成高之前，該分頻器輸出 第13頁 本紙張尺度適用中關家標準（CNS) A4規格（21GX297公釐) ------------------------裝..................訂..................線- (請先閲讀背面之注意事項再填窝本頁) 521498 五、發明説明（/j ) 5 10 15 20 #號把其之狀態從高改變成低。g · 高-至-低轉態在C(b)與c(b + i P該分頻器輸出信號的 緣位置能夠藉著尋找在該串正^的某處發生 ，而該邊 元來被確認。 器輪出中之第一個零值位 該等XOR閘62(1)至62 ( 等正反器61 (1)至61 (口）之I 滿足以上的目的，對該 算。由於一 X〇R間在其之兩個^入^續的輸出執行臟運 高，出現於該等X0R輪出 相同時變成 位準信號’會表示被尋找之：者偵齡5，中之-者的高 获之冋-至-低轉態的出現。在本例 該第一 b個正反器61(1)至6i(b)被設定為一，而 餘下的^反器61(b+1)i 6l(p)被設定為零。由於該第b 個正反器61(b)的輸出與第（b+1)個土反器61(b+1)的輸 出不同_，該第b個X〇R閘62(b)主張其之輸出為高。這不 會發生於其他的X0R閘，而因此，僅該第b個偵測信號 D(b)在所有其他偵測信號維持低時變成高。 從該邊緣偵測器60接收該等债測信號D(l)至D(p-l) ，該經延遲之信號選擇器70連續地把兩個偵測信號結合並 且把最終的信號對輸入到該等NaR閘70(1)至70 (s)。回 想2-輸入NOR閘在它們的輸入皆為低時產生一高位準輸出 ，及在它們任一者的輸入為高時產生一低位準輸出。由於 在本例子中僅該第b個债測信號d (b)為高’該第⑴/2)個 NOR閘7〇(b/2)會是為該唯一作動閘，其之輸出是為低， 假設b是為一偶數。當b是為奇數時，該單一低位準輸出 會出現於該N〇R閘70 ( (b+1) / 2)。注意’所有其他的 ...............%..................訂................% (請先閲讀背面之注意事項再填寫本頁) 第14頁 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 521498521498 A7 -------- B7______ 5. Description of the Invention (Appeal) The elements 51 (I) to Sl (g-U are the same. The delay elements of the fourth group are 5 (i) to 51 (m). Their delayed outputs are supplied to the edge detector 60. These p delayed turn-out signals (p = mi + 1) are labeled c (1) to C (p). 5 Please refer to Figure 3 again The edge detector 60 confirms the falling edge of the frequency divider output signal by applying a mutually exclusive -OR operation to the delayed output signals C (l) to C (p) and its frequency divider output signal. (Described later). The edge detector 60 notifies the delayed signal selector 70 of the phase detection result by sending a detection signal. FIG. 5 shows details of the edge detector 60. The depicted edge detector 60 includes several D-type flip-flops 61 (1) to 61 (p) and XOR gates 62 (1) to 62 (pl). The clock input terminals (CK) of the converters 61 (1) to 61 (p) are driven by the delayed output signals C (l) to (p) supplied from the delay element array 50, and their data input terminals (⑴ Series 15 are commonly connected to this divider output signal. Every two The output terminals (Q) of the adjacent flip-flops are connected to the corresponding XOR gates 62⑴ to π (p — D. The outputs of those XOR gates 62 (1) to 62 (pl) are sent to the The delayed signal selectors 70 are indicated by:) (1) to ^ (pq). Those signals D (l) to are called detection signals. 2 Please refer to FIG. 3 again, the delayed signal The signal selector 70 selects one of the delayed output signals Fd) to F (g) based on the detection signal D (1) received from the edge detector 60. Fig. 6 shows the The detailed structure of the delayed selector No. 7〇. The depicted selector 70 includes the following elements: a first group ^ input NOR gate 7〇 (1) page 12 This paper size applies Chinese national standards (⑽) A4 specification (21〇297 public love) ~ .............. # (Please read the Note for refilling this page) • 、% 丨 521498 A7 B7 V. Description of the invention (/ C?) 5 10 15 20 to 70 (S), a second group 2-input N0R gate 71 (1) to 7i (s), and a multi-input NOR gate 72. The first set of NOR gates 70 (1) to 70 (8) detect every two consecutive detection signals D (n) and D ( n + 1) Perform a logical OR operation, where the range is from work to P-2. These NOR gates 70 (1) to 70 (S) output the results with negative logic, and these results are then supplied to the second group The NOR gates (1) to (s) 俾 perform logic OR operations with these delayed output signals F (1) to (q). The result of their inversion is the OR & inversion of the multi-input NOR gate 72. FIG. 7 is a timing chart showing the operation of the first embodiment. Please refer to section (A) first. The frequency divider 40 receives an input clock signal with a period: interval of τ. The frequency divider 40 divides this signal by two, thereby generating a frequency divider output signal, as shown in part (B) of FIG. Due to its composition of the delay elements 51 (1) to 5: L (m), the delay element array 50 generates a series of delayed signals having a delay time which is continuously increased by an increase amount of τ. Among these signals, the rising edges of the delayed output signals C (l) to c (p) to C (p) generated by the fourth group of delay elements 51 (i) to 51 (m) are continuously triggered at The corresponding D_ type flip-flops 61 (1) to 61 (p) in the edge detector 60 enable them to latch the same frequency divider output signal at different timings. Refer to parts (F) to (H) of Fig. 7. Three consecutive delay outputs L numbers C (b-1), c (b), and C (b + 1) are displayed. As shown in Fig. 7, when the delayed output signal C ^ b-D becomes high, the frequency divider output signal (B) is high, and it is still high at the rising edge of the next signal c (b). However, 'Before the third signal C (b + 1) becomes high, the frequency divider outputs page 13. This paper size applies the Zhongguanjia Standard (CNS) A4 specification (21GX297 mm) ------- ----------------- Equipment ............ Order ............ ..... Line-(Please read the notes on the back before filling in this page) 521498 V. Description of the invention (/ j) 5 10 15 20 # Change its state from high to low. g · high-to-low transitions at C (b) and c (b + i P The edge position of the frequency divider output signal can be found somewhere in the string positive ^, and the edge element is Confirm. The first zero value in the gear rotation. The XOR gates 62 (1) to 62 (I of the flip-flops 61 (1) to 61 (port)) meet the above purpose. X0R performs a dirty high on its two ^ in ^ continued outputs. When the X0R turns out to be the same, it becomes a level signal. It will indicate that it is being sought: the age of detection is 5, the middle of the high The occurrence of the 冋 -to-low transition state. In this example, the first b flip-flops 61 (1) to 6i (b) are set to one, and the remaining ^ flip-flops 61 (b + 1) i 6l (p) is set to zero. Since the output of the bth flip-flop 61 (b) is different from the output of the (b + 1) th earth flip-flop 61 (b + 1), the bth X 〇R gate 62 (b) asserts that its output is high. This does not happen to other X0R gates, and therefore, only the b-th detection signal D (b) becomes high when all other detection signals remain low After receiving the debt measurement signals D (l) to D (pl) from the edge detector 60, the delayed signal selector 70 continuously turns The two detection signals are combined and the final signal pair is input to the NaR gates 70 (1) to 70 (s). Recall that the 2-input NOR gates produce a high level output when their inputs are both low, and A low level output is generated when the input of either of them is high. Because in this example only the b-th debt measurement signal d (b) is high, the ⑴ / 2) NOR gate 7〇 (b / 2 ) Will be the only actuating gate whose output is low, assuming b is an even number. When b is an odd number, the single low level output will appear in the NOR gate 70 ((b + 1) / 2). Pay attention to 'all other .........% ... ..........% (Please read the notes on the back before filling out this page) Page 14 This paper size applies to China National Standard (CNS) A4 (210X297 mm) 521498
五、發明説明（Q 5 10 15 NOR輸出維持於高狀態。 由於以上的結果，大多數的NOR閘71(1)至71 (8)停 留在低輸出狀態，不管它們之對應之經延遲的信號輸入。 唯一例外的是為從先前之N〇R閘7〇 (1)至7〇 (s)中之一者 接收低位準輸入之一者。這N0R閘輸出正被接收之經延遲 之輸出信號的反相版本。在本例子中，僅該N〇R閘 71 (b/2)或者 71 ( (b+D/2)輸出 F(b/2)或者 F((b+1)/2)之延遲輸出信號的反相版本，因為它從先前 之NOR閘7〇(b/2)或者70((b+1)/2)接收低位準信號。 該多-輸入NOR閘72對所有之該等N〇R閘71(1)至 71 (S)的輸出執行邏輯〇R運算並且把結果反相。在本例子 中，該NOR閘72輸出F(b/2)或者F( (b+i)/2)的延遲 輸出信_號，因為它是為來自該等N〇R閘71(1)至7i(㈦之 唯一的作動輸入信號。應要再次注意的是，使用該指數 (b/2)抑或是（b+l)/2係端視該數目b是偶數或者是奇數 而定。 經濟部智慧財產局員工消費合作社印製 在設計該經延遲之信號選擇器7G上的其中—個關鍵問 題是為如何選擇與-作動偵測信號相關之適當的延遲輸出 信號。在本實施例中，該經延遲之信號選擇器7Q被設計來 20選擇-特定的延遲輸出信號以致於其之延遲時間值會是為 由該作動偵測信號所確認之週期時間的一半。該n〇r閘72 因此輸出具有半-週期延遲的分頻器輸出信號。 »月再人參閱第7圖所示，該被選擇的延遲輸出信號 FU)被顯示在部份（E)中，其中，a = b〆2或者（b+i)/2 -........... ..第15百 本紙張尺度適用中國國家標準（CNS ) A4規格（210X;公慶_了 ---------抑衣------、玎------0 (請先閲讀背面之注意事項再填寫本頁) 521498 A7 B7 五、發明説明（0 ) ，端視b是偶數或奇數而定。這信號F (a)相對於原來之分 頻器輸出信號具有T/2的延遲。該經延遲之信號選擇器70 選擇並且把它輸出作為在第7圖之部份（I)中所顯示的選擇 器輸出信號。 5 在此要注意的是，該經延遲的信號選擇器70具有其自 己的延遲時間，因為其之内部邏輯閘（例如，在第6圖之電 路中的兩個NOR-閘級）具有相同的傳播延遲量。當決定哪 個延遲輸出信號選擇與一特定之偵測信號相關時，這延遲 時間必須加入考量。 10 最後級的XOR閘80 (第3圖）在該選擇器輸出信號與該 原本之分頻器輸出信號之間執行一邏輯X〇R運算，該選擇 器輸出信號以T/2的延遲時間跟隨該原本的分頻器輸出信 號。如先前所述，一邏輯XOR運算僅在兩個輸入彼此不同 時產生一高位準輸出。該XOR閘80因此產生在第7圖之 15 部份（J)中所示的輸出時鐘信號，其具有T的週期時間和 5 0 %的作用比。 如以上所述，本發明的第一實施例藉由以下步驟來校正 一約定輸入時鐘信號的作用比：（a)分割約定時鐘信號的頻 率，（b)產生經分割之時鐘信號之很多延遲版本，（c)藉著 20 把它與所產生之經延遲的信號作比較來測量該經分割之時 鐘信號之特定邊緣的時序，（d)選擇一與所測量之邊緣時序 相關之適當的延遲信號，及（e)藉著在所選擇之信號與原本 之經分割的時鐘信號之間執行XOR運算來產生一輸出時鐘 信號。藉由這簡單方法，所提議的時鐘信號校正電路產生 第16頁 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） ……，，#…. (請先閲讀背面之注意事項再填寫本頁) •、可| 521498 A7 ----------- -B7 ____ 五、發明說明^ ' 一具有精準之作用比的輸出時鐘信號。 雖然該第一實施例係假設I/2的分割比率，本發明不 傾向於受限到該特定的比率。一輸入時鐘信號的頻率可以 被除以任何其他的數目。要藉著設定該分割因素到三或者 5 更大來產生一具有不同之週期時間的時鐘信號會是有可能 的0 丨該作用比亦可以是為一設計選擇。該所提議的時鐘信號 枝正電路可以產生5〇%以外的作用比。該作用比係藉著在 該邊緣偵測器6〇與該經延遲之信號選擇器之間的信號 1〇連接來被決定，其是為完全可構築來符合實際需要。 再者，以上所述的第一實施例可以被稍微變化俾可提供 其之作用比校正能力上之改進的動態範圍。回想第4圖的 延遲元-件陣列5〇包含四組延遲元件，在其之中該第四組元 件供應該邊緣偵測器60延遲輸出信號（：（1)至c(p)，而 15該第二組元件供應該經延遲之信號選擇器70延遲輸出信號 F(l)至F(q)。雖然那兩組係被實施如分開的元件區塊， 要使它們全部或部份重疊亦是有可能的。 第8圖顯示延遲元件之如此的另一結構。在所描繪的 延遲元件陣列中5〇a，該第二組延遲元件部份地與該第四 20組重疊；即，該等延遲輸出信號C(l)至C(k+1)和F(u) 至F(q)係從共用的延遲元件擷取。實際上，如此的一種配 置表示增加數量的延遲信號被供應至該邊緣偵測器6〇和經 延遲之信號偵測器70。雖然該電路因為增加的佈線量而變 知更複雜’以上之另一種結構使該時鐘信號校正電路能夠 第17頁 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） ......................裝................訂 ................線· (請先閲讀背面之注意事項再填窝本頁) 521498 五、發明説明（/5 ) 接受具有各種週期時間之廣泛的輸人時鐘信號。有: Πί輸出的線性’使得電路設計更容易。然 ^ ^第8圖中所示的延遲元件就它們的負載條 ^必 眾所周知的是，具有較重負載的邏輯電:=:::時間’其係與被連接至其那裡之輪入的 在第8圖的例子中，像51⑴至51(g_D般的一些延 遲元件僅連接至它們之後續的元件，但沒有連接至外㈣ 路。與那些延遲70件比較起來，其他的元件被期待顯示較 大的延遲時間，因為它們必須驅動一個或者兩個以上的邏 ^閘。-要補償如此之負載不平衡，端視輸人負載的數目而 定，適當的電容器可以被加入，如在第9圖中所示，因此 所有的延遲元件會具有相同的傳播延遲時間。 在第9圖的例子中，該第一延遲元件51(1)具有兩個 電容器Cp(l)和Cp(5)，因為該元件沒有其他的連接。雖 然未在第9圖中描繪，後續的延遲元件具有相同的電容器 。第g個和後面的延遲元件52(g)至5i(h-l)被負載有一 額外的電容器，像最後一組延遲元件般51(i + 1)至51(m) ，因為它們僅具有一個外部負載連接。那些電容器在第9 圖中被標示Cp(2)至Cp(8)。餘下的延遲元件51(h)至 51(i)不具有電容器，因為它們具有兩個外部負載連接。 如上所述，延遲元件的負載條件係藉著加入適當數目的 5 10 20 第18頁 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公爱） (請先閲讀背面之注意事項再填窝本頁) ’訂- 4 ^21498 A7 B7 五 5 10 15 20 、發明説明（/6 ) 補償電容器來被相等化。那些電容器使得所有的延遲元件 以相同的延遲時間運作，藉此改進整體時鐘信號校正電路 的精準度。補償的另一種方法，虛設裝置（例如，邏輯運算 器）可以被使用取代電容器。 再者，電路設計者可以計算每一延遲元件必須驅動的總 輪入電容，取代計數被連接至其那裡之裝置的數目。在這 情況中，補償電容器或者虛設元件的數目（或者等效電容） 係必須根據每一個別之延遲元件之實際負載電容來被決定 〇 接著請參閱第10至12圖，本發明的另一實施例會被 描述。第10圖顯示第二實施例之時鐘信號校正電路的結構 。這電路與在第3圖中之早前說明之第一實施例共享很多 共用組件。因此，後面的部份會集中在不同的點，而相同 的標號係標示相同的元件。 簡而言之’該第二實施例與第一實施例不同的是在於一 分數（fraction)校正器100係插入於該經延遲的信號選 擇器7 0與X〇R閘8 〇之間。藉者處理一分數延遲時間，如 果有的話，該分數校正器100改進該時鐘信號校正電路的 精準度。該名詞”分數π係指當當該邊緣偵測器60無法指定 獨特之延遲輸出信號給該經延遲之信號選擇器7〇時發生之 不確定的分數延遲時間。在進入分數校正器1〇〇的細節之 前，下面的部份提供一些簡單的背景知識。 第11(A)和11(B)圖說明該分數校正器100的原理。 首先，第11(A)圖顯示沒有分數被產生的情況。每一盒子 第19頁 (請先閲讀背面之注意事項再填寫本頁) •、tr— .線丨 521498 A7 _B7_ 五、發明説明（〇 ) 表示一單一延遲元件產生的一單元延遲時間。在那些盒子 上的標號巧（1) ”至”F(5) ”表示被供應至該經延遲之信號 選擇器70之其之對應的延遲輸出信號F(l)至F(5)。在 該等盒子下面的其他標號nC(l) ”至”C(4) ”表示被供應至 5 該邊緣偵測器60之其之對應的延遲輸出信號C(l)至C(4) 〇 例如，考量該邊緣偵測器60於該延遲輸出信號C(4) 之升緣處偵測該分頻器輸出信號的降緣。在此應要注意的 是，在該降緣之被觀察時序上係有一些不確定。確實地說 10 ，該降緣會在C(3)與C(4)之間的某處發生，如由晝有影 線的盒子所顯示，意指該被觀察時序可能包含最多一個單 元延遲時間τ的錯誤。 如先前所述，該經延遲的信號選擇器70被設計來選擇 該等延遲輸出信號中之與從該邊緣偵測器60供應之作動偵 15 測信號相關之一者。在第11 (Α)圖的情況中，該經延遲之 信號選擇器70選擇第四個延遲輸出信號F(4)，因為其之 延遲時間係相等於C (3)之延遲時間的一半且顯而易知地其 最可能為該分頻器輸出信號的半-週期點。 以上的例子顯示能夠確實地提供所需之延遲時間（即， 2 0 被觀察之邊緣的延遲時間的一半）之適當之延遲輸出信號的 情況。然而，這不會是為經常的情況。見第11 (B)圖所示 的另一種情況，當第五個延遲輸出信號C (5)變成高時，一 降緣被偵測，意指該分頻器輸出信號係在C(4)與C(5)之 間的某處改變，如由影線所示。在這情況中，最可能的半- 第20頁 本紙張尺度適用中國國家標準（CNS) Α4規格（210X297公釐） .....................%…： (請先閲讀背面之注意事項再填寫本頁)V. Description of the invention (Q 5 10 15 NOR output is maintained at high state. As a result of the above, most NOR gates 71 (1) to 71 (8) stay at low output state, regardless of their corresponding delayed signals The only exception is one that receives one of the low level inputs from one of the previous NOR gates 70 (1) to 70 (s). This NOR gate output is receiving a delayed output signal that is being received Inverted version of. In this example, only the NOR gate 71 (b / 2) or 71 ((b + D / 2) outputs F (b / 2) or F ((b + 1) / 2) The inverted version of the delayed output signal because it receives the low level signal from the previous NOR gate 70 (b / 2) or 70 ((b + 1) / 2). The multi-input NOR gate 72 Wait for the outputs of the NO gates 71 (1) to 71 (S) to perform a logical OR operation and invert the result. In this example, the NOR gate 72 outputs F (b / 2) or F ((b + i ) / 2) delay output signal _, because it is the only actuation input signal from these NOR gates 71 (1) to 7i (㈦). It should be noted again that the index (b / 2) Whether it is (b + l) / 2 or not depends on whether the number b is even or odd. One of the key issues printed by the Intellectual Property Bureau employee consumer cooperative on designing the delayed signal selector 7G is how to select an appropriate delayed output signal related to the -action detection signal. In this embodiment, the The delayed signal selector 7Q is designed to select 20-specific delayed output signals so that their delay time value will be half of the cycle time confirmed by the action detection signal. The nor gate 72 therefore outputs Frequency divider output signal with half-period delay. »The monthly output signal FU) shown in Figure 7 is displayed in section (E), where a = b〆2 or (B + i) / 2 -.................. The 150th paper size applies the Chinese National Standard (CNS) A4 specification (210X; --Suppression ------, 玎 ------ 0 (Please read the notes on the back before filling in this page) 521498 A7 B7 V. Description of the invention (0), the end view b is even or odd This signal F (a) has a T / 2 delay relative to the original frequency divider output signal. The delayed signal selector 70 selects and outputs it as The signal is output for the selector shown in part (I) of Figure 7. 5 It should be noted here that the delayed signal selector 70 has its own delay time because of its internal logic gate ( For example, the two NOR-gate stages in the circuit of Figure 6) have the same amount of propagation delay. When deciding which delayed output signal to choose in relation to a particular detection signal, this delay time must be considered. 10 The final XOR gate 80 (Figure 3) performs a logical XOR operation between the selector output signal and the original divider output signal. The selector output signal follows with a delay time of T / 2 The original divider output signal. As mentioned earlier, a logical XOR operation produces a high-level output only when the two inputs are different from each other. The XOR gate 80 thus generates an output clock signal as shown in Part 15 (J) of FIG. 7, which has a cycle time of T and an effective ratio of 50%. As described above, the first embodiment of the present invention corrects the effect ratio of a conventional input clock signal by the following steps: (a) dividing the frequency of the conventional clock signal, and (b) generating many delayed versions of the divided clock signal (C) Measure the timing of a particular edge of the divided clock signal by comparing it with the generated delayed signal by 20, (d) select an appropriate delayed signal related to the measured edge timing , And (e) generating an output clock signal by performing an XOR operation between the selected signal and the original divided clock signal. With this simple method, the proposed clock signal correction circuit produces page 16. The paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) ......, #…. (Please read the precautions on the back before (Fill in this page) • 、 may | 521498 A7 ----------- -B7 ____ 5. Description of the invention ^ 'An output clock signal with accurate effect ratio. Although this first embodiment assumes a division ratio of I / 2, the present invention does not tend to be limited to this specific ratio. The frequency of an input clock signal can be divided by any other number. It may be possible to generate a clock signal with a different cycle time by setting the division factor to three or five or greater. The effect ratio may also be a design choice. The proposed clock signal branch circuit can produce an effect ratio other than 50%. The effect ratio is determined by a signal 10 connection between the edge detector 60 and the delayed signal selector, which is completely configurable to meet actual needs. Furthermore, the first embodiment described above can be slightly changed to provide an improved dynamic range of its effect over the correction ability. Recall that the delay element-element array 50 of FIG. 4 includes four sets of delay elements, among which the fourth set of elements supplies the edge detector 60 delayed output signals (: (1) to c (p), and 15 The second group of components supplies the delayed signal selector 70 with delayed output signals F (l) to F (q). Although those two groups are implemented as separate component blocks, it is necessary to make them all or partly overlap It is possible. Figure 8 shows such another structure of the delay element. In the depicted delay element array 50a, the second group of delay elements partially overlaps the fourth 20 group; that is, the The equal delay output signals C (l) to C (k + 1) and F (u) to F (q) are taken from a common delay element. In fact, such a configuration means that an increased number of delay signals are supplied to The edge detector 60 and the delayed signal detector 70. Although the circuit becomes more complicated due to the increased amount of wiring, another structure above allows the clock signal correction circuit to be applicable on page 17 of this paper China National Standard (CNS) A4 specification (210X297 mm) ..................... ... Order ...... Line · (Please read the notes on the back before filling in this page) 521498 V. Description of the Invention (/ 5) Accepted with various cycle times A wide range of input clock signals. The linearity of the output makes circuit design easier. However, the delay elements shown in Figure 8 are well-known for their load bars. It must be well known that the logic has a heavier load. Electricity: = ::: time 'It is related to the rotation which is connected to it. In the example in Fig. 8, some delay elements like 51⑴ to 51 (g_D are only connected to their subsequent elements, but no Connected to the external circuit. Compared to those with 70 delays, other components are expected to show a larger delay time because they must drive one or more logic gates.-To compensate for such a load imbalance, the end Depending on the number of input loads, appropriate capacitors can be added, as shown in Figure 9, so all delay elements will have the same propagation delay time. In the example in Figure 9, the first delay Element 51 (1) has two capacitors Cp (l) and Cp (5) because this element No other connections. Although not depicted in Figure 9, subsequent delay elements have the same capacitors. The g and subsequent delay elements 52 (g) to 5i (hl) are loaded with an additional capacitor, like the last one Group delay elements are 51 (i + 1) to 51 (m) because they have only one external load connection. Those capacitors are labeled Cp (2) to Cp (8) in Figure 9. The remaining delay elements 51 ( h) to 51 (i) do not have capacitors because they have two external load connections. As mentioned above, the load conditions of the delay elements are by adding an appropriate number of 5 10 20 p. 18 This paper applies Chinese national standards ( CNS) A4 specification (210X297 public love) (Please read the precautions on the back before filling in this page) 'Reorder-4 ^ 21498 A7 B7 5 5 10 15 20, invention description (/ 6) compensation capacitors to be equalized. Those capacitors allow all delay elements to operate at the same delay time, thereby improving the accuracy of the overall clock signal correction circuit. As another method of compensation, a dummy device (for example, a logic operator) can be used instead of a capacitor. Furthermore, instead of counting the number of devices connected to each circuit, the circuit designer can calculate the total wheel-in capacitance that each delay element must drive. In this case, the number of compensation capacitors or dummy elements (or equivalent capacitance) must be determined according to the actual load capacitance of each individual delay element. Then refer to Figures 10 to 12 for another implementation of the present invention. The routine will be described. FIG. 10 shows the structure of a clock signal correction circuit of the second embodiment. This circuit shares many common components with the first embodiment described earlier in FIG. Therefore, the following sections will focus on different points, and the same reference numerals indicate the same components. In short, the second embodiment differs from the first embodiment in that a fraction corrector 100 is inserted between the delayed signal selector 70 and the XOR gate 800. The borrower processes a fractional delay time, and if so, the fractional corrector 100 improves the accuracy of the clock signal correction circuit. The term "fractional π" refers to the uncertain fractional delay time that occurs when the edge detector 60 cannot assign a unique delayed output signal to the delayed signal selector 70. After entering the fractional corrector 100, Before going into detail, the following sections provide some simple background knowledge. Figures 11 (A) and 11 (B) illustrate the principle of the score corrector 100. First, Figure 11 (A) shows the situation where no score is generated. Page 19 of each box (please read the precautions on the back before filling this page) • tr— .line 丨 521498 A7 _B7_ V. Description of the invention (〇) represents a unit delay time generated by a single delay element. In those Reference numerals (1) ”to“ F (5) ”on the box indicate the corresponding delayed output signals F (1) to F (5) supplied to the delayed signal selector 70. The other labels nC (l) ”to“ C (4) ”below these boxes indicate that they are supplied to 5 of the edge detector 60 and their corresponding delayed output signals C (l) to C (4). Consider that the edge detector 60 detects the falling edge of the frequency divider output signal at the rising edge of the delayed output signal C (4). It should be noted here that the timing of the falling edge is observed. There is some uncertainty. Indeed, 10, the falling edge will occur somewhere between C (3) and C (4), as shown by the box with hatching in the day, meaning that the observed timing may be Contains errors of at most one unit delay time τ. As mentioned earlier, the delayed signal selector 70 is designed to select among the delayed output signals related to the motion detection signals supplied from the edge detector 60 In the case of FIG. 11 (A), the delayed signal selector 70 selects the fourth delayed output signal F (4) because its delay time is equal to the delay time of C (3) It is obvious that it is most likely to be the half-period point of the frequency divider output signal. The above example shows that Ground to provide an appropriate delayed output signal with the required delay time (ie, half the delay time of the edge being observed at 20). However, this will not be the case often. See Figure 11 (B). As shown in another case, when the fifth delayed output signal C (5) becomes high, a falling edge is detected, which means that the frequency divider output signal is between C (4) and C (5). Somewhere changed, as shown by the hatching. In this case, the most likely half-page 20 This paper size applies the Chinese National Standard (CNS) Α4 specification (210X297 mm) ......... ............%…: (Please read the notes on the back before filling this page)
、可I 521498 A7 --------- B7_ 五、發明説明（/忿） 週期點被假設為在F (4 )與F ( 5 )之間的中間點，如由第 11(B)圖中之點箭嘴所示，因為它產生信號c(4)之延遲時 間的一半。然而，在第3圖中所示之第一實施例無法提供 包括一分數延遲值之如此之中點時序。為了這原因，該經 5延遲之信號選擇器70必須選擇該第四個延遲輸出信號F(4) 或第五個延遲輸出信號F(S)中之任一者，拋棄取整誤差及 I 後續不精準的問題。 該第二實施例係傾向於校正當該經延遲之信號選擇器需 要分數延遲時間時，在第11(八）和11(B)圖中所描述之如 1〇此的錯誤。這目的係藉著使用另一個延遲元件來被達成， 該另一個延遲元件把一分數延遲加入所選擇的延遲輪出俨 號。 ° 第；L2圖顯示該分數校正器1〇〇的詳細結構。這分數校 正器1〇〇被構築有後面的組件：2_輸入〇R閘1〇〇(1)至 15 1〇〇 (V)、多-輸入OR閘101、延遲元件102、及選擇器 103 〇· 1 該等2-輸入〇R閘100(1)至1〇〇(”對每一對連續的 偶數偵測信號，像D(2)和d(4)般，執行邏輯〇R運算。 該多-輸入OR閘101把那些〇R閘100 (丄）至1〇〇 (v)的輸 20 出結合。當任一個偶數偵測信號被作動時，該OR閘1〇1 變成高。否則，其之輸出停留在低位準。 該延遲元件1〇2具有（r /2)的延遲時間，即，該延遲 元件陣列50之一單一元件提供之單元延遲時間r的_半。 這額外的延遲Γ/2被加入至由該經延遲之信號選擇器7〇 第21頁 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） ........................裝..................訂..................線. (請先閱讀背面之注意事项再填寫本頁) 521498 A7 I' -— _______ 五、發明説明（q ) 所選擇的信號。該選擇器1〇3端視從該多-輸入OR閘l〇1 供應的選擇命令信號而定，選擇該經延遲的信號或者原來 的信號。更特別地，當該選擇命令信號是為低（”〇”）時， 它選擇直接從該經延遲之信號選擇器7Q接收之原來的信號 5 。當該命令信號是為高（，，1")時，該選擇器1〇3選擇從該 延遲元件1〇2接收之該經延遲的信號。下一個部份將會描 述第二實施例的運作。 現在，回想在第11(A)圖中所假設的情況，該邊緣偵 測器6〇係於C(4)的時序處偵測該分頻器輸出信號的降緣 10 ，使得該第三偵測信號D(3)作動。在這情況中，被作動的 偵測信號D(3)致使該經延遲的信號偵測器70把該第四個 延遲輸出信號F(4)輸出到該分數校正器ι〇〇。在該分數校 正器100中’該〇r閘101的輸出保持低，因為其之輸入 中沒有一者是為高。據此，該選擇器1〇3允許該延遲輸出 15 信號F(4)到達該x〇R閘80。那就是說，第二實施例的時 鐘信號校正電路確實地帶來與在第11(A)圖中所說明之相 同的結果。 然後，考量在第11(B)圖中所討論之其他的例子情況 ，該邊緣偵測器60於C(5)的時序偵測該分頻器輸出信號 20 的降緣。由於該第四個偵測信號D (4)在這情況中變成作動 ，該經延遲之信號選擇器7〇選擇該第四個延遲輸出信號 F(4)並且把該第四個延遲輸出信號F(4)輸出到該分數校 正器100。該被作動的偵測信號D(4)亦致使該分數校正器 | 100中的OR閘101輸出一高位準信號。該選擇器103因 第22頁 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） (請先閲讀背面之注意事項再塡窝本頁) -訂· ·%· 521498 A7 B7 五、發明説明（20) 5 10 15 20 此選擇該延遲元件1〇2的輸出，供應該x〇R閘8〇該具有 r /2之額外之延遲的延遲輸出信號FU)。這樣，當一分 數延遲係由該邊緣偵測器6〇和經延遲的信號選擇器7〇要 求時，該第二實施例的分數校正器1〇〇產生更精確的延遲 時間，如由第11(B)圖中的點箭嘴所示。 雖然該第二實施例業已對該分數延遲是為該單元延遲時 間r之一半的假設作描述，本發明應不受限於這特定因素 。要構築該被建議的電路俾以該單元延遲時間的yb調^ 一約定之時鐘信號的作用比亦是有可能。這特徵係藉著構 築該分數校正器100具有（b-Ι)個具有該單元延遲之1/b 之延遲時間的延遲元件來被完成，因此任何的分數延遲量 將會從那些可細調的延遲元件產生出來。 接著請參閱第13和14圖所示，本發明的又另一實施 例將會作描述。第13圖是為本發明第三實施例之時鐘信號 校正電路的方塊圖。由於這電路與較早在第3圖中說明之 第一實施例共享很多共用組件，後面的部份將會聚焦於其 之不同的點上’而相同的標號係用來標示相同的元件。與 該第一實施例比較起來，該第三實施例使用一作用比偵測 器U0、2-輸入AND閘A(l)至A(p)、及一反相器116 作為額外的組件。有關其他的功能方塊，請參閱第3圖及 該描述的相關部份。 該作用比偵測器110測試由該XOR閘80所產生的輸 出時鐘信號，俾可決定它是否具有預定的作用比。該測試 結果經由一校正完成信號報告，如果該輸出時鐘信號通過 第23頁 本紙張尺度適用中國國家標準（CNS) A4規格（210 X 297公釐） (請先閲讀背面之注意事项再填窝本頁) •裝· •紅丨 •線丨 ^1498 A7 p--------J7__ 五、發明説明（2 '-- 該測試的話，它將會被設定為高。該作用比偵測器110具 有一接收一外部重置信號的重置（R)輸入端。 第14圖顯示該作用比偵測器11〇的詳細結構。該被描 5繪的偵測器I10具有下面的組件：一延遲元件陣列1]L1、 5 一 D-型正反器陣列112、XOR閘113(1)至UWP-D、 | 2-輸入AND閘114(1)至li4(p-i)、及一多-輸入⑽閘 115 〇 該延遲元件陣列111·包含數個各具有^之延遲時間的 1 延遲70件，該等延遲元件的第一個元件接收一輸出時鐘信 10號。由於那些串聯的延遲元件，該延遲元件陣列in產生 一串經延遲的信號，它們具有連續地以τ之增加量增加的 延遲時間。 該D-型正反器陣列1：L2是為共享一共用資料輸入端（D) ^ D-型正反器的聚集，該輸出時鐘信號係被供應到該共用 15資料輸入端（D)。它們的時鐘輸入C(l)至C(p)係由從該 延遲疋件陣列11Λ供應之連續地經延遲的輸出時鐘信號所 驅動。該D-型正反器陣列11；2因此於c(1)至c(p)的每 一升緣處閂鎖該輸出時鐘信號，該等結果出現於有關的輸 出端Q(l)至Q(p)。所有該等内部正反器係由經由該陣列 20 I12之重置（R)端輸入的外部重置信號消除。 該等X〇R閘113(1)至ll3(p-l)係連接至該D-型正 反器陣列112的輸出端Q(1)至Q(p)，每一 x〇R閘 113(1)至ll3(p-l)對兩個連續的信號執行邏輯X〇R運算 該等後續的AND閘II4⑴至114 對兩個X〇R輸 __ 第24頁 本紙張尺度適财關家標準（CNS) A4規格（2歌297公釐） (請先閲讀背面之注意事項再填寫本頁) •訂丨 _%· 521498 A7 B7 五、發明説明（沙） 出執行邏輯AND運算，該兩個XOR輸出係通過該與一個 XOR閘相關之延遲時間是為該與另一 XOR閘相關之延遲時 間兩倍或一半的方式來被選擇。該OR閘115對先前之 AND閘114 (1)至114 (p-1)的所有輸出執行邏輯OR運算 5 ° 請再參閱第13圖所示，該反相器116把由該作用比偵 測器110所產生之校正完成信號的反相版本供應給該等 1 AND閘A (1)至A (p)。根據這信號，該等AND閘A (1)至 A(p)在該等延遲輸出信號C(l)至C(p)到達該邊緣偵測器 10 60之前通過或者阻擋該等延遲輸出信號C(l)至C(p)。 該第三實施例的時鐘信號校正電路運作如下。初始地， 第13圖的電路接收一外部重置信號，及一剛變成可利用的 輸入時鐘信號。該重置信號清除該作用比偵測器110,藉 此使得該校正完成信號為低。該校正完成信號的這低位準 15 使得該反相器116變成高，並且允許該邊緣偵測器60透 過該等AND閘A(l)至A(p)從該延遲元件陣列50接收延 遲輸出信號C(l)至C(p)。然後，該邊緣偵測器60和經 延遲的信號選擇器70照常一起運作，偵測該分頻器輸出信 號的邊緣，及根據所偵測的邊緣位置選擇一具有半-週期延 20 遲之適當的延遲輸出信號。該XOR閘80現在從兩個異相 90度的半-率分頻器輸出信號重新產生一原來-率時鐘信號 。據此，該最終的輸出時鐘信號得到50%之經校正的作用 比。 在該分數校正器100内部，該延遲元件陣列111把一 第25頁 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） .....................:裝..................訂------------------緣 (請先閲讀背面之注意事項再填寫本頁) 521498 A7 _B7_ 五、發明説明（25 ) 串藉由連續地以τ之增加量延遲該輸出時鐘信號來從該輸 出時鐘信號產生的觸發信號供應給該D-型正反器陣列II2 。該D-型正反器陣列112於從該延遲元件陣列111供應 之該等觸發信號的每一升緣處取樣該約定的輸出時鐘信號 5 ，藉此從其之輸出端Q(l)至Q(p)發送該等經閂鎖的信號 。該等XOR閘113(1)至113(p-l)把每兩個連續的輸出 信號比較，藉此指出具有高位準輸出之輸出時鐘信號的每 一邊緣位置。 由於該輸出時鐘信號必須具有一經校正的作用比，其之 10 邊緣應該在一特定對的XOR輸出找到。該等AND閘114 (1) 至114(p-l)被配置來偵測該等邊緣位置的各種圖型，而 該OR閘115從該等AND閘114 (1)至114 (p- 1)收集該 等結果俾產生一校正完成信號。因此，如果該約定之輸出 時鐘信號之被偵測的邊緣與任何被準備的圖型相稱的話， 15 該〇R閘115主張該校正完成信號。 該作用比偵測器110的高位準輸出通知後續電路（圖中 未示）該時鐘信號的作用比業已被成功地校正。它亦使得該 反相器116變成低，其致使該等AND閘A (1)至A (p)阻擋 該等延遲輸出信號C(l)至C(p)。然後，由於在該邊緣偵 20 測器60内的正反器61(1)至61(p)將不再會被觸發，它 們維持保持它們之先前的狀態（即，記憶邊緣之先前的位元 圖型）。該等偵測信號亦據此維持它們的目前狀態，允許該 經延遲之信號選擇器70維持目前選擇的延遲輸出信號。因 此，該XOR閘80持續產生具有與先前建立之相同之作用 第26頁 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)可可 521498 A7 --------- B7_ V. Description of the Invention (/ 忿) The cycle point is assumed to be the intermediate point between F (4) and F (5), as described by section 11 (B The point of the arrow in the figure is shown because it produces half the delay time of the signal c (4). However, the first embodiment shown in FIG. 3 cannot provide such a midpoint timing including a fractional delay value. For this reason, the 5-delayed signal selector 70 must select either the fourth delayed output signal F (4) or the fifth delayed output signal F (S), discarding the rounding error and I subsequent Inaccurate issues. This second embodiment is intended to correct errors such as those described in Figures 11 (A) and 11 (B) when the delayed signal selector requires a fractional delay time. This is achieved by using another delay element which adds a fractional delay to the selected delay wheel out number. ° No .; L2 figure shows the detailed structure of the score corrector 100. This score corrector 100 is constructed with the following components: 2_input gates 100 (1) to 15 100 (V), multi-input OR gate 101, delay element 102, and selector 103 〇 1 These 2-input OR gates 100 (1) to 100 ("perform logical OR operations on each pair of consecutive even-numbered detection signals, like D (2) and d (4). The multi-input OR gate 101 combines the outputs of those OR gates 100 (丄) to 100 (v). When any even detection signal is activated, the OR gate 101 goes high. Otherwise Its output stays at a low level. The delay element 102 has a delay time of (r / 2), that is, a half of the unit delay time r provided by a single element of the delay element array 50. This additional delay Γ / 2 is added to the delayed signal selector 70. Page 21 The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) .............. ............................................... Order ........ line. (Please read the precautions on the back before filling this page) 521498 A7 I '-— _______ V. Description of the invention (q) The signal selected. The selector 10 Depending on the selection command signal supplied from the multi-input OR gate 101, the delayed signal or the original signal is selected. More specifically, when the selection command signal is low ("〇"), It selects the original signal 5 received directly from the delayed signal selector 7Q. When the command signal is high (,, 1 "), the selector 103 selects to receive the signal from the delay element 102 This delayed signal. The operation of the second embodiment will be described in the next section. Now, recalling what is assumed in Fig. 11 (A), the edge detector 60 is based on C (4). The falling edge 10 of the frequency divider output signal is detected at the timing, so that the third detection signal D (3) is activated. In this case, the activated detection signal D (3) causes the delayed signal detection Detector 70 outputs the fourth delayed output signal F (4) to the fractional corrector ι〇〇. In the fractional corrector 100, the output of the gate 101 is kept low, because none of its inputs The selector is high. Accordingly, the selector 103 allows the delayed output 15 signal F (4) to reach the x〇R gate 80. That That is, the clock signal correction circuit of the second embodiment does bring about the same result as explained in Fig. 11 (A). Then, considering the other example cases discussed in Fig. 11 (B), The edge detector 60 detects the falling edge of the frequency divider output signal 20 at the timing of C (5). Since the fourth detection signal D (4) becomes active in this case, the delayed signal The selector 70 selects the fourth delayed output signal F (4) and outputs the fourth delayed output signal F (4) to the fraction corrector 100. The activated detection signal D (4) also causes the OR gate 101 in the fraction corrector | 100 to output a high level signal. The selector 103 applies the Chinese National Standard (CNS) A4 specification (210X297 mm) because of the paper size on page 22. (Please read the precautions on the back before digging this page)-Order · ·% · 521498 A7 B7 V. Description of the invention (20) 5 10 15 20 This selects the output of the delay element 102 and supplies the x〇R gate 8〇 the delayed output signal FU with an additional delay of r / 2). In this way, when a fractional delay is required by the edge detector 60 and the delayed signal selector 70, the fractional corrector 100 of the second embodiment generates a more accurate delay time, such as by the 11th (B) It is indicated by a dotted arrow in the figure. Although the second embodiment has described the assumption that the fractional delay is one and a half times the unit delay time r, the present invention should not be limited to this specific factor. To construct the proposed circuit, it is also possible to adjust the effect ratio of the agreed clock signal with yb of the unit delay time. This feature is accomplished by constructing the fractional corrector 100 with (b-1) delay elements having a delay time of 1 / b of the unit delay, so any fractional delay amount will be fine-tuned from those Delay elements are generated. Referring next to Figures 13 and 14, still another embodiment of the present invention will be described. Fig. 13 is a block diagram of a clock signal correction circuit according to a third embodiment of the present invention. Since this circuit shares many common components with the first embodiment described earlier in Figure 3, the following sections will focus on their different points' and the same reference numerals are used to identify the same components. Compared with the first embodiment, the third embodiment uses an effect ratio detector U0, 2-input AND gates A (l) to A (p), and an inverter 116 as additional components. For other function blocks, please refer to Figure 3 and the relevant part of the description. The duty ratio detector 110 tests the output clock signal generated by the XOR gate 80, and can determine whether it has a predetermined duty ratio. The test result is reported by a calibration completion signal. If the output clock signal passes page 23 of this paper, the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applied. (Please read the precautions on the back before filling the book. Page) • Equipment · • Red 丨 • Wire 丨 ^ 1498 A7 p -------- J7__ 5. Description of the invention (2 '-For this test, it will be set to high. This effect is higher than detection The detector 110 has a reset (R) input terminal for receiving an external reset signal. Fig. 14 shows the detailed structure of the action ratio detector 110. The detector I10 depicted in Fig. 5 has the following components: A delay element array 1] L1, 5 a D-type flip-flop array 112, XOR gate 113 (1) to UWP-D, | 2-input AND gate 114 (1) to li4 (pi), and one more- Input gate 115. The delay element array 111 includes 70 delays of 1 each with a delay time of ^. The first element of these delay elements receives an output clock signal number 10. Because those delay elements are connected in series, The delay element array in produces a series of delayed signals with delays that increase continuously in increments of τ. The D-type flip-flop array 1: L2 is a collection of D-type flip-flops for sharing a common data input (D). The output clock signal is supplied to the common 15 data input (D ). Their clock inputs C (l) to C (p) are driven by a continuously delayed output clock signal supplied from the delay file array 11Λ. The D-type flip-flop array 11; 2 therefore The output clock signal is latched at each rising edge of c (1) to c (p), and the results appear at the relevant output terminals Q (l) to Q (p). All such internal flip-flops are The external reset signal input through the reset (R) terminal of the array 20 I12 is eliminated. The XOR gates 113 (1) to 113 (pl) are connected to the output terminal of the D-type flip-flop array 112 Q (1) to Q (p), each x〇R gate 113 (1) to ll3 (pl) performs a logical XOR operation on two consecutive signals The subsequent AND gates II4⑴ to 114 pair two X 〇R Loss __ Page 24 This paper size is suitable for financial and family care standards (CNS) A4 specifications (2 songs 297 mm) (Please read the precautions on the back before filling this page) • Order 丨 _% · 521498 A7 B7 V. Description of the Invention (Sand) Execution Logic AN D operation, the two XOR outputs are selected by the way that the delay time associated with one XOR gate is twice or half the delay time associated with the other XOR gate. The OR gate 115 corresponds to the previous AND gate All outputs from 114 (1) to 114 (p-1) are logically ORed 5 °. Please refer to FIG. 13 again. The inverter 116 converts the correction completion signal generated by the duty ratio detector 110 Inverted versions are supplied to these 1 AND gates A (1) to A (p). According to this signal, the AND gates A (1) to A (p) pass or block the delayed output signals C before the delayed output signals C (l) to C (p) reach the edge detector 10 60 (l) to C (p). The clock signal correction circuit of the third embodiment operates as follows. Initially, the circuit of Figure 13 receives an external reset signal and an input clock signal that has just become available. The reset signal clears the effect than the detector 110, thereby making the correction completion signal low. The low level 15 of the correction completion signal makes the inverter 116 high and allows the edge detector 60 to receive a delayed output signal from the delay element array 50 through the AND gates A (l) to A (p). C (l) to C (p). Then, the edge detector 60 works with the delayed signal selector 70 as usual, detects the edge of the frequency divider output signal, and selects an appropriate one with a half-period delay of 20 delays according to the detected edge position. Delayed output signal. The XOR gate 80 now regenerates an original-rate clock signal from two out-of-phase 90-degree half-rate divider output signals. Based on this, the final output clock signal has a corrected effect ratio of 50%. Inside the fraction corrector 100, the delay element array 111 applies a Chinese standard (CNS) A4 (210X297 mm) to a page 25 of this paper size ............... ......: installed ........ Order ------- fate (Please read first Note on the back, please fill out this page again) 521498 A7 _B7_ V. Description of the Invention (25) The trigger signal generated from the output clock signal is supplied to the D-type by delaying the output clock signal continuously with an increase of τ. Flip-Flop Array II2. The D-type flip-flop array 112 samples the agreed output clock signal 5 at each rising edge of the trigger signals supplied from the delay element array 111, thereby from its output terminals Q (l) to Q (p) sending those latched signals. The XOR gates 113 (1) to 113 (p-1) compare every two consecutive output signals, thereby indicating each edge position of an output clock signal having a high level output. Since the output clock signal must have a corrected effect ratio, its 10 edges should be found on a specific pair of XOR outputs. The AND gates 114 (1) to 114 (pl) are configured to detect various patterns of the edge positions, and the OR gate 115 collects the AND gates 114 (1) to 114 (p-1) After the result, a correction completion signal is generated. Therefore, if the detected edge of the agreed output clock signal is commensurate with any prepared pattern, the OR gate 115 asserts the correction completion signal. The high-level output of the duty ratio detector 110 notifies subsequent circuits (not shown) that the duty ratio of the clock signal has been successfully corrected. It also causes the inverter 116 to go low, which causes the AND gates A (1) to A (p) to block the delayed output signals C (l) to C (p). Then, since the flip-flops 61 (1) to 61 (p) in the edge detector 20 detector 60 will no longer be triggered, they maintain their previous state (ie, remember the previous bit of the edge Graphics). The detection signals also maintain their current state accordingly, allowing the delayed signal selector 70 to maintain the currently selected delayed output signal. Therefore, the XOR gate 80 continues to have the same effect as previously established. Page 26 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page)
521498 A7 _B7___ 五、發明説明（24) 比的輸出時鐘信號。 從以上說明可見，當該時鐘信號已獲得想要的作用比時 ，該時鐘信號校正電路把一校正完成信號輸出至後續的電 路。第三實施例的這特徵確保後續的電路方塊在沒有被不 5 被期待的時鐘作用比所迷惑下適當地運作。 該第三實施例亦被設計俾可在想要之作用比被建立時停 止運作該邊緣偵測器6〇。這功能固定該被偵測的邊緣位置 ，藉此消除若該邊緣偵測器60不被停止的話會發生的時鐘 抖動。然而，該邊緣偵測器6〇可以被構築來繼續其對某事 10 件的運作（例如，預定周期的屆滿）。這另一種結構避免把 作用比意外地鎖在錯誤之點的危險。 再者，在該第三實施例中，一外部源（例如，一先前之 電路方_塊）提供一重置信號來初始化該時鐘信號校正電路。 一個簡單實施是為與該系統的電源起動處理同步地產生如 15 此之重置信號。 請參閱第I5圖所示，本發明之又另一實施例被描繪。 第I5圖是為本發明第四實施例之時鐘信號校正電路的方塊 圖。由於這電路與早前在第3圖中所說明之第一實施例共 享很多共用組件，後面的部份將會聚焦於其之不同的點上 20 ，而相同的標號標示相同的元件。 與該第一實施例（第3圖）不同，該第四實施例耳有一 計數器120、一 D-型正反器121、及ANr)閘A(1)至A(p) 。該計數器12〇，例如，計算一輸入時鐘信號之升緣的數 目並且在一預先定義的計數值到達時輸出一高位準信號。 第27頁 本紙張尺度適用中國國家標準（CNS〉A4規格（210X297公爱） (請先閲讀背面之注意事項再填窝本頁) .訂丨 :線丨 521498 A7 ___B7_ 五、發明説明（26 ) (請先閲讀背面之注意事項再填寫本頁) 該計數器120具有一由外部重置信號所驅動的重置輸入。 該D-型正反器121藉由輸入至其之設定（S)輸入之有源外 部重置信號來被初始化地設定到高狀態。當該計數器輸出 變成高時，該正反器121接收目前狀態的外部重置信號。 5 這正反器121的輸出（Q)被使用作為在第三實施例中的校 正完成信號，然而，在第四實施例中，其是為一作動-低（ 或者負邏輯）信號。該等AND閘A (1)至A (p)僅在該校正 完成信號為高（即，不作動）時把該等延遲輸出信號C(l)至 C(p)傳送到該延遲元件陣列50。 10 該第四實施例運作如下。在由外部重置信號初始化之後 ，該計數器120計數被供應之輸入時鐘信號的每一升緣。 初始地，該D-型正反器121被設定到高狀態，因為該外部 重置信j虎被主張短時間。該校正完成信號，這正反器121 的輸出，據此變成高。由於該校正完成信號是為一作動-低 15 邏輯信號，如先前所述，這初始高狀態意指校正未被完成 。該等AND閘A (1)至A (p)因此供應該邊緣偵測器60延 遲輸出信號C(l)至C(p)，允許它開始尋找經分割之時鐘 信號的邊緣，如在第三實施例中一樣。當一邊緣被確認時 ，該邊緣偵測器60透過一組偵測信號通知該經延遲之信號 20 選擇器70該結果。根據那些偵測信號，該經延遲之信號選 擇器70選擇該等延遲輸出信號中之一者傳送到該XOR閘 8 0。結果，具有經校正之作用比的輸出時鐘信號出現於該 XOR閘80的輸出。 當一預定的時間（其必須夠長來完成該校正）係在該外 第28頁 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 521498 A7 B7 五、發明説明（26 ) 5 10 15 20 部重置信號被使成無效之後通過時，該計數器12〇輪出— 高位準信號。這信號使該D-型正反器121變成低，因為它 取樣已變成低之目前狀態的外部重置信號。現在該校正完 成信號被作動，該等AND閘A(l)至A (p)關閉它們的輸出 ，致使該邊緣偵測器6〇保持目前狀態。一無抖動 (jitter-free)輸出時鐘信號係這樣子被獲得，如同早前 描述的第三實施例一樣。 總括來說，該第四實施例提供一簡單電路來提供一校正 完成信號並且避免時鐘抖動。該被建議的電路以一計數器 12〇計數該輸入時鐘信號並且在一預定之時間的屆滿之後 設定一 D-型正反器121，藉此主張一校正完成信號來停止 該邊緣偵測器60的運作。 雖弊第一至第四實施例業已在假設該邊緣偵測器6〇直 接把其之所有的偵測信號供應給該經延遲之信號選擇器7〇 下作描述，本發明不被限定於該特定的結構。或者，該邊 緣偵測器6〇可以被設計來僅發送偶數的偵測信號，及一指 出奇數之偵測信號變成作動的信號。即，該邊緣 貞測器6 〇 在偶數之偵測信號中之任一者被作動時直接把偶數的彳貞測 信號發送至該經延遲之信號選擇器7〇。當奇數的偵測信號 變成作動時，該邊緣偵測器6〇主張最近之偶數的偵測信號 ’並且把它與該奇數之指出信號一起發送，以致於該作動 偵測信號在該經延遲之信號選擇器7〇的該側上被確認。這 另一種結構幾乎把偵測信號之導線的數目縮減一半，藉此 簡化並加速該電路。 第29頁 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） (請先閲讀背面之注意事项再填窝本頁) •裝· 、可_ :線· 5 以上的討論現在將會被摘要如下。轉本發明之一特徵 ’-分頻器把-約定之時鐘信號的頻率除以_自 η 2生-經分割的時鐘信號^這經分割之時鐘信號的相位 位：1目位_器確認。—延遲單祕據該被確認的信號相 一來把-適當的延遲加人該經分割的時鐘信號，藉此產生 :經延遲之經分割的時鐘信號一邏輯運算器藉著對原來 2分割的時鐘信號與該經延遲之經分割的時鐘信號執行 =輯運算來產生-輸出時鐘信號。藉由如此的配置，被建 ίο 15 20 ^時鐘㈣校正電路以簡單和精準的方式校 信號 的作用比失真。 根據本發明的另-特徵’以上的時鐘信號校正電路被整 :成-半導體裝置，其以簡單和精準的方式校正輸入時鐘 ^號的作用比失真。 根據本發明的又另一特徵，一校正電路校正由一輸入電 =所接收之時鐘信號的作用比失真。—輸㈣路輸出具有 =校正之作用比的時鐘信號，且—通知電路通知立他電 路該被接收之時鐘信號的作用已被校正。這時鐘信號校正 電路確保在整個系統中之輸出時鐘信號的正確使用"。； 前文是為本發明之原理的例證而已。再者，由於若干變 化和改變對於熟知此項技術的人仕來說會隨時呈現，本發 明係不被限定於所顯示和描述的結構和應用，而據此，所 有適當的變化和等效物會被視為落於在後附之申請^利$ 圍與它們之等效物中之本發明的範圍之内。 # ^ 元件標號對照表 第30頁 本紙張尺度適用中國國家標準（CNS) Α4規格（210X297公釐） 521498 A7 B7 五、發明說明（之各） 10 分頻器 12 選擇器 C (1)至 C (m) D (1)至 D (m) 延遲元件陣列 互斥OR陣列 11 13 延遲輸出信號 選擇器輪出信號 5 10 15 20 20 分頻器 21 相位偵測器 22 延遲單元 23 邏輯運算器 40 分頻器 50 延遲元件陣列 60 邊緣偵測器 80 XOR閘 70 經延遲之信號選擇器 C(l)至C(p) 信號 F (1)至 F (q)信號 51 (1)至 51(m) 延遲元件 61(1)至 61(p) D-型正反器 62 (1)至 62(p-1) X〇R閘 CK 時鐘輸入端 D 資料輸入端 Q 輸出端 D(l)至 D(p- 1) 偵測信號 70 (1)至 70 (s) N〇R閘 71 (1)至 71 (s) NOR閘 72 N〇R閘 80 X〇R閘 100 分數校正器 100 (1)至 100(V) OR閘 101 OR閘 1〇2 延遲元件 103 選擇器 110 作用比偵測器 116 反相器 A(l)至 A(p) AND閘 111 延遲元件陣列 112 D-型正反器 .....—...............裝 ................訂·….............線. (請先閲讀背面之注意事項再填寫本頁) 第31頁 本紙張尺度適用中國國家標準（⑽）A4規格（21〇χ297公釐） 521498 X〇R閘 AND閘 120 計數器 A7 B7 五、發明説明（约） 113 (1)至 113 (p-l) 114 (1)至 114 (p-1) 115 OR 閘 121 D-型正反器 5 第32頁 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)521498 A7 _B7___ V. Description of the invention (24) The output clock signal of the ratio. It can be seen from the above description that when the clock signal has obtained a desired effect ratio, the clock signal correction circuit outputs a correction completion signal to a subsequent circuit. This feature of the third embodiment ensures that subsequent circuit blocks operate properly without being confused by the unexpected clock ratio. This third embodiment is also designed to stop the operation of the edge detector 60 when the desired effect ratio is established. This function fixes the detected edge position, thereby eliminating clock jitter that would occur if the edge detector 60 were not stopped. However, the edge detector 60 can be constructed to continue its operation on 10 things (for example, the expiration of a predetermined period). This alternative structure avoids the danger of locking the action more than accidentally locking it at the wrong point. Furthermore, in the third embodiment, an external source (e.g., a previous circuit block) provides a reset signal to initialize the clock signal correction circuit. A simple implementation is to generate a reset signal such as 15 in synchronization with the system's power-on process. Please refer to FIG. I5, yet another embodiment of the present invention is depicted. Figure I5 is a block diagram of a clock signal correction circuit according to a fourth embodiment of the present invention. Since this circuit shares many common components with the first embodiment described earlier in FIG. 3, the latter part will focus on its different points 20, and the same reference numerals indicate the same components. Unlike the first embodiment (FIG. 3), the fourth embodiment has a counter 120, a D-type flip-flop 121, and ANr) gates A (1) to A (p). The counter 12, for example, counts the number of rising edges of an input clock signal and outputs a high level signal when a predetermined count value is reached. Page 27 This paper size applies to Chinese national standards (CNS> A4 size (210X297 public love) (please read the precautions on the back before filling in this page). Order 丨: line 丨 521498 A7 ___B7_ V. Description of the invention (26) (Please read the precautions on the back before filling in this page) The counter 120 has a reset input driven by an external reset signal. The D-type flip-flop 121 is set by the input (S) input to it. The active external reset signal is initialized to the high state. When the counter output goes high, the flip-flop 121 receives the external reset signal in the current state. 5 The output (Q) of the flip-flop 121 is used As the correction completion signal in the third embodiment, however, in the fourth embodiment, it is an active-low (or negative logic) signal. The AND gates A (1) to A (p) are only When the correction completion signal is high (ie, inactive), the delay output signals C (l) to C (p) are transmitted to the delay element array 50. 10 The fourth embodiment operates as follows. It is reset by the external After the signal is initialized, the counter 120 counts the supplied input clock Each rising edge of the number. Initially, the D-type flip-flop 121 is set to a high state because the external reset signal is asserted for a short time. The correction completion signal, the output of the flip-flop 121, It becomes high accordingly. Since the correction completion signal is an actuation-low 15 logic signal, as mentioned earlier, this initial high state means that the correction has not been completed. The AND gates A (1) to A (p) therefore The edge detector 60 is supplied with delayed output signals C (l) to C (p), allowing it to start looking for edges of the divided clock signal, as in the third embodiment. When an edge is confirmed, the edge The detector 60 notifies the delayed signal through a set of detection signals, and the selector 70 selects the result. Based on those detection signals, the delayed signal selector 70 selects one of the delayed output signals to transmit to the XOR gate 8 0. As a result, an output clock signal with a corrected effect ratio appears at the output of the XOR gate 80. When a predetermined time (which must be long enough to complete the correction) is outside the page Standards apply to China National Standard (CNS) A4 specifications (210X29 7mm) 521498 A7 B7 V. Description of the invention (26) 5 10 15 20 When the reset signal is invalidated and passed, the counter rolls out 120 — a high level signal. This signal makes the D-type positive and negative The device 121 goes low because it samples the external reset signal of the current state that has become low. Now the correction completion signal is activated, the AND gates A (l) to A (p) turn off their outputs, causing the edge detection The tester 60 remains in its current state. A jitter-free output clock signal is obtained in this way, as in the third embodiment described earlier. In summary, the fourth embodiment provides a simple circuit to provide a correction completion signal and avoid clock jitter. The proposed circuit counts the input clock signal with a counter 120 and sets a D-type flip-flop 121 after the expiration of a predetermined time, thereby asserting a correction completion signal to stop the edge detector 60. Operation. Although the first to fourth embodiments have been described assuming that the edge detector 60 directly supplies all of its detection signals to the delayed signal selector 70, the present invention is not limited to this Specific structure. Alternatively, the edge detector 60 can be designed to send only even-numbered detection signals, and a detection signal indicating an odd-number becomes an activated signal. That is, the edge-stability detector 60 sends an even-numbered detection signal directly to the delayed signal selector 7 when any one of the even-numbered detection signals is activated. When the odd-numbered detection signal becomes active, the edge detector 60 claims the nearest even-numbered detection signal 'and sends it with the odd-numbered pointing signal, so that the active detection signal is at the delayed time. The signal selector 70 is confirmed on this side. This alternative structure simplifies and speeds up the circuit by almost halving the number of wires that detect the signal. Page 29 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling in this page) • Installation ·, OK _: Line · 5 The above discussion will now It is summarized as follows. Turning to one of the features of the present invention, the frequency divider divides the frequency of the agreed clock signal by _ 2 from η-the divided clock signal ^ the phase of the divided clock signal bit: 1 mesh bit. -The delay single secret is based on the confirmed signals one by one.-An appropriate delay is added to the divided clock signal, thereby generating: the delayed divided clock signal. The clock signal and the delayed divided clock signal are executed to generate an output clock signal. With such a configuration, a 15 20 clock correction circuit is built to correct the signal's effect ratio distortion in a simple and accurate manner. According to another feature of the present invention, the above-mentioned clock signal correction circuit is integrated into a semiconductor device that corrects the distortion of the function ratio of the input clock in a simple and accurate manner. According to still another feature of the present invention, a correction circuit corrects an effect ratio distortion of a clock signal received by an input voltage. -The input circuit outputs a clock signal having an effect ratio of correction, and-the notification circuit notifies the other circuit that the effect of the received clock signal has been corrected. This clock signal correction circuit ensures the correct use of the output clock signal throughout the system. The foregoing is merely an illustration of the principles of the present invention. Furthermore, since several changes and modifications will be readily apparent to those skilled in the art, the present invention is not limited to the structures and applications shown and described, and accordingly, all appropriate changes and equivalents Will be deemed to fall within the scope of the invention as set forth in the appended claims and their equivalents. # ^ Component number comparison table, page 30. This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 521498 A7 B7 V. Description of invention (each) 10 Frequency divider 12 Selector C (1) to C (m) D (1) to D (m) Delay element array mutually exclusive OR array 11 13 Delay output signal selector wheel out signal 5 10 15 20 20 Frequency divider 21 Phase detector 22 Delay unit 23 Logic operator 40 Frequency divider 50 Delay element array 60 Edge detector 80 XOR gate 70 Delayed signal selector C (l) to C (p) signal F (1) to F (q) signal 51 (1) to 51 (m ) Delay elements 61 (1) to 61 (p) D-type flip-flops 62 (1) to 62 (p-1) X〇R gate CK clock input D data input Q output D (l) to D (p- 1) Detection signal 70 (1) to 70 (s) NOR gate 71 (1) to 71 (s) NOR gate 72 N〇R gate 80 X〇R gate 100 Fraction corrector 100 (1) To 100 (V) OR gate 101 OR gate 102 delay element 103 selector 110 function ratio detector 116 inverter A (l) to A (p) AND gate 111 delay element array 112 D-type flip-flop .....—............... install ... ............ Order ................ line. (Please read the precautions on the back before filling this page) Page 31 This paper applies to the standard Chinese national standard (⑽) A4 specification (21 × 297 mm) 521498 X〇R gate AND gate 120 counter A7 B7 V. Description of invention (approx.) 113 (1) to 113 (pl) 114 (1) to 114 (p -1) 115 OR gate 121 D-type flip-flop 5 page 32 This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page)