TW520532B - Method for forming T-shape gates - Google Patents

Abstract

The present invention provides a method for forming T-shape gates, which comprises first providing a semiconductor substrate formed thereon an insulation layer, a conductive layer and a hard mask layer; next, etching the hard mask and conductive layer to make the conductive layer form a gate and retain an idle conductive layer; then, performing an oxidization process to form a silicon oxide layer on the surface of the exposed gate and idle polysilicon layer; and finally, anisotropically etching the silicon oxide layer exposed out of the surface of the idle polysilicon layer, isotropically etching the gate and idle polysilicon layer, and removing the hard mask layer.

Description

520532 V. Description of the invention (1)-^ ^ t it ^, #, tJ # t The distance between the pole channels Λ "7 reduces the line width of the closed pole 'and shortens the source. The effect is to speed up the transmission speed and achieve Increasing the accumulation degree = With the advancement of semiconductor technology, the process technology has been moving toward J 'household: the accumulation degree of components increases with the size): Two == pole patterns are required after lithography is formed on the photoresist layer The smaller the idler line width, the more important the lithographic resolution = light: = the narrower the case. The thinner the photoresist layer, the lower the resolution :: Yes, the thinner the photoresist layer, the lower the etch resistance. Q-phase = Patent No. 6'174,818 discloses an improved method. The curtain is composed of an oxynitride layer covered with a oxidized oxide layer and a hard cover layer. The oxide oxidized layer and oxynitride layer have a specific thickness. The role of the Lu impedance reflective layer. After the gate electrode has a shifting step, it can be further reduced, because: ㈡ = turn has a smaller line width. The gate electrode of j has the disadvantage of this method. When the photoresist is further reduced, the layer, especially the part of the edge of the pattern, is removed and the first resistance is destroyed. This method will also increase by half. The conductor elements are densely arranged, = integrity. The difference in critical dimension error between the other loose regions is not uniform and the arrangement is relatively uneven. The yield distance, k is the whole integrated circuit method. Please refer to section 1a-lc Figure, Figure 1a'lc is a conventional method for forming closed poles.

520532

Please refer to FIG. 1a, the oxide layer 102 is sequentially formed on the semiconductor substrate ι2, and more than one stone n q ^ ^ ^, there is a gate. The gate silicon layer 103, the hard mask layer 104, and the patterned Laiyang π 八 Eighth, for the gate element formed on the patterned photoresist 105, please refer to FIG. Ib. Then, the patterned photoresist 1 is used. 5 | Tomb 2: Insects: Hard cover curtain layer 104 and polycrystalline silicon layer 103, so that silicon wafer = gate 103a. / Formally

The gate defined by the minimum line width that can be achieved on the source is reduced in line width. However, it is difficult to achieve the value less than 0.05. Please refer to Figure lc. After removing the pattern, the gate 103a is formed. It can be seen that the line width dimension of the gate electrode 103a is patterned. Current lithography technology has its luminosity. Therefore, the pattern of the photoresist layer is limited by the characteristics of the photoresist layer and the line width of the micro #m. The line width of the photoresist 105 and the hard mask layer 104 and the gate 103a is dl. Therefore, depending on the patterned photoresist layer 105, in view of this, the purpose of the present invention is to provide a method for forming a τ gate, which can reduce and control the gate line width during the manufacturing process, while increasing the accumulation degree of the device. .

According to the above objective, the present invention provides a method for forming a gate electrode, which includes the following steps #: Provide—a semiconductor substrate on which an insulating layer, a conductive layer, a hard mask layer, and a patterned photoresist layer are formed. ; Use patterned photoresist layer as mask to etch hard cover and conductive layer to make conductive layer form a gate and leave an idle conductive layer; remove patterned photoresist layer; apply quick and chemical treatment to make A silicon oxide layer is formed on the exposed gate and the surface of the idle polycrystalline silicon layer; the surface of the exposed polycrystalline silicon layer is anisotropically etched

JZUJJZ V. Description of the invention (3) The oxide layer on the surface; etc. 6 In addition to the hard cover curtain layer.蚀刻 etch the gate and the idle polycrystalline silicon layer; and according to the above purpose, this method includes the following steps: j. Provide a square-gate oxide layer and a 121-stone substrate to form a T-type gate; Sequentially forming layers on a silicon substrate; using a patterned photoresist layer ::, a hard mask layer and -patterned photoresist polycrystalline silicon layer to form an n: etching the hard mask layer and the polycrystalline silicon layer to make the photoresist layer; Shi i-an idle polycrystalline ... the surface of the patterned polycrystalline polycrystalline layer is removed to form a second oxide: the closed pole of the surface and the oxidized polycrystalline silicon on the exposed surface of the idle layer, etc .: etc. Shi Xi layer; and remove the hard cover curtain layer. θ, Specific Money Carved Gate and Idle Polycrystalline Example: The diagram of the pole is the formation of the T-shaped closed circuit of the present invention = see Figure 2a 'First' Provide a semiconductor substrate 201, which can be formed on the semiconductor substrate 201 Any required originals. Next, a method of forming an insulating layer 002 'on the substrate 201 can be formed by & Li & Fung using a dry oxidation method to form a thermal oxide layer in a high temperature environment where oxygen is present or a thin oxide layer by an oxidation process. Then, a conductive layer 203 is formed over the insulating layer 202. The method for forming the conductive layer 203 may be to deposit (CVD) the insulating layer 202 to deposit a polycrystalline silicon layer on the insulating layer 202. A hard mask layer 204 is then formed over the conductive layer 203, and a photoresist layer is formed on the hard mask layer 204. The photolithography is performed using a photomask (not shown) having a desired pattern to light the light. A pattern is formed on the resist layer, and the etching method is shown in FIG. 0503-7579TWF (N); TSMC2001-1234; Claire.ptd Page 6 520532

A patterned photoresist layer to form a patterned photoresist 205. Among them, the semiconductor substrate 201 is, for example, a silicon substrate; the insulating layer 202 is, for example, a gate oxide layer; the conductive layer 203 is, for example, a polycrystalline silicon layer, and the hard cover curtain layer 204 is, for example, tetraethoxysilicic acid A salt (TEOS) or silicon oxynitride (Si ON) is used to protect the conductive layer 203 for subsequent processing; the patterned photoresist layer 205 is a photoresist that has passed a mask-defined pattern ^.

Please refer to FIG. 2b. Next, the patterned photoresist 20 is used as a mask to dry-etch the hard mask layer 204 by anisotropic method. Then, the same method is used to dry-etch the isotropic film. The conductive layer 2 0 3 is etched, and the conductive layer 2 0 3 becomes the gate electrode 203 a and the idle conductive layer 203 b. The idle conductive layer 20 b is a conductive layer left on the surface of the insulating layer 202. The thickness of the idle conductive layer 20 is related to the line width of the T-gate formed at last. The thicker the thickness of the idle power-up layer 20, the narrower the line width of the τ-type gate; the idle conductive layer 2 〇3 The thinner the thickness of b, the wider the line width of the T-gate; the line width of the T-gate will not exceed the gate line width defined by the pattern on the patterned photoresistor 205 at the widest. Among them, the idle conductive layer 203b is, for example, an idle polycrystalline silicon layer. Referring to FIG. 2c, the patterned photoresist 205 is removed, and the semiconductor substrate 205 formed with the conductive layer 2j) 4, the gate 203a, and the idle conductive layer 20 is subjected to an oxidation treatment. Among them, the oxidation treatment is, for example, a rapid oxidation treatment (〇2

flash), and the rapid oxidation treatment is, for example, oxygen plasma treatment.凊 Refer to Figure 2d 'because the rapid oxidation treatment will not have an effect on the hard cover layer 2J4, so after the rapid oxidation treatment is performed, the oxygen plasma only interacts with the question electrode 203a and the idle conductive layer 203b, making the electrode closed. An oxide layer 2G6 is formed on the surfaces of 203a and the idle conductive layer 2G3b. Of which, oxygen

520532 V. Description of the invention (5) The chemical layer 2 0 6 is, for example, an oxide layer. Please refer to FIG. 2e. Then, anisotropic etching is performed on the oxide layer 206 formed on the idle layer. The surface of the conductive layer 203b is surface-etched to remove the idle conductive layer 20 3b. The emulsified layer 206 leaves the oxidizers on the sides of the gate electrode 203a. In v, the method of anisotropic etching is to use a plasma such as a fluorine-containing gas plasma. Water enters dry etching. Please refer to Figure 2f for electricity. For gate 203 & and idle conductive layer 203 == 3 'Idle conductive layer' and make the gate 2 ° 3a form a T-gate. 203c. Among them, the isotropic method can be performed by wet etching or dry etching by plasma. Drying example: gas = plasma or hydrogen bromide gas plasma.疋 3 milk body Please refer to Figure 2g. Finally, remove the hard cover layer 204 and the oxidized sound 206a. In this way, a τ gate 203c can be obtained. It can be seen in Fig. 2g that the gate line width dimension of the original patterned photoresistive sound 2 is dl. After the ^ electrode me proposed in the present invention, the size of the electrode line width becomes d2, d == " The 'τ-type gate 2G3c can effectively reduce the size of the gate line width, and the size of the gate line width is limited by the patterned photoresist layer 2 05. The gate line of the T-type gate 203c The width d2 can be smaller by the idle width f; when the thickness of the idle conductive layer 203b is thinner, the visibility of the gate line width d2 is larger. When the thickness of the idle conductive layer is not thick, it takes time to remove The interposed conductive layer 20 is fluttered, so the isotropy is also removed: When the gate electrode 203a is also removed, the closed electrode line 0503-7579TWF (N) of the τ-type closed electrode 203c; TSMC2001-1234; Claire. ptd Page 8

When the width is d 2 66, the book size is small. Similarly, when the thickness of the idle conductive layer 203b is thinner, it takes less time to go to the second idle conductive layer 203b, so the isotropic etching width d2 of the electrode 203a is also less, making the T-gate 20 The gate electrode's% & inch will be larger. Pole, J: Ben, Ming provided the method of forming a τ gate can reduce the gate, and the end? ： 1 The distance between the source and drain channels of the source is effective in accelerating the transmission speed, and the purpose of increasing the accumulation degree is achieved. With the reduction of the same component, the user can reduce the applied voltage and extend the limitation. Ϊ The present invention has been disclosed as above with a preferred embodiment. However, it is not intended to be used within the scope. You can: & Changes and decorations can be made without departing from the spirit field of the present invention. Therefore, the scope of protection of the present invention shall be defined by the scope of the patent application attached to moxibustion.

520532 Brief description of the drawings In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in conjunction with the accompanying drawings to make a detailed description as follows: Section 1 a- Figure 1c is not intended to describe the flow of the gate forming method. Figures 2a-2g are schematic flowcharts of the method for forming a T-gate according to the present invention. Explanation of symbols: 101 ~ semiconductor substrate; 103 ~ polycrystalline silicon layer; 104 ~ hard mask layer; 201 ~ semiconductor substrate; 230 ~ conductive layer; 203b ~ idle conductive layer; 204 ~ hard mask layer; 2 0 6, 20 6a ~ oxide layer 102 ~ gate oxide layer; 103 ~ a gate; 105 ~ patterned photoresist layer; 02 ~ insulation layer; 02 ~ 3a ~ gate; 2 0 3 c ~ T gate; 2 05 ~ patterned photoresist;

0503-7579TWF (N); TSMC2001-1234; Claire.ptd page 10

Claims (1)

6. Scope of Patent Application-1 · A method for forming a τ-type gate, including the following steps: Knowing a semiconductor substrate, an insulating layer, a conductive layer, and a hard cover screen are formed on the semiconductor substrate. The hard cover curtain layer and the etched part of the conductive layer; the side also performs an oxidation treatment to form an oxide layer on the surface of the conductive layer exposed on the surface; anisotropically etch the oxide layer on the exposed surface of the conductive layer; Removing the conductive layer; and removing the hard mask layer. 2. The method for forming a τ gate according to item 1 of the scope of patent application, wherein the insulating layer is an oxide layer. 3. The method for forming a T-gate according to item 2 of the scope of the patent application, wherein the oxide layer is a gate oxide layer. 4. The method for forming a T-gate as described in the second item of the patent application, wherein the oxide layer is silicon dioxide. 5. The method for forming a τ-type gate as described in item 1 of the scope of the patent application, wherein the conductive layer is a polycrystalline silicon layer. 6. The method for forming a T-gate as described in item 1 of the scope of the patent application, wherein the delta oxidized layer is a stone oxide layer. 1. The method for forming a T-gate according to the scope of the patent application, wherein the oxidation treatment is a rapid oxidation treatment. 8. The method for forming a T-gate as described in item 7 of the scope of the patent application, wherein the rapid oxidation treatment is performed with an oxygen electric paddle. 9. The method for forming a T-gate as described in item 1 of the scope of patent application, 520532 6. Scope of patent application "-wherein the anisotropic etching is dry etching with plasma. 10. The method of forming a τ gate as described in item 9 of the scope of the patent application, wherein the plasma is a fluorine-containing gas plasma. Η · The method of forming a τ gate as described in item 1 of the scope of patent application ', wherein the isotropic etching is dry etching using a plasma. 12, 12 The method for forming a T-gate as described in item 11 of the scope of the patent application, wherein the edge plasma is a chlorine-containing gas plasma or a hydrogen bromide gas plasma-- 〇, 13. The method of forming a T-gate according to item 1, wherein the isotropic coin is engraved with a plasma to perform a wet residual etching. 14. A method for forming a τ-type gate, including the following steps: providing a silicon substrate; sequentially forming a gate oxide layer, a polycrystalline silicon layer, a hard mask layer, and a patterned photoresist on the silicon substrate; Etching the hard mask layer and the polycrystalline silicon layer using the patterned photoresist layer as a mask to make the polycrystalline silicon layer form a gate and leave an idle polycrystalline silicon layer; remove the patterned photoresist layer; A rapid oxidation process is performed to form a silicon oxide layer on the exposed surface of the gate and the idle polycrystalline silicon layer; anisotropically etch the silicon oxide layer on the exposed surface of the idle polycrystalline silicon layer; A gate electrode and the idle polycrystalline silicon layer; and removing the hard cover curtain layer. 1 5 · The method for forming a T-gate as described in item 14 of the scope of patent application 520532 6. Method of applying for patent scope, in which the rapid oxidation treatment is a treatment method using an oxyfluoride plasma 16 · The method of forming a T-shaped gate electrode as described in item 4 of the scope of patent application, wherein the anisotropic etching is Plasma dry etching 17 • As described in item 6 of the patent application scope, wherein the plasma is a fluorine-containing gas plasma. 1 8 · The method for forming a T-gate by performing dry etching as described in item 4 of the scope of patent application, wherein isotropic etching is performed by plasma / 1 9 A square shaped T-gate as described in item 7 of the scope, wherein the plasma is a gas-containing gas plasma or a hydrogen bromide gas plasma. Among them-〇20 · As described in item 14 of the scope of patent application A method for forming a T-gate, in which the isotropic etching is performed by wet etching with a plasma. law 〇503-7579TWF (N); TSMC2001-1234; Claire.ptd 13th