TW520531B - Electronic device having a reduced leakage current of an edge of a doped region and method thereof - Google Patents

Abstract

A method for forming a protective ring on the top surface of the Source/Drain region of a transistor along its periphery other than directly under the gate of the transistor. This protective ring blocks silicide formation at the edge of the silicide on top of the S/D layer. The protective ring also is not directly connected to any silicide that may form on any exposed sidewalls of the S/D implants, though there is a high resistance connection through the S/D implant itself. The protective ring thus reduces the amount of leakage current that may occur in the transistor.

Description

520531 V. Description of the invention (1) Background of the invention In order to implant a source / drain (s / D) of a field effect transistor (FET / S) to form a low impedance contact, a silicide layer is often formed on the top surface of the silicon substrate. on. Under the S / D edge and the shallow trench insulation (s), which is used to insulate these devices, the silicide layer can be close enough to the S / D joint surface to cause leakage. This problem becomes more significant when the fet junction is historically shallower. The ST I is a typical silicon oxide, which will be etched during wafer processing and will not be completely recessed. The silicon below the surrounding is sinking near the STI and S / D interfaces near the top surface of the wafer. Low, or both. This allows the silicon implanted on an S / D side wall to be exposed. When silicide is formed on top of the S / D, it is simultaneously formed on the exposed edge. The formation of the silicide also has the effect of bringing the silicide closer to the edge of the FET than to the center of the S / D junction. In addition, in some examples, the S / D interface will be raised upward at the s / d interface. A relatively short path for leakage potential can also occur due to this phenomenon. The structure shown in Figure 1 shows this situation. Both the ST-sink portion i0 and the recess i2 are displayed. The distance A is also greater than the distance b. As such, the s / D leakage potential directly to the substrate 14 without previously entering the S / D diffusion layer 16 increases. SUMMARY OF THE INVENTION In view of the above, the present invention provides a guard ring along the top of a source / drain region of a transistor rather than directly under the transistor gate. The guard ring fills the silicide at the edge of the silicide on top of the S / D layer. The guard ring is also not directly connected to any silicide that will form on any exposed side walls of the s / D implant, even if there is a high impedance connection to the S / D implant itself. In this way, the protection ring reduces

520531 V. Description of the invention (2) Leakage due to conditions. The present invention includes two preferred embodiments. In the first embodiment, a dielectric spacer film is generated along the inner wall of the ST I. The second specific embodiment creates a dielectric feature along the top edge of the ST I. The two specific embodiments are different from each other in that the first preferred embodiment generates a silicide packing structure after forming the FET gate and the S / D implanted region. The second preferred embodiment generates the FET gate and a silicide packing structure before S / D implantation. However, two specific embodiments provide a non-conductive padding film to prevent the silicide formed near the edge of the S / D to the STI, and thereby reduce the amount of current flowing into the resistor. These and other features of the present invention will become apparent when reference is made to the accompanying drawings, which are reviewed in the following detailed description of the preferred embodiments presented by the present invention. Brief Description of the Drawings Figure 1 is a cross-sectional view showing the conventional technique of sinking and sinking. FIG. 2 is a cross-sectional view of the S / D and STI regions of a transistor formed according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view of a uniform tri-silicon nitride layer deposited on the structure shown in FIG. 2. FIG. 4 is a cross-sectional view of a silicon nitride deposited in a recessed portion after the silicon trinitride layer shown in FIG. 3 is removed. Figure 5 is a cross-sectional view of a deposited rock formation. FIG. 6 is a cross-sectional view of a filling silicide formed on the ST I region. FIG. 7 shows the deposition of oxide and nitride according to a second embodiment of the present invention.

520531

A cross-sectional view of an object layer on a Shixi substrate. FIG. 8 is a cross-sectional view with a portion of the oxide layer shown in FIG. 7 removed. Fig. 9 is a sectional view using a thick CVD layer. FIG. 10 is a cross-sectional view of a small pad formed on the silicon substrate after the CVD layer is removed. V. Description of the invention (3) FIG. 11 is a cross-sectional view of a shallow groove formed in a sigma substrate. FIG. 12 is a cross-sectional view of depositing the STI in the groove shown in FIG. 11. FIG. 13 is a cross-sectional view of removing the oxidized and nitrided layer and leaving the small-packed CVD layer shown in FIG. 10. Figure 14 is a sectional view of the S / D implant. Figure 15 is a cross-sectional view of a silicide layer deposited. Fig. 16 is a cross-sectional view showing that no silicide is formed on the ST! Region. FIG. 17 is a top view of a transistor made according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE PRESENT INVENTION The present invention will now be described with reference to the drawings, in which the same reference numerals refer to the same elements throughout. The first preferred embodiment of the present invention is shown in FIG. 2. As mentioned above, the first embodiment provides a dielectric spacer on the STI and 5/1) interfaces to fill the formation of silicide. The preferred method for forming this spacer is shown in Figures 2-6. Referring to FIG. 2, a cross-sectional view of a part of the transistor device 20 is shown. The device shown includes the STI depression 22 and sinking 24 described above. According to the method of the present invention, a uniform dielectric different from a 200 angstrom thick film 30 of silicon dioxide is deposited on the entire device 20 as shown in FIG. Preferably, the dielectric is tri-silicon tetranitride. Although, a thick film of 200 angstroms is preferably 30 Å.

520531 V. Description of the invention (4) Thick cymbals can be deposited to a thickness between 50 and 300 Angstroms without departing from the main spirit and scope of the present invention. This uniform layer 30 is preferably engraved by reactive ion etching (R I £) with a method for forming the spacer 40 as shown in FIG. 4. In the preferred embodiment presented, the standard R & E chemistry uses carbon tetrahydrocarbon, hydrogen trifluoride carbon, and hydrogen. The spacer 40 is formed in a gap 42 under the S / D and STI boundaries. Turning next to Fig. 5, a silicide metal 50 (titanium, cobalt, etc.) is then deposited on the device 20 as shown. A tempering and striping process is performed in a manner generally known in remote art. After the tempering and silicidation strip processing step tank, the completed silicidation layer 52 is shown in FIG. 6. As can be seen, the dielectric uniform film 30 is padded on the edge 54 of the S / D implantation 16 to form a ε layer. One interesting aspect of the above approach is that it is self-adjusting. In other words, the deeper the depression 12 or the depression 14 shown in FIG. 1, the more spacers 30 are formed. As a result, when the leakage potential is increased, the processing ability to solve the problem is also increased. ~ A second preferred embodiment of the present invention will now be described in further detail. When the second embodiment of the present invention is used, the silicide plug film 30 is deposited on the structure of the FET gate 158 (see FIG. 17) and S / D implantation 18 (see FIG. 丨). Once produced, the silicide packing film 30 is constructed by a metal, so that it maintains the popularity of the FET gate and S / D implantation 16 processing steps, and completes the silicide packing function when the silicide layer 50 is deposited. . Referring first to FIG. 7, a silicon wafer 60 already has any of the only removable pad films 6 2, 6 4 on its top surface 70. In the preferred embodiment, the two pad films will be silicon dioxide and silicon trinitride. However, when this

520531 V. Description of the invention (5)]: ’For other compositions, the present invention is functional, so that-thin atmosphere film can only act on i :; Ming-9 o'clock under thick oxide film. ) When the sn pattern is continued, such as: compound J is too thin oxide to the pad of the dioxide dioxide and trinitride film 6; the reverse = ion money engraved for a while, and then, use four gasification carbon eve ;: Gas; the second exposed RIE chemical method of nitride below. In FIG. 8, a: = lice standard ^ ΡίΓ L ~ 7 skin 04 silicon dioxide film 62. In addition, 4 RI E stops at the silicon dioxide film 62 2-"#", and the wet etching step strips the road, and the oxide state is recessed into the tetranitride tristate The next d two go. %%: the bismuth is added under the tetranitride three supplements, and the oxidization is stopped at the two s and the β β. For both the exposed stone film 6 2 In FIG. 9, a 200 Å chemical vapor deposition (_) film 90 layer is deposited on the structure shown in FIG. 8. A thin film 90, which can be selectively etched to nitrides and oxides, is preferred. In a preferred embodiment of the present invention, a dielectric having selectivity to the names of Shi Xi, Shi Shi Xi, and Nitride Shi Xi can be used, for example, 'using oxide, oxide, or germanium nitride. Other alternative embodiments include insulating films such as oxides, or other oxides, nitrides, or other dielectrics. In addition, although a thickness of 200 angstroms is preferred, the CVD film 90 can be taken to a thickness between 50 and 300 angstroms without departing from the present invention. This C V D film is deposited and filled in the recessed portion 92 shown in Fig. 9. After a reactive ion treatment, a small packing 94 of the thin film 90 (preferably, composed of zirconia, alumina, or germanium nitride) as shown in FIG. 10 is retained. The S T I groove 100 is then formed in the substrate 80 as shown in FIG. 11. Place

Page 10 520531 V. Description of the invention (6) The next step in the process is to form the shallow trench insulation region 1 1 2. FIG. 12 shows the device after the STI region 11 is formed. In FIG. 13 ', the pad of silicon dioxide 62 and tetranitride Sanshiyu 64 are removed leaving behind a dioxin, a dioxin, or a nitrided plug 94 after that. As shown in Fig. 13, a ST I recess 10 is retained as described above. Referring now to FIG. 14, the S / D implant 120 is added to the structure shown in FIG. The small plugs 9 4 formed in Figs. 8 and 9 are too small to have any significant effect on producing the implant 120. Accordingly, the implant 120 was filled under the small plug 94. As shown in FIG. 15, a silicide-forming metal 130 is deposited on the structure shown in FIG. 14. The completed structure 140 is shown in FIG. 16, where 'the silicide 130 has been packed in the deposited hafnium oxide, aluminum oxide, or germanium nitride, or other such packing films. Area 142 of 92. The stone compound 130 is formed on the surface 144 of the S / D implant 120 inside the small packing 94. A side member 146 of a silicide 130 is also formed on the recessed portion 10/3) and implanted on the vertical side wall 1 48, and is located under the small packing 9 4. A top view of a single transistor device 150 manufactured in accordance with the present invention is shown in FIG. In the preferred embodiment of the present invention, the side 152 of the channel region 152 of the device 150 does not have the protection ring 156 of the dioxide file, alumina, or the germanium nitride packing film 92. However, the guard ring 156 extends around the boundary of the sun region 112 around the S / D implant 120. A gate 158 extends beyond the S / D implantation 20 and the sn region 112 'in a general manner as a body device 150. A person who has learned about the art of the specific embodiments described above will become apparent and significantly alter or modify those well-known to those skilled in the art. Therefore, an attempt

520531 V. Description of the invention (7) The foregoing detailed description is to be regarded as illustrative rather than limiting, and it is understood that the scope of the following patent applications, including all equivalents, is intended to define the spirit and scope of the present invention.

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Claims (1)

520531 Case No. 89116357 Rev. VI. Patent Application Scope 1. An electronic device for reducing leakage current at the edge of a doped region-a substrate with a surface, a doped region recessed under the surface, the doped region There is a coplanar plane on the substrate surface, an edge immediately adjacent to the insulating region, and a spacer formed near the edge of the doped region. 2. For example, the electronic device under the scope of patent application 1. Metal silicide formed on the top surface of the doped region 3. For example, the electronic device under the scope of patent application Shi Xi. 4. If the electronic device under the scope of patent application includes a source /; and a pole implant. 5. If the electronic device in the scope of patent application No. 1 is close to the insulation area. 6. If the electronic device in the scope of patent application No. 1 includes a shallow trench insulation area. 7. The electronic device such as the scope of patent application No. 1 includes tri-silicon nitride. 8. If the electronic device under the scope of the patent application is applied by depositing a uniform film, it is formed by a silicon selector. 9. If the electronic device is under the scope of patent application, the reactive ion etching is used. 10. An electrical method for reducing the leakage current at the edge of a doped region, including the following steps: comprising: an insulating region, a surface of a surface, and further including a substrate in which the substrate is the doping. The method of enclosing the spacer plate and the insulating region and enclosing the spacer and the spacer system is #etching. The method includes providing a substrate having a surface, a sub-device, and an insulation recessed under the surface. O: \ 65 \ 65251-911220.ptc Page 14 520531 _Case No. 89116357_f / Year / January 20th Amendment__ VI. Patent application area, and a doped area, the doped area has a coplanar plane at A surface of the substrate surface and an edge immediately adjacent to the insulating region; depositing a uniform insulator on the substrate; etching the uniform layer to leave a spacer leaning against the edge of the doped region; and forming a metal silicide on On the top surface of the doped region. 11. The method as claimed in item 10 of the patent scope, wherein the substrate is Shi Xi. 12. The method of claim 10, wherein the doped region includes a source / electrode implant. 13. The method of claim 10, wherein the spacer is also adjacent to the insulation region. 14. The method of claim 10, wherein the insulating region includes a shallow trench insulating region. 15. The method of claim 10, wherein the spacer comprises trisilicon tetranitride. 16. The method of claim 10, wherein the spacer is formed by depositing a uniform film, which is etched by a silicon selection method. 17. The method of claim 16 in the scope of patent application, wherein the method includes reactive ion etching. 18. An electronic device for reducing leakage current at the edge of a doped region, comprising: a substrate having a surface, an insulating region recessed under the surface, and a doped region, the doped region having a coplanar surface on the substrate surface Surface and an edge immediately adjacent to the insulating region; a silicidated padding layer formed near the top surface of the doped region; O: \ 65 \ 65251-911220.ptc Page 15 520531 _ Case No. 89Π6357_f / year / A month "〇 ___ ___ 6. The doped region in the scope of the patent application is next to the insulating region; and A region edge is formed on an inner region of the top surface of the doped region and is limited by the metal silicide of the silicide padding layer. 19. The electronic device according to item 18 of the patent application, wherein the substrate is silicon. 20. The electronic device of claim 18, wherein the doped region includes a source / electrode implant. 2 1. The electronic device according to item 18 of the patent application scope, wherein the insulation region includes a shallow trench insulation region. 22. The electronic device according to item 18 of the patent application scope, further comprising a second metal petroxide formed downward from the silicided padding layer along the edge of the doped region. -2 3. A method of forming an electronic device that reduces leakage current at the edge of a doped region, comprising the following steps: providing a substrate; depositing a first insulator on the substrate; depositing a first insulator on the first insulator Two insulators; forming a first groove in the first and second insulators, the groove having a side wall; removing a part of the first insulation from the side wall of the groove under the second insulator To form a cavity; to fill the cavity with a third insulator; to form a pair of second grooves in the silicon substrate which are right at the first grooves of the first and second insulators; O: \ 65 \ 65251-911220.ptc Page 16 520531 _Case No. 89116357_f / year / a month △ 0 amended__ Sixth, the scope of the patent application is to fill the second slot with a fourth insulator; remove the first And a second insulator to expose the silicon substrate; doping the exposed portion of the silicon substrate to form a doped region; and forming an inner region formed inward from the doped region on the top surface of the doped region The metal silicide is limited by the third insulator. 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