520507 7 5 8 6twf·d〇c/0 0 6 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（f ) 本發明是有關於一種規劃記憶體的方法，且特別是 有關於一種可規劃可重新程式化非揮發性記憶體之控制單 元與方法。 一般而言，可重新程式化非揮發性記憶體（re-programmable non-volatile memory)可以儲存非揮發性（nonvolatile) 的資料 ，所以可重新程式化非揮發性記憶體常被 使用在於儲存微處理器或微控制器之程式碼部分。市面上 已經將可重新程式化非揮發性記憶體內嵌於微處理器或微 控制器內，請參照第1圖，其繪示的是傳統80C32加上內 嵌式可重新程式化非揮發性記憶體的架構；但是這些內嵌 式可重新程式化非揮發性記憶體的微處理器或微控制器必 須將程式預先燒錄在內嵌式可重新程式化非揮發性記憶體 內或是使用於系統內燒錄(In System Programming)的方式重 新寫入程式。對於程式的燒錄，市面上已經有許多方法可 以使用；但是對於非揮發性資料的重新燒錄則必須再另外 加上一塊可重新程式化非揮發性記憶體作爲儲存資料的專 屬區域，請參照第2圖，其繪示的是傳統80C32加上內嵌 式可重新程式化非揮發性記憶體的架構加上93C46之應 用，並請參照第3圖，其繪示的是傳統80C32加上二內嵌 式可重新程式化非揮發性記憶體的架構之應用。對於這種 另外加一塊內嵌式可重新程式化非揮發性記憶體的架構， 如第2圖之206與第3圖之306，即使程式內嵌式可重新 程式化非揮發性記憶體未被使用完畢亦不能轉換爲非揮發 資料記憶體使用，這樣會對可重新程式化非揮發性記憶體 -----------^--------^--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 520507 75 8 6twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（2) 的資源運用造成浪費。 有鑑於此，本發明提供一種可規劃可重新程式化非 揮發性記憶體之控制單元，以改善習知的問題，其簡述如 下：一種可規劃可重新程式化非揮發性記憶體之控制單 元，耦接至微處理器，用以控制與規劃可重新程式化非揮 發性記憶體之儲存區，包括：可重新程式化非揮發性記憶 體，耦接至微處理器，用以抹除，寫入，讀取與記憶資料； 可重新程式化非揮發性記憶體存取控制單元，耦接至微處 理器與可重新程式化非揮發性記憶體，用以控制可重新程 式化非揮發性記憶體之一保護範圍。 其中，在根據本發明的一個較佳實施例中，上述之 可重新程式化非揮發性記憶體存取控制單元，包括：暫存 器族，包含複數個暫存器，用以規劃可重新程式化非揮發 性記憶體之儲存區；讀寫電路，用以將微處理器之暫存器 信號轉換爲可重新程式化非揮發性記憶體之界面信號；保 護電路，用以判斷欲寫入與抹除之位址是否在可重新程式 化非揮發性記憶體之保護範圍之內；時序控制電路，用以 控制程式化非揮發性記憶體存取控制單元讀取資料。 此外’在根據本發明的一個較佳實施例中，上述之 暫存器族包括：保護起始位址之高位元組暫存器（以下通 稱PBH)，用以定義保護範圍之起使位址的高位元組；保 護結束位址之高位元組暫存器（以下通稱PEH)，用以定義 保護範圍之一結束位址高位元組；寫入暫存器（以下通稱 FDAI)，用以儲存爸欠寫人可重新程式化非揮發性言己H體的 4 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐〉 ------------裝--------訂---------線 (請先閱讀背面之注咅？事項再填寫本頁) A7 520507 7586twf. doc/006 -〜----- - ^ 五、發明說明（多） 資料；讀取暫存器（以下通稱FDA0)，用以儲存讀取可霆 新程式化非揮發性記憶體所得的資料；存取位址之低位元 組暫存器（以下通稱FAL)，用以定義存取位址之低位元 組；存取位址之高位元組暫存器（以下通稱FAH)，用以 定義存取位址之高位元組；記憶體存取控制暫存器（以下 通稱FCTL)。 另外，在根據本發明的一個較佳實施例中，上述之 FCTL包括8個位元：即第0位元至第7位元。其中，第〇 位元（以下通稱CHA)，當CHA爲高準位時，則致能可重新 程式化非揮發性記憶體內部的升壓電路，此時才能夠執行 寫入和淸除的動作；第1位元(以下通稱YEI)，當YEI爲 低準位時，不可將資料寫入可重新程式化非揮發性記憶體 中；第2位元（以下通稱SERA)，當SERA爲高準位時，將 [FAH，FAL]所指的節區內所有的値全部淸除；第3位元(以 下通稱PGM)，當PGM爲高準位，且當CHA與YEI高準 位時，可將FADI的値寫入[FAH，FAL]所指的位址的動作致 能；第4位元（以下通稱RD)，當RD爲高準位時，讀取 [FAH，FAL]所指位址中的値，再將資料輸出至FDA0中。 其中，在根據本發明的一個較佳實施例中，上述之 可規劃可重新程式化非揮發性記憶體之控制單元更包括： 計數器，可以利用韌體直接控制計數器計數可重新程式化 非揮發性記憶體寫入與抹除的時間。 此外，上述之PBH與PEH可由該可重新程式化非揮 發性記憶體存取控制單元或外在程式或控制界面或暫存器 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) " — ------------t--------訂---------線 (請先閱讀背面之注音P事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 520507 A7 B7 7586twf·doc/006 五、發明說明（斗） 設定之。 本發明另提供一種可規劃可重新程式化非揮發性記 憶體之方法，係利用定義保護起始位址之高位元組與保護 結束位址之高位元組’規劃可重新程式化非揮發性記憶體 內部之保護範圍，在保護範圍內，可重新程式化非揮發性 記憶體只能儲存資料，不能被寫入與抹除資料。其中可重 新程式化非揮發性記憶體，用以抹除，寫入，讀取與記憶 資料。 其中，在根據本發明的一個較佳實施例中，上述之 定義方法可利用外在程式或控制界面或暫存器或控制單元 定義保護起始位址之局位兀組與保護起始位址之低位元 組。 簡而言之，本發明之架構乃只使用一塊可重新程式 化非揮發性記憶體，此可重新程式化非揮發性記憶體可以 彈性規劃爲可以更改區段及不可更改區段。可以更改區段 用來儲存非揮發資料，此區段記憶體是可以被讀取、寫入 以及抹除；不可更改區段則用來儲存程式，此區段記憶體 是僅可被讀取。此架構可將未被程式使用完畢之部分彈性 規劃爲非揮發資料記憶體之儲存空間，則此資料記憶體儲 存區段具有可以隨時修改又具有非揮發性之能力。 爲讓本發明之上述和其他目的、特徵和優點，能更 加明顯易懂，下文特舉較佳實施例，並配合所附圖示，做 詳細說明如下： 圖示簡單說明= 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） (請先閱讀背面之注意事項再填寫本頁) ▼裝--------訂---------線j 經濟部智慧財產局員工消費合作社印製 520507 A7 75 8 6twf. doc/006 1'發明說明（f) 第1圖繪示的是傳統80C32加上內嵌式可重新程式 化非揮發性記憶體的架構； 第2圖繪示的是傳統80C32加上內嵌式可重新程式 化非揮發性記憶體的架構加上93C46之應用； 第3圖繪示的是傳統80C32加上二內嵌式可重新程 式化非揮發性記憶體的架構之應用； 第4圖繪示的是本發明應用在80C32之架構圖； 第5圖繪示的是第4圖中可規劃可重新程式化非揮發 ft記憶體之控制單元404及時間計數器的使用示意圖； 第6圖繪示的是快閃記憶體之資料讀取時序圖； 第7圖繪示的是快閃記憶體之資料寫入時序圖；以及 第8圖繪示的是快閃記憶體之資料節區抹除時序圖。 氣要元件標號： 2〇2 ·· 80C32微處理器 2〇4 :位址解碼器與可重新程式化記憶體 2〇6 ： 93C46 3〇2 ·· 80C32微處理器 3〇4 :位址解碼器與用於程式區段之可重新程式化記憶體 3〇6 :位址解碼器與用於資料區段之可重新程式化記憶體 402 : 80C32微處理器 404 :可規劃可重新程式化非揮發性記憶體之控制單元 4〇6 ·•位址解碼器與節區可抹除快閃記憶體 4〇8 ··可重新程式化非揮發性記憶體存取控制單元 410，412 ··匯流排 --；----- --- 及通用中國國家標準（CNS)/\'4規格（210 X 297公H一"' " -------------------^------I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 520507 A7 B7 7586twf.doc/006 五、發明說明（έ) 502 :可重新程式化非揮發性記憶體存取控制單元 504:節區可抹除可重新程式化非揮發性記憶體 (請先閱讀背面之注意事項再填寫本頁) 506 :暫存器族 508 ··讀寫電路 51〇：保護電路 512 :時序控制電路 514 :時間計數器 輕隹實施胤: 請參照第4圖，其繪示的是本發明應用在80C32之 架構圖。整個方塊圖與傳統的架構大部分相同，都是把記 憶體內嵌在80C32裡面’只是在可重新程式化非揮發性記 憶體部分必須選擇節區可抹除快閃記憶體406與增加一組 可重新程式化非揮發性記憶體存取控制單元408°在快閃 記憶體406中’可重新程式化非揮發性記憶體存取控制單 元408會將快閃記憶體406分爲可以更改區段與不可更改 區段，可以更改區段通常是用來儲存非揮發資料’此區段 的記憶體是可以被讚取、寫入以及抹除，不可更改區段通 常用來儲存程式，此區段的記憶體僅可被讀取。 經濟部智慧財產局員工消費合作社印製 當80C32有一筆資料要存入可抹除快閃記憶體406中 時，可重新程式化非揮發性記憶體存取控制單元408會自 動判斷該筆資料位址是否在不可更改的區段’如被寫入的 資料位於快閃記憶體保護範圍內，則該寫入動作是被禁止 的。反之如被抹除的資料位於快閃記憶體保護範圍內’則 該動作亦是被禁止的。 8 本紙張尺度適用中國國家標準（CNS)/\4規格（210 x 297公f ) 520507 /586twf.doc/006 A7 B7 五、發明說明（Γ| ) 此外，在可抹除快快閃記憶體節區抹除、燒錄過程 中可以靠韌體控制計數器來計算抹除、寫入的時間。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 請參照第5圖，其繪示的是第4圖中可規劃可重新程 式化非揮發性記憶體之控制單元404及時間計數器的使用 示意圖。在本發明可規劃可重新程式化非揮發性記憶體之 控制單元包括：可重新程式化非揮發性記憶體存取控制單 元502與可重新程式化非揮發性記憶體504。其中可重新 程式化非揮發性記憶體存取控制單元502,用以控制該可 重新程式化非揮發性記憶體之一保護範圍，重新程式化非 揮發性記憶體存取控制單元502，用以用以抹除，寫入， 讀取與記憶資料。其中可重新程式化非揮發性記憶體存取 控制單元502包括：暫存器族506、讀寫電路508、保護電 路510、時序控制電路512。暫存器族506，包含複數個暫 存器，用以規劃可重新程式化非揮發性記憶體之儲存區。 讀寫電路508，用以將微處理器之暫存器信號轉換爲可重 新程式化非揮發性記憶體504之界面信號。保護電路510， 用以判斷欲寫入與抹除之位址是否在可重新程式化非揮發 性記憶體504保護範圍之內。時序控制電路512控制可重 新程式化非揮發性記憶體存取控制單元讀取資料。時間計 數器514則可利用爲控制器內原有之時間計數器來控制節 區可抹除可程式化非揮發性記憶體504的寫入及抹除的時 間。 其中，上述之暫存器族506包括：保護起始位址之高 位元組暫存器（以下通稱ΡΒΗ)，保護結束位址之高位元組 木紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 520507 7586twf.doc/006 A7 B7 五、發明說明（） (以下通稱PEH)，寫入暫存器（以下通稱FDAI)，讀取暫存 器（以下通稱FDAO)，存取位址之低位元組暫存器（以下通 稱FAL)，存取位址之高位元組暫存器(以下通稱FAH)，記 憶體存取控制暫存器（以下通稱FCTL)。 其中，PBH:爲快閃記憶體保護起始位址高位元組， 若PBH已定，低位元組不管爲何値皆爲保護位址。假設以 節區抹除區段長度爲256位元組爲例，所以低位元組所定 義的位址都落在同一節區內，單一節區內的資料被保護的 情況是一致的，故不用定義保護位之址低位元組。PBH所 表示的位址即表示快閃記憶體被系統所保護的起始位址； PEH:爲快閃記憶體保護結束位址高位元組，若peh已定， 低位元組不管爲何値皆爲保護位址。在被保護的區域內快 閃記憶體僅能當成程式的儲存之用不能夠當成資料之讀寫 之區域，所以資料只能被讀取不能被寫入或抹除，被保護 的區域外才能當成資料之讀寫之區域。這個保護動作是由 硬體來達成’此一動作可以保護軔體在開發時不小心的誤 動作。FDAI:爲快閃記憶體資料寫入暫存器，儲存欲寫入 快閃記憶體的資料。FDAO:爲快閃記憶體資料讀取暫存器， 儲存已讀取快閃記憶體的資料。FAL:爲快閃記憶體資料存 取位址之低位元組暫存器，用以定義存取位址之低位元 組。FAH:爲快閃記憶體資料存取位址之高位元組暫存器， 用以定義存取位址之高位元組。FCTL:爲快閃記憶體存取 控制暫存器。 其中’上述之FCTL中各位元的定義列於下表。 10 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐） -----------·裝--------訂---------線# (請先閱讀背面之注意事項再填寫本頁) 520507 經濟部智慧財產局員工消費合作社印製520507 7 5 8 6twf · doc / 0 0 6 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (f) The present invention relates to a method for planning memory, and in particular to a method for planning memory. Control units and methods for reprogrammable non-volatile memory can be planned. Generally speaking, re-programmable non-volatile memory can store nonvolatile data, so reprogrammable non-volatile memory is often used to store microprocessing Part of the code for a microcontroller or microcontroller. Reprogrammable non-volatile memory has been embedded in microprocessors or microcontrollers on the market. Please refer to Figure 1. It shows the traditional 80C32 plus embedded re-programmable non-volatile memory. Architecture; however, these embedded reprogrammable non-volatile memory microprocessors or microcontrollers must have the program pre-programmed in the embedded re-programmable non-volatile memory or used in the system Rewrite the program in In System Programming. For the programming of the program, there are many methods available on the market; but for the re-programming of non-volatile data, an additional piece of re-programmable non-volatile memory can be used as the exclusive area for storing data. Please refer to Figure 2 shows the application of traditional 80C32 plus embedded reprogrammable non-volatile memory plus 93C46, and please refer to Figure 3, which shows traditional 80C32 plus two Application of embedded reprogrammable non-volatile memory architecture. For this structure with an additional embedded re-programmable non-volatile memory, such as Figure 206 in Figure 2 and Figure 306 in Figure 3, even if the program-embedded non-volatile memory is not reprogrammed After use, it cannot be converted to non-volatile data memory. This will reprogrammable non-volatile memory ----------- ^ -------- ^ ---- ----- (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 520507 75 8 6twf.doc / 006 A7 B7 Wisdom of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Property Bureau V. Invention Description (2) The use of resources caused waste. In view of this, the present invention provides a control unit that can program reprogrammable non-volatile memory to improve the conventional problem, which is briefly described as follows: A control unit that can program reprogrammable non-volatile memory , Which is coupled to the microprocessor for controlling and planning the storage area of the reprogrammable non-volatile memory, including: the re-programmable non-volatile memory, which is coupled to the microprocessor for erasing, Write, read and memorize data; re-programmable non-volatile memory access control unit, coupled to the microprocessor and re-programmable non-volatile memory to control re-programmable non-volatile memory Memory protection range. Wherein, in a preferred embodiment according to the present invention, the reprogrammable non-volatile memory access control unit described above includes: a register family including a plurality of registers for planning a reprogrammable program. Nonvolatile memory storage area; read-write circuit to convert the microprocessor's register signal to reprogrammable non-volatile memory interface signal; protection circuit to determine whether to write and Whether the erased address is within the protection range of the reprogrammable non-volatile memory; the timing control circuit is used to control the program-controlled non-volatile memory access control unit to read data. In addition, in a preferred embodiment according to the present invention, the above-mentioned register family includes: a high-order byte register (hereinafter referred to as PBH) for protecting the start address, which is used to define the starting range of the protection address The upper byte of the end address of protection (hereinafter referred to as PEH), which is used to define the upper byte of the end address of one of the protection scopes; write to the register (hereinafter referred to as FDAI) to store Dad owes the writer to re-program the non-volatile non-volatile H-size 4 paper sizes that are applicable to the Chinese National Standard (CNS) A4 specification (21 × x297 mm) ------------ equipment -------- Order --------- line (Please read the note on the back? Matters before filling out this page) A7 520507 7586twf. Doc / 006-~ ------^ V. Description of the invention (multiple) data; read register (hereinafter referred to as FDA0), which is used to store the data obtained by reading the new stylized non-volatile memory; the low byte register of the access address (Hereinafter referred to as FAL) to define the low byte of the access address; high byte register (hereinafter referred to as FAH) of the access address to define the high byte of the access address The memory access control register (hereinafter referred to as FCTL). In addition, in a preferred embodiment of the present invention, the above-mentioned FCTL includes 8 bits: the 0th bit to the 7th bit. Among them, the 0th bit (hereinafter referred to as CHA), when CHA is at a high level, can enable the re-programming of the boost circuit inside the non-volatile memory, and then the writing and erasing operations can be performed at this time. ; The first bit (hereinafter referred to as YEI), when YEI is at a low level, data cannot be written into reprogrammable non-volatile memory; the second bit (hereinafter referred to as SERA), when SERA is a high standard Position, delete all 値 in the section area referred to by [FAH, FAL]; the third bit (hereinafter referred to as PGM), when PGM is high, and when CHA and YEI are high, you can The operation of writing FADI's 値 into the address pointed by [FAH, FAL] is enabled; the fourth bit (hereinafter referred to as RD), when RD is high, read the address pointed by [FAH, FAL] And then output the data to FDA0. Among them, in a preferred embodiment of the present invention, the above-mentioned programmable non-volatile memory can be re-programmed. The control unit of the body further includes: a counter, which can be directly controlled by the firmware to count the reprogrammable non-volatile memory writing and erasing time. In addition, the above-mentioned PBH and PEH can be re-programmed non-volatile Memory access control unit or external program or control interface or register 5 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) " — ---------- --t -------- Order --------- line (please read the note P on the back before filling this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 520507 A7 B7 7586twf · Doc / 006 V. Description of Invention (Battle) Set it. The invention also provides a method for planning and reprogrammable non-volatile memory, which uses non-volatile memory that defines the high byte of the protection start address and the high byte of the protection end address to plan the re-programmable non-volatile memory. Within the protection scope, the reprogrammable non-volatile memory can only store data, and cannot be written or erased. Non-volatile memory can be reprogrammed to erase, write, read and memorize data. Among them, in a preferred embodiment according to the present invention, the above-mentioned definition method may use an external program or a control interface or a register or a control unit to define the local group and the protective start address of the protection start address. Low byte. In short, the architecture of the present invention uses only one re-programmable non-volatile memory, and this re-programmable non-volatile memory can be flexibly planned into changeable and non-changeable sections. You can change the section to store non-volatile data. This section of memory can be read, written, and erased. The non-changeable section is used to store programs. This section of memory can only be read. This architecture can plan part of the program that has not been used up flexibly as the storage space of non-volatile data memory. This data memory storage section has the ability to be modified and non-volatile at any time. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments and the accompanying drawings in detail, as follows: Brief description of the drawings = This paper size applies to China National Standard (CNS) A4 Specification (210x297 mm) (Please read the precautions on the back before filling out this page) ▼ Install -------- Order --------- line j Ministry of Economy Wisdom Printed by the Property Cooperative Consumer Cooperative 520507 A7 75 8 6twf. Doc / 006 1'Invention Note (f) Figure 1 shows the structure of the traditional 80C32 plus embedded reprogrammable non-volatile memory; Figure 2 shows the application of traditional 80C32 plus embedded reprogrammable non-volatile memory plus 93C46; Figure 3 shows the traditional 80C32 plus two embedded reprogrammable non-volatile memory The application of the architecture of volatile memory; Figure 4 shows the architecture of the present invention applied to 80C32; Figure 5 shows the control unit that can be reprogrammed non-volatile ft memory in Figure 4 404 and time counter use diagram; Figure 6 shows the flash memory Read timing diagram material; FIG. 7 is a schematic diagram of the flash memory data write timing diagram; and FIG. 8 shows the data section of the flash memory region erase timing chart. Key component labels: 2 0 2 · 80C32 microprocessor 2 0 4: address decoder and reprogrammable memory 2 06: 93C46 3 2 · 80C32 microprocessor 3 0 4: address decoding And reprogrammable memory for program sections 306: address decoder and reprogrammable memory for data sections 402: 80C32 microprocessor 404: programmable reprogrammable non-programmable memory Volatile memory control unit 406 · • Address decoder and node area can be erased flash memory 408 ·· Reprogrammable non-volatile memory access control unit 410,412 ·· Confluence Row-; ------- and common Chinese National Standard (CNS) / \ '4 specifications (210 X 297 male H a "' " ------------- ------ ^ ------ I (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 520507 A7 B7 7586twf.doc / 006 V. Description of the invention ( 502) Re-programmable non-volatile memory access control unit 504: Section area can be erased and re-programmable non-volatile memory (please read the precautions on the back before filling this page) 506: Register family 508 ·· Read and write circuit 51: protection circuit 512: timing control circuit 514: time counter light implementation: Please refer to Fig. 4, which shows the architecture diagram of the present invention applied to 80C32. The whole block The diagram is mostly the same as the traditional architecture, and the memory is embedded in the 80C32. 'Only the reprogrammable non-volatile memory must select the section to erase the flash memory 406 and add a set of reprogrammable Non-volatile memory access control unit 408 ° in flash memory 406 'Re-programmable non-volatile memory access control unit 408 divides flash memory 406 into changeable sections and non-changeable Section, which can be changed. The section is usually used to store non-volatile data. The memory of this section can be liked, written, and erased. The non-changeable section is usually used to store programs. The memory of this section Can only be read. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. When 80C32 has a piece of data to be stored in erasable flash memory 406, non-volatile memory access control can be reprogrammed The unit 408 will automatically determine whether the data address is in an unchangeable section. If the written data is within the flash memory protection range, the write operation is prohibited. Otherwise, the erased data If it is within the flash memory protection range, then this action is also forbidden. 8 This paper size applies the Chinese National Standard (CNS) / \ 4 specification (210 x 297 male f) 520507 /586twf.doc/006 A7 B7 5 Explanation of the invention (Γ |) In addition, during the erasing and burning of erasable flash memory, the firmware control counter can be used to calculate the erasing and writing time. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Please refer to Figure 5, which shows the non-volatile memory that can be reprogrammed in Figure 4 The use of the control unit 404 and the time counter. The control unit that can program the reprogrammable non-volatile memory in the present invention includes: a re-programmable non-volatile memory access control unit 502 and a re-programmable non-volatile memory 504. The reprogrammable non-volatile memory access control unit 502 is used to control a protection range of the re-programmable non-volatile memory, and the re-programmable non-volatile memory access control unit 502 is used to Used to erase, write, read and memorize data. The reprogrammable non-volatile memory access control unit 502 includes a register family 506, a read / write circuit 508, a protection circuit 510, and a timing control circuit 512. The register family 506 includes a plurality of registers for planning a storage area in which non-volatile memory can be reprogrammed. The read / write circuit 508 is used to convert the register signal of the microprocessor into the interface signal of the reprogrammable non-volatile memory 504. The protection circuit 510 is used to determine whether the address to be written and erased is within the protection range of the reprogrammable non-volatile memory 504. The timing control circuit 512 controls the reprogrammable non-volatile memory access control unit to read data. The time counter 514 can use the original time counter in the controller to control the writing and erasing time of the erasable and programmable non-volatile memory 504. Among them, the above-mentioned register family 506 includes: a high byte register for protecting the start address (hereinafter referred to as PB), and a paper size for protecting the high byte of the end address is applicable to the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 520507 7586twf.doc / 006 A7 B7 V. Description of the invention () (hereinafter referred to as PEH), write it into the temporary register (hereinafter referred to as FDAI), read the temporary Register (hereinafter referred to as FDAO), the low byte register (hereinafter referred to as FAL) of the access address, the high byte register (hereinafter referred to as FAH) of the access address, the memory access control register (Hereinafter referred to as FCTL). Among them, PBH: is the upper byte of the flash memory protection start address. If the PBH is determined, the lower byte is the protected address no matter what. Assume that the length of the erasure section of the section is 256 bytes. Therefore, the addresses defined by the lower bytes fall in the same section. The data in a single section is protected in the same way, so it is not necessary. Defines the lower byte of the protection bit address. The address indicated by PBH is the starting address of the flash memory protected by the system; PEH: is the high byte of the end address of flash memory protection. If peh is set, the low byte is whatever it is Protect the address. In the protected area, flash memory can only be used as a program storage area and cannot be used as data read / write area, so data can only be read and cannot be written or erased. Outside the protected area can be used as The area where data is read and written. This protection action is achieved by hardware ’This action can protect the carcass from accidental misoperation during development. FDAI: Writes data to the flash memory and stores the data to be written to the flash memory. FDAO: It is a flash memory data read register to store the data of the read flash memory. FAL: The low byte register for the flash memory data access address. It is used to define the low byte access address. FAH: It is the high byte register of flash memory data access address. It is used to define the high byte of access address. FCTL: Control register for flash memory access. Among them, the definition of each element in the above-mentioned FCTL is listed in the following table. 10 This paper size applies to China National Standard (CNS) A4 (21〇χ 297 mm) ----------- · installation -------- order ------- -线 # (Please read the notes on the back before filling out this page) 520507 Printed by the Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs
7^86twf.doc/006 A7 ----------B7 五、發明說明（C| ) —-—---- 位元 第 7 第 6 第 5 第 4 第 3 第 2 第 1 第 〇 位元 位元 位元 位元 位元 位元 位元 位元 名稱 - - - RD PGM SERA YEI CHA 名稱 定義 RD 爲高準位時，讀取快閃記憶體[fah，fal]所指位址 中的値，快閃記憶體將資料輸出於FDAO中。 PGM 爲高準位時，可將FADI的値寫入[FAH，FAL]所指 的位址的動作致能。寫入時CHA及YEI也必須爲 爲高準位。 SERA 爲高準位時，將[FAH，FAL]所指的節區內所有的値 全部淸除。淸除時CHA也必須爲爲高準位。 YEI 若PGM及CHA爲高準位且YEI爲高準位時，才真 正將FADI的値寫入[FAH，FAL]所指的位址中。若 PGM及CHA爲高準位但是YEI爲低準位時則尙未 將FADI的値寫入[FAH，FAL]所指的位址中。 CHA 爲高準位時，則致能快閃記憶體的內部升壓電路。 快閃記憶體內部升壓電路被致能時才能夠執行寫 入和淸除的動作。 -----------Aw ^--------^--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公f ) 520507 7586twf·d〇c/006 A7 _________B7 五、發明說明（P) 80C32暫存器與快閃記憶體界面信號之真値表7 ^ 86twf.doc / 006 A7 ---------- B7 V. Description of the invention (C |) —-—---- Bit 7th 6th 5th 4th 3rd 2nd 1st Bit 0 Bit Bit Bit Bit Name---RD PGM SERA YEI CHA Name Definition When RD is high level, read the position indicated by flash memory [fah, fal] In the address, the flash memory outputs the data to the FDAO. When PGM is high level, the operation of writing FADI's 値 to the address pointed by [FAH, FAL] can be enabled. CHA and YEI must also be high when writing. When SERA is at the high level, all the 値 in the section indicated by [FAH, FAL] are deleted. CHA must also be at a high level during eradication. YEI If PGM and CHA are at high level and YEI is at high level, the 値 of FADI is actually written into the address pointed by [FAH, FAL]. If PGM and CHA are at the high level but YEI is at the low level, then the FADI value is not written into the address indicated by [FAH, FAL]. When CHA is at a high level, the internal boost circuit of the flash memory is enabled. Writing and erasing can only be performed when the internal boost circuit of the flash memory is enabled. ----------- Aw ^ -------- ^ --------- (Please read the notes on the back before filling this page) This paper size is applicable to China Standard (CNS) A4 specification (210 x 297 male f) 520507 7586twf · doc / 006 A7 _________B7 V. Description of the invention (P) 80C32 register and flash memory interface signals
—8032 暫存器 快閃記憶體界面信號 RD PGM SER YEI CHA XE SE ΥΕ 〇Ε PRO ERA NVS A G SE TR Η X X X X Η Η Η Η L L L L Η X X L Η L L L Η L L L Η X L H Η L L L Η L Η L Η X H H Η L Η L Η L Η L L H X L Η L L L L Η L L L H X H Η L L L L Η Η L L L X X L L L L L L L 上列真値表所代表意義爲[FAH，FAL]的値落在PBH與PEH 所保護的範圍之外時的動作。 ([FAH，FAL]的値落在PBH與PEH所保護的範圍之內時， PROG、ERASE、NVSTR 皆爲低準位） -----------裝--------訂--------- (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮） 520507 7586twf.doc/006 A7 B7 五、發明說明（丨I) 經濟部智慧財產局員工消費合作社印製 快閃記憶體界面信號之定義 信號名 稱 方 向 功能描述 XADR 快閃記憶體X方向的輸入位址。XADR及 YADR由[FAH，FAL]所組合成之位址產 生。 YADR I 快閃記憶體Y方向的輸入位址。XADR及 YADR由[FAH，FAL]所組合成之位址產 生。 DIN I 快閃記憶體資料寫入時的資料匯流排。 DOUT 〇 快閃記憶體資料讀取時的資料匯流排。 XE I 爲高準位時，X方向位址致能。如ΧΕ=〇，則 每一列存取皆被禁止。 SE I 爲高準位時，輸出感測放大器致能。 YE I 爲高準位時，Υ方向位址致能。如γΕ=〇，則 每一行存取皆被禁止。 〇E I 爲高準位時，輸出致能。如〇Ε=〇，則D0UT 爲高阻抗。 PROG I 爲高準位時，設定爲寫入快閃記憶體致能 動作。 NVSTR I 爲高準位時，則致能快閃記憶體的內部升 壓電路。快閃記憶體內部升壓電路被致能 時才能夠執行寫入和淸除的動你。 "~" -—---------- X/J |「 erase I 爲高準位時，設定爲淸除快閃記憶體致能 動作。 (請先閱讀背面之注意事項再填寫本頁) 13 520507 7586twf.doc/〇〇6 A7 _ B7 五、發明說明（d) (請先閱讀背面之注意事項再填寫本頁) 第6圖，第7圖第與8圖所示爲快閃記憶體資料讀 取、寫入、節區抹除時序。透過80C32暫存器與快閃記 憶體界面信號之真値表，整個快閃記憶體控制時序可由 80C32的軔體來控制，配合時間計數器以及配合快閃記憶 體之資料讀取、寫入、節區抹除時序，便可以達成資料讀 取、寫入、節區抹除的功能。 經濟部智慧財產局員工消費合作社印製 如果在軔體中出現有寫入的動作，硬體會去比較 [FAH，FAL]的値是否在PBH與PEH所定的範圍之內。如果 [FAH，FAL]的値落在PBH與PEH所定的範圍之內，則硬體 不讓PROG及NVSTR產生高準位，則快閃記憶體無法達 成寫入的動作；如果[FAH，FAL]的値落在PBH與PEH所定 的範圍之外，則硬體接受軔體的指示可以允許PROG及 NVSTR產生高準位，則快閃記憶體可以達成寫入的動作。 如果在軔體中出現有抹除的動作，硬體會也去比較 [FAH，FAL]的値是否在PBH與PEH所定的範圍之內。如果 .[FAH，FAL]的値落在PBH與PEH所定的範圍之內，則硬體 不讓ERASE及NVSTR產生高準位，則快閃記憶體無法達 成抹除的動作；如果[FAH，FAL]的値落在PBH與PEH所定 的範圍之外，則硬體接受軔體的指示可以允許ERASE及 NVSTR產生高準位，則快閃記憶體可以達成抹除的動作。 透過設定PBH、PEH兩個暫存器即可彈性規劃快閃 記憶體被保護區段，亦即程式區段與資料區段可以透過設 定PBH、PEH兩個暫存器來劃分。如此就可以彈性規劃快 閃記憶體的使用方式，輕易地將程式區段未使用完畢之部 14 本紙張尺度適用中國國家標準（CNS)A‘1規格（210 X 297公釐） 520507 7586twf.doc/006 A/ 五、發明說明（/3) 分規劃爲資料區段來記錄非揮發性資料了。 另外這些暫存器亦可開放給外在的電路來存取。只 要將這些暫存器電路修改成外界可以存取的界面，則外在 的電路也可以來規劃程式區段與資料區段了。 綜上所述，本發明具有可以充分的利用可重新程式 化非揮發性記憶體的優點。 雖然本發明已以較佳實施例揭露於上，然其並非用 以限定本發明，任何熟習此技藝者，再不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印·製 15 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）—8032 Flash memory interface signal RD PGM SER YEI CHA XE SE ΥΕ 〇Ε PRO ERA NVS AG SE TR Η XXXX Η Η Η LLLL Η XXL Η LLL Η LLL Η XLH Η LLL Η L Η L Η XHH Η L Η L Η L Η LLHXL Η LLLL Η LLLHXH Η LLLL Η Η LLLXXLLLLLLL The table below represents the meaning of [FAH, FAL] when the 値 falls outside the range protected by PBH and PEH. (When [FAH, FAL] falls within the range protected by PBH and PEH, PROG, ERASE, NVSTR are all low level) ----------- install ------ --Order --------- (Please read the note on the back? Matters before filling out this page) Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 (public) X 520507 7586twf.doc / 006 A7 B7 V. Description of the invention (丨 I) Definition of flash memory interface signals printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economy Signal name direction Function description XADR Flash memory X The input address of the direction. XADR and YADR are generated from the addresses combined by [FAH, FAL]. YADR I Input address of the flash memory in the Y direction. XADR and YADR are generated from the addresses combined by [FAH, FAL]. Data bus for DIN I flash memory data writing. DOUT 〇 Data bus for flash memory data reading. When XE I is at high level, the X-direction address is enabled. If XE = 0, access to each column is prohibited. When SE I is high, the output sense amplifier is enabled. When YE I is at the high level, the Υ direction address is enabled. If γE = 0, access to each row is prohibited. 〇E I When the high level, the output is enabled. If OE = 〇, DOUT is high impedance. When PROG I is at high level, it is set to write to flash memory to enable. When NVSTR I is at a high level, the internal boost circuit of the flash memory is enabled. The internal boost circuit of the flash memory can enable you to perform writing and erasing only when it is enabled. " ~ " ------------- X / J | "When erase I is high level, set to erase flash memory enable operation. (Please read the precautions on the back first) (Fill in this page again) 13 520507 7586twf.doc / 〇〇6 A7 _ B7 V. Description of the invention (d) (Please read the notes on the back before filling this page) Figure 6, Figure 7 and Figure 8 For the flash memory data read, write, and section erase timing. Through the 80C32 register and the flash memory interface signal truth table, the entire flash memory control timing can be controlled by the 80C32 carcass, With the time counter and the data read, write, and section erasure timing of flash memory, the functions of data reading, writing, and section erasure can be achieved. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs If there is a writing action in the carcass, the hardware will compare whether the radiography of [FAH, FAL] is within the range specified by PBH and PEH. If the radiography of [FAH, FAL] falls within the range of PBH and PEH Within, the hardware will not allow PROG and NVSTR to generate a high level, and the flash memory cannot achieve the writing operation; If [FAH, FAL] falls outside the range specified by PBH and PEH, the hardware receiving the instruction of the body can allow PROG and NVSTR to generate high levels, and the flash memory can achieve the writing action. There is an erasing action in the carcass. The hardware will also compare whether the 値 of [FAH, FAL] is within the range specified by PBH and PEH. If the [of [FAH, FAL] falls within the range of PBH and PEH Within the range, the hardware does not allow ERASE and NVSTR to generate high levels, and the flash memory cannot achieve the erasing action; if [FAH, FAL] falls outside the range specified by PBH and PEH, the hardware Receiving the instructions from the carcass can allow ERASE and NVSTR to generate a high level, then the flash memory can achieve the erasing action. By setting the two registers of PBH and PEH, the flash memory protected section can be flexibly planned. That is, the program section and the data section can be divided by setting two registers, PBH and PEH. In this way, the use of flash memory can be flexibly planned, and 14 unused sections of the program section can be easily removed. Paper size applies to China National Standard (CNS) A'1 specifications (210 X 297 mm) 520507 7586twf.doc / 006 A / V. Description of the Invention (/ 3) It is divided into data sections to record non-volatile data. In addition, these registers can also be opened to external circuits. As long as these register circuits are modified into interfaces that can be accessed by the outside world, external circuits can also be used to plan program sections and data sections. In summary, the present invention can be fully utilized Benefits of reprogrammable non-volatile memory. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can depart from the spirit and scope of the present invention and can make various modifications and retouches. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling out this page) Printed and produced by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 15 The paper size applies to China National Standard (CNS) A4 (210 X 297 mm)