TW519838B - Multi-tasking message extractor - Google Patents

Abstract

An apparatus and method for extracting messages from a data stream has multi-tasking capabilities for accommodating a greater number of data streams and for combining data from different streams. The message extractor includes a packet identifier filter, a control message processor, and two buffers, each buffer divided into a plurality of address locations associated with a plurality of channels. One buffer is used to store extracted message portions, and the other buffer is used to store state data corresponding to the extracted message portions. The control message processor includes a single message processor that is shared by all of the message extraction channels associated with the device. As message portions are filtered and captured, they are stored into the first buffer, while the state data is stored in the second buffer. As additional message portions are received, the system uses identifying data in the data stream to match new message portions with message portions that have already been received and stored to form complete messages. A multi-tasking message extractor reduces the cost of performance by only requiring one message extractor attached to less expensive RAM rather than increasing the number of message extractors themselves.

Description

Printed clothing for employees' cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 519838 A7 —----- B7 V. Description of the invention (i) References to this application refer to the US provisional application filed on October 7, 1999 For the benefit of patent application number 60/158, 032, this publication is incorporated herein by reference in its entirety. FIELD OF THE INVENTION The present invention relates to the field of message grabbers for extracting information from an input data stream, and more particularly to a message grabber for use in more efficient applications such as head-end applications. BACKGROUND OF THE INVENTION Special application integrated circuits (ASIC) are often used to obtain data such as packet data from a data stream. The message grabber is often used in the video decoding device to receive the cable signal to obtain video and audio data and subscriber information that matches a specified video decoding device. The head-end device has more functional requirements than the basic video decoding device, including more multiplexing, encryption, and decryption functions, and therefore requires more information grabbers to accommodate the increased number of functions. The re-multiplexing function especially requires more information grabbers in ASICC because re-multiplexing requires the device to extract services and messages from a larger number of data streams and combine them into different data streams. However, the function of adding more message grabbers to accommodate the booster port of the head-end device requires additional A S I C space for the size of the 7-8 K A S I C brake of each message grabber. In order to save the ASIC space and maintain the multiplexing function, the processor that implements the multiplexing function can be continuous. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -4 _ (Please read the back first (Notes for filling in this page)

519838 Α7 -__ Β7 V. Description of the invention (2) Re-designate the message grabber to refer to different packet identification codes at different times to extract the required information from the data stream. However, using the processor to reassign the message grabber reduces the amount of time the processor spends on the core work related to re-multiplexing itself, reducing the speed of receiving and processing messages. For example, if multiple operations are performed, encryption and decryption can be performed to accommodate the larger message capture requirements of the head-end device without consuming additional aSI space or processor speed. SUMMARY OF THE INVENTION Therefore, the present invention focuses on a message extraction device and method having improved message extraction capabilities. In particular, the present invention focuses on a device for extracting information from a digital data stream containing a message, which includes: a message processor that receives the digital data stream and extracts a message portion from the digital data stream; a first buffer Device, the buffer device is connected to a plurality of locations of a plurality of channels to store the captured information portion; and a second buffer is connected to a plurality of locations of a plurality of channels to store a status corresponding to the captured information portion data. By fetching and storing message parts and their associated status data in individual buffers, the system can combine complete messages from multiple channels in a multiplexed manner. An embodiment of the present invention focuses on a device for capturing information from a data stream, which includes: an input interface for receiving packet data in the data stream; and a packet identifier filter, which is connected to the input interface for selective filtering The packet information also has a CPU interface that allows communication between the device and a CPU; and a message processor that filters from the packet identification code (please read the precautions on the back before filling this page). . Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) -5- —1 — 519838 A7 B7 V. Description of the invention (3) Receiver selection The filtered packet data is built into many channels. This embodiment also includes a first buffer and a second buffer processor for storing the captured message portion. The processor even stores the corresponding information if the message components are distributed in multiple packets of the data stream. The status data of the medium packet data until the entire message has been completely processed. The present invention also includes a method for capturing a message from a data stream, storing the message portion in an internal buffer, and storing the state of the message processor corresponding to the message portion in an external buffer until processed. The entire message. When the state and content of the incomplete message comes to the packet data, they are stored by using, because the incomplete message and its state can be stored due to the multiplexing feature of the invention when other messages are being processed, the invention can process multiple messages No need for multiple message grabbers and later reloading incomplete message data to complete processing. According to the multiplexed message extractor of the present invention, only a message extractor attached to a less expensive R AM is required instead of a multiple message extractor, thereby reducing performance costs. Brief Description of the Drawings Figure 1A is a representative block diagram of an embodiment of the message processor of the present invention; Figure 1B is a block diagram of the central processing unit interface used in conjunction with the device shown in Figure 1; Figure 2 In order to explain the timing diagram of the resynchronization before transmitting the byte data to the filter of the invention system; Fig. 3 is used to explain the internal clock activation used in the invention. Specifications (210 X 297 mm) (Please read the notes on the back before filling out this page) Order:-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Online Economics 519838 A7 B7 V. Description of the invention (4) Timing chart of timing; (Please read the notes on the back before filling out this page) Figures 4 A and 4 B are explanatory diagrams of the filter memory structure and control structure used in the invention; Figures 5 A to 5 D show the displacement data of the device that can be invented Various ways of packetization; Figure 6 is a state diagram illustrating the operation of the message grabber of the invention; Figure 7 is an explanatory diagram of the RAM and the address filter shift register in the message processor of the invention; Figure 8 is the invention Place in the middle Filter control circuit diagram; Figure 9 is the CRC and error detection circuit diagram of the invention; Figure 10 is a flowchart showing the control of reading message buffer in the invention; Figure 11 is a message interrupt control diagram; And FIG. 12 illustrates a message error control circuit. Component comparison table 1 0 0: Device 10 2 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs: Input interface: Message processor: Header code, 6 0 6: Program status: Idle status' · Program message status: Packet capture function : Uniprocessor 1 0 4: Packet ID filter 106 40: Unit address 500 5 0 2: Packet body 6 0 0 6 0 2, 6 0 8: Idle state 10 8 612: Address filtering state 614 61 : Message length status 620 7 0 〇: Processor status machine 104. This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 519838 Α7 ________ Β7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Description of the invention (5) 7 0 2: Multiplexer 8 0 4: Comparator 9 0 0: Error detection circuit 902: CRC generator 12 0 0 8 0 0 8 0 6 6 16 9 0 4 2.0 2: Error Circuit: address filtering control circuit: multiplexer: CRC confirmation status: CRC shift register preferred embodiment details The control message processor according to the present invention is preferably in the form of a gate array. The control message processor (programmable field gate-FP GA) is best designed to meet the functional requirements of the headend. Generally, the purpose of CMP-FPGA is to retrieve control information from a data stream such as M, store the information in a message and correspondingly The message status is stored in a status buffer, and the processor element (CPU) has messages to process. More particularly, CMP-FPGA has a shared channel among multiple channels. Here, each state and all parts of the message processor are completed in a state buffer and the captured messages are stored in. The status buffer and the message buffer are divided into a number of definite parts. First, a brief description will be used to implement the head-end function message, and then the implementation details will be explained with respect to the diagram. Instead of using software, F P G Α filters video streams such as MPG format, as in the present invention. Optimal feature pack for address-based filtering CMP — Filters prepared for each channel in the FPGA are unit addresses 40, 40, and multicast address 16. Programmable arrays! J (Compatible PEG message buffer and Notifications, such as the calculated field C MP characteristics at this message. In the input streamer, the centrally-invented controllers all store a parameter of the channel processor ’s channel access characteristics—a preferred C MP stream. The message includes broadcast filtering and Internet address and / or all broadcasts (please read the precautions on the back before filling this page) ·. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)- 8-519838 A7 _ B7 V. Description of the invention (6) Broadcasting information. In the invention device, the language filtering capability is optional and can be omitted, and it has no adverse effect in the overall device. (Please read the precautions on the back before reading) (Fill in this page) The filtering process will be described in more detail below. As a general event, if activated, the filter in the device will save the device to enable only the address filter to be activated, and filter messages that match a predetermined data. Another feature of the invention is that the filtering program is optional; that is, the device can choose whether to store all messages received by the CMP-FPGA in the data stream or only messages that meet the predetermined message filtering parameters. The invention device is also preferably equipped with Single packet capture capability, where a single packet is captured and stored in RAM. Other functions of a preferred embodiment of the inventive device include cyclic margin check (CRC) calculation and check of a header code before continuing processing (Eg, 4-byte M PEG header) message confirmation function. The device should preferably also have an error handling function that indicates the existence of any packet error via the error flag. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints it upon request The invention's data storage is best to use a dual-port RAM as the memory. Depending on the mode of operation of the invention device, the message buffer is determined as a 2K or 8K circular buffer (the details will be described below). For simplicity, for The diagram illustrates that the following embodiment is designed to extract messages and packets from up to 32 different specified packet identification code sources from an M PEG input stream. For example, when operating in 2K mode, the device will use 32 processors and when operating in 8K mode, it will be 20 processors. Of course, this invention is not limited to any particular number of processors. Or any The size of the buffer for special messages; these details can be modified as long as they do not depart from the scope of the invention. Figure 1A is a representative block diagram illustrating the configuration of an embodiment of the present invention. ) A4 size (210 X 297 mm) 519838 A7

Fifth, the invention description (7), and FIG. 1B illustrates the control and the CPU interface for reading and writing data from the CMP-FPGA 100. In this example, CMP- (please read the notes on the back before filling this page) FPGA 1 00 is designed to grab up to 32 different packet identification codes from an MPEG stream. CMP — FPGA 1 0 0 can be built into 3 2 channels' each channel is equipped with 2 K circular buffer or 16 channels are equipped with 2 K circular buffer and 2 channels are equipped with 8 K circular buffer as storage for capturing information Message buffer. The packet data input to the device 1000 can be a one-byte wide information bus data, and the data has a data confirmation signal for confirming the data bytes in each packet. This acknowledgement feature allows interruption of the incoming data stream without packet corruption. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the CMP-FPGA 1 00 usually includes three modules. An input interface 102, a packet identification code (p id) filter 104, and a message processor 106. The message processor 106 is shared by all 32 different message extraction channels, and as shown above, it is therefore possible to retrieve up to 32 messages with different packet identifiers from a data stream. The input interface 1 2 receives the multiplexed data with the packet identification information (p ID) and the flow identification information (PID-S ο n RCE). The flow identification information is uniquely identified from the different flows in a hypothetical flow. Similar to named packets. Because packets in different streams can have the same packet identification code (P ID), the packet identification information (P ID) and the flow identification information (P ID-S ο n RC Ε) are necessary to enable the processor to tell them that they are separate In this case, flow identification information is necessary. The multiplexed data has preferably been converted into parallel packet data as individual data bytes accompanied by an enable signal to confirm each data byte in the packet. When you receive RMB-10- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 519838 A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. As shown in Figure 2, the start signal of BYTE — CLK — EN and CRC-CLK — EN is generated from the combination of CMP — BYTE — VAL ID and CMP — BYTE — CLK signals. Once the interface generates BYTE — CLK — EN and CRC-CLK — EN activation signals, as shown in Figure 3. Using the generated activation, the signal recalculates the CMP-BYTE — DTAT and CMP-BYTE-SYN C signals The clock. The CMP — CLKIN in this example is a 13 · 5MHz clock. CMP — BYTE CLK, CMP-BYTE DATA, CMP-BYTE SYNC and CMP-BYTE VAL ID should all have a setting of at least 1 1 · Oms and a reservation of 0 ms. As seen in Figure 3, compared with the timing diagram in Figure 2, the re-synchronized CMP — BYTE — DATA and C MP — BYTE — SYNC signal timing subtly fits CMP — CLK IN and CMP — BYTE — CLK. The resynchronized byte data is then sent to the PID filter module 104 for additional processing. Next, the C MP-F P G A packet identification code (P I D) filter 104 provides modes, filtering, activation, and mask control for each signal processing channel. Each channel can be P I D filter 1 0 4 for any mode. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -11-(Please read the precautions on the back before filling this page)

519838 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of Invention (9) Establish a plan. Fig. 4A is a representative diagram of the RAM used as the message buffer and Fig. 4B is a control diagram of the PID filter 104. In this example, depending on the storage mode in which the CMP-FPGA 100 operates, there are 32 or 20 programmable message processing channels. More specifically, there are two different storage modes that control the loop storage buffer depth for each channel and the number of channels available. For example, if the storage mode of the message buffer is set to 2 K ′, all 32 channels have a 2 K circular buffer to store the information associated with each channel. However, if the setting mode is 8 K, only 16 channels have 2 K circular buffers to store messages, and 4 channels have 8 K circular buffers to store messages. The P I D filter 104 also has two different modes, an acquisition mode and a message mode, identifying the type of data to be stored in the message buffer. In addition to the synchronization bytes in the packet, the capture mode allows a full packet to be captured and stored in one of the channel buffers. The capture mode can filter any bit in the 3 control byte of the MPEG prefix in the packet or any bit in the mask header to convert the masked bits into "don't care" bits. In message mode, the messages contained in the packet are allowed to be processed with filtered or unfiltered addresses. The address filtering function can be turned on or off through a control RAM interface. If the address filtering function is disabled, all the messages received by the PID filter 104 with the active packet identification code are transmitted to the message processor 106 (shown as BYTEDATA in the first figure). However, if address filtering is turned on, only one of the four allowed address types selected is sent to the message processor 106 and stored as BYTEDATA. In one embodiment, the allowed address types are as follows: Unit address 40, multiple points (please read the precautions on the back before filling this page)

·-0 This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) -12 · 519838 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-A7 B7 5. Description of the invention (10) Broadcasting 1 6 and broadcast. The broadcast address pattern can be processed forever in the example and the other three address patterns are processed only if the address pattern has been selected and the address is defined in the CP. The PI D filter module provides filtering control through a single RAM with multiple addressing locations and acts as a message buffer 'to store up to 32 different channels of messages. The message buffer can be divided into two pages, so that when the internal processor uses another page, the CPPU can write the filtering control information into one page. After CPU writes all the filtering control information to the message buffer, the paging is changed when the incoming data stream is synchronized. The P ID filter 104 can also have a pipeline delay of level 32, allowing each of the 32 different programmable P IDs to be compared with the incoming packet ID. If the programmable P ID matches the incoming packet ID and the 3-bit source ID (PID-SoURCE), the address count of P ID D A A M is locked. The latched data is used to provide the channel address to the control channel processor RAM in the message processor 106. As part of the P ID verification process, the entire header code in the packet is checked to determine whether the packet is valid. During the verification process, the packet in the inspection must meet one or more predetermined conditions, such as whether the error bit in the packet has no effect and whether the random control bit indicates that the packet is not random. If the channel is activated and if the packet meets the predetermined conditions according to the channel, the packet is transmitted to the message processor 106 for address filtering, the message is confirmed, and stored in the message buffer. For example, if the PID filter 104 sets the packet capture mode (more details below), before activating the capture function, the PID filter 104 confirms the entire header code. Can clearly compare the control bits, or if the bit is one (please read the precautions on the back before filling this page)

This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -13-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 519838 Α7 Β7 V. Description of the invention (n) Regardless of "bit", add Masks. To implement the packet capture function, 'p 1 D filter 1 0 4 must first confirm that the channel is enabled, the packet capture mode is enabled and all filtering masks are programmed. Now refer to Figures 5A to 5D and In Figure 6, the PID filter 104 provides start and end signals to four different types, from packet to packet, to process the message transition. In the header code byte (eg, 4 in the case of MPEG packet data) These signals are used during the byte period, which allows the P ID filter 104 to have enough time to transition to the next packet for message processing. During and from the state buffer, the old control variable state is stored and loaded for each channel The state of the new control variable, the state buffer is separate from the message buffer described above. The message processor 106 takes the expected information from the data stream. As one of the usual events of this example, each message extraction channel has dual functions The message extraction channel can be constructed to retrieve a single packet and store it in the message buffer, or it can be constructed to retrieve the information stored inside the packet. The information extracted from the packet can be filtered by the address; on the other hand, The address filtering function can be turned off to receive all the messages stored in the packet without any filtering. More specifically, each message extraction channel can be filtered according to the following parameters: P ID 値, unit address 40; network address 40; Multicast 16 addresses; and / or all broadcast messages. Of course, other parameters can be included in the filter if desired. C MP-FPG Α is programmable to fetch all messages or based on message bits Address filtering to retrieve messages. Each message retrieved from the MP EG stream is stored in a circular buffered message buffer. When each of the 32 message channels is built with a 2K cycle (please read the back first) Please pay attention to this page, please fill in this page). -I line · This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) -14- 519838 Α7 Β7 i. Description of the invention (12) Buffer size, 2 K buffer The maximum allowed message size is 1K. Channels in the 8K buffer mode will receive messages up to 4K in size. The message processor 10 implements two independent procedures. The first procedure counts down from a new message. Start indicator (NMS P) and output a new message interrupt signal (NEWMIP). The second procedure includes capturing the message, processing and storing the message itself and storing it in a circular buffer on the character boundary. These individual procedures will be described in more detail The description is as follows: For the new message indicator program, when the load start indicator in the message processor 106 and the NMS P byte 0 are not equal to zero, the catalyst program is triggered. If the N M S P byte is equal to zero, the message processor 106 will start to avoid the new message indicator procedure. If N M S P is larger than the packet length, the new message indicator procedure is terminated at the end of the packet. Figures 5 Α to 5 D illustrate different boundary conditions at the displacement data to avoid damaging the information in the process. More specifically, Figures 5 A and 5 D illustrate the displacement when a new message start point (NMSP) byte is located between a header portion and a body portion of a packet, and the 5 C and Figure 5D illustrates the displacement when the bytes left from a previously processed packet are inserted into the body of a packet. From Figures 5 Α to 5 D, it can be seen that the packet contains a 4-bit header code 5 0 0 and a packet body 5 2. The message processor 106 is started with one of three conditions. When (1) a "Go to Message Processor" (GO-MP) signal is high; (2) when the channel corresponding to the packet in process is ENABLE; (3)-when the load start signal is high; and (4) When the NMSP byte is equal to zero, the message processing will be started as soon as possible (please read the precautions on the back before filling this page) ·-0. The paper printed by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs applies the Chinese national standard (CNS) A4 specification (210 X 297 mm) -15- 519838 Α7 Β7 V. Description of invention (13) (Please read the precautions on the back before filling this page). As soon as the NEWMIP signal is high, the message processor 106 indicates to start operation. On the other hand, when (1) the message of the ongoing signal M I PO is a tube; and (2) when the signal of G I MP is a message, the message processor 106 starts operation. The message processor also has multiple priority interrupts to restart message processing. If the read indicator and the write indicator do overlap in a 2K / 8K loop message buffer, the highest priority interrupt occurs. Before the 2K / 8K message buffer address overlaps, the processing program will immediately exit, discard the current message in the buffer, and send an overflow error signal to the PID filter 104. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The next type of interruption is the end-of-packet indicator PK-ND signal. When processing a packet according to the boundary conditions it encounters, after selecting one of four different PKT — END signals PKT — END 1 — 4, PKT-END is an output signal. When PKT_END1-3 occurs, all the status data of the current program is stored in the status buffer and the program status is returned to idle, and when PK T — EN D 4 occurs, the old status data is written to the status buffer. Generally, when PKT-END occurs, all states of the current program are stored in a state buffer and the program state of the message processor is returned to idle.

In Figure 5A, the N SMP byte is inserted between the header code 501 and the packet body 502, and the G0-MIP signal is high at the NSMP position. At the end of the packet body, ρκ 丁 一 END signal is high. C R C is stored as a complete message at the end of the packet body. The state of the message processor returns to idle. The message data is saved to the message buffer and the current state data is saved to the state Is punch. Figure 5 B shows that in the GOM IP_ 16- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 519838 Α7 Β7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 14) When the signal is high, there is no case of NS MP bytes; in this case, the packet body is forced to 502 forward one byte and as shown in Figure 5A, when the message processor touches the packet body 5 0 2 When the last byte is PKT — END signal is high. Figure 5C shows the case where a byte from the previous packet is not processed before reading the new packet; in this case, the byte from the previous packet is inserted in the header and the body of the new packet. In the meantime, the bytes in the new packet are forced forward by two bytes. Figure 5D shows a similar situation to Figure 5C, except that N M S P is inserted between the header and bytes from the previous packet. Note that in Figure 5D, there are two PKT — END signals that start writing state data into the state buffer. The PKT-E ND 2 signal is equivalent to the end of the packet and like the example above, causing C R C to be stored for complete information, saving the current state data to the state buffer, and setting the message processor state back to idle. However, the P K T — EN D 4 signal also starts to write the status data of the previous packet to the status buffer. When the message program receives a new message interrupt signal (NEW MI P) from the first program and a packet is being processed by the second program, another type of program interruption occurs, and the countdown of the new message starts at N M S P. This interruption can occur any time a packet is being processed for a message. When NEWMIP occurs while a message is being processed, the current message will be discarded, a packet error flag will be set, and a new message procedure will be initiated. When NEWMIP occurs, if a message is not being processed or a message has been successfully retrieved, a new message will be started without error. Figure 6 shows the program status of the messages in the inventive system. While it is processing, the state corresponding to each packet is stored in the state buffer. (Please read the precautions on the back before filling this page) ·, ··· This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -17- Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 519838 Α7 Β7 V. Description of the invention (15) The first program state 6 0 0 in the message processor is started by moving between the idle state 6 0 2 and the state of the new message start indicator NS M P countdown 6 0 4. Once the NMS P byte reaches zero, a new message is output from the message processor's countdown state 6 0 4 to interrupt the NEWMIP and transition the message processor to its second program state 6 0 6 and then to an idle state 6 0 8 starts. The message processor uses N M S P to find the beginning of a new message at state 6 10. When the beginning of a new message is found, all information about the message (for example, message length, and address type) is retrieved. Then the message processor compares the address type with the expected expected address type, and if the corresponding address type is met, it jumps to the address filtering state 6 1 2; if it does not match, the message processor waits for PK Τ — END signal And once it receives the signal from the P ID filter, it returns to idle. The address is compared with the filtered address during the address filtering state 6 1 2 and if the address filter matches the address, the processor jumps to the program message state 6 1 4; if not, the message processor waits Ρ Κ Τ-END signal and return to idle 108 once the signal is received. In the program message state 6 1 4, the message length is counted down to 4 bytes of C R C data, and then the message processor jumps to the code recognition C R C state 6 1 6. Compare the calculated C R C with the C R c at the end of the captured message. If so, the message processor has successfully retrieved the message. Once the messages are retrieved and confirmed in states 6 1 4 and 6 1 6 respectively, in state 6 1 8 the message processor starts searching for a new message in the data stream. If no new message is found, the message processor waits for a signal of κ κ τ_END and returns to the idle state once the signal is received. 6 0 8 ° However, 'if the message ’s paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) -18-(Please read the notes on the back before filling this page)

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 519838 A7 B7 V. Description of the invention (16) If the processor really finds a new message, the NEWMIP goes high and the message processor returns to the message length state, restarting the message capture of the new message program. Note that during any of these states, the NEWMIP signal allows the message processor to retain the current state at any time and return to the message length state of 6 10, effectively suspending the processing of the message and resetting the state machine, and starting a new message. As can be seen in the figure, the message processor also has an alternative packet capture control function in state 6 2 0, where the message processor only stores one packet in the state buffer and will not grab another packet until it has reached the state. The buffer reads the previous packet status data. In particular, the alternative packet capture function 620 allows the CPU to close the message processing of any channel, capture a single packet, and store the captured packet in the message buffer. In this function, each control bit in the header byte can be compared or masked; therefore, the packet can be uniquely identified by the combination of the comparison bit and the mask. The captured packet is preferably stored from the address 0 of the message buffer associated with the captured packet channel. In the alternative packet capture state 6 2 0, another packet is not captured until the first packet has been read. When the packet capture function is activated, any unread or uncompleted messages will be deleted and will not be stored in any buffer. The “click” packet capture function can be activated on any channel 6 2 0. This mode selects a packet by filtering any bit in the header of a 4-byte packet. These bits can be coincident or they can be masked so that they can be ignored when a packet is selected for storage in the state buffer. Note that for each state, the message processor can also log the message write indicator WRPTR and check to make sure that the write indicator and the address indicator do not overlap. If (Please read the notes on the back before filling out this page)

This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -19- 519838

5. Description of the invention (17) (Please read the notes on the back before filling this page) If they really overlap, the message processor indicates that the ADRPTR failed and returns to the idle state without saving the message. Therefore, when the message processor receives a P K T — E ND signal or an ADRPTR fault indication, the message processor returns from any state to idle. Figure 7 illustrates the state buffer and address filter shift register of the message processor 106. As can be seen in Figure 6, CMP-FGPA 100 has only one message processor state machine shared between 32 different channels. 7 0. 3 2 different channels borrow to save the state of the message processor state machine economy The Ministry of Intellectual Property Bureau employee consumer cooperative prints each state of 700 and completes all calculations in the state buffer, which can share a single processor 104. In this particular example, the state buffer is 32 positions deep, accommodates 32 different channels and is as wide as needed, and stores each processing state of the respective channel. The status buffer address is locked by a latch counter P from the PID filter comparator circuit. At the end of each packet, the message processor stops using the state machine program (shown in Figure 6), the state returns to idle, and all states at that point are maintained in the state buffer. When a new packet is ready to be processed, the message processor loads all previous state information from the state buffer and continuously processes the information in the new packet, as necessary, as shown above and shown in Figures 5A to 5D. Displace the data to avoid destroying the messages in progress. Moreover, as shown in Figure 7 below, before the message processor processes the stream and the message is stored in the state buffer, BYTE — DATA multiplexer 7 0 2 uses different displacement versions of the multiplexed data stream to modify the process. Data stream. FIG. 8 is an address filtering control circuit 800 of one of the message processors 104, which corresponds to the address filtering state of FIG. 6 12. As above -20- This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 519838 Α7 Β7 5. Description of the invention (18) Description, address filtering control The circuit compares the message address pattern to any or all of the enabled address patterns. The address filtering control circuit 800 also compares the address of any or all programmable addresses. There are four address types activated with an address filter; the broadcast address type is always activated, while the other three address types mentioned above (network address 40, unit address 40, and multicast bits) The address 16) is activated by planning a channel to control the RAM 802 and more particularly by linking one of the enable bits in the control RAM 802 to a specific address type. If the one-bit address type is activated, the address must be programmed to enable address filtering. In the actual filtering process, if the address type of the received packet is valid, as shown in Figure 6, the message processor status will jump from the message length state 6 1 0 to the address filtering state 6 1 2. In the address filtering state 6 1 2, the programmed address is compared with the message address taken from the message received in the comparator. The output of the comparator 8 0 4 is transmitted to the multiplexer 8 0 6. If the comparator indicates that the received message address matches a programmed address, then the message processor state The machine jumps from the address filtering state 6 1 2 to the message processor state 6 1 4. However, if address filtering is disabled, all messages received by the message processor are treated as a broadcast message and addresses are not compared. For example, setting all control RAM 8 bits to 0 can disable address filtering. In this case, the state machine immediately jumps from the address filtering state 6 1 2 to the message processor state 6 1 4 without any address comparison. Figure 9 shows one of the message processors 106, CRC and error detection circuit 900. This corresponds to the C R C confirmation state 6 1 6 shown in FIG. 6. Use message tuple calculations during message processing (please read the notes on the back before filling this page)

This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) -21-519838 A7 B7 V. Description of the invention (19) C R C. If the calculated C R C 値 matches the c R C embedded in the message, the message is regarded as legitimate and the message processor finishes storing the valid message and writes the message buffer index corresponding to the valid message. Note that since all channels share the same CRC confirmation circuit 9 0 0, the CRC generator 9 0 2 and the CRC shift register 9 0 4 in the CRC confirmation circuit 9 0 should be loadable. More specifically, the CRC circuit 900 should be able to stop the processing of a channel's information, save the status data corresponding to that channel in a status buffer, load and process a new channel, and resume processing of the previous channel without damaging any messages or omissions. Post information. To prevent data from being missed when reading the message buffer, the CPU preferably follows the procedure described in the flowchart in FIG. Before reading the message buffer, it is assumed that the control channel processor has been reset and the message buffer is empty. Moreover, in this example, it is assumed that any incoming message has successfully passed the address filtering and C R C confirmation stages. When a control signal processor interrupt signal is detected as the active low signal, CP has the option of masking interrupt when processing the message. When a new message arrives on a particular channel, the message-ready flag MSG-RbY associated with that particular channel goes high, indicating that the channel has a stored message. C P U identifies all channels with stored information in step 1 0 and first initiates a read request in step 1 0 2 to read the reading index R D P T R of the highest priority channel. This transfers the current write indicator to the WRPTR register. For a specified channel, if the write indicator WRPTR is updated while a read request is being processed, the MS G-R b Y flag of that channel will not be reset in step 1004. However, if the writing index is stable, please go to the next step (please read the precautions on the back before filling this page). X 297 mm) -22- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 519838 A7 B7 V. Description of Invention (20) Step 1 0 0 6 will reset the “30 — 1 ^ 6 ¥ flag of that channel. The CPU then reads the WRPTR register corresponding to the same channel as the read request from the previous step 002. In step 10, the CPU uses the internal offset of the read index RDPTR to add the channel offset. , Find a position to read the first message from the message buffer. The length of each message is determined by the message length 値 embedded in the message. There may be several messages in the buffer and the CPU starts from the old RDPTR 値 and the length of the embedded message値 Calculate the new reading index RDPTR. Use WRPTR in the reading channel to get all the messages and calculate the RDPTR which needs to be written back to the control message processor. After all the messages in that channel have been read from the message buffer The CPU writes the RDPTR to the control message processor and checks in step 10 10 whether there is another channel containing the message to be read. If so, the CPU moves to another channel and repeats steps 1 0 0 2 to 1 0 0 8 until all messages have been read. Once all messages have been read, the CPU interrupts in step 1 0 1 2 without masking and checks the interrupt status in step 1 0 1 4. The interrupt is still low when it is not masked Signal, which indicates that a new message has been received during the previous message processing operation. If this occurs, the CPU returns to step 1000 to start a new message processing operation. However, if the C MP interrupt in step 10 14 is If the high signal is not active, it indicates that there is no new message to be processed in any channel. In this case, the CPU can rest while waiting for the channel to receive a new message. Now refer to Figure 11 and MSG of Figure 10 above — The R by flag and interrupt signal are generated by writing to WRPTR RAM. The writing index WRPTR is written by the message processor 1 0 4 when completing each message (please read the precautions on the back before filling this page)

This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) -23- 8 3 8 9 IX 5 Α7-^ ___B7___ V. Description of the invention (21) (Please read the notes on the back before filling in this Page) into the RAM address with its channel. Each of the 32 channels has its own associated M S G — R b y flag control circuit. As can be seen in the figure, the interrupt signal generated by the OR gate of all M S G — R b y signals is received as input. When C P U is interrupted, it reads a * MS G-R b y register to determine which channel has a message. During processing of each message, the CPU requests the read and write indicator WRPTR. The WRPTR interface transmits data to WRPTR-HOLD-REG for C P U to read, and resets the MS G-R b y flag during this transmission. However, if a new message is received during data transmission, the M S G-R b y flag will not be reset. The processing of each message is completed by writing and reading the indicator RbPTR and the address position at the end of the message reading process. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 12 illustrates a message error control circuit in one of the message processors 104. As indicated above, the message processor identifies missing messages due to corrupted packets or buffer overflows. To achieve this, the circuit shown in Figure 12 includes two error circuits 1200, 1202 for each 32 channels. An error circuit 1 2 0 0 generates a flag. The flag identifies a missing message due to a damaged packet, and another error circuit 1 2 0 2 generates a flag that identifies the missing message due to an overflow in the message buffer. These registers are set when an error is detected and erased after the CPU status has been read by the CPU. Therefore, the inventive system is a multiplexed, multi-channel information grabber, which can be expanded to any depth by taking the depth of R AM to capture more information. More specifically, this invention system uses two separate buffers to capture and process the multiple message parts contained in the packet in a multiplexed manner to store the captured information. -24- This paper size applies the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) 519838 Α7 Β7 V. Description of the invention (22) (Please read the precautions on the back before filling out this page) Information and status information corresponding to the information captured, each buffer has a large number corresponding to many ways position. This capability allows the invented system to extract from multiple streams of packet data, extract and combine multiple complete messages. The preferred multiplexing message extractor according to the present invention should take into account many parameters, which can be achieved fully functionally in a head-end application, or in any other application where the inventive device will be used. For example, for a typical re-multiplexing application, there are more than 600 control states for each packet in the data stream that should be stored and loaded in the proper order. Moreover, it is preferable to have a 4-byte wide time, during which time an old message is unloaded during processing and an effective message is reloaded to be captured during this time. Although conversion to an ASIC is an option that will fall within the scope of this invention, the present invention is best implemented with a decentralized RAM-type FPGA / ASIC (ie, Xilink, OR CA). Those who are familiar with this technology will understand that clothing printed by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs will be able to modify and change the invention information extractor without departing from the scope of the invention. For example, although it has been described that the invention's message extractor extracts information from a data stream in the MPEG digital format, it can modify the extractor to extract information from the data stream in two other formats that are currently known and subsequently developed. In addition, the invention's message grabber can be used to extract information from a signal such as MPG in a larger digital broadcast structure such as the Digital Video Broadcasting (DVB) format (which uses the MPG format as its video format). Therefore, it is not intended that the invention be limited by any particular example provided herein. It should be understood that various alternatives to the embodiments of the invention described herein can be used in implementing the invention. The following request is expected to define the scope of the invention and -25- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 male f) 519838 A7 B7 Therefore, 5. Description of the invention (23) The methods and equipment within the scope of these requests are Peer device. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy

Claims (1)

519838 A8 B8 C8 D8 Month; • Supplementary VI. Attachment to the scope of patent application (please read the notes on the back before filling out this page) No. 89 1 2 1032 Chinese Patent Application Amendment 7 Month correction 1 · A device for extracting information from a digital data stream containing a message, including: ~ a message processor that receives a digital data stream and extracts a message portion from the digital data stream; a first buffer The buffer is connected to a plurality of locations of a plurality of channels to store the captured information portion; and a second buffer is connected to a plurality of locations of a plurality of channels to store the status data corresponding to the captured information portion. . 2. If the equipment in the scope of patent application No. 1 further includes a central processing unit interface for connecting the equipment to a central processing unit. 3 · A device for capturing information from a data stream, including: an input interface for receiving packet data in the data stream; printed by an employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, connected to the input interface, and selectively filtering packets Packet ID filter for data, the packet ID filter device, a central processing unit (CPU) interface allowing communication between the device and a CPU; a message processor, the message processor receives selective filtering from the packet ID filter The packet information and extracting the message part from the packet information; a first buffer, which is connected to many locations in many channels to store the retrieved message part; and this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 519838 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 D8 6. Scope of patent application A second buffer, which is connected to many positions in many channels, to store the status data corresponding to the captured message part. 4. The device according to item 3 of the patent application, wherein the input interface converts the packet data into parallel packet data. 5 · For the device in the scope of patent application, the parallel packet data is transmitted to a packet identification filter with an activation signal to confirm the byte data in the packet. 6 · If the device in the scope of patent application No. 5, the input interface generates at least one clock start signal to resynchronize the byte data. '7 · If the device of the scope of patent application No. 3, wherein the packet identification code filter provides at least one selected from each channel in the message processor, and is controlled by the mode' filter control, activation control and mask control group one. 8. The device according to item 7 of the scope of patent application, wherein the mode control includes selecting one of a plurality of storage modes, and each storage mode is equivalent to the buffer size of the first buffer. 9 _If the device in the scope of patent application item 7, the mode control includes selecting one of the capture mode and the message mode. In the capture mode, the packet data is stored in the first buffer as a complete packet without a synchronization bit. group. In message mode, messages in packet data are allowed to be processed. 1 〇 If the device in the scope of patent application item 7, the filtering control includes selecting whether the address filtering is on or off and where, when the address furnace is turned on, all the information in the packet data is processed and the address filtering When closed, the selected message in the packet data is processed. 1 1 · If the device in the scope of patent application is item 3, the paper size of the filter template is applicable to China National Standards (CNS) 8-4 specifications (21 ^ X 297 public funds) Γ-: (Please read the precautions on the back first (Fill in this page again)-Order 519838 ABCD 6. Scope of patent application The model has a pipeline delay device, which allows the packet identification code of an incoming packet to be compared with at least one predetermined packet identification code. 1 2 · If the device in the scope of the patent application is No. 3, the filtering module therein checks the header code of the incoming packet with at least one predetermined condition to confirm the incoming packet. 1 3 _If the device in the scope of patent application is the third item, the message processor implements the first procedure to find the starting point of the new message in the packet data and implements the second procedure to retrieve and store the message. 1 4 · If the device in the scope of patent application No. 3, the first buffer is a circular buffer. 15. The device according to item 14 of the scope of patent application, wherein the first buffer includes 32 2 K buffers each, which are used to store the available channels of the message. 16. The device according to item 14 of the scope of patent application, wherein the first buffer includes 16 channels with 2 K buffers and 4 channels with 8 K buffers for storing messages. 17 · The device according to item 3 of the scope of patent application, wherein the message processor includes: a processor state machine shared among a plurality of channels, wherein state data from the processor state machine is stored in a second buffer; A single-site filtering control circuit; and a confirmation circuit that calculates the confirmation code and compares the calculated confirmation code with the embedded confirmation code in the message part of the packet data. 1 8. If the device in the scope of patent application No. 17 is used, the information in this paper applies the Chinese National Standard (CNS) A4 specification (210X297 male i ^ (Please read the precautions on the back before filling this page) If the Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative 519838 A8 B8 C8 D8 6. The scope of the patent application processor also includes an alternative packet capture control that stops processing a single channel of information and captures a single packet. Stored in the first buffer. 1 9 · If the device in the scope of patent application No. 17 further includes a buffer control, when at least one of the first and second buffers is being read, the buffer control controls c The operation of the PU. 2 · If the device in the scope of patent application No. 19, further includes a message ready interrupt control connected to the buffer control, wherein the message ready interrupt control generates a signal based on the status data in the second buffer. Decide which channel has the information to be processed when the CPU is interrupted. 2 1 · If the device in the scope of patent application No. 17 includes a message for identifying missing information Existing message error interface. 2 2 _If the device in the scope of patent application No. 21, the message error interface includes a first error circuit to identify the missing message due to the damaged packet and an identification to the first buffer overflow The second error circuit of the missing information of the stream 0 2 3 · As in the device of the scope of application for patent No. 22, the first and second error circuits are prepared for one of the channels. 2 4 · —kind A method for extracting information from a data stream, including receiving packet data in the data stream; selectively filtering the packet data; extracting at least a part of the message from the packet data; storing the at least part of the message together with a message The first buffer size of the processor applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling out this page) Order the Ministry of Economic Affairs Intellectual Property Bureau Employee Consumer Cooperatives Print the Ministry of Economics Wisdom Printed by the Consumers' Cooperative of the Property Bureau 519838 A8, Yuan 7 a-device w supplement D8____ Sixth, the scope of the patent application and the storage symbol The status information of the at least part of the information is in a second buffer. 2 5 · The method according to item 24 of the patent application scope further includes the step of converting the packet data into parallel packet data. 2 6. The method of scope item 24 further includes the step of providing at least one selected from the group consisting of mode control, filter control, activation control, and mask control for each channel in the message processor. 2 7 · If applied The method of item 26 of the patent, wherein the mode control step includes selecting one of a plurality of storage modes, and each storage mode is equivalent to a buffer size. 28. The method according to item 26 of the scope of patent application, wherein the mode control includes selecting one of an acquisition mode and a message mode. In the acquisition mode, the packet data is stored in the first buffer as a complete packet without the 1. Synchronization bytes, in message mode, allow processing of messages in packet data. 2 9 · The method according to item 26 of the scope of patent application, wherein the filtering control step includes selecting whether the address filtering is on or off, and wherein, when the address filtering is on, the method includes processing all information in the packet data. Steps, and when the address filtering is turned off, the selected information in the packet data is processed. 0 3 0 · If the method in the scope of the patent application is No. 24, it also includes a data flow delay step, which allows one to come in. The packet identification code and at least one Comparison of stylized packet identifiers. This paper size applies to Chinese national standard (CNS> A4 size (210X297mm) -5- -------------.--- Order ------- # (Please read first Note on the back, please fill in this page again) 519838 A8 B8 C8 D8 91. 29 VI. Application for patent scope 3 1 · If the method of patent application scope No. 24, it also includes checking the standard of the package in at least one predetermined condition The first code confirms the step of entering the packet. 3 2 _ If the method of the scope of patent application No. 24, the method includes the steps of calculating a confirmation code; and comparing the calculated confirmation code with the embedded confirmation code ratio of the message in the packet data. 3 3 · The method according to item 32 of the patent application scope further includes the steps of selectively stopping the processing of a single channel of information; and capturing a single packet and storing it in the first buffer. 3 4. The method of item 33 of the patent scope further includes the step of generating at least one signal, which is used to determine which channel has the message ready to be processed when the CPU is interrupted. 3 5 Method, including identifying at least packets and buffer overflows due to corruption One of the steps for missing information (please read the notes on the back before filling this page) I. Order i # Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -6-This paper size applies Chinese National Standards (CNS) M Specifications (210X 297 mm)